1 /* tc-aarch64.c -- Assemble for the AArch64 ISA
3 Copyright 2009, 2010, 2011, 2012, 2013
4 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the license, or
12 (at your option) any later version.
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "bfd_stdint.h"
28 #include "safe-ctype.h"
33 #include "elf/aarch64.h"
34 #include "dw2gencfi.h"
37 #include "dwarf2dbg.h"
39 /* Types of processor to assemble for. */
41 #define CPU_DEFAULT AARCH64_ARCH_V8
44 #define streq(a, b) (strcmp (a, b) == 0)
46 static aarch64_feature_set cpu_variant;
48 /* Variables that we set while parsing command-line options. Once all
49 options have been read we re-process these values to set the real
51 static const aarch64_feature_set *mcpu_cpu_opt = NULL;
52 static const aarch64_feature_set *march_cpu_opt = NULL;
54 /* Constants for known architecture features. */
55 static const aarch64_feature_set cpu_default = CPU_DEFAULT;
57 static const aarch64_feature_set aarch64_arch_any = AARCH64_ANY;
58 static const aarch64_feature_set aarch64_arch_none = AARCH64_ARCH_NONE;
61 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
62 static symbolS *GOT_symbol;
75 /* Bits for DEFINED field in neon_type_el. */
77 #define NTA_HASINDEX 2
81 enum neon_el_type type;
82 unsigned char defined;
87 #define FIXUP_F_HAS_EXPLICIT_SHIFT 0x00000001
91 bfd_reloc_code_real_type type;
94 enum aarch64_opnd opnd;
96 unsigned need_libopcodes_p : 1;
99 struct aarch64_instruction
101 /* libopcodes structure for instruction intermediate representation. */
103 /* Record assembly errors found during the parsing. */
106 enum aarch64_operand_error_kind kind;
109 /* The condition that appears in the assembly line. */
111 /* Relocation information (including the GAS internal fixup). */
113 /* Need to generate an immediate in the literal pool. */
114 unsigned gen_lit_pool : 1;
117 typedef struct aarch64_instruction aarch64_instruction;
119 static aarch64_instruction inst;
121 static bfd_boolean parse_operands (char *, const aarch64_opcode *);
122 static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
124 /* Diagnostics inline function utilites.
126 These are lightweight utlities which should only be called by parse_operands
127 and other parsers. GAS processes each assembly line by parsing it against
128 instruction template(s), in the case of multiple templates (for the same
129 mnemonic name), those templates are tried one by one until one succeeds or
130 all fail. An assembly line may fail a few templates before being
131 successfully parsed; an error saved here in most cases is not a user error
132 but an error indicating the current template is not the right template.
133 Therefore it is very important that errors can be saved at a low cost during
134 the parsing; we don't want to slow down the whole parsing by recording
135 non-user errors in detail.
137 Remember that the objective is to help GAS pick up the most approapriate
138 error message in the case of multiple templates, e.g. FMOV which has 8
144 inst.parsing_error.kind = AARCH64_OPDE_NIL;
145 inst.parsing_error.error = NULL;
148 static inline bfd_boolean
151 return inst.parsing_error.kind != AARCH64_OPDE_NIL;
154 static inline const char *
155 get_error_message (void)
157 return inst.parsing_error.error;
161 set_error_message (const char *error)
163 inst.parsing_error.error = error;
166 static inline enum aarch64_operand_error_kind
167 get_error_kind (void)
169 return inst.parsing_error.kind;
173 set_error_kind (enum aarch64_operand_error_kind kind)
175 inst.parsing_error.kind = kind;
179 set_error (enum aarch64_operand_error_kind kind, const char *error)
181 inst.parsing_error.kind = kind;
182 inst.parsing_error.error = error;
186 set_recoverable_error (const char *error)
188 set_error (AARCH64_OPDE_RECOVERABLE, error);
191 /* Use the DESC field of the corresponding aarch64_operand entry to compose
192 the error message. */
194 set_default_error (void)
196 set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
200 set_syntax_error (const char *error)
202 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
206 set_first_syntax_error (const char *error)
209 set_error (AARCH64_OPDE_SYNTAX_ERROR, error);
213 set_fatal_syntax_error (const char *error)
215 set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
218 /* Number of littlenums required to hold an extended precision number. */
219 #define MAX_LITTLENUMS 6
221 /* Return value for certain parsers when the parsing fails; those parsers
222 return the information of the parsed result, e.g. register number, on
224 #define PARSE_FAIL -1
226 /* This is an invalid condition code that means no conditional field is
228 #define COND_ALWAYS 0x10
232 const char *template;
238 const char *template;
245 bfd_reloc_code_real_type reloc;
248 /* Structure for a hash table entry for a register. */
252 unsigned char number;
254 unsigned char builtin;
257 /* Macros to define the register types and masks for the purpose
260 #undef AARCH64_REG_TYPES
261 #define AARCH64_REG_TYPES \
262 BASIC_REG_TYPE(R_32) /* w[0-30] */ \
263 BASIC_REG_TYPE(R_64) /* x[0-30] */ \
264 BASIC_REG_TYPE(SP_32) /* wsp */ \
265 BASIC_REG_TYPE(SP_64) /* sp */ \
266 BASIC_REG_TYPE(Z_32) /* wzr */ \
267 BASIC_REG_TYPE(Z_64) /* xzr */ \
268 BASIC_REG_TYPE(FP_B) /* b[0-31] *//* NOTE: keep FP_[BHSDQ] consecutive! */\
269 BASIC_REG_TYPE(FP_H) /* h[0-31] */ \
270 BASIC_REG_TYPE(FP_S) /* s[0-31] */ \
271 BASIC_REG_TYPE(FP_D) /* d[0-31] */ \
272 BASIC_REG_TYPE(FP_Q) /* q[0-31] */ \
273 BASIC_REG_TYPE(CN) /* c[0-7] */ \
274 BASIC_REG_TYPE(VN) /* v[0-31] */ \
275 /* Typecheck: any 64-bit int reg (inc SP exc XZR) */ \
276 MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
277 /* Typecheck: any int (inc {W}SP inc [WX]ZR) */ \
278 MULTI_REG_TYPE(R_Z_SP, REG_TYPE(R_32) | REG_TYPE(R_64) \
279 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
280 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
281 /* Typecheck: any [BHSDQ]P FP. */ \
282 MULTI_REG_TYPE(BHSDQ, REG_TYPE(FP_B) | REG_TYPE(FP_H) \
283 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
284 /* Typecheck: any int or [BHSDQ]P FP or V reg (exc SP inc [WX]ZR) */ \
285 MULTI_REG_TYPE(R_Z_BHSDQ_V, REG_TYPE(R_32) | REG_TYPE(R_64) \
286 | REG_TYPE(Z_32) | REG_TYPE(Z_64) | REG_TYPE(VN) \
287 | REG_TYPE(FP_B) | REG_TYPE(FP_H) \
288 | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q)) \
289 /* Any integer register; used for error messages only. */ \
290 MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \
291 | REG_TYPE(SP_32) | REG_TYPE(SP_64) \
292 | REG_TYPE(Z_32) | REG_TYPE(Z_64)) \
293 /* Pseudo type to mark the end of the enumerator sequence. */ \
296 #undef BASIC_REG_TYPE
297 #define BASIC_REG_TYPE(T) REG_TYPE_##T,
298 #undef MULTI_REG_TYPE
299 #define MULTI_REG_TYPE(T,V) BASIC_REG_TYPE(T)
301 /* Register type enumerators. */
304 /* A list of REG_TYPE_*. */
308 #undef BASIC_REG_TYPE
309 #define BASIC_REG_TYPE(T) 1 << REG_TYPE_##T,
311 #define REG_TYPE(T) (1 << REG_TYPE_##T)
312 #undef MULTI_REG_TYPE
313 #define MULTI_REG_TYPE(T,V) V,
315 /* Values indexed by aarch64_reg_type to assist the type checking. */
316 static const unsigned reg_type_masks[] =
321 #undef BASIC_REG_TYPE
323 #undef MULTI_REG_TYPE
324 #undef AARCH64_REG_TYPES
326 /* Diagnostics used when we don't get a register of the expected type.
327 Note: this has to synchronized with aarch64_reg_type definitions
330 get_reg_expected_msg (aarch64_reg_type reg_type)
337 msg = N_("integer 32-bit register expected");
340 msg = N_("integer 64-bit register expected");
343 msg = N_("integer register expected");
345 case REG_TYPE_R_Z_SP:
346 msg = N_("integer, zero or SP register expected");
349 msg = N_("8-bit SIMD scalar register expected");
352 msg = N_("16-bit SIMD scalar or floating-point half precision "
353 "register expected");
356 msg = N_("32-bit SIMD scalar or floating-point single precision "
357 "register expected");
360 msg = N_("64-bit SIMD scalar or floating-point double precision "
361 "register expected");
364 msg = N_("128-bit SIMD scalar or floating-point quad precision "
365 "register expected");
368 msg = N_("C0 - C15 expected");
370 case REG_TYPE_R_Z_BHSDQ_V:
371 msg = N_("register expected");
373 case REG_TYPE_BHSDQ: /* any [BHSDQ]P FP */
374 msg = N_("SIMD scalar or floating-point register expected");
376 case REG_TYPE_VN: /* any V reg */
377 msg = N_("vector register expected");
380 as_fatal (_("invalid register type %d"), reg_type);
385 /* Some well known registers that we refer to directly elsewhere. */
388 /* Instructions take 4 bytes in the object file. */
391 /* Define some common error messages. */
392 #define BAD_SP _("SP not allowed here")
394 static struct hash_control *aarch64_ops_hsh;
395 static struct hash_control *aarch64_cond_hsh;
396 static struct hash_control *aarch64_shift_hsh;
397 static struct hash_control *aarch64_sys_regs_hsh;
398 static struct hash_control *aarch64_pstatefield_hsh;
399 static struct hash_control *aarch64_sys_regs_ic_hsh;
400 static struct hash_control *aarch64_sys_regs_dc_hsh;
401 static struct hash_control *aarch64_sys_regs_at_hsh;
402 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
403 static struct hash_control *aarch64_reg_hsh;
404 static struct hash_control *aarch64_barrier_opt_hsh;
405 static struct hash_control *aarch64_nzcv_hsh;
406 static struct hash_control *aarch64_pldop_hsh;
408 /* Stuff needed to resolve the label ambiguity
417 static symbolS *last_label_seen;
419 /* Literal pool structure. Held on a per-section
420 and per-sub-section basis. */
422 #define MAX_LITERAL_POOL_SIZE 1024
423 typedef struct literal_pool
425 expressionS literals[MAX_LITERAL_POOL_SIZE];
426 unsigned int next_free_entry;
432 struct literal_pool *next;
435 /* Pointer to a linked list of literal pools. */
436 static literal_pool *list_of_pools = NULL;
440 /* This array holds the chars that always start a comment. If the
441 pre-processor is disabled, these aren't very useful. */
442 const char comment_chars[] = "";
444 /* This array holds the chars that only start a comment at the beginning of
445 a line. If the line seems to have the form '# 123 filename'
446 .line and .file directives will appear in the pre-processed output. */
447 /* Note that input_file.c hand checks for '#' at the beginning of the
448 first line of the input file. This is because the compiler outputs
449 #NO_APP at the beginning of its output. */
450 /* Also note that comments like this one will always work. */
451 const char line_comment_chars[] = "#";
453 const char line_separator_chars[] = ";";
455 /* Chars that can be used to separate mant
456 from exp in floating point numbers. */
457 const char EXP_CHARS[] = "eE";
459 /* Chars that mean this number is a floating point constant. */
463 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
465 /* Prefix character that indicates the start of an immediate value. */
466 #define is_immediate_prefix(C) ((C) == '#')
468 /* Separator character handling. */
470 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
472 static inline bfd_boolean
473 skip_past_char (char **str, char c)
484 #define skip_past_comma(str) skip_past_char (str, ',')
486 /* Arithmetic expressions (possibly involving symbols). */
488 static bfd_boolean in_my_get_expression_p = FALSE;
490 /* Third argument to my_get_expression. */
491 #define GE_NO_PREFIX 0
492 #define GE_OPT_PREFIX 1
494 /* Return TRUE if the string pointed by *STR is successfully parsed
495 as an valid expression; *EP will be filled with the information of
496 such an expression. Otherwise return FALSE. */
499 my_get_expression (expressionS * ep, char **str, int prefix_mode,
504 int prefix_present_p = 0;
511 if (is_immediate_prefix (**str))
514 prefix_present_p = 1;
521 memset (ep, 0, sizeof (expressionS));
523 save_in = input_line_pointer;
524 input_line_pointer = *str;
525 in_my_get_expression_p = TRUE;
526 seg = expression (ep);
527 in_my_get_expression_p = FALSE;
529 if (ep->X_op == O_illegal || (reject_absent && ep->X_op == O_absent))
531 /* We found a bad expression in md_operand(). */
532 *str = input_line_pointer;
533 input_line_pointer = save_in;
534 if (prefix_present_p && ! error_p ())
535 set_fatal_syntax_error (_("bad expression"));
537 set_first_syntax_error (_("bad expression"));
542 if (seg != absolute_section
543 && seg != text_section
544 && seg != data_section
545 && seg != bss_section && seg != undefined_section)
547 set_syntax_error (_("bad segment"));
548 *str = input_line_pointer;
549 input_line_pointer = save_in;
556 *str = input_line_pointer;
557 input_line_pointer = save_in;
561 /* Turn a string in input_line_pointer into a floating point constant
562 of type TYPE, and store the appropriate bytes in *LITP. The number
563 of LITTLENUMS emitted is stored in *SIZEP. An error message is
564 returned, or NULL on OK. */
567 md_atof (int type, char *litP, int *sizeP)
569 return ieee_md_atof (type, litP, sizeP, target_big_endian);
572 /* We handle all bad expressions here, so that we can report the faulty
573 instruction in the error message. */
575 md_operand (expressionS * exp)
577 if (in_my_get_expression_p)
578 exp->X_op = O_illegal;
581 /* Immediate values. */
583 /* Errors may be set multiple times during parsing or bit encoding
584 (particularly in the Neon bits), but usually the earliest error which is set
585 will be the most meaningful. Avoid overwriting it with later (cascading)
586 errors by calling this function. */
589 first_error (const char *error)
592 set_syntax_error (error);
595 /* Similiar to first_error, but this function accepts formatted error
598 first_error_fmt (const char *format, ...)
603 /* N.B. this single buffer will not cause error messages for different
604 instructions to pollute each other; this is because at the end of
605 processing of each assembly line, error message if any will be
606 collected by as_bad. */
607 static char buffer[size];
611 int ret ATTRIBUTE_UNUSED;
612 va_start (args, format);
613 ret = vsnprintf (buffer, size, format, args);
614 know (ret <= size - 1 && ret >= 0);
616 set_syntax_error (buffer);
620 /* Register parsing. */
622 /* Generic register parser which is called by other specialized
624 CCP points to what should be the beginning of a register name.
625 If it is indeed a valid register name, advance CCP over it and
626 return the reg_entry structure; otherwise return NULL.
627 It does not issue diagnostics. */
630 parse_reg (char **ccp)
636 #ifdef REGISTER_PREFIX
637 if (*start != REGISTER_PREFIX)
643 if (!ISALPHA (*p) || !is_name_beginner (*p))
648 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
650 reg = (reg_entry *) hash_find_n (aarch64_reg_hsh, start, p - start);
659 /* Return TRUE if REG->TYPE is a valid type of TYPE; otherwise
662 aarch64_check_reg_type (const reg_entry *reg, aarch64_reg_type type)
664 if (reg->type == type)
669 case REG_TYPE_R64_SP: /* 64-bit integer reg (inc SP exc XZR). */
670 case REG_TYPE_R_Z_SP: /* Integer reg (inc {X}SP inc [WX]ZR). */
671 case REG_TYPE_R_Z_BHSDQ_V: /* Any register apart from Cn. */
672 case REG_TYPE_BHSDQ: /* Any [BHSDQ]P FP or SIMD scalar register. */
673 case REG_TYPE_VN: /* Vector register. */
674 gas_assert (reg->type < REG_TYPE_MAX && type < REG_TYPE_MAX);
675 return ((reg_type_masks[reg->type] & reg_type_masks[type])
676 == reg_type_masks[reg->type]);
678 as_fatal ("unhandled type %d", type);
683 /* Parse a register and return PARSE_FAIL if the register is not of type R_Z_SP.
684 Return the register number otherwise. *ISREG32 is set to one if the
685 register is 32-bit wide; *ISREGZERO is set to one if the register is
686 of type Z_32 or Z_64.
687 Note that this function does not issue any diagnostics. */
690 aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
691 int *isreg32, int *isregzero)
694 const reg_entry *reg = parse_reg (&str);
699 if (! aarch64_check_reg_type (reg, REG_TYPE_R_Z_SP))
708 *isreg32 = reg->type == REG_TYPE_SP_32;
713 *isreg32 = reg->type == REG_TYPE_R_32;
720 *isreg32 = reg->type == REG_TYPE_Z_32;
732 /* Parse the qualifier of a SIMD vector register or a SIMD vector element.
733 Fill in *PARSED_TYPE and return TRUE if the parsing succeeds;
734 otherwise return FALSE.
736 Accept only one occurrence of:
737 8b 16b 4h 8h 2s 4s 1d 2d
740 parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
744 unsigned element_size;
745 enum neon_el_type type;
755 width = strtoul (ptr, &ptr, 10);
756 if (width != 1 && width != 2 && width != 4 && width != 8 && width != 16)
758 first_error_fmt (_("bad size %d in vector width specifier"), width);
763 switch (TOLOWER (*ptr))
791 first_error_fmt (_("unexpected character `%c' in element size"), *ptr);
793 first_error (_("missing element size"));
796 if (width != 0 && width * element_size != 64 && width * element_size != 128)
799 ("invalid element size %d and vector size combination %c"),
805 parsed_type->type = type;
806 parsed_type->width = width;
813 /* Parse a single type, e.g. ".8b", leading period included.
814 Only applicable to Vn registers.
816 Return TRUE on success; otherwise return FALSE. */
818 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
824 if (! parse_neon_type_for_operand (vectype, &str))
826 first_error (_("vector type expected"));
838 /* Parse a register of the type TYPE.
840 Return PARSE_FAIL if the string pointed by *CCP is not a valid register
841 name or the parsed register is not of TYPE.
843 Otherwise return the register number, and optionally fill in the actual
844 type of the register in *RTYPE when multiple alternatives were given, and
845 return the register shape and element index information in *TYPEINFO.
847 IN_REG_LIST should be set with TRUE if the caller is parsing a register
851 parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
852 struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
855 const reg_entry *reg = parse_reg (&str);
856 struct neon_type_el atype;
857 struct neon_type_el parsetype;
858 bfd_boolean is_typed_vecreg = FALSE;
861 atype.type = NT_invtype;
869 set_default_error ();
873 if (! aarch64_check_reg_type (reg, type))
875 DEBUG_TRACE ("reg type check failed");
876 set_default_error ();
881 if (type == REG_TYPE_VN
882 && parse_neon_operand_type (&parsetype, &str))
884 /* Register if of the form Vn.[bhsdq]. */
885 is_typed_vecreg = TRUE;
887 if (parsetype.width == 0)
888 /* Expect index. In the new scheme we cannot have
889 Vn.[bhsdq] represent a scalar. Therefore any
890 Vn.[bhsdq] should have an index following it.
891 Except in reglists ofcourse. */
892 atype.defined |= NTA_HASINDEX;
894 atype.defined |= NTA_HASTYPE;
896 atype.type = parsetype.type;
897 atype.width = parsetype.width;
900 if (skip_past_char (&str, '['))
904 /* Reject Sn[index] syntax. */
905 if (!is_typed_vecreg)
907 first_error (_("this type of register can't be indexed"));
911 if (in_reg_list == TRUE)
913 first_error (_("index not allowed inside register list"));
917 atype.defined |= NTA_HASINDEX;
919 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
921 if (exp.X_op != O_constant)
923 first_error (_("constant expression required"));
927 if (! skip_past_char (&str, ']'))
930 atype.index = exp.X_add_number;
932 else if (!in_reg_list && (atype.defined & NTA_HASINDEX) != 0)
934 /* Indexed vector register expected. */
935 first_error (_("indexed vector register expected"));
939 /* A vector reg Vn should be typed or indexed. */
940 if (type == REG_TYPE_VN && atype.defined == 0)
942 first_error (_("invalid use of vector register"));
958 Return the register number on success; return PARSE_FAIL otherwise.
960 If RTYPE is not NULL, return in *RTYPE the (possibly restricted) type of
961 the register (e.g. NEON double or quad reg when either has been requested).
963 If this is a NEON vector register with additional type information, fill
964 in the struct pointed to by VECTYPE (if non-NULL).
966 This parser does not handle register list. */
969 aarch64_reg_parse (char **ccp, aarch64_reg_type type,
970 aarch64_reg_type *rtype, struct neon_type_el *vectype)
972 struct neon_type_el atype;
974 int reg = parse_typed_reg (&str, type, rtype, &atype,
975 /*in_reg_list= */ FALSE);
977 if (reg == PARSE_FAIL)
988 static inline bfd_boolean
989 eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
993 && e1.defined == e2.defined
994 && e1.width == e2.width && e1.index == e2.index;
997 /* This function parses the NEON register list. On success, it returns
998 the parsed register list information in the following encoded format:
1000 bit 18-22 | 13-17 | 7-11 | 2-6 | 0-1
1001 4th regno | 3rd regno | 2nd regno | 1st regno | num_of_reg
1003 The information of the register shape and/or index is returned in
1006 It returns PARSE_FAIL if the register list is invalid.
1008 The list contains one to four registers.
1009 Each register can be one of:
1012 All <T> should be identical.
1013 All <index> should be identical.
1014 There are restrictions on <Vt> numbers which are checked later
1015 (by reg_list_valid_p). */
1018 parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
1022 struct neon_type_el typeinfo, typeinfo_first;
1027 bfd_boolean error = FALSE;
1028 bfd_boolean expect_index = FALSE;
1032 set_syntax_error (_("expecting {"));
1038 typeinfo_first.defined = 0;
1039 typeinfo_first.type = NT_invtype;
1040 typeinfo_first.width = -1;
1041 typeinfo_first.index = 0;
1050 str++; /* skip over '-' */
1053 val = parse_typed_reg (&str, REG_TYPE_VN, NULL, &typeinfo,
1054 /*in_reg_list= */ TRUE);
1055 if (val == PARSE_FAIL)
1057 set_first_syntax_error (_("invalid vector register in list"));
1061 /* reject [bhsd]n */
1062 if (typeinfo.defined == 0)
1064 set_first_syntax_error (_("invalid scalar register in list"));
1069 if (typeinfo.defined & NTA_HASINDEX)
1070 expect_index = TRUE;
1074 if (val < val_range)
1076 set_first_syntax_error
1077 (_("invalid range in vector register list"));
1086 typeinfo_first = typeinfo;
1087 else if (! eq_neon_type_el (typeinfo_first, typeinfo))
1089 set_first_syntax_error
1090 (_("type mismatch in vector register list"));
1095 for (i = val_range; i <= val; i++)
1097 ret_val |= i << (5 * nb_regs);
1102 while (skip_past_comma (&str) || (in_range = 1, *str == '-'));
1104 skip_whitespace (str);
1107 set_first_syntax_error (_("end of vector register list not found"));
1112 skip_whitespace (str);
1116 if (skip_past_char (&str, '['))
1120 my_get_expression (&exp, &str, GE_NO_PREFIX, 1);
1121 if (exp.X_op != O_constant)
1123 set_first_syntax_error (_("constant expression required."));
1126 if (! skip_past_char (&str, ']'))
1129 typeinfo_first.index = exp.X_add_number;
1133 set_first_syntax_error (_("expected index"));
1140 set_first_syntax_error (_("too many registers in vector register list"));
1143 else if (nb_regs == 0)
1145 set_first_syntax_error (_("empty vector register list"));
1151 *vectype = typeinfo_first;
1153 return error ? PARSE_FAIL : (ret_val << 2) | (nb_regs - 1);
1156 /* Directives: register aliases. */
1159 insert_reg_alias (char *str, int number, aarch64_reg_type type)
1164 if ((new = hash_find (aarch64_reg_hsh, str)) != 0)
1167 as_warn (_("ignoring attempt to redefine built-in register '%s'"),
1170 /* Only warn about a redefinition if it's not defined as the
1172 else if (new->number != number || new->type != type)
1173 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1178 name = xstrdup (str);
1179 new = xmalloc (sizeof (reg_entry));
1182 new->number = number;
1184 new->builtin = FALSE;
1186 if (hash_insert (aarch64_reg_hsh, name, (void *) new))
1192 /* Look for the .req directive. This is of the form:
1194 new_register_name .req existing_register_name
1196 If we find one, or if it looks sufficiently like one that we want to
1197 handle any error here, return TRUE. Otherwise return FALSE. */
1200 create_register_alias (char *newname, char *p)
1202 const reg_entry *old;
1203 char *oldname, *nbuf;
1206 /* The input scrubber ensures that whitespace after the mnemonic is
1207 collapsed to single spaces. */
1209 if (strncmp (oldname, " .req ", 6) != 0)
1213 if (*oldname == '\0')
1216 old = hash_find (aarch64_reg_hsh, oldname);
1219 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1223 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1224 the desired alias name, and p points to its end. If not, then
1225 the desired alias name is in the global original_case_string. */
1226 #ifdef TC_CASE_SENSITIVE
1229 newname = original_case_string;
1230 nlen = strlen (newname);
1233 nbuf = alloca (nlen + 1);
1234 memcpy (nbuf, newname, nlen);
1237 /* Create aliases under the new name as stated; an all-lowercase
1238 version of the new name; and an all-uppercase version of the new
1240 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
1242 for (p = nbuf; *p; p++)
1245 if (strncmp (nbuf, newname, nlen))
1247 /* If this attempt to create an additional alias fails, do not bother
1248 trying to create the all-lower case alias. We will fail and issue
1249 a second, duplicate error message. This situation arises when the
1250 programmer does something like:
1253 The second .req creates the "Foo" alias but then fails to create
1254 the artificial FOO alias because it has already been created by the
1256 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
1260 for (p = nbuf; *p; p++)
1263 if (strncmp (nbuf, newname, nlen))
1264 insert_reg_alias (nbuf, old->number, old->type);
1270 /* Should never be called, as .req goes between the alias and the
1271 register name, not at the beginning of the line. */
1273 s_req (int a ATTRIBUTE_UNUSED)
1275 as_bad (_("invalid syntax for .req directive"));
1278 /* The .unreq directive deletes an alias which was previously defined
1279 by .req. For example:
1285 s_unreq (int a ATTRIBUTE_UNUSED)
1290 name = input_line_pointer;
1292 while (*input_line_pointer != 0
1293 && *input_line_pointer != ' ' && *input_line_pointer != '\n')
1294 ++input_line_pointer;
1296 saved_char = *input_line_pointer;
1297 *input_line_pointer = 0;
1300 as_bad (_("invalid syntax for .unreq directive"));
1303 reg_entry *reg = hash_find (aarch64_reg_hsh, name);
1306 as_bad (_("unknown register alias '%s'"), name);
1307 else if (reg->builtin)
1308 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1315 hash_delete (aarch64_reg_hsh, name, FALSE);
1316 free ((char *) reg->name);
1319 /* Also locate the all upper case and all lower case versions.
1320 Do not complain if we cannot find one or the other as it
1321 was probably deleted above. */
1323 nbuf = strdup (name);
1324 for (p = nbuf; *p; p++)
1326 reg = hash_find (aarch64_reg_hsh, nbuf);
1329 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1330 free ((char *) reg->name);
1334 for (p = nbuf; *p; p++)
1336 reg = hash_find (aarch64_reg_hsh, nbuf);
1339 hash_delete (aarch64_reg_hsh, nbuf, FALSE);
1340 free ((char *) reg->name);
1348 *input_line_pointer = saved_char;
1349 demand_empty_rest_of_line ();
1352 /* Directives: Instruction set selection. */
1355 /* This code is to handle mapping symbols as defined in the ARM AArch64 ELF
1356 spec. (See "Mapping symbols", section 4.5.4, ARM AAELF64 version 0.05).
1357 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1358 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1360 /* Create a new mapping symbol for the transition to STATE. */
1363 make_mapping_symbol (enum mstate state, valueT value, fragS * frag)
1366 const char *symname;
1373 type = BSF_NO_FLAGS;
1377 type = BSF_NO_FLAGS;
1383 symbolP = symbol_new (symname, now_seg, value, frag);
1384 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1386 /* Save the mapping symbols for future reference. Also check that
1387 we do not place two mapping symbols at the same offset within a
1388 frag. We'll handle overlap between frags in
1389 check_mapping_symbols.
1391 If .fill or other data filling directive generates zero sized data,
1392 the mapping symbol for the following code will have the same value
1393 as the one generated for the data filling directive. In this case,
1394 we replace the old symbol with the new one at the same address. */
1397 if (frag->tc_frag_data.first_map != NULL)
1399 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
1400 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP,
1403 frag->tc_frag_data.first_map = symbolP;
1405 if (frag->tc_frag_data.last_map != NULL)
1407 know (S_GET_VALUE (frag->tc_frag_data.last_map) <=
1408 S_GET_VALUE (symbolP));
1409 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
1410 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP,
1413 frag->tc_frag_data.last_map = symbolP;
1416 /* We must sometimes convert a region marked as code to data during
1417 code alignment, if an odd number of bytes have to be padded. The
1418 code mapping symbol is pushed to an aligned address. */
1421 insert_data_mapping_symbol (enum mstate state,
1422 valueT value, fragS * frag, offsetT bytes)
1424 /* If there was already a mapping symbol, remove it. */
1425 if (frag->tc_frag_data.last_map != NULL
1426 && S_GET_VALUE (frag->tc_frag_data.last_map) ==
1427 frag->fr_address + value)
1429 symbolS *symp = frag->tc_frag_data.last_map;
1433 know (frag->tc_frag_data.first_map == symp);
1434 frag->tc_frag_data.first_map = NULL;
1436 frag->tc_frag_data.last_map = NULL;
1437 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
1440 make_mapping_symbol (MAP_DATA, value, frag);
1441 make_mapping_symbol (state, value + bytes, frag);
1444 static void mapping_state_2 (enum mstate state, int max_chars);
1446 /* Set the mapping state to STATE. Only call this when about to
1447 emit some STATE bytes to the file. */
1450 mapping_state (enum mstate state)
1452 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1454 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
1456 if (mapstate == state)
1457 /* The mapping symbol has already been emitted.
1458 There is nothing else to do. */
1460 else if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
1461 /* This case will be evaluated later in the next else. */
1463 else if (TRANSITION (MAP_UNDEFINED, MAP_INSN))
1465 /* Only add the symbol if the offset is > 0:
1466 if we're at the first frag, check it's size > 0;
1467 if we're not at the first frag, then for sure
1468 the offset is > 0. */
1469 struct frag *const frag_first = seg_info (now_seg)->frchainP->frch_root;
1470 const int add_symbol = (frag_now != frag_first)
1471 || (frag_now_fix () > 0);
1474 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
1477 mapping_state_2 (state, 0);
1481 /* Same as mapping_state, but MAX_CHARS bytes have already been
1482 allocated. Put the mapping symbol that far back. */
1485 mapping_state_2 (enum mstate state, int max_chars)
1487 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
1489 if (!SEG_NORMAL (now_seg))
1492 if (mapstate == state)
1493 /* The mapping symbol has already been emitted.
1494 There is nothing else to do. */
1497 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1498 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
1501 #define mapping_state(x) /* nothing */
1502 #define mapping_state_2(x, y) /* nothing */
1505 /* Directives: sectioning and alignment. */
1508 s_bss (int ignore ATTRIBUTE_UNUSED)
1510 /* We don't support putting frags in the BSS segment, we fake it by
1511 marking in_bss, then looking at s_skip for clues. */
1512 subseg_set (bss_section, 0);
1513 demand_empty_rest_of_line ();
1514 mapping_state (MAP_DATA);
1518 s_even (int ignore ATTRIBUTE_UNUSED)
1520 /* Never make frag if expect extra pass. */
1522 frag_align (1, 0, 0);
1524 record_alignment (now_seg, 1);
1526 demand_empty_rest_of_line ();
1529 /* Directives: Literal pools. */
1531 static literal_pool *
1532 find_literal_pool (int size)
1536 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1538 if (pool->section == now_seg
1539 && pool->sub_section == now_subseg && pool->size == size)
1546 static literal_pool *
1547 find_or_make_literal_pool (int size)
1549 /* Next literal pool ID number. */
1550 static unsigned int latest_pool_num = 1;
1553 pool = find_literal_pool (size);
1557 /* Create a new pool. */
1558 pool = xmalloc (sizeof (*pool));
1562 /* Currently we always put the literal pool in the current text
1563 section. If we were generating "small" model code where we
1564 knew that all code and initialised data was within 1MB then
1565 we could output literals to mergeable, read-only data
1568 pool->next_free_entry = 0;
1569 pool->section = now_seg;
1570 pool->sub_section = now_subseg;
1572 pool->next = list_of_pools;
1573 pool->symbol = NULL;
1575 /* Add it to the list. */
1576 list_of_pools = pool;
1579 /* New pools, and emptied pools, will have a NULL symbol. */
1580 if (pool->symbol == NULL)
1582 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1583 (valueT) 0, &zero_address_frag);
1584 pool->id = latest_pool_num++;
1591 /* Add the literal of size SIZE in *EXP to the relevant literal pool.
1592 Return TRUE on success, otherwise return FALSE. */
1594 add_to_lit_pool (expressionS *exp, int size)
1599 pool = find_or_make_literal_pool (size);
1601 /* Check if this literal value is already in the pool. */
1602 for (entry = 0; entry < pool->next_free_entry; entry++)
1604 if ((pool->literals[entry].X_op == exp->X_op)
1605 && (exp->X_op == O_constant)
1606 && (pool->literals[entry].X_add_number == exp->X_add_number)
1607 && (pool->literals[entry].X_unsigned == exp->X_unsigned))
1610 if ((pool->literals[entry].X_op == exp->X_op)
1611 && (exp->X_op == O_symbol)
1612 && (pool->literals[entry].X_add_number == exp->X_add_number)
1613 && (pool->literals[entry].X_add_symbol == exp->X_add_symbol)
1614 && (pool->literals[entry].X_op_symbol == exp->X_op_symbol))
1618 /* Do we need to create a new entry? */
1619 if (entry == pool->next_free_entry)
1621 if (entry >= MAX_LITERAL_POOL_SIZE)
1623 set_syntax_error (_("literal pool overflow"));
1627 pool->literals[entry] = *exp;
1628 pool->next_free_entry += 1;
1631 exp->X_op = O_symbol;
1632 exp->X_add_number = ((int) entry) * size;
1633 exp->X_add_symbol = pool->symbol;
1638 /* Can't use symbol_new here, so have to create a symbol and then at
1639 a later date assign it a value. Thats what these functions do. */
1642 symbol_locate (symbolS * symbolP,
1643 const char *name,/* It is copied, the caller can modify. */
1644 segT segment, /* Segment identifier (SEG_<something>). */
1645 valueT valu, /* Symbol value. */
1646 fragS * frag) /* Associated fragment. */
1648 unsigned int name_length;
1649 char *preserved_copy_of_name;
1651 name_length = strlen (name) + 1; /* +1 for \0. */
1652 obstack_grow (¬es, name, name_length);
1653 preserved_copy_of_name = obstack_finish (¬es);
1655 #ifdef tc_canonicalize_symbol_name
1656 preserved_copy_of_name =
1657 tc_canonicalize_symbol_name (preserved_copy_of_name);
1660 S_SET_NAME (symbolP, preserved_copy_of_name);
1662 S_SET_SEGMENT (symbolP, segment);
1663 S_SET_VALUE (symbolP, valu);
1664 symbol_clear_list_pointers (symbolP);
1666 symbol_set_frag (symbolP, frag);
1668 /* Link to end of symbol chain. */
1670 extern int symbol_table_frozen;
1672 if (symbol_table_frozen)
1676 symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
1678 obj_symbol_new_hook (symbolP);
1680 #ifdef tc_symbol_new_hook
1681 tc_symbol_new_hook (symbolP);
1685 verify_symbol_chain (symbol_rootP, symbol_lastP);
1686 #endif /* DEBUG_SYMS */
1691 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1698 for (align = 2; align <= 4; align++)
1700 int size = 1 << align;
1702 pool = find_literal_pool (size);
1703 if (pool == NULL || pool->symbol == NULL || pool->next_free_entry == 0)
1706 mapping_state (MAP_DATA);
1708 /* Align pool as you have word accesses.
1709 Only make a frag if we have to. */
1711 frag_align (align, 0, 0);
1713 record_alignment (now_seg, align);
1715 sprintf (sym_name, "$$lit_\002%x", pool->id);
1717 symbol_locate (pool->symbol, sym_name, now_seg,
1718 (valueT) frag_now_fix (), frag_now);
1719 symbol_table_insert (pool->symbol);
1721 for (entry = 0; entry < pool->next_free_entry; entry++)
1722 /* First output the expression in the instruction to the pool. */
1723 emit_expr (&(pool->literals[entry]), size); /* .word|.xword */
1725 /* Mark the pool as empty. */
1726 pool->next_free_entry = 0;
1727 pool->symbol = NULL;
1732 /* Forward declarations for functions below, in the MD interface
1734 static fixS *fix_new_aarch64 (fragS *, int, short, expressionS *, int, int);
1735 static struct reloc_table_entry * find_reloc_table_entry (char **);
1737 /* Directives: Data. */
1738 /* N.B. the support for relocation suffix in this directive needs to be
1739 implemented properly. */
1742 s_aarch64_elf_cons (int nbytes)
1746 #ifdef md_flush_pending_output
1747 md_flush_pending_output ();
1750 if (is_it_end_of_statement ())
1752 demand_empty_rest_of_line ();
1756 #ifdef md_cons_align
1757 md_cons_align (nbytes);
1760 mapping_state (MAP_DATA);
1763 struct reloc_table_entry *reloc;
1767 if (exp.X_op != O_symbol)
1768 emit_expr (&exp, (unsigned int) nbytes);
1771 skip_past_char (&input_line_pointer, '#');
1772 if (skip_past_char (&input_line_pointer, ':'))
1774 reloc = find_reloc_table_entry (&input_line_pointer);
1776 as_bad (_("unrecognized relocation suffix"));
1778 as_bad (_("unimplemented relocation suffix"));
1779 ignore_rest_of_line ();
1783 emit_expr (&exp, (unsigned int) nbytes);
1786 while (*input_line_pointer++ == ',');
1788 /* Put terminator back into stream. */
1789 input_line_pointer--;
1790 demand_empty_rest_of_line ();
1793 #endif /* OBJ_ELF */
1795 /* Output a 32-bit word, but mark as an instruction. */
1798 s_aarch64_inst (int ignored ATTRIBUTE_UNUSED)
1802 #ifdef md_flush_pending_output
1803 md_flush_pending_output ();
1806 if (is_it_end_of_statement ())
1808 demand_empty_rest_of_line ();
1813 frag_align_code (2, 0);
1815 mapping_state (MAP_INSN);
1821 if (exp.X_op != O_constant)
1823 as_bad (_("constant expression required"));
1824 ignore_rest_of_line ();
1828 if (target_big_endian)
1830 unsigned int val = exp.X_add_number;
1831 exp.X_add_number = SWAP_32 (val);
1833 emit_expr (&exp, 4);
1835 while (*input_line_pointer++ == ',');
1837 /* Put terminator back into stream. */
1838 input_line_pointer--;
1839 demand_empty_rest_of_line ();
1843 /* Emit BFD_RELOC_AARCH64_TLSDESC_CALL on the next BLR instruction. */
1846 s_tlsdesccall (int ignored ATTRIBUTE_UNUSED)
1850 /* Since we're just labelling the code, there's no need to define a
1853 /* Make sure there is enough room in this frag for the following
1854 blr. This trick only works if the blr follows immediately after
1855 the .tlsdesc directive. */
1857 fix_new_aarch64 (frag_now, frag_more (0) - frag_now->fr_literal, 4, &exp, 0,
1858 BFD_RELOC_AARCH64_TLSDESC_CALL);
1860 demand_empty_rest_of_line ();
1862 #endif /* OBJ_ELF */
1864 static void s_aarch64_arch (int);
1865 static void s_aarch64_cpu (int);
1867 /* This table describes all the machine specific pseudo-ops the assembler
1868 has to support. The fields are:
1869 pseudo-op name without dot
1870 function to call to execute this pseudo-op
1871 Integer arg to pass to the function. */
1873 const pseudo_typeS md_pseudo_table[] = {
1874 /* Never called because '.req' does not start a line. */
1876 {"unreq", s_unreq, 0},
1878 {"even", s_even, 0},
1879 {"ltorg", s_ltorg, 0},
1880 {"pool", s_ltorg, 0},
1881 {"cpu", s_aarch64_cpu, 0},
1882 {"arch", s_aarch64_arch, 0},
1883 {"inst", s_aarch64_inst, 0},
1885 {"tlsdesccall", s_tlsdesccall, 0},
1886 {"word", s_aarch64_elf_cons, 4},
1887 {"long", s_aarch64_elf_cons, 4},
1888 {"xword", s_aarch64_elf_cons, 8},
1889 {"dword", s_aarch64_elf_cons, 8},
1895 /* Check whether STR points to a register name followed by a comma or the
1896 end of line; REG_TYPE indicates which register types are checked
1897 against. Return TRUE if STR is such a register name; otherwise return
1898 FALSE. The function does not intend to produce any diagnostics, but since
1899 the register parser aarch64_reg_parse, which is called by this function,
1900 does produce diagnostics, we call clear_error to clear any diagnostics
1901 that may be generated by aarch64_reg_parse.
1902 Also, the function returns FALSE directly if there is any user error
1903 present at the function entry. This prevents the existing diagnostics
1904 state from being spoiled.
1905 The function currently serves parse_constant_immediate and
1906 parse_big_immediate only. */
1908 reg_name_p (char *str, aarch64_reg_type reg_type)
1912 /* Prevent the diagnostics state from being spoiled. */
1916 reg = aarch64_reg_parse (&str, reg_type, NULL, NULL);
1918 /* Clear the parsing error that may be set by the reg parser. */
1921 if (reg == PARSE_FAIL)
1924 skip_whitespace (str);
1925 if (*str == ',' || is_end_of_line[(unsigned int) *str])
1931 /* Parser functions used exclusively in instruction operands. */
1933 /* Parse an immediate expression which may not be constant.
1935 To prevent the expression parser from pushing a register name
1936 into the symbol table as an undefined symbol, firstly a check is
1937 done to find out whether STR is a valid register name followed
1938 by a comma or the end of line. Return FALSE if STR is such a
1942 parse_immediate_expression (char **str, expressionS *exp)
1944 if (reg_name_p (*str, REG_TYPE_R_Z_BHSDQ_V))
1946 set_recoverable_error (_("immediate operand required"));
1950 my_get_expression (exp, str, GE_OPT_PREFIX, 1);
1952 if (exp->X_op == O_absent)
1954 set_fatal_syntax_error (_("missing immediate expression"));
1961 /* Constant immediate-value read function for use in insn parsing.
1962 STR points to the beginning of the immediate (with the optional
1963 leading #); *VAL receives the value.
1965 Return TRUE on success; otherwise return FALSE. */
1968 parse_constant_immediate (char **str, int64_t * val)
1972 if (! parse_immediate_expression (str, &exp))
1975 if (exp.X_op != O_constant)
1977 set_syntax_error (_("constant expression required"));
1981 *val = exp.X_add_number;
1986 encode_imm_float_bits (uint32_t imm)
1988 return ((imm >> 19) & 0x7f) /* b[25:19] -> b[6:0] */
1989 | ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
1992 /* Return TRUE if the single-precision floating-point value encoded in IMM
1993 can be expressed in the AArch64 8-bit signed floating-point format with
1994 3-bit exponent and normalized 4 bits of precision; in other words, the
1995 floating-point value must be expressable as
1996 (+/-) n / 16 * power (2, r)
1997 where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
2000 aarch64_imm_float_p (uint32_t imm)
2002 /* If a single-precision floating-point value has the following bit
2003 pattern, it can be expressed in the AArch64 8-bit floating-point
2006 3 32222222 2221111111111
2007 1 09876543 21098765432109876543210
2008 n Eeeeeexx xxxx0000000000000000000
2010 where n, e and each x are either 0 or 1 independently, with
2015 /* Prepare the pattern for 'Eeeeee'. */
2016 if (((imm >> 30) & 0x1) == 0)
2017 pattern = 0x3e000000;
2019 pattern = 0x40000000;
2021 return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
2022 && ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
2025 /* Like aarch64_imm_float_p but for a double-precision floating-point value.
2027 Return TRUE if the value encoded in IMM can be expressed in the AArch64
2028 8-bit signed floating-point format with 3-bit exponent and normalized 4
2029 bits of precision (i.e. can be used in an FMOV instruction); return the
2030 equivalent single-precision encoding in *FPWORD.
2032 Otherwise return FALSE. */
2035 aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
2037 /* If a double-precision floating-point value has the following bit
2038 pattern, it can be expressed in the AArch64 8-bit floating-point
2041 6 66655555555 554444444...21111111111
2042 3 21098765432 109876543...098765432109876543210
2043 n Eeeeeeeeexx xxxx00000...000000000000000000000
2045 where n, e and each x are either 0 or 1 independently, with
2049 uint32_t high32 = imm >> 32;
2051 /* Lower 32 bits need to be 0s. */
2052 if ((imm & 0xffffffff) != 0)
2055 /* Prepare the pattern for 'Eeeeeeeee'. */
2056 if (((high32 >> 30) & 0x1) == 0)
2057 pattern = 0x3fc00000;
2059 pattern = 0x40000000;
2061 if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
2062 && (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
2064 /* Convert to the single-precision encoding.
2066 n Eeeeeeeeexx xxxx00000...000000000000000000000
2068 n Eeeeeexx xxxx0000000000000000000. */
2069 *fpword = ((high32 & 0xfe000000) /* nEeeeee. */
2070 | (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
2077 /* Parse a floating-point immediate. Return TRUE on success and return the
2078 value in *IMMED in the format of IEEE754 single-precision encoding.
2079 *CCP points to the start of the string; DP_P is TRUE when the immediate
2080 is expected to be in double-precision (N.B. this only matters when
2081 hexadecimal representation is involved).
2083 N.B. 0.0 is accepted by this function. */
2086 parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
2090 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2091 int found_fpchar = 0;
2093 unsigned fpword = 0;
2094 bfd_boolean hex_p = FALSE;
2096 skip_past_char (&str, '#');
2099 skip_whitespace (fpnum);
2101 if (strncmp (fpnum, "0x", 2) == 0)
2103 /* Support the hexadecimal representation of the IEEE754 encoding.
2104 Double-precision is expected when DP_P is TRUE, otherwise the
2105 representation should be in single-precision. */
2106 if (! parse_constant_immediate (&str, &val))
2111 if (! aarch64_double_precision_fmovable (val, &fpword))
2114 else if ((uint64_t) val > 0xffffffff)
2123 /* We must not accidentally parse an integer as a floating-point number.
2124 Make sure that the value we parse is not an integer by checking for
2125 special characters '.' or 'e'. */
2126 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
2127 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
2141 if ((str = atof_ieee (str, 's', words)) == NULL)
2144 /* Our FP word must be 32 bits (single-precision FP). */
2145 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
2147 fpword <<= LITTLENUM_NUMBER_OF_BITS;
2152 if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
2160 set_fatal_syntax_error (_("invalid floating-point constant"));
2164 /* Less-generic immediate-value read function with the possibility of loading
2165 a big (64-bit) immediate, as required by AdvSIMD Modified immediate
2168 To prevent the expression parser from pushing a register name into the
2169 symbol table as an undefined symbol, a check is firstly done to find
2170 out whether STR is a valid register name followed by a comma or the end
2171 of line. Return FALSE if STR is such a register. */
2174 parse_big_immediate (char **str, int64_t *imm)
2178 if (reg_name_p (ptr, REG_TYPE_R_Z_BHSDQ_V))
2180 set_syntax_error (_("immediate operand required"));
2184 my_get_expression (&inst.reloc.exp, &ptr, GE_OPT_PREFIX, 1);
2186 if (inst.reloc.exp.X_op == O_constant)
2187 *imm = inst.reloc.exp.X_add_number;
2194 /* Set operand IDX of the *INSTR that needs a GAS internal fixup.
2195 if NEED_LIBOPCODES is non-zero, the fixup will need
2196 assistance from the libopcodes. */
2199 aarch64_set_gas_internal_fixup (struct reloc *reloc,
2200 const aarch64_opnd_info *operand,
2201 int need_libopcodes_p)
2203 reloc->type = BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2204 reloc->opnd = operand->type;
2205 if (need_libopcodes_p)
2206 reloc->need_libopcodes_p = 1;
2209 /* Return TRUE if the instruction needs to be fixed up later internally by
2210 the GAS; otherwise return FALSE. */
2212 static inline bfd_boolean
2213 aarch64_gas_internal_fixup_p (void)
2215 return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
2218 /* Assign the immediate value to the relavant field in *OPERAND if
2219 RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
2220 needs an internal fixup in a later stage.
2221 ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
2222 IMM.VALUE that may get assigned with the constant. */
2224 assign_imm_if_const_or_fixup_later (struct reloc *reloc,
2225 aarch64_opnd_info *operand,
2227 int need_libopcodes_p,
2230 if (reloc->exp.X_op == O_constant)
2233 operand->addr.offset.imm = reloc->exp.X_add_number;
2235 operand->imm.value = reloc->exp.X_add_number;
2236 reloc->type = BFD_RELOC_UNUSED;
2240 aarch64_set_gas_internal_fixup (reloc, operand, need_libopcodes_p);
2241 /* Tell libopcodes to ignore this operand or not. This is helpful
2242 when one of the operands needs to be fixed up later but we need
2243 libopcodes to check the other operands. */
2244 operand->skip = skip_p;
2248 /* Relocation modifiers. Each entry in the table contains the textual
2249 name for the relocation which may be placed before a symbol used as
2250 a load/store offset, or add immediate. It must be surrounded by a
2251 leading and trailing colon, for example:
2253 ldr x0, [x1, #:rello:varsym]
2254 add x0, x1, #:rello:varsym */
2256 struct reloc_table_entry
2260 bfd_reloc_code_real_type adrp_type;
2261 bfd_reloc_code_real_type movw_type;
2262 bfd_reloc_code_real_type add_type;
2263 bfd_reloc_code_real_type ldst_type;
2266 static struct reloc_table_entry reloc_table[] = {
2267 /* Low 12 bits of absolute address: ADD/i and LDR/STR */
2271 BFD_RELOC_AARCH64_ADD_LO12,
2272 BFD_RELOC_AARCH64_LDST_LO12},
2274 /* Higher 21 bits of pc-relative page offset: ADRP */
2276 BFD_RELOC_AARCH64_ADR_HI21_PCREL,
2281 /* Higher 21 bits of pc-relative page offset: ADRP, no check */
2283 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
2288 /* Most significant bits 0-15 of unsigned address/value: MOVZ */
2291 BFD_RELOC_AARCH64_MOVW_G0,
2295 /* Most significant bits 0-15 of signed address/value: MOVN/Z */
2298 BFD_RELOC_AARCH64_MOVW_G0_S,
2302 /* Less significant bits 0-15 of address/value: MOVK, no check */
2305 BFD_RELOC_AARCH64_MOVW_G0_NC,
2309 /* Most significant bits 16-31 of unsigned address/value: MOVZ */
2312 BFD_RELOC_AARCH64_MOVW_G1,
2316 /* Most significant bits 16-31 of signed address/value: MOVN/Z */
2319 BFD_RELOC_AARCH64_MOVW_G1_S,
2323 /* Less significant bits 16-31 of address/value: MOVK, no check */
2326 BFD_RELOC_AARCH64_MOVW_G1_NC,
2330 /* Most significant bits 32-47 of unsigned address/value: MOVZ */
2333 BFD_RELOC_AARCH64_MOVW_G2,
2337 /* Most significant bits 32-47 of signed address/value: MOVN/Z */
2340 BFD_RELOC_AARCH64_MOVW_G2_S,
2344 /* Less significant bits 32-47 of address/value: MOVK, no check */
2347 BFD_RELOC_AARCH64_MOVW_G2_NC,
2351 /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
2354 BFD_RELOC_AARCH64_MOVW_G3,
2357 /* Get to the page containing GOT entry for a symbol. */
2359 BFD_RELOC_AARCH64_ADR_GOT_PAGE,
2363 /* 12 bit offset into the page containing GOT entry for that symbol. */
2368 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC},
2370 /* Get to the page containing GOT TLS entry for a symbol */
2372 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
2377 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2381 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
2384 /* Get to the page containing GOT TLS entry for a symbol */
2386 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
2391 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2395 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
2396 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC},
2398 /* Get to the page containing GOT TLS entry for a symbol */
2400 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
2405 /* 12 bit offset into the page containing GOT TLS entry for a symbol */
2406 {"gottprel_lo12", 0,
2410 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC},
2412 /* Get tp offset for a symbol. */
2416 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2419 /* Get tp offset for a symbol. */
2423 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
2426 /* Get tp offset for a symbol. */
2430 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
2433 /* Get tp offset for a symbol. */
2434 {"tprel_lo12_nc", 0,
2437 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
2440 /* Most significant bits 32-47 of address/value: MOVZ. */
2443 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
2447 /* Most significant bits 16-31 of address/value: MOVZ. */
2450 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
2454 /* Most significant bits 16-31 of address/value: MOVZ, no check. */
2457 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
2461 /* Most significant bits 0-15 of address/value: MOVZ. */
2464 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
2468 /* Most significant bits 0-15 of address/value: MOVZ, no check. */
2471 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
2476 /* Given the address of a pointer pointing to the textual name of a
2477 relocation as may appear in assembler source, attempt to find its
2478 details in reloc_table. The pointer will be updated to the character
2479 after the trailing colon. On failure, NULL will be returned;
2480 otherwise return the reloc_table_entry. */
2482 static struct reloc_table_entry *
2483 find_reloc_table_entry (char **str)
2486 for (i = 0; i < ARRAY_SIZE (reloc_table); i++)
2488 int length = strlen (reloc_table[i].name);
2490 if (strncasecmp (reloc_table[i].name, *str, length) == 0
2491 && (*str)[length] == ':')
2493 *str += (length + 1);
2494 return &reloc_table[i];
2501 /* Mode argument to parse_shift and parser_shifter_operand. */
2502 enum parse_shift_mode
2504 SHIFTED_ARITH_IMM, /* "rn{,lsl|lsr|asl|asr|uxt|sxt #n}" or
2506 SHIFTED_LOGIC_IMM, /* "rn{,lsl|lsr|asl|asr|ror #n}" or
2508 SHIFTED_LSL, /* bare "lsl #n" */
2509 SHIFTED_LSL_MSL, /* "lsl|msl #n" */
2510 SHIFTED_REG_OFFSET /* [su]xtw|sxtx {#n} or lsl #n */
2513 /* Parse a <shift> operator on an AArch64 data processing instruction.
2514 Return TRUE on success; otherwise return FALSE. */
2516 parse_shift (char **str, aarch64_opnd_info *operand, enum parse_shift_mode mode)
2518 const struct aarch64_name_value_pair *shift_op;
2519 enum aarch64_modifier_kind kind;
2525 for (p = *str; ISALPHA (*p); p++)
2530 set_syntax_error (_("shift expression expected"));
2534 shift_op = hash_find_n (aarch64_shift_hsh, *str, p - *str);
2536 if (shift_op == NULL)
2538 set_syntax_error (_("shift operator expected"));
2542 kind = aarch64_get_operand_modifier (shift_op);
2544 if (kind == AARCH64_MOD_MSL && mode != SHIFTED_LSL_MSL)
2546 set_syntax_error (_("invalid use of 'MSL'"));
2552 case SHIFTED_LOGIC_IMM:
2553 if (aarch64_extend_operator_p (kind) == TRUE)
2555 set_syntax_error (_("extending shift is not permitted"));
2560 case SHIFTED_ARITH_IMM:
2561 if (kind == AARCH64_MOD_ROR)
2563 set_syntax_error (_("'ROR' shift is not permitted"));
2569 if (kind != AARCH64_MOD_LSL)
2571 set_syntax_error (_("only 'LSL' shift is permitted"));
2576 case SHIFTED_REG_OFFSET:
2577 if (kind != AARCH64_MOD_UXTW && kind != AARCH64_MOD_LSL
2578 && kind != AARCH64_MOD_SXTW && kind != AARCH64_MOD_SXTX)
2580 set_fatal_syntax_error
2581 (_("invalid shift for the register offset addressing mode"));
2586 case SHIFTED_LSL_MSL:
2587 if (kind != AARCH64_MOD_LSL && kind != AARCH64_MOD_MSL)
2589 set_syntax_error (_("invalid shift operator"));
2598 /* Whitespace can appear here if the next thing is a bare digit. */
2599 skip_whitespace (p);
2601 /* Parse shift amount. */
2603 if (mode == SHIFTED_REG_OFFSET && *p == ']')
2604 exp.X_op = O_absent;
2607 if (is_immediate_prefix (*p))
2612 my_get_expression (&exp, &p, GE_NO_PREFIX, 0);
2614 if (exp.X_op == O_absent)
2616 if (aarch64_extend_operator_p (kind) == FALSE || exp_has_prefix)
2618 set_syntax_error (_("missing shift amount"));
2621 operand->shifter.amount = 0;
2623 else if (exp.X_op != O_constant)
2625 set_syntax_error (_("constant shift amount required"));
2628 else if (exp.X_add_number < 0 || exp.X_add_number > 63)
2630 set_fatal_syntax_error (_("shift amount out of range 0 to 63"));
2635 operand->shifter.amount = exp.X_add_number;
2636 operand->shifter.amount_present = 1;
2639 operand->shifter.operator_present = 1;
2640 operand->shifter.kind = kind;
2646 /* Parse a <shifter_operand> for a data processing instruction:
2649 #<immediate>, LSL #imm
2651 Validation of immediate operands is deferred to md_apply_fix.
2653 Return TRUE on success; otherwise return FALSE. */
2656 parse_shifter_operand_imm (char **str, aarch64_opnd_info *operand,
2657 enum parse_shift_mode mode)
2661 if (mode != SHIFTED_ARITH_IMM && mode != SHIFTED_LOGIC_IMM)
2666 /* Accept an immediate expression. */
2667 if (! my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX, 1))
2670 /* Accept optional LSL for arithmetic immediate values. */
2671 if (mode == SHIFTED_ARITH_IMM && skip_past_comma (&p))
2672 if (! parse_shift (&p, operand, SHIFTED_LSL))
2675 /* Not accept any shifter for logical immediate values. */
2676 if (mode == SHIFTED_LOGIC_IMM && skip_past_comma (&p)
2677 && parse_shift (&p, operand, mode))
2679 set_syntax_error (_("unexpected shift operator"));
2687 /* Parse a <shifter_operand> for a data processing instruction:
2692 #<immediate>, LSL #imm
2694 where <shift> is handled by parse_shift above, and the last two
2695 cases are handled by the function above.
2697 Validation of immediate operands is deferred to md_apply_fix.
2699 Return TRUE on success; otherwise return FALSE. */
2702 parse_shifter_operand (char **str, aarch64_opnd_info *operand,
2703 enum parse_shift_mode mode)
2706 int isreg32, isregzero;
2707 enum aarch64_operand_class opd_class
2708 = aarch64_get_operand_class (operand->type);
2711 aarch64_reg_parse_32_64 (str, 0, 0, &isreg32, &isregzero)) != PARSE_FAIL)
2713 if (opd_class == AARCH64_OPND_CLASS_IMMEDIATE)
2715 set_syntax_error (_("unexpected register in the immediate operand"));
2719 if (!isregzero && reg == REG_SP)
2721 set_syntax_error (BAD_SP);
2725 operand->reg.regno = reg;
2726 operand->qualifier = isreg32 ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
2728 /* Accept optional shift operation on register. */
2729 if (! skip_past_comma (str))
2732 if (! parse_shift (str, operand, mode))
2737 else if (opd_class == AARCH64_OPND_CLASS_MODIFIED_REG)
2740 (_("integer register expected in the extended/shifted operand "
2745 /* We have a shifted immediate variable. */
2746 return parse_shifter_operand_imm (str, operand, mode);
2749 /* Return TRUE on success; return FALSE otherwise. */
2752 parse_shifter_operand_reloc (char **str, aarch64_opnd_info *operand,
2753 enum parse_shift_mode mode)
2757 /* Determine if we have the sequence of characters #: or just :
2758 coming next. If we do, then we check for a :rello: relocation
2759 modifier. If we don't, punt the whole lot to
2760 parse_shifter_operand. */
2762 if ((p[0] == '#' && p[1] == ':') || p[0] == ':')
2764 struct reloc_table_entry *entry;
2772 /* Try to parse a relocation. Anything else is an error. */
2773 if (!(entry = find_reloc_table_entry (str)))
2775 set_syntax_error (_("unknown relocation modifier"));
2779 if (entry->add_type == 0)
2782 (_("this relocation modifier is not allowed on this instruction"));
2786 /* Save str before we decompose it. */
2789 /* Next, we parse the expression. */
2790 if (! my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX, 1))
2793 /* Record the relocation type (use the ADD variant here). */
2794 inst.reloc.type = entry->add_type;
2795 inst.reloc.pc_rel = entry->pc_rel;
2797 /* If str is empty, we've reached the end, stop here. */
2801 /* Otherwise, we have a shifted reloc modifier, so rewind to
2802 recover the variable name and continue parsing for the shifter. */
2804 return parse_shifter_operand_imm (str, operand, mode);
2807 return parse_shifter_operand (str, operand, mode);
2810 /* Parse all forms of an address expression. Information is written
2811 to *OPERAND and/or inst.reloc.
2813 The A64 instruction set has the following addressing modes:
2816 [base] // in SIMD ld/st structure
2817 [base{,#0}] // in ld/st exclusive
2819 [base,Xm{,LSL #imm}]
2820 [base,Xm,SXTX {#imm}]
2821 [base,Wm,(S|U)XTW {#imm}]
2826 [base],Xm // in SIMD ld/st structure
2827 PC-relative (literal)
2831 (As a convenience, the notation "=immediate" is permitted in conjunction
2832 with the pc-relative literal load instructions to automatically place an
2833 immediate value or symbolic address in a nearby literal pool and generate
2834 a hidden label which references it.)
2836 Upon a successful parsing, the address structure in *OPERAND will be
2837 filled in the following way:
2839 .base_regno = <base>
2840 .offset.is_reg // 1 if the offset is a register
2842 .offset.regno = <Rm>
2844 For different addressing modes defined in the A64 ISA:
2847 .pcrel=0; .preind=1; .postind=0; .writeback=0
2849 .pcrel=0; .preind=1; .postind=0; .writeback=1
2851 .pcrel=0; .preind=0; .postind=1; .writeback=1
2852 PC-relative (literal)
2853 .pcrel=1; .preind=1; .postind=0; .writeback=0
2855 The shift/extension information, if any, will be stored in .shifter.
2857 It is the caller's responsibility to check for addressing modes not
2858 supported by the instruction, and to set inst.reloc.type. */
2861 parse_address_main (char **str, aarch64_opnd_info *operand, int reloc,
2862 int accept_reg_post_index)
2866 int isreg32, isregzero;
2867 expressionS *exp = &inst.reloc.exp;
2869 if (! skip_past_char (&p, '['))
2871 /* =immediate or label. */
2872 operand->addr.pcrel = 1;
2873 operand->addr.preind = 1;
2875 if (skip_past_char (&p, '='))
2876 /* =immediate; need to generate the literal in the liternal pool. */
2877 inst.gen_lit_pool = 1;
2879 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2881 set_syntax_error (_("invalid address"));
2891 /* Accept SP and reject ZR */
2892 reg = aarch64_reg_parse_32_64 (&p, 0, 1, &isreg32, &isregzero);
2893 if (reg == PARSE_FAIL || isreg32)
2895 set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
2898 operand->addr.base_regno = reg;
2901 if (skip_past_comma (&p))
2904 operand->addr.preind = 1;
2906 /* Reject SP and accept ZR */
2907 reg = aarch64_reg_parse_32_64 (&p, 1, 0, &isreg32, &isregzero);
2908 if (reg != PARSE_FAIL)
2911 operand->addr.offset.regno = reg;
2912 operand->addr.offset.is_reg = 1;
2913 /* Shifted index. */
2914 if (skip_past_comma (&p))
2917 if (! parse_shift (&p, operand, SHIFTED_REG_OFFSET))
2918 /* Use the diagnostics set in parse_shift, so not set new
2919 error message here. */
2923 [base,Xm{,LSL #imm}]
2924 [base,Xm,SXTX {#imm}]
2925 [base,Wm,(S|U)XTW {#imm}] */
2926 if (operand->shifter.kind == AARCH64_MOD_NONE
2927 || operand->shifter.kind == AARCH64_MOD_LSL
2928 || operand->shifter.kind == AARCH64_MOD_SXTX)
2932 set_syntax_error (_("invalid use of 32-bit register offset"));
2938 set_syntax_error (_("invalid use of 64-bit register offset"));
2944 /* [Xn,#:<reloc_op>:<symbol> */
2945 skip_past_char (&p, '#');
2946 if (reloc && skip_past_char (&p, ':'))
2948 struct reloc_table_entry *entry;
2950 /* Try to parse a relocation modifier. Anything else is
2952 if (!(entry = find_reloc_table_entry (&p)))
2954 set_syntax_error (_("unknown relocation modifier"));
2958 if (entry->ldst_type == 0)
2961 (_("this relocation modifier is not allowed on this "
2966 /* [Xn,#:<reloc_op>: */
2967 /* We now have the group relocation table entry corresponding to
2968 the name in the assembler source. Next, we parse the
2970 if (! my_get_expression (exp, &p, GE_NO_PREFIX, 1))
2972 set_syntax_error (_("invalid relocation expression"));
2976 /* [Xn,#:<reloc_op>:<expr> */
2977 /* Record the load/store relocation type. */
2978 inst.reloc.type = entry->ldst_type;
2979 inst.reloc.pc_rel = entry->pc_rel;
2981 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
2983 set_syntax_error (_("invalid expression in the address"));
2990 if (! skip_past_char (&p, ']'))
2992 set_syntax_error (_("']' expected"));
2996 if (skip_past_char (&p, '!'))
2998 if (operand->addr.preind && operand->addr.offset.is_reg)
3000 set_syntax_error (_("register offset not allowed in pre-indexed "
3001 "addressing mode"));
3005 operand->addr.writeback = 1;
3007 else if (skip_past_comma (&p))
3010 operand->addr.postind = 1;
3011 operand->addr.writeback = 1;
3013 if (operand->addr.preind)
3015 set_syntax_error (_("cannot combine pre- and post-indexing"));
3019 if (accept_reg_post_index
3020 && (reg = aarch64_reg_parse_32_64 (&p, 1, 1, &isreg32,
3021 &isregzero)) != PARSE_FAIL)
3026 set_syntax_error (_("invalid 32-bit register offset"));
3029 operand->addr.offset.regno = reg;
3030 operand->addr.offset.is_reg = 1;
3032 else if (! my_get_expression (exp, &p, GE_OPT_PREFIX, 1))
3035 set_syntax_error (_("invalid expression in the address"));
3040 /* If at this point neither .preind nor .postind is set, we have a
3041 bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
3042 if (operand->addr.preind == 0 && operand->addr.postind == 0)
3044 if (operand->addr.writeback)
3047 set_syntax_error (_("missing offset in the pre-indexed address"));
3050 operand->addr.preind = 1;
3051 inst.reloc.exp.X_op = O_constant;
3052 inst.reloc.exp.X_add_number = 0;
3059 /* Return TRUE on success; otherwise return FALSE. */
3061 parse_address (char **str, aarch64_opnd_info *operand,
3062 int accept_reg_post_index)
3064 return parse_address_main (str, operand, 0, accept_reg_post_index);
3067 /* Return TRUE on success; otherwise return FALSE. */
3069 parse_address_reloc (char **str, aarch64_opnd_info *operand)
3071 return parse_address_main (str, operand, 1, 0);
3074 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
3075 Return TRUE on success; otherwise return FALSE. */
3077 parse_half (char **str, int *internal_fixup_p)
3083 skip_past_char (&p, '#');
3085 gas_assert (internal_fixup_p);
3086 *internal_fixup_p = 0;
3090 struct reloc_table_entry *entry;
3092 /* Try to parse a relocation. Anything else is an error. */
3094 if (!(entry = find_reloc_table_entry (&p)))
3096 set_syntax_error (_("unknown relocation modifier"));
3100 if (entry->movw_type == 0)
3103 (_("this relocation modifier is not allowed on this instruction"));
3107 inst.reloc.type = entry->movw_type;
3110 *internal_fixup_p = 1;
3112 /* Avoid parsing a register as a general symbol. */
3114 if (aarch64_reg_parse_32_64 (&p, 0, 0, &dummy, &dummy) != PARSE_FAIL)
3118 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3125 /* Parse an operand for an ADRP instruction:
3127 Return TRUE on success; otherwise return FALSE. */
3130 parse_adrp (char **str)
3137 struct reloc_table_entry *entry;
3139 /* Try to parse a relocation. Anything else is an error. */
3141 if (!(entry = find_reloc_table_entry (&p)))
3143 set_syntax_error (_("unknown relocation modifier"));
3147 if (entry->adrp_type == 0)
3150 (_("this relocation modifier is not allowed on this instruction"));
3154 inst.reloc.type = entry->adrp_type;
3157 inst.reloc.type = BFD_RELOC_AARCH64_ADR_HI21_PCREL;
3159 inst.reloc.pc_rel = 1;
3161 if (! my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX, 1))
3168 /* Miscellaneous. */
3170 /* Parse an option for a preload instruction. Returns the encoding for the
3171 option, or PARSE_FAIL. */
3174 parse_pldop (char **str)
3177 const struct aarch64_name_value_pair *o;
3180 while (ISALNUM (*q))
3183 o = hash_find_n (aarch64_pldop_hsh, p, q - p);
3191 /* Parse an option for a barrier instruction. Returns the encoding for the
3192 option, or PARSE_FAIL. */
3195 parse_barrier (char **str)
3198 const asm_barrier_opt *o;
3201 while (ISALPHA (*q))
3204 o = hash_find_n (aarch64_barrier_opt_hsh, p, q - p);
3212 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
3213 Returns the encoding for the option, or PARSE_FAIL.
3215 If IMPLE_DEFINED_P is non-zero, the function will also try to parse the
3216 implementation defined system register name S3_<op1>_<Cn>_<Cm>_<op2>. */
3219 parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
3223 const struct aarch64_name_value_pair *o;
3227 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3229 *p++ = TOLOWER (*q);
3231 /* Assert that BUF be large enough. */
3232 gas_assert (p - buf == q - *str);
3234 o = hash_find (sys_regs, buf);
3237 if (!imple_defined_p)
3241 /* Parse S3_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
3243 unsigned int op0, op1, cn, cm, op2;
3244 if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
3246 /* Register access is encoded as follows:
3248 11 xxx 1x11 xxxx xxx. */
3249 if (op0 != 3 || op1 > 7 || (cn | 0x4) != 0xf || cm > 15 || op2 > 7)
3251 value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
3261 /* Parse a system reg for ic/dc/at/tlbi instructions. Returns the table entry
3262 for the option, or NULL. */
3264 static const aarch64_sys_ins_reg *
3265 parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
3269 const aarch64_sys_ins_reg *o;
3272 for (q = *str; ISALNUM (*q) || *q == '_'; q++)
3274 *p++ = TOLOWER (*q);
3277 o = hash_find (sys_ins_regs, buf);
3285 #define po_char_or_fail(chr) do { \
3286 if (! skip_past_char (&str, chr)) \
3290 #define po_reg_or_fail(regtype) do { \
3291 val = aarch64_reg_parse (&str, regtype, &rtype, NULL); \
3292 if (val == PARSE_FAIL) \
3294 set_default_error (); \
3299 #define po_int_reg_or_fail(reject_sp, reject_rz) do { \
3300 val = aarch64_reg_parse_32_64 (&str, reject_sp, reject_rz, \
3301 &isreg32, &isregzero); \
3302 if (val == PARSE_FAIL) \
3304 set_default_error (); \
3307 info->reg.regno = val; \
3309 info->qualifier = AARCH64_OPND_QLF_W; \
3311 info->qualifier = AARCH64_OPND_QLF_X; \
3314 #define po_imm_nc_or_fail() do { \
3315 if (! parse_constant_immediate (&str, &val)) \
3319 #define po_imm_or_fail(min, max) do { \
3320 if (! parse_constant_immediate (&str, &val)) \
3322 if (val < min || val > max) \
3324 set_fatal_syntax_error (_("immediate value out of range "\
3325 #min " to "#max)); \
3330 #define po_misc_or_fail(expr) do { \
3335 /* encode the 12-bit imm field of Add/sub immediate */
3336 static inline uint32_t
3337 encode_addsub_imm (uint32_t imm)
3342 /* encode the shift amount field of Add/sub immediate */
3343 static inline uint32_t
3344 encode_addsub_imm_shift_amount (uint32_t cnt)
3350 /* encode the imm field of Adr instruction */
3351 static inline uint32_t
3352 encode_adr_imm (uint32_t imm)
3354 return (((imm & 0x3) << 29) /* [1:0] -> [30:29] */
3355 | ((imm & (0x7ffff << 2)) << 3)); /* [20:2] -> [23:5] */
3358 /* encode the immediate field of Move wide immediate */
3359 static inline uint32_t
3360 encode_movw_imm (uint32_t imm)
3365 /* encode the 26-bit offset of unconditional branch */
3366 static inline uint32_t
3367 encode_branch_ofs_26 (uint32_t ofs)
3369 return ofs & ((1 << 26) - 1);
3372 /* encode the 19-bit offset of conditional branch and compare & branch */
3373 static inline uint32_t
3374 encode_cond_branch_ofs_19 (uint32_t ofs)
3376 return (ofs & ((1 << 19) - 1)) << 5;
3379 /* encode the 19-bit offset of ld literal */
3380 static inline uint32_t
3381 encode_ld_lit_ofs_19 (uint32_t ofs)
3383 return (ofs & ((1 << 19) - 1)) << 5;
3386 /* Encode the 14-bit offset of test & branch. */
3387 static inline uint32_t
3388 encode_tst_branch_ofs_14 (uint32_t ofs)
3390 return (ofs & ((1 << 14) - 1)) << 5;
3393 /* Encode the 16-bit imm field of svc/hvc/smc. */
3394 static inline uint32_t
3395 encode_svc_imm (uint32_t imm)
3400 /* Reencode add(s) to sub(s), or sub(s) to add(s). */
3401 static inline uint32_t
3402 reencode_addsub_switch_add_sub (uint32_t opcode)
3404 return opcode ^ (1 << 30);
3407 static inline uint32_t
3408 reencode_movzn_to_movz (uint32_t opcode)
3410 return opcode | (1 << 30);
3413 static inline uint32_t
3414 reencode_movzn_to_movn (uint32_t opcode)
3416 return opcode & ~(1 << 30);
3419 /* Overall per-instruction processing. */
3421 /* We need to be able to fix up arbitrary expressions in some statements.
3422 This is so that we can handle symbols that are an arbitrary distance from
3423 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
3424 which returns part of an address in a form which will be valid for
3425 a data instruction. We do this by pushing the expression into a symbol
3426 in the expr_section, and creating a fix for that. */
3429 fix_new_aarch64 (fragS * frag,
3431 short int size, expressionS * exp, int pc_rel, int reloc)
3441 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
3445 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
3452 /* Diagnostics on operands errors. */
3454 /* By default, output one-line error message only.
3455 Enable the verbose error message by -merror-verbose. */
3456 static int verbose_error_p = 0;
3458 #ifdef DEBUG_AARCH64
3459 /* N.B. this is only for the purpose of debugging. */
3460 const char* operand_mismatch_kind_names[] =
3463 "AARCH64_OPDE_RECOVERABLE",
3464 "AARCH64_OPDE_SYNTAX_ERROR",
3465 "AARCH64_OPDE_FATAL_SYNTAX_ERROR",
3466 "AARCH64_OPDE_INVALID_VARIANT",
3467 "AARCH64_OPDE_OUT_OF_RANGE",
3468 "AARCH64_OPDE_UNALIGNED",
3469 "AARCH64_OPDE_REG_LIST",
3470 "AARCH64_OPDE_OTHER_ERROR",
3472 #endif /* DEBUG_AARCH64 */
3474 /* Return TRUE if LHS is of higher severity than RHS, otherwise return FALSE.
3476 When multiple errors of different kinds are found in the same assembly
3477 line, only the error of the highest severity will be picked up for
3478 issuing the diagnostics. */
3480 static inline bfd_boolean
3481 operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs,
3482 enum aarch64_operand_error_kind rhs)
3484 gas_assert (AARCH64_OPDE_RECOVERABLE > AARCH64_OPDE_NIL);
3485 gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_RECOVERABLE);
3486 gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR);
3487 gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR);
3488 gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT);
3489 gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE);
3490 gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED);
3491 gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST);
3495 /* Helper routine to get the mnemonic name from the assembly instruction
3496 line; should only be called for the diagnosis purpose, as there is
3497 string copy operation involved, which may affect the runtime
3498 performance if used in elsewhere. */
3501 get_mnemonic_name (const char *str)
3503 static char mnemonic[32];
3506 /* Get the first 15 bytes and assume that the full name is included. */
3507 strncpy (mnemonic, str, 31);
3508 mnemonic[31] = '\0';
3510 /* Scan up to the end of the mnemonic, which must end in white space,
3511 '.', or end of string. */
3512 for (ptr = mnemonic; is_part_of_name(*ptr); ++ptr)
3517 /* Append '...' to the truncated long name. */
3518 if (ptr - mnemonic == 31)
3519 mnemonic[28] = mnemonic[29] = mnemonic[30] = '.';
3525 reset_aarch64_instruction (aarch64_instruction *instruction)
3527 memset (instruction, '\0', sizeof (aarch64_instruction));
3528 instruction->reloc.type = BFD_RELOC_UNUSED;
3531 /* Data strutures storing one user error in the assembly code related to
3534 struct operand_error_record
3536 const aarch64_opcode *opcode;
3537 aarch64_operand_error detail;
3538 struct operand_error_record *next;
3541 typedef struct operand_error_record operand_error_record;
3543 struct operand_errors
3545 operand_error_record *head;
3546 operand_error_record *tail;
3549 typedef struct operand_errors operand_errors;
3551 /* Top-level data structure reporting user errors for the current line of
3553 The way md_assemble works is that all opcodes sharing the same mnemonic
3554 name are iterated to find a match to the assembly line. In this data
3555 structure, each of the such opcodes will have one operand_error_record
3556 allocated and inserted. In other words, excessive errors related with
3557 a single opcode are disregarded. */
3558 operand_errors operand_error_report;
3560 /* Free record nodes. */
3561 static operand_error_record *free_opnd_error_record_nodes = NULL;
3563 /* Initialize the data structure that stores the operand mismatch
3564 information on assembling one line of the assembly code. */
3566 init_operand_error_report (void)
3568 if (operand_error_report.head != NULL)
3570 gas_assert (operand_error_report.tail != NULL);
3571 operand_error_report.tail->next = free_opnd_error_record_nodes;
3572 free_opnd_error_record_nodes = operand_error_report.head;
3573 operand_error_report.head = NULL;
3574 operand_error_report.tail = NULL;
3577 gas_assert (operand_error_report.tail == NULL);
3580 /* Return TRUE if some operand error has been recorded during the
3581 parsing of the current assembly line using the opcode *OPCODE;
3582 otherwise return FALSE. */
3583 static inline bfd_boolean
3584 opcode_has_operand_error_p (const aarch64_opcode *opcode)
3586 operand_error_record *record = operand_error_report.head;
3587 return record && record->opcode == opcode;
3590 /* Add the error record *NEW_RECORD to operand_error_report. The record's
3591 OPCODE field is initialized with OPCODE.
3592 N.B. only one record for each opcode, i.e. the maximum of one error is
3593 recorded for each instruction template. */
3596 add_operand_error_record (const operand_error_record* new_record)
3598 const aarch64_opcode *opcode = new_record->opcode;
3599 operand_error_record* record = operand_error_report.head;
3601 /* The record may have been created for this opcode. If not, we need
3603 if (! opcode_has_operand_error_p (opcode))
3605 /* Get one empty record. */
3606 if (free_opnd_error_record_nodes == NULL)
3608 record = xmalloc (sizeof (operand_error_record));
3614 record = free_opnd_error_record_nodes;
3615 free_opnd_error_record_nodes = record->next;
3617 record->opcode = opcode;
3618 /* Insert at the head. */
3619 record->next = operand_error_report.head;
3620 operand_error_report.head = record;
3621 if (operand_error_report.tail == NULL)
3622 operand_error_report.tail = record;
3624 else if (record->detail.kind != AARCH64_OPDE_NIL
3625 && record->detail.index <= new_record->detail.index
3626 && operand_error_higher_severity_p (record->detail.kind,
3627 new_record->detail.kind))
3629 /* In the case of multiple errors found on operands related with a
3630 single opcode, only record the error of the leftmost operand and
3631 only if the error is of higher severity. */
3632 DEBUG_TRACE ("error %s on operand %d not added to the report due to"
3633 " the existing error %s on operand %d",
3634 operand_mismatch_kind_names[new_record->detail.kind],
3635 new_record->detail.index,
3636 operand_mismatch_kind_names[record->detail.kind],
3637 record->detail.index);
3641 record->detail = new_record->detail;
3645 record_operand_error_info (const aarch64_opcode *opcode,
3646 aarch64_operand_error *error_info)
3648 operand_error_record record;
3649 record.opcode = opcode;
3650 record.detail = *error_info;
3651 add_operand_error_record (&record);
3654 /* Record an error of kind KIND and, if ERROR is not NULL, of the detailed
3655 error message *ERROR, for operand IDX (count from 0). */
3658 record_operand_error (const aarch64_opcode *opcode, int idx,
3659 enum aarch64_operand_error_kind kind,
3662 aarch64_operand_error info;
3663 memset(&info, 0, sizeof (info));
3667 record_operand_error_info (opcode, &info);
3671 record_operand_error_with_data (const aarch64_opcode *opcode, int idx,
3672 enum aarch64_operand_error_kind kind,
3673 const char* error, const int *extra_data)
3675 aarch64_operand_error info;
3679 info.data[0] = extra_data[0];
3680 info.data[1] = extra_data[1];
3681 info.data[2] = extra_data[2];
3682 record_operand_error_info (opcode, &info);
3686 record_operand_out_of_range_error (const aarch64_opcode *opcode, int idx,
3687 const char* error, int lower_bound,
3690 int data[3] = {lower_bound, upper_bound, 0};
3691 record_operand_error_with_data (opcode, idx, AARCH64_OPDE_OUT_OF_RANGE,
3695 /* Remove the operand error record for *OPCODE. */
3696 static void ATTRIBUTE_UNUSED
3697 remove_operand_error_record (const aarch64_opcode *opcode)
3699 if (opcode_has_operand_error_p (opcode))
3701 operand_error_record* record = operand_error_report.head;
3702 gas_assert (record != NULL && operand_error_report.tail != NULL);
3703 operand_error_report.head = record->next;
3704 record->next = free_opnd_error_record_nodes;
3705 free_opnd_error_record_nodes = record;
3706 if (operand_error_report.head == NULL)
3708 gas_assert (operand_error_report.tail == record);
3709 operand_error_report.tail = NULL;
3714 /* Given the instruction in *INSTR, return the index of the best matched
3715 qualifier sequence in the list (an array) headed by QUALIFIERS_LIST.
3717 Return -1 if there is no qualifier sequence; return the first match
3718 if there is multiple matches found. */
3721 find_best_match (const aarch64_inst *instr,
3722 const aarch64_opnd_qualifier_seq_t *qualifiers_list)
3724 int i, num_opnds, max_num_matched, idx;
3726 num_opnds = aarch64_num_of_operands (instr->opcode);
3729 DEBUG_TRACE ("no operand");
3733 max_num_matched = 0;
3736 /* For each pattern. */
3737 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
3740 const aarch64_opnd_qualifier_t *qualifiers = *qualifiers_list;
3742 /* Most opcodes has much fewer patterns in the list. */
3743 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
3745 DEBUG_TRACE_IF (i == 0, "empty list of qualifier sequence");
3746 if (i != 0 && idx == -1)
3747 /* If nothing has been matched, return the 1st sequence. */
3752 for (j = 0, num_matched = 0; j < num_opnds; ++j, ++qualifiers)
3753 if (*qualifiers == instr->operands[j].qualifier)
3756 if (num_matched > max_num_matched)
3758 max_num_matched = num_matched;
3763 DEBUG_TRACE ("return with %d", idx);
3767 /* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
3768 corresponding operands in *INSTR. */
3771 assign_qualifier_sequence (aarch64_inst *instr,
3772 const aarch64_opnd_qualifier_t *qualifiers)
3775 int num_opnds = aarch64_num_of_operands (instr->opcode);
3776 gas_assert (num_opnds);
3777 for (i = 0; i < num_opnds; ++i, ++qualifiers)
3778 instr->operands[i].qualifier = *qualifiers;
3781 /* Print operands for the diagnosis purpose. */
3784 print_operands (char *buf, const aarch64_opcode *opcode,
3785 const aarch64_opnd_info *opnds)
3789 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
3791 const size_t size = 128;
3794 /* We regard the opcode operand info more, however we also look into
3795 the inst->operands to support the disassembling of the optional
3797 The two operand code should be the same in all cases, apart from
3798 when the operand can be optional. */
3799 if (opcode->operands[i] == AARCH64_OPND_NIL
3800 || opnds[i].type == AARCH64_OPND_NIL)
3803 /* Generate the operand string in STR. */
3804 aarch64_print_operand (str, size, 0, opcode, opnds, i, NULL, NULL);
3808 strcat (buf, i == 0 ? " " : ",");
3810 /* Append the operand string. */
3815 /* Send to stderr a string as information. */
3818 output_info (const char *format, ...)
3824 as_where (&file, &line);
3828 fprintf (stderr, "%s:%u: ", file, line);
3830 fprintf (stderr, "%s: ", file);
3832 fprintf (stderr, _("Info: "));
3833 va_start (args, format);
3834 vfprintf (stderr, format, args);
3836 (void) putc ('\n', stderr);
3839 /* Output one operand error record. */
3842 output_operand_error_record (const operand_error_record *record, char *str)
3844 int idx = record->detail.index;
3845 const aarch64_opcode *opcode = record->opcode;
3846 enum aarch64_opnd opd_code = (idx != -1 ? opcode->operands[idx]
3847 : AARCH64_OPND_NIL);
3848 const aarch64_operand_error *detail = &record->detail;
3850 switch (detail->kind)
3852 case AARCH64_OPDE_NIL:
3856 case AARCH64_OPDE_SYNTAX_ERROR:
3857 case AARCH64_OPDE_RECOVERABLE:
3858 case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
3859 case AARCH64_OPDE_OTHER_ERROR:
3860 gas_assert (idx >= 0);
3861 /* Use the prepared error message if there is, otherwise use the
3862 operand description string to describe the error. */
3863 if (detail->error != NULL)
3865 if (detail->index == -1)
3866 as_bad (_("%s -- `%s'"), detail->error, str);
3868 as_bad (_("%s at operand %d -- `%s'"),
3869 detail->error, detail->index + 1, str);
3872 as_bad (_("operand %d should be %s -- `%s'"), idx + 1,
3873 aarch64_get_operand_desc (opd_code), str);
3876 case AARCH64_OPDE_INVALID_VARIANT:
3877 as_bad (_("operand mismatch -- `%s'"), str);
3878 if (verbose_error_p)
3880 /* We will try to correct the erroneous instruction and also provide
3881 more information e.g. all other valid variants.
3883 The string representation of the corrected instruction and other
3884 valid variants are generated by
3886 1) obtaining the intermediate representation of the erroneous
3888 2) manipulating the IR, e.g. replacing the operand qualifier;
3889 3) printing out the instruction by calling the printer functions
3890 shared with the disassembler.
3892 The limitation of this method is that the exact input assembly
3893 line cannot be accurately reproduced in some cases, for example an
3894 optional operand present in the actual assembly line will be
3895 omitted in the output; likewise for the optional syntax rules,
3896 e.g. the # before the immediate. Another limitation is that the
3897 assembly symbols and relocation operations in the assembly line
3898 currently cannot be printed out in the error report. Last but not
3899 least, when there is other error(s) co-exist with this error, the
3900 'corrected' instruction may be still incorrect, e.g. given
3901 'ldnp h0,h1,[x0,#6]!'
3902 this diagnosis will provide the version:
3903 'ldnp s0,s1,[x0,#6]!'
3904 which is still not right. */
3905 size_t len = strlen (get_mnemonic_name (str));
3908 const size_t size = 2048;
3910 aarch64_inst *inst_base = &inst.base;
3911 const aarch64_opnd_qualifier_seq_t *qualifiers_list;
3914 reset_aarch64_instruction (&inst);
3915 inst_base->opcode = opcode;
3917 /* Reset the error report so that there is no side effect on the
3918 following operand parsing. */
3919 init_operand_error_report ();
3922 result = parse_operands (str + len, opcode)
3923 && programmer_friendly_fixup (&inst);
3924 gas_assert (result);
3925 result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
3927 gas_assert (!result);
3929 /* Find the most matched qualifier sequence. */
3930 qlf_idx = find_best_match (inst_base, opcode->qualifiers_list);
3931 gas_assert (qlf_idx > -1);
3933 /* Assign the qualifiers. */
3934 assign_qualifier_sequence (inst_base,
3935 opcode->qualifiers_list[qlf_idx]);
3937 /* Print the hint. */
3938 output_info (_(" did you mean this?"));
3939 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
3940 print_operands (buf, opcode, inst_base->operands);
3941 output_info (_(" %s"), buf);
3943 /* Print out other variant(s) if there is any. */
3945 !empty_qualifier_sequence_p (opcode->qualifiers_list[1]))
3946 output_info (_(" other valid variant(s):"));
3948 /* For each pattern. */
3949 qualifiers_list = opcode->qualifiers_list;
3950 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
3952 /* Most opcodes has much fewer patterns in the list.
3953 First NIL qualifier indicates the end in the list. */
3954 if (empty_qualifier_sequence_p (*qualifiers_list) == TRUE)
3959 /* Mnemonics name. */
3960 snprintf (buf, size, "\t%s", get_mnemonic_name (str));
3962 /* Assign the qualifiers. */
3963 assign_qualifier_sequence (inst_base, *qualifiers_list);
3965 /* Print instruction. */
3966 print_operands (buf, opcode, inst_base->operands);
3968 output_info (_(" %s"), buf);
3974 case AARCH64_OPDE_OUT_OF_RANGE:
3975 as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
3976 detail->error ? detail->error : _("immediate value"),
3977 detail->data[0], detail->data[1], detail->index + 1, str);
3980 case AARCH64_OPDE_REG_LIST:
3981 if (detail->data[0] == 1)
3982 as_bad (_("invalid number of registers in the list; "
3983 "only 1 register is expected at operand %d -- `%s'"),
3984 detail->index + 1, str);
3986 as_bad (_("invalid number of registers in the list; "
3987 "%d registers are expected at operand %d -- `%s'"),
3988 detail->data[0], detail->index + 1, str);
3991 case AARCH64_OPDE_UNALIGNED:
3992 as_bad (_("immediate value should be a multiple of "
3993 "%d at operand %d -- `%s'"),
3994 detail->data[0], detail->index + 1, str);
4003 /* Process and output the error message about the operand mismatching.
4005 When this function is called, the operand error information had
4006 been collected for an assembly line and there will be multiple
4007 errors in the case of mulitple instruction templates; output the
4008 error message that most closely describes the problem. */
4011 output_operand_error_report (char *str)
4013 int largest_error_pos;
4014 const char *msg = NULL;
4015 enum aarch64_operand_error_kind kind;
4016 operand_error_record *curr;
4017 operand_error_record *head = operand_error_report.head;
4018 operand_error_record *record = NULL;
4020 /* No error to report. */
4024 gas_assert (head != NULL && operand_error_report.tail != NULL);
4026 /* Only one error. */
4027 if (head == operand_error_report.tail)
4029 DEBUG_TRACE ("single opcode entry with error kind: %s",
4030 operand_mismatch_kind_names[head->detail.kind]);
4031 output_operand_error_record (head, str);
4035 /* Find the error kind of the highest severity. */
4036 DEBUG_TRACE ("multiple opcode entres with error kind");
4037 kind = AARCH64_OPDE_NIL;
4038 for (curr = head; curr != NULL; curr = curr->next)
4040 gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
4041 DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
4042 if (operand_error_higher_severity_p (curr->detail.kind, kind))
4043 kind = curr->detail.kind;
4045 gas_assert (kind != AARCH64_OPDE_NIL);
4047 /* Pick up one of errors of KIND to report. */
4048 largest_error_pos = -2; /* Index can be -1 which means unknown index. */
4049 for (curr = head; curr != NULL; curr = curr->next)
4051 if (curr->detail.kind != kind)
4053 /* If there are multiple errors, pick up the one with the highest
4054 mismatching operand index. In the case of multiple errors with
4055 the equally highest operand index, pick up the first one or the
4056 first one with non-NULL error message. */
4057 if (curr->detail.index > largest_error_pos
4058 || (curr->detail.index == largest_error_pos && msg == NULL
4059 && curr->detail.error != NULL))
4061 largest_error_pos = curr->detail.index;
4063 msg = record->detail.error;
4067 gas_assert (largest_error_pos != -2 && record != NULL);
4068 DEBUG_TRACE ("Pick up error kind %s to report",
4069 operand_mismatch_kind_names[record->detail.kind]);
4072 output_operand_error_record (record, str);
4075 /* Write an AARCH64 instruction to buf - always little-endian. */
4077 put_aarch64_insn (char *buf, uint32_t insn)
4079 unsigned char *where = (unsigned char *) buf;
4081 where[1] = insn >> 8;
4082 where[2] = insn >> 16;
4083 where[3] = insn >> 24;
4087 get_aarch64_insn (char *buf)
4089 unsigned char *where = (unsigned char *) buf;
4091 result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
4096 output_inst (struct aarch64_inst *new_inst)
4100 to = frag_more (INSN_SIZE);
4102 frag_now->tc_frag_data.recorded = 1;
4104 put_aarch64_insn (to, inst.base.value);
4106 if (inst.reloc.type != BFD_RELOC_UNUSED)
4108 fixS *fixp = fix_new_aarch64 (frag_now, to - frag_now->fr_literal,
4109 INSN_SIZE, &inst.reloc.exp,
4112 DEBUG_TRACE ("Prepared relocation fix up");
4113 /* Don't check the addend value against the instruction size,
4114 that's the job of our code in md_apply_fix(). */
4115 fixp->fx_no_overflow = 1;
4116 if (new_inst != NULL)
4117 fixp->tc_fix_data.inst = new_inst;
4118 if (aarch64_gas_internal_fixup_p ())
4120 gas_assert (inst.reloc.opnd != AARCH64_OPND_NIL);
4121 fixp->tc_fix_data.opnd = inst.reloc.opnd;
4122 fixp->fx_addnumber = inst.reloc.flags;
4126 dwarf2_emit_insn (INSN_SIZE);
4129 /* Link together opcodes of the same name. */
4133 aarch64_opcode *opcode;
4134 struct templates *next;
4137 typedef struct templates templates;
4140 lookup_mnemonic (const char *start, int len)
4142 templates *templ = NULL;
4144 templ = hash_find_n (aarch64_ops_hsh, start, len);
4148 /* Subroutine of md_assemble, responsible for looking up the primary
4149 opcode from the mnemonic the user wrote. STR points to the
4150 beginning of the mnemonic. */
4153 opcode_lookup (char **str)
4156 const aarch64_cond *cond;
4160 /* Scan up to the end of the mnemonic, which must end in white space,
4161 '.', or end of string. */
4162 for (base = end = *str; is_part_of_name(*end); end++)
4169 inst.cond = COND_ALWAYS;
4171 /* Handle a possible condition. */
4174 cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
4177 inst.cond = cond->value;
4191 if (inst.cond == COND_ALWAYS)
4193 /* Look for unaffixed mnemonic. */
4194 return lookup_mnemonic (base, len);
4198 /* append ".c" to mnemonic if conditional */
4199 memcpy (condname, base, len);
4200 memcpy (condname + len, ".c", 2);
4203 return lookup_mnemonic (base, len);
4209 /* Internal helper routine converting a vector neon_type_el structure
4210 *VECTYPE to a corresponding operand qualifier. */
4212 static inline aarch64_opnd_qualifier_t
4213 vectype_to_qualifier (const struct neon_type_el *vectype)
4215 /* Element size in bytes indexed by neon_el_type. */
4216 const unsigned char ele_size[5]
4219 if (!vectype->defined || vectype->type == NT_invtype)
4220 goto vectype_conversion_fail;
4222 gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
4224 if (vectype->defined & NTA_HASINDEX)
4225 /* Vector element register. */
4226 return AARCH64_OPND_QLF_S_B + vectype->type;
4229 /* Vector register. */
4230 int reg_size = ele_size[vectype->type] * vectype->width;
4232 if (reg_size != 16 && reg_size != 8)
4233 goto vectype_conversion_fail;
4234 /* The conversion is calculated based on the relation of the order of
4235 qualifiers to the vector element size and vector register size. */
4236 offset = (vectype->type == NT_q)
4237 ? 8 : (vectype->type << 1) + (reg_size >> 4);
4238 gas_assert (offset <= 8);
4239 return AARCH64_OPND_QLF_V_8B + offset;
4242 vectype_conversion_fail:
4243 first_error (_("bad vector arrangement type"));
4244 return AARCH64_OPND_QLF_NIL;
4247 /* Process an optional operand that is found omitted from the assembly line.
4248 Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
4249 instruction's opcode entry while IDX is the index of this omitted operand.
4253 process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
4254 int idx, aarch64_opnd_info *operand)
4256 aarch64_insn default_value = get_optional_operand_default_value (opcode);
4257 gas_assert (optional_operand_p (opcode, idx));
4258 gas_assert (!operand->present);
4262 case AARCH64_OPND_Rd:
4263 case AARCH64_OPND_Rn:
4264 case AARCH64_OPND_Rm:
4265 case AARCH64_OPND_Rt:
4266 case AARCH64_OPND_Rt2:
4267 case AARCH64_OPND_Rs:
4268 case AARCH64_OPND_Ra:
4269 case AARCH64_OPND_Rt_SYS:
4270 case AARCH64_OPND_Rd_SP:
4271 case AARCH64_OPND_Rn_SP:
4272 case AARCH64_OPND_Fd:
4273 case AARCH64_OPND_Fn:
4274 case AARCH64_OPND_Fm:
4275 case AARCH64_OPND_Fa:
4276 case AARCH64_OPND_Ft:
4277 case AARCH64_OPND_Ft2:
4278 case AARCH64_OPND_Sd:
4279 case AARCH64_OPND_Sn:
4280 case AARCH64_OPND_Sm:
4281 case AARCH64_OPND_Vd:
4282 case AARCH64_OPND_Vn:
4283 case AARCH64_OPND_Vm:
4284 case AARCH64_OPND_VdD1:
4285 case AARCH64_OPND_VnD1:
4286 operand->reg.regno = default_value;
4289 case AARCH64_OPND_Ed:
4290 case AARCH64_OPND_En:
4291 case AARCH64_OPND_Em:
4292 operand->reglane.regno = default_value;
4295 case AARCH64_OPND_IDX:
4296 case AARCH64_OPND_BIT_NUM:
4297 case AARCH64_OPND_IMMR:
4298 case AARCH64_OPND_IMMS:
4299 case AARCH64_OPND_SHLL_IMM:
4300 case AARCH64_OPND_IMM_VLSL:
4301 case AARCH64_OPND_IMM_VLSR:
4302 case AARCH64_OPND_CCMP_IMM:
4303 case AARCH64_OPND_FBITS:
4304 case AARCH64_OPND_UIMM4:
4305 case AARCH64_OPND_UIMM3_OP1:
4306 case AARCH64_OPND_UIMM3_OP2:
4307 case AARCH64_OPND_IMM:
4308 case AARCH64_OPND_WIDTH:
4309 case AARCH64_OPND_UIMM7:
4310 case AARCH64_OPND_NZCV:
4311 operand->imm.value = default_value;
4314 case AARCH64_OPND_EXCEPTION:
4315 inst.reloc.type = BFD_RELOC_UNUSED;
4318 case AARCH64_OPND_BARRIER_ISB:
4319 operand->barrier = aarch64_barrier_options + default_value;
4326 /* Process the relocation type for move wide instructions.
4327 Return TRUE on success; otherwise return FALSE. */
4330 process_movw_reloc_info (void)
4335 is32 = inst.base.operands[0].qualifier == AARCH64_OPND_QLF_W ? 1 : 0;
4337 if (inst.base.opcode->op == OP_MOVK)
4338 switch (inst.reloc.type)
4340 case BFD_RELOC_AARCH64_MOVW_G0_S:
4341 case BFD_RELOC_AARCH64_MOVW_G1_S:
4342 case BFD_RELOC_AARCH64_MOVW_G2_S:
4343 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4344 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4345 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4346 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4347 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4349 (_("the specified relocation type is not allowed for MOVK"));
4355 switch (inst.reloc.type)
4357 case BFD_RELOC_AARCH64_MOVW_G0:
4358 case BFD_RELOC_AARCH64_MOVW_G0_S:
4359 case BFD_RELOC_AARCH64_MOVW_G0_NC:
4360 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
4361 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
4364 case BFD_RELOC_AARCH64_MOVW_G1:
4365 case BFD_RELOC_AARCH64_MOVW_G1_S:
4366 case BFD_RELOC_AARCH64_MOVW_G1_NC:
4367 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
4368 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
4371 case BFD_RELOC_AARCH64_MOVW_G2:
4372 case BFD_RELOC_AARCH64_MOVW_G2_S:
4373 case BFD_RELOC_AARCH64_MOVW_G2_NC:
4374 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
4377 set_fatal_syntax_error
4378 (_("the specified relocation type is not allowed for 32-bit "
4384 case BFD_RELOC_AARCH64_MOVW_G3:
4387 set_fatal_syntax_error
4388 (_("the specified relocation type is not allowed for 32-bit "
4395 /* More cases should be added when more MOVW-related relocation types
4396 are supported in GAS. */
4397 gas_assert (aarch64_gas_internal_fixup_p ());
4398 /* The shift amount should have already been set by the parser. */
4401 inst.base.operands[1].shifter.amount = shift;
4405 /* A primitive log caculator. */
4407 static inline unsigned int
4408 get_logsz (unsigned int size)
4410 const unsigned char ls[16] =
4411 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
4417 gas_assert (ls[size - 1] != (unsigned char)-1);
4418 return ls[size - 1];
4421 /* Determine and return the real reloc type code for an instruction
4422 with the pseudo reloc type code BFD_RELOC_AARCH64_LDST_LO12. */
4424 static inline bfd_reloc_code_real_type
4425 ldst_lo12_determine_real_reloc_type (void)
4428 enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
4429 enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
4431 const bfd_reloc_code_real_type reloc_ldst_lo12[5] = {
4432 BFD_RELOC_AARCH64_LDST8_LO12, BFD_RELOC_AARCH64_LDST16_LO12,
4433 BFD_RELOC_AARCH64_LDST32_LO12, BFD_RELOC_AARCH64_LDST64_LO12,
4434 BFD_RELOC_AARCH64_LDST128_LO12
4437 gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12);
4438 gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
4440 if (opd1_qlf == AARCH64_OPND_QLF_NIL)
4442 aarch64_get_expected_qualifier (inst.base.opcode->qualifiers_list,
4444 gas_assert (opd1_qlf != AARCH64_OPND_QLF_NIL);
4446 logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
4447 gas_assert (logsz >= 0 && logsz <= 4);
4449 return reloc_ldst_lo12[logsz];
4452 /* Check whether a register list REGINFO is valid. The registers must be
4453 numbered in increasing order (modulo 32), in increments of one or two.
4455 If ACCEPT_ALTERNATE is non-zero, the register numbers should be in
4458 Return FALSE if such a register list is invalid, otherwise return TRUE. */
4461 reg_list_valid_p (uint32_t reginfo, int accept_alternate)
4463 uint32_t i, nb_regs, prev_regno, incr;
4465 nb_regs = 1 + (reginfo & 0x3);
4467 prev_regno = reginfo & 0x1f;
4468 incr = accept_alternate ? 2 : 1;
4470 for (i = 1; i < nb_regs; ++i)
4472 uint32_t curr_regno;
4474 curr_regno = reginfo & 0x1f;
4475 if (curr_regno != ((prev_regno + incr) & 0x1f))
4477 prev_regno = curr_regno;
4483 /* Generic instruction operand parser. This does no encoding and no
4484 semantic validation; it merely squirrels values away in the inst
4485 structure. Returns TRUE or FALSE depending on whether the
4486 specified grammar matched. */
4489 parse_operands (char *str, const aarch64_opcode *opcode)
4492 char *backtrack_pos = 0;
4493 const enum aarch64_opnd *operands = opcode->operands;
4496 skip_whitespace (str);
4498 for (i = 0; operands[i] != AARCH64_OPND_NIL; i++)
4501 int isreg32, isregzero;
4502 int comma_skipped_p = 0;
4503 aarch64_reg_type rtype;
4504 struct neon_type_el vectype;
4505 aarch64_opnd_info *info = &inst.base.operands[i];
4507 DEBUG_TRACE ("parse operand %d", i);
4509 /* Assign the operand code. */
4510 info->type = operands[i];
4512 if (optional_operand_p (opcode, i))
4514 /* Remember where we are in case we need to backtrack. */
4515 gas_assert (!backtrack_pos);
4516 backtrack_pos = str;
4519 /* Expect comma between operands; the backtrack mechanizm will take
4520 care of cases of omitted optional operand. */
4521 if (i > 0 && ! skip_past_char (&str, ','))
4523 set_syntax_error (_("comma expected between operands"));
4527 comma_skipped_p = 1;
4529 switch (operands[i])
4531 case AARCH64_OPND_Rd:
4532 case AARCH64_OPND_Rn:
4533 case AARCH64_OPND_Rm:
4534 case AARCH64_OPND_Rt:
4535 case AARCH64_OPND_Rt2:
4536 case AARCH64_OPND_Rs:
4537 case AARCH64_OPND_Ra:
4538 case AARCH64_OPND_Rt_SYS:
4539 po_int_reg_or_fail (1, 0);
4542 case AARCH64_OPND_Rd_SP:
4543 case AARCH64_OPND_Rn_SP:
4544 po_int_reg_or_fail (0, 1);
4547 case AARCH64_OPND_Rm_EXT:
4548 case AARCH64_OPND_Rm_SFT:
4549 po_misc_or_fail (parse_shifter_operand
4550 (&str, info, (operands[i] == AARCH64_OPND_Rm_EXT
4552 : SHIFTED_LOGIC_IMM)));
4553 if (!info->shifter.operator_present)
4555 /* Default to LSL if not present. Libopcodes prefers shifter
4556 kind to be explicit. */
4557 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4558 info->shifter.kind = AARCH64_MOD_LSL;
4559 /* For Rm_EXT, libopcodes will carry out further check on whether
4560 or not stack pointer is used in the instruction (Recall that
4561 "the extend operator is not optional unless at least one of
4562 "Rd" or "Rn" is '11111' (i.e. WSP)"). */
4566 case AARCH64_OPND_Fd:
4567 case AARCH64_OPND_Fn:
4568 case AARCH64_OPND_Fm:
4569 case AARCH64_OPND_Fa:
4570 case AARCH64_OPND_Ft:
4571 case AARCH64_OPND_Ft2:
4572 case AARCH64_OPND_Sd:
4573 case AARCH64_OPND_Sn:
4574 case AARCH64_OPND_Sm:
4575 val = aarch64_reg_parse (&str, REG_TYPE_BHSDQ, &rtype, NULL);
4576 if (val == PARSE_FAIL)
4578 first_error (_(get_reg_expected_msg (REG_TYPE_BHSDQ)));
4581 gas_assert (rtype >= REG_TYPE_FP_B && rtype <= REG_TYPE_FP_Q);
4583 info->reg.regno = val;
4584 info->qualifier = AARCH64_OPND_QLF_S_B + (rtype - REG_TYPE_FP_B);
4587 case AARCH64_OPND_Vd:
4588 case AARCH64_OPND_Vn:
4589 case AARCH64_OPND_Vm:
4590 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4591 if (val == PARSE_FAIL)
4593 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4596 if (vectype.defined & NTA_HASINDEX)
4599 info->reg.regno = val;
4600 info->qualifier = vectype_to_qualifier (&vectype);
4601 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4605 case AARCH64_OPND_VdD1:
4606 case AARCH64_OPND_VnD1:
4607 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4608 if (val == PARSE_FAIL)
4610 set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4613 if (vectype.type != NT_d || vectype.index != 1)
4615 set_fatal_syntax_error
4616 (_("the top half of a 128-bit FP/SIMD register is expected"));
4619 info->reg.regno = val;
4620 /* N.B: VdD1 and VnD1 are treated as an fp or advsimd scalar register
4621 here; it is correct for the purpose of encoding/decoding since
4622 only the register number is explicitly encoded in the related
4623 instructions, although this appears a bit hacky. */
4624 info->qualifier = AARCH64_OPND_QLF_S_D;
4627 case AARCH64_OPND_Ed:
4628 case AARCH64_OPND_En:
4629 case AARCH64_OPND_Em:
4630 val = aarch64_reg_parse (&str, REG_TYPE_VN, NULL, &vectype);
4631 if (val == PARSE_FAIL)
4633 first_error (_(get_reg_expected_msg (REG_TYPE_VN)));
4636 if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
4639 info->reglane.regno = val;
4640 info->reglane.index = vectype.index;
4641 info->qualifier = vectype_to_qualifier (&vectype);
4642 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4646 case AARCH64_OPND_LVn:
4647 case AARCH64_OPND_LVt:
4648 case AARCH64_OPND_LVt_AL:
4649 case AARCH64_OPND_LEt:
4650 if ((val = parse_neon_reg_list (&str, &vectype)) == PARSE_FAIL)
4652 if (! reg_list_valid_p (val, /* accept_alternate */ 0))
4654 set_fatal_syntax_error (_("invalid register list"));
4657 info->reglist.first_regno = (val >> 2) & 0x1f;
4658 info->reglist.num_regs = (val & 0x3) + 1;
4659 if (operands[i] == AARCH64_OPND_LEt)
4661 if (!(vectype.defined & NTA_HASINDEX))
4663 info->reglist.has_index = 1;
4664 info->reglist.index = vectype.index;
4666 else if (!(vectype.defined & NTA_HASTYPE))
4668 info->qualifier = vectype_to_qualifier (&vectype);
4669 if (info->qualifier == AARCH64_OPND_QLF_NIL)
4673 case AARCH64_OPND_Cn:
4674 case AARCH64_OPND_Cm:
4675 po_reg_or_fail (REG_TYPE_CN);
4678 set_fatal_syntax_error (_(get_reg_expected_msg (REG_TYPE_CN)));
4681 inst.base.operands[i].reg.regno = val;
4684 case AARCH64_OPND_SHLL_IMM:
4685 case AARCH64_OPND_IMM_VLSR:
4686 po_imm_or_fail (1, 64);
4687 info->imm.value = val;
4690 case AARCH64_OPND_CCMP_IMM:
4691 case AARCH64_OPND_FBITS:
4692 case AARCH64_OPND_UIMM4:
4693 case AARCH64_OPND_UIMM3_OP1:
4694 case AARCH64_OPND_UIMM3_OP2:
4695 case AARCH64_OPND_IMM_VLSL:
4696 case AARCH64_OPND_IMM:
4697 case AARCH64_OPND_WIDTH:
4698 po_imm_nc_or_fail ();
4699 info->imm.value = val;
4702 case AARCH64_OPND_UIMM7:
4703 po_imm_or_fail (0, 127);
4704 info->imm.value = val;
4707 case AARCH64_OPND_IDX:
4708 case AARCH64_OPND_BIT_NUM:
4709 case AARCH64_OPND_IMMR:
4710 case AARCH64_OPND_IMMS:
4711 po_imm_or_fail (0, 63);
4712 info->imm.value = val;
4715 case AARCH64_OPND_IMM0:
4716 po_imm_nc_or_fail ();
4719 set_fatal_syntax_error (_("immediate zero expected"));
4722 info->imm.value = 0;
4725 case AARCH64_OPND_FPIMM0:
4728 bfd_boolean res1 = FALSE, res2 = FALSE;
4729 /* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
4730 it is probably not worth the effort to support it. */
4731 if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
4732 && !(res2 = parse_constant_immediate (&str, &val)))
4734 if ((res1 && qfloat == 0) || (res2 && val == 0))
4736 info->imm.value = 0;
4737 info->imm.is_fp = 1;
4740 set_fatal_syntax_error (_("immediate zero expected"));
4744 case AARCH64_OPND_IMM_MOV:
4747 if (reg_name_p (str, REG_TYPE_R_Z_SP))
4750 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
4752 /* The MOV immediate alias will be fixed up by fix_mov_imm_insn
4753 later. fix_mov_imm_insn will try to determine a machine
4754 instruction (MOVZ, MOVN or ORR) for it and will issue an error
4755 message if the immediate cannot be moved by a single
4757 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
4758 inst.base.operands[i].skip = 1;
4762 case AARCH64_OPND_SIMD_IMM:
4763 case AARCH64_OPND_SIMD_IMM_SFT:
4764 if (! parse_big_immediate (&str, &val))
4766 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4768 /* need_libopcodes_p */ 1,
4771 N.B. although AARCH64_OPND_SIMD_IMM doesn't permit any
4772 shift, we don't check it here; we leave the checking to
4773 the libopcodes (operand_general_constraint_met_p). By
4774 doing this, we achieve better diagnostics. */
4775 if (skip_past_comma (&str)
4776 && ! parse_shift (&str, info, SHIFTED_LSL_MSL))
4778 if (!info->shifter.operator_present
4779 && info->type == AARCH64_OPND_SIMD_IMM_SFT)
4781 /* Default to LSL if not present. Libopcodes prefers shifter
4782 kind to be explicit. */
4783 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4784 info->shifter.kind = AARCH64_MOD_LSL;
4788 case AARCH64_OPND_FPIMM:
4789 case AARCH64_OPND_SIMD_FPIMM:
4793 = (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
4795 if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
4799 set_fatal_syntax_error (_("invalid floating-point constant"));
4802 inst.base.operands[i].imm.value = encode_imm_float_bits (qfloat);
4803 inst.base.operands[i].imm.is_fp = 1;
4807 case AARCH64_OPND_LIMM:
4808 po_misc_or_fail (parse_shifter_operand (&str, info,
4809 SHIFTED_LOGIC_IMM));
4810 if (info->shifter.operator_present)
4812 set_fatal_syntax_error
4813 (_("shift not allowed for bitmask immediate"));
4816 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4818 /* need_libopcodes_p */ 1,
4822 case AARCH64_OPND_AIMM:
4823 if (opcode->op == OP_ADD)
4824 /* ADD may have relocation types. */
4825 po_misc_or_fail (parse_shifter_operand_reloc (&str, info,
4826 SHIFTED_ARITH_IMM));
4828 po_misc_or_fail (parse_shifter_operand (&str, info,
4829 SHIFTED_ARITH_IMM));
4830 switch (inst.reloc.type)
4832 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
4833 info->shifter.amount = 12;
4835 case BFD_RELOC_UNUSED:
4836 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4837 if (info->shifter.kind != AARCH64_MOD_NONE)
4838 inst.reloc.flags = FIXUP_F_HAS_EXPLICIT_SHIFT;
4839 inst.reloc.pc_rel = 0;
4844 info->imm.value = 0;
4845 if (!info->shifter.operator_present)
4847 /* Default to LSL if not present. Libopcodes prefers shifter
4848 kind to be explicit. */
4849 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
4850 info->shifter.kind = AARCH64_MOD_LSL;
4854 case AARCH64_OPND_HALF:
4856 /* #<imm16> or relocation. */
4857 int internal_fixup_p;
4858 po_misc_or_fail (parse_half (&str, &internal_fixup_p));
4859 if (internal_fixup_p)
4860 aarch64_set_gas_internal_fixup (&inst.reloc, info, 0);
4861 skip_whitespace (str);
4862 if (skip_past_comma (&str))
4864 /* {, LSL #<shift>} */
4865 if (! aarch64_gas_internal_fixup_p ())
4867 set_fatal_syntax_error (_("can't mix relocation modifier "
4868 "with explicit shift"));
4871 po_misc_or_fail (parse_shift (&str, info, SHIFTED_LSL));
4874 inst.base.operands[i].shifter.amount = 0;
4875 inst.base.operands[i].shifter.kind = AARCH64_MOD_LSL;
4876 inst.base.operands[i].imm.value = 0;
4877 if (! process_movw_reloc_info ())
4882 case AARCH64_OPND_EXCEPTION:
4883 po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp));
4884 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
4886 /* need_libopcodes_p */ 0,
4890 case AARCH64_OPND_NZCV:
4892 const asm_nzcv *nzcv = hash_find_n (aarch64_nzcv_hsh, str, 4);
4896 info->imm.value = nzcv->value;
4899 po_imm_or_fail (0, 15);
4900 info->imm.value = val;
4904 case AARCH64_OPND_COND:
4905 info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
4907 if (info->cond == NULL)
4909 set_syntax_error (_("invalid condition"));
4914 case AARCH64_OPND_ADDR_ADRP:
4915 po_misc_or_fail (parse_adrp (&str));
4916 /* Clear the value as operand needs to be relocated. */
4917 info->imm.value = 0;
4920 case AARCH64_OPND_ADDR_PCREL14:
4921 case AARCH64_OPND_ADDR_PCREL19:
4922 case AARCH64_OPND_ADDR_PCREL21:
4923 case AARCH64_OPND_ADDR_PCREL26:
4924 po_misc_or_fail (parse_address_reloc (&str, info));
4925 if (!info->addr.pcrel)
4927 set_syntax_error (_("invalid pc-relative address"));
4930 if (inst.gen_lit_pool
4931 && (opcode->iclass != loadlit || opcode->op == OP_PRFM_LIT))
4933 /* Only permit "=value" in the literal load instructions.
4934 The literal will be generated by programmer_friendly_fixup. */
4935 set_syntax_error (_("invalid use of \"=immediate\""));
4938 if (inst.reloc.exp.X_op == O_symbol && find_reloc_table_entry (&str))
4940 set_syntax_error (_("unrecognized relocation suffix"));
4943 if (inst.reloc.exp.X_op == O_constant && !inst.gen_lit_pool)
4945 info->imm.value = inst.reloc.exp.X_add_number;
4946 inst.reloc.type = BFD_RELOC_UNUSED;
4950 info->imm.value = 0;
4951 switch (opcode->iclass)
4955 /* e.g. CBZ or B.COND */
4956 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
4957 inst.reloc.type = BFD_RELOC_AARCH64_BRANCH19;
4961 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL14);
4962 inst.reloc.type = BFD_RELOC_AARCH64_TSTBR14;
4966 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL26);
4967 inst.reloc.type = (opcode->op == OP_BL)
4968 ? BFD_RELOC_AARCH64_CALL26 : BFD_RELOC_AARCH64_JUMP26;
4971 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL19);
4972 inst.reloc.type = BFD_RELOC_AARCH64_LD_LO19_PCREL;
4975 gas_assert (operands[i] == AARCH64_OPND_ADDR_PCREL21);
4976 inst.reloc.type = BFD_RELOC_AARCH64_ADR_LO21_PCREL;
4982 inst.reloc.pc_rel = 1;
4986 case AARCH64_OPND_ADDR_SIMPLE:
4987 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
4988 /* [<Xn|SP>{, #<simm>}] */
4989 po_char_or_fail ('[');
4990 po_reg_or_fail (REG_TYPE_R64_SP);
4991 /* Accept optional ", #0". */
4992 if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
4993 && skip_past_char (&str, ','))
4995 skip_past_char (&str, '#');
4996 if (! skip_past_char (&str, '0'))
4998 set_fatal_syntax_error
4999 (_("the optional immediate offset can only be 0"));
5003 po_char_or_fail (']');
5004 info->addr.base_regno = val;
5007 case AARCH64_OPND_ADDR_REGOFF:
5008 /* [<Xn|SP>, <R><m>{, <extend> {<amount>}}] */
5009 po_misc_or_fail (parse_address (&str, info, 0));
5010 if (info->addr.pcrel || !info->addr.offset.is_reg
5011 || !info->addr.preind || info->addr.postind
5012 || info->addr.writeback)
5014 set_syntax_error (_("invalid addressing mode"));
5017 if (!info->shifter.operator_present)
5019 /* Default to LSL if not present. Libopcodes prefers shifter
5020 kind to be explicit. */
5021 gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
5022 info->shifter.kind = AARCH64_MOD_LSL;
5024 /* Qualifier to be deduced by libopcodes. */
5027 case AARCH64_OPND_ADDR_SIMM7:
5028 po_misc_or_fail (parse_address (&str, info, 0));
5029 if (info->addr.pcrel || info->addr.offset.is_reg
5030 || (!info->addr.preind && !info->addr.postind))
5032 set_syntax_error (_("invalid addressing mode"));
5035 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5037 /* need_libopcodes_p */ 1,
5041 case AARCH64_OPND_ADDR_SIMM9:
5042 case AARCH64_OPND_ADDR_SIMM9_2:
5043 po_misc_or_fail (parse_address_reloc (&str, info));
5044 if (info->addr.pcrel || info->addr.offset.is_reg
5045 || (!info->addr.preind && !info->addr.postind)
5046 || (operands[i] == AARCH64_OPND_ADDR_SIMM9_2
5047 && info->addr.writeback))
5049 set_syntax_error (_("invalid addressing mode"));
5052 if (inst.reloc.type != BFD_RELOC_UNUSED)
5054 set_syntax_error (_("relocation not allowed"));
5057 assign_imm_if_const_or_fixup_later (&inst.reloc, info,
5059 /* need_libopcodes_p */ 1,
5063 case AARCH64_OPND_ADDR_UIMM12:
5064 po_misc_or_fail (parse_address_reloc (&str, info));
5065 if (info->addr.pcrel || info->addr.offset.is_reg
5066 || !info->addr.preind || info->addr.writeback)
5068 set_syntax_error (_("invalid addressing mode"));
5071 if (inst.reloc.type == BFD_RELOC_UNUSED)
5072 aarch64_set_gas_internal_fixup (&inst.reloc, info, 1);
5073 else if (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12)
5074 inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
5075 /* Leave qualifier to be determined by libopcodes. */
5078 case AARCH64_OPND_SIMD_ADDR_POST:
5079 /* [<Xn|SP>], <Xm|#<amount>> */
5080 po_misc_or_fail (parse_address (&str, info, 1));
5081 if (!info->addr.postind || !info->addr.writeback)
5083 set_syntax_error (_("invalid addressing mode"));
5086 if (!info->addr.offset.is_reg)
5088 if (inst.reloc.exp.X_op == O_constant)
5089 info->addr.offset.imm = inst.reloc.exp.X_add_number;
5092 set_fatal_syntax_error
5093 (_("writeback value should be an immediate constant"));
5100 case AARCH64_OPND_SYSREG:
5101 if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1))
5104 set_syntax_error (_("unknown or missing system register name"));
5107 inst.base.operands[i].sysreg = val;
5110 case AARCH64_OPND_PSTATEFIELD:
5111 if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0))
5114 set_syntax_error (_("unknown or missing PSTATE field name"));
5117 inst.base.operands[i].pstatefield = val;
5120 case AARCH64_OPND_SYSREG_IC:
5121 inst.base.operands[i].sysins_op =
5122 parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
5124 case AARCH64_OPND_SYSREG_DC:
5125 inst.base.operands[i].sysins_op =
5126 parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
5128 case AARCH64_OPND_SYSREG_AT:
5129 inst.base.operands[i].sysins_op =
5130 parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
5132 case AARCH64_OPND_SYSREG_TLBI:
5133 inst.base.operands[i].sysins_op =
5134 parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
5136 if (inst.base.operands[i].sysins_op == NULL)
5138 set_fatal_syntax_error ( _("unknown or missing operation name"));
5143 case AARCH64_OPND_BARRIER:
5144 case AARCH64_OPND_BARRIER_ISB:
5145 val = parse_barrier (&str);
5146 if (val != PARSE_FAIL
5147 && operands[i] == AARCH64_OPND_BARRIER_ISB && val != 0xf)
5149 /* ISB only accepts options name 'sy'. */
5151 (_("the specified option is not accepted in ISB"));
5152 /* Turn off backtrack as this optional operand is present. */
5156 /* This is an extension to accept a 0..15 immediate. */
5157 if (val == PARSE_FAIL)
5158 po_imm_or_fail (0, 15);
5159 info->barrier = aarch64_barrier_options + val;
5162 case AARCH64_OPND_PRFOP:
5163 val = parse_pldop (&str);
5164 /* This is an extension to accept a 0..31 immediate. */
5165 if (val == PARSE_FAIL)
5166 po_imm_or_fail (0, 31);
5167 inst.base.operands[i].prfop = aarch64_prfops + val;
5171 as_fatal (_("unhandled operand code %d"), operands[i]);
5174 /* If we get here, this operand was successfully parsed. */
5175 inst.base.operands[i].present = 1;
5179 /* The parse routine should already have set the error, but in case
5180 not, set a default one here. */
5182 set_default_error ();
5184 if (! backtrack_pos)
5185 goto parse_operands_return;
5187 /* Reaching here means we are dealing with an optional operand that is
5188 omitted from the assembly line. */
5189 gas_assert (optional_operand_p (opcode, i));
5191 process_omitted_operand (operands[i], opcode, i, info);
5193 /* Try again, skipping the optional operand at backtrack_pos. */
5194 str = backtrack_pos;
5197 /* If this is the last operand that is optional and omitted, but without
5198 the presence of a comma. */
5199 if (i && comma_skipped_p && i == aarch64_num_of_operands (opcode) - 1)
5201 set_fatal_syntax_error
5202 (_("unexpected comma before the omitted optional operand"));
5203 goto parse_operands_return;
5206 /* Clear any error record after the omitted optional operand has been
5207 successfully handled. */
5211 /* Check if we have parsed all the operands. */
5212 if (*str != '\0' && ! error_p ())
5214 /* Set I to the index of the last present operand; this is
5215 for the purpose of diagnostics. */
5216 for (i -= 1; i >= 0 && !inst.base.operands[i].present; --i)
5218 set_fatal_syntax_error
5219 (_("unexpected characters following instruction"));
5222 parse_operands_return:
5226 DEBUG_TRACE ("parsing FAIL: %s - %s",
5227 operand_mismatch_kind_names[get_error_kind ()],
5228 get_error_message ());
5229 /* Record the operand error properly; this is useful when there
5230 are multiple instruction templates for a mnemonic name, so that
5231 later on, we can select the error that most closely describes
5233 record_operand_error (opcode, i, get_error_kind (),
5234 get_error_message ());
5239 DEBUG_TRACE ("parsing SUCCESS");
5244 /* It does some fix-up to provide some programmer friendly feature while
5245 keeping the libopcodes happy, i.e. libopcodes only accepts
5246 the preferred architectural syntax.
5247 Return FALSE if there is any failure; otherwise return TRUE. */
5250 programmer_friendly_fixup (aarch64_instruction *instr)
5252 aarch64_inst *base = &instr->base;
5253 const aarch64_opcode *opcode = base->opcode;
5254 enum aarch64_op op = opcode->op;
5255 aarch64_opnd_info *operands = base->operands;
5257 DEBUG_TRACE ("enter");
5259 switch (opcode->iclass)
5262 /* TBNZ Xn|Wn, #uimm6, label
5263 Test and Branch Not Zero: conditionally jumps to label if bit number
5264 uimm6 in register Xn is not zero. The bit number implies the width of
5265 the register, which may be written and should be disassembled as Wn if
5266 uimm is less than 32. */
5267 if (operands[0].qualifier == AARCH64_OPND_QLF_W)
5269 if (operands[1].imm.value >= 32)
5271 record_operand_out_of_range_error (opcode, 1, _("immediate value"),
5275 operands[0].qualifier = AARCH64_OPND_QLF_X;
5279 /* LDR Wt, label | =value
5280 As a convenience assemblers will typically permit the notation
5281 "=value" in conjunction with the pc-relative literal load instructions
5282 to automatically place an immediate value or symbolic address in a
5283 nearby literal pool and generate a hidden label which references it.
5284 ISREG has been set to 0 in the case of =value. */
5285 if (instr->gen_lit_pool
5286 && (op == OP_LDR_LIT || op == OP_LDRV_LIT || op == OP_LDRSW_LIT))
5288 int size = aarch64_get_qualifier_esize (operands[0].qualifier);
5289 if (op == OP_LDRSW_LIT)
5291 if (instr->reloc.exp.X_op != O_constant
5292 && instr->reloc.exp.X_op != O_big
5293 && instr->reloc.exp.X_op != O_symbol)
5295 record_operand_error (opcode, 1,
5296 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
5297 _("constant expression expected"));
5300 if (! add_to_lit_pool (&instr->reloc.exp, size))
5302 record_operand_error (opcode, 1,
5303 AARCH64_OPDE_OTHER_ERROR,
5304 _("literal pool insertion failed"));
5310 /* Allow MOVI V0.16B, 97, LSL 0, although the preferred architectural
5311 syntax requires that the LSL shifter can only be used when the
5312 destination register has the shape of 4H, 8H, 2S or 4S. */
5313 if (op == OP_V_MOVI_B && operands[1].shifter.kind == AARCH64_MOD_LSL
5314 && (operands[0].qualifier == AARCH64_OPND_QLF_V_8B
5315 || operands[0].qualifier == AARCH64_OPND_QLF_V_16B))
5317 if (operands[1].shifter.amount != 0)
5319 record_operand_error (opcode, 1,
5320 AARCH64_OPDE_OTHER_ERROR,
5321 _("shift amount non-zero"));
5324 operands[1].shifter.kind = AARCH64_MOD_NONE;
5325 operands[1].qualifier = AARCH64_OPND_QLF_NIL;
5331 Unsigned Extend Byte|Halfword|Word: UXT[BH] is architectural alias
5332 for UBFM Wd,Wn,#0,#7|15, while UXTW is pseudo instruction which is
5333 encoded using ORR Wd, WZR, Wn (MOV Wd,Wn).
5334 A programmer-friendly assembler should accept a destination Xd in
5335 place of Wd, however that is not the preferred form for disassembly.
5337 if ((op == OP_UXTB || op == OP_UXTH || op == OP_UXTW)
5338 && operands[1].qualifier == AARCH64_OPND_QLF_W
5339 && operands[0].qualifier == AARCH64_OPND_QLF_X)
5340 operands[0].qualifier = AARCH64_OPND_QLF_W;
5345 /* In the 64-bit form, the final register operand is written as Wm
5346 for all but the (possibly omitted) UXTX/LSL and SXTX
5348 As a programmer-friendly assembler, we accept e.g.
5349 ADDS <Xd>, <Xn|SP>, <Xm>{, UXTB {#<amount>}} and change it to
5350 ADDS <Xd>, <Xn|SP>, <Wm>{, UXTB {#<amount>}}. */
5351 int idx = aarch64_operand_index (opcode->operands,
5352 AARCH64_OPND_Rm_EXT);
5353 gas_assert (idx == 1 || idx == 2);
5354 if (operands[0].qualifier == AARCH64_OPND_QLF_X
5355 && operands[idx].qualifier == AARCH64_OPND_QLF_X
5356 && operands[idx].shifter.kind != AARCH64_MOD_LSL
5357 && operands[idx].shifter.kind != AARCH64_MOD_UXTX
5358 && operands[idx].shifter.kind != AARCH64_MOD_SXTX)
5359 operands[idx].qualifier = AARCH64_OPND_QLF_W;
5367 DEBUG_TRACE ("exit with SUCCESS");
5371 /* A wrapper function to interface with libopcodes on encoding and
5372 record the error message if there is any.
5374 Return TRUE on success; otherwise return FALSE. */
5377 do_encode (const aarch64_opcode *opcode, aarch64_inst *instr,
5380 aarch64_operand_error error_info;
5381 error_info.kind = AARCH64_OPDE_NIL;
5382 if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
5386 gas_assert (error_info.kind != AARCH64_OPDE_NIL);
5387 record_operand_error_info (opcode, &error_info);
5392 #ifdef DEBUG_AARCH64
5394 dump_opcode_operands (const aarch64_opcode *opcode)
5397 while (opcode->operands[i] != AARCH64_OPND_NIL)
5399 aarch64_verbose ("\t\t opnd%d: %s", i,
5400 aarch64_get_operand_name (opcode->operands[i])[0] != '\0'
5401 ? aarch64_get_operand_name (opcode->operands[i])
5402 : aarch64_get_operand_desc (opcode->operands[i]));
5406 #endif /* DEBUG_AARCH64 */
5408 /* This is the guts of the machine-dependent assembler. STR points to a
5409 machine dependent instruction. This function is supposed to emit
5410 the frags/bytes it assembles to. */
5413 md_assemble (char *str)
5416 templates *template;
5417 aarch64_opcode *opcode;
5418 aarch64_inst *inst_base;
5419 unsigned saved_cond;
5421 /* Align the previous label if needed. */
5422 if (last_label_seen != NULL)
5424 symbol_set_frag (last_label_seen, frag_now);
5425 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
5426 S_SET_SEGMENT (last_label_seen, now_seg);
5429 inst.reloc.type = BFD_RELOC_UNUSED;
5431 DEBUG_TRACE ("\n\n");
5432 DEBUG_TRACE ("==============================");
5433 DEBUG_TRACE ("Enter md_assemble with %s", str);
5435 template = opcode_lookup (&p);
5438 /* It wasn't an instruction, but it might be a register alias of
5439 the form alias .req reg directive. */
5440 if (!create_register_alias (str, p))
5441 as_bad (_("unknown mnemonic `%s' -- `%s'"), get_mnemonic_name (str),
5446 skip_whitespace (p);
5449 as_bad (_("unexpected comma after the mnemonic name `%s' -- `%s'"),
5450 get_mnemonic_name (str), str);
5454 init_operand_error_report ();
5456 saved_cond = inst.cond;
5457 reset_aarch64_instruction (&inst);
5458 inst.cond = saved_cond;
5460 /* Iterate through all opcode entries with the same mnemonic name. */
5463 opcode = template->opcode;
5465 DEBUG_TRACE ("opcode %s found", opcode->name);
5466 #ifdef DEBUG_AARCH64
5468 dump_opcode_operands (opcode);
5469 #endif /* DEBUG_AARCH64 */
5471 /* Check that this instruction is supported for this CPU. */
5472 if (!opcode->avariant
5473 || !AARCH64_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
5475 as_bad (_("selected processor does not support `%s'"), str);
5479 mapping_state (MAP_INSN);
5481 inst_base = &inst.base;
5482 inst_base->opcode = opcode;
5484 /* Truly conditionally executed instructions, e.g. b.cond. */
5485 if (opcode->flags & F_COND)
5487 gas_assert (inst.cond != COND_ALWAYS);
5488 inst_base->cond = get_cond_from_value (inst.cond);
5489 DEBUG_TRACE ("condition found %s", inst_base->cond->names[0]);
5491 else if (inst.cond != COND_ALWAYS)
5493 /* It shouldn't arrive here, where the assembly looks like a
5494 conditional instruction but the found opcode is unconditional. */
5499 if (parse_operands (p, opcode)
5500 && programmer_friendly_fixup (&inst)
5501 && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
5503 if (inst.reloc.type == BFD_RELOC_UNUSED
5504 || !inst.reloc.need_libopcodes_p)
5508 /* If there is relocation generated for the instruction,
5509 store the instruction information for the future fix-up. */
5510 struct aarch64_inst *copy;
5511 gas_assert (inst.reloc.type != BFD_RELOC_UNUSED);
5512 if ((copy = xmalloc (sizeof (struct aarch64_inst))) == NULL)
5514 memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
5520 template = template->next;
5521 if (template != NULL)
5523 reset_aarch64_instruction (&inst);
5524 inst.cond = saved_cond;
5527 while (template != NULL);
5529 /* Issue the error messages if any. */
5530 output_operand_error_report (str);
5533 /* Various frobbings of labels and their addresses. */
5536 aarch64_start_line_hook (void)
5538 last_label_seen = NULL;
5542 aarch64_frob_label (symbolS * sym)
5544 last_label_seen = sym;
5546 dwarf2_emit_label (sym);
5550 aarch64_data_in_code (void)
5552 if (!strncmp (input_line_pointer + 1, "data:", 5))
5554 *input_line_pointer = '/';
5555 input_line_pointer += 5;
5556 *input_line_pointer = 0;
5564 aarch64_canonicalize_symbol_name (char *name)
5568 if ((len = strlen (name)) > 5 && streq (name + len - 5, "/data"))
5569 *(name + len - 5) = 0;
5574 /* Table of all register names defined by default. The user can
5575 define additional names with .req. Note that all register names
5576 should appear in both upper and lowercase variants. Some registers
5577 also have mixed-case names. */
5579 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
5580 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
5581 #define REGSET31(p,t) \
5582 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
5583 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
5584 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
5585 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t), \
5586 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
5587 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
5588 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
5589 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t)
5590 #define REGSET(p,t) \
5591 REGSET31(p,t), REGNUM(p,31,t)
5593 /* These go into aarch64_reg_hsh hash-table. */
5594 static const reg_entry reg_names[] = {
5595 /* Integer registers. */
5596 REGSET31 (x, R_64), REGSET31 (X, R_64),
5597 REGSET31 (w, R_32), REGSET31 (W, R_32),
5599 REGDEF (wsp, 31, SP_32), REGDEF (WSP, 31, SP_32),
5600 REGDEF (sp, 31, SP_64), REGDEF (SP, 31, SP_64),
5602 REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
5603 REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
5605 /* Coprocessor register numbers. */
5606 REGSET (c, CN), REGSET (C, CN),
5608 /* Floating-point single precision registers. */
5609 REGSET (s, FP_S), REGSET (S, FP_S),
5611 /* Floating-point double precision registers. */
5612 REGSET (d, FP_D), REGSET (D, FP_D),
5614 /* Floating-point half precision registers. */
5615 REGSET (h, FP_H), REGSET (H, FP_H),
5617 /* Floating-point byte precision registers. */
5618 REGSET (b, FP_B), REGSET (B, FP_B),
5620 /* Floating-point quad precision registers. */
5621 REGSET (q, FP_Q), REGSET (Q, FP_Q),
5623 /* FP/SIMD registers. */
5624 REGSET (v, VN), REGSET (V, VN),
5639 #define B(a,b,c,d) (((a) << 3) | ((b) << 2) | ((c) << 1) | (d))
5640 static const asm_nzcv nzcv_names[] = {
5641 {"nzcv", B (n, z, c, v)},
5642 {"nzcV", B (n, z, c, V)},
5643 {"nzCv", B (n, z, C, v)},
5644 {"nzCV", B (n, z, C, V)},
5645 {"nZcv", B (n, Z, c, v)},
5646 {"nZcV", B (n, Z, c, V)},
5647 {"nZCv", B (n, Z, C, v)},
5648 {"nZCV", B (n, Z, C, V)},
5649 {"Nzcv", B (N, z, c, v)},
5650 {"NzcV", B (N, z, c, V)},
5651 {"NzCv", B (N, z, C, v)},
5652 {"NzCV", B (N, z, C, V)},
5653 {"NZcv", B (N, Z, c, v)},
5654 {"NZcV", B (N, Z, c, V)},
5655 {"NZCv", B (N, Z, C, v)},
5656 {"NZCV", B (N, Z, C, V)}
5669 /* MD interface: bits in the object file. */
5671 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5672 for use in the a.out file, and stores them in the array pointed to by buf.
5673 This knows about the endian-ness of the target machine and does
5674 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5675 2 (short) and 4 (long) Floating numbers are put out as a series of
5676 LITTLENUMS (shorts, here at least). */
5679 md_number_to_chars (char *buf, valueT val, int n)
5681 if (target_big_endian)
5682 number_to_chars_bigendian (buf, val, n);
5684 number_to_chars_littleendian (buf, val, n);
5687 /* MD interface: Sections. */
5689 /* Estimate the size of a frag before relaxing. Assume everything fits in
5693 md_estimate_size_before_relax (fragS * fragp, segT segtype ATTRIBUTE_UNUSED)
5699 /* Round up a section size to the appropriate boundary. */
5702 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
5707 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
5708 of an rs_align_code fragment. */
5711 aarch64_handle_align (fragS * fragP)
5713 /* NOP = d503201f */
5714 /* AArch64 instructions are always little-endian. */
5715 static char const aarch64_noop[4] = { 0x1f, 0x20, 0x03, 0xd5 };
5717 int bytes, fix, noop_size;
5721 if (fragP->fr_type != rs_align_code)
5724 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
5725 p = fragP->fr_literal + fragP->fr_fix;
5728 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
5729 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
5732 gas_assert (fragP->tc_frag_data.recorded);
5735 noop = aarch64_noop;
5736 noop_size = sizeof (aarch64_noop);
5737 fragP->fr_var = noop_size;
5739 if (bytes & (noop_size - 1))
5741 fix = bytes & (noop_size - 1);
5743 insert_data_mapping_symbol (MAP_INSN, fragP->fr_fix, fragP, fix);
5750 while (bytes >= noop_size)
5752 memcpy (p, noop, noop_size);
5758 fragP->fr_fix += fix;
5761 /* Called from md_do_align. Used to create an alignment
5762 frag in a code section. */
5765 aarch64_frag_align_code (int n, int max)
5769 /* We assume that there will never be a requirement
5770 to support alignments greater than x bytes. */
5771 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
5773 ("alignments greater than %d bytes not supported in .text sections"),
5774 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
5776 p = frag_var (rs_align_code,
5777 MAX_MEM_FOR_RS_ALIGN_CODE,
5779 (relax_substateT) max,
5780 (symbolS *) NULL, (offsetT) n, (char *) NULL);
5784 /* Perform target specific initialisation of a frag.
5785 Note - despite the name this initialisation is not done when the frag
5786 is created, but only when its type is assigned. A frag can be created
5787 and used a long time before its type is set, so beware of assuming that
5788 this initialisationis performed first. */
5792 aarch64_init_frag (fragS * fragP ATTRIBUTE_UNUSED,
5793 int max_chars ATTRIBUTE_UNUSED)
5797 #else /* OBJ_ELF is defined. */
5799 aarch64_init_frag (fragS * fragP, int max_chars)
5801 /* Record a mapping symbol for alignment frags. We will delete this
5802 later if the alignment ends up empty. */
5803 if (!fragP->tc_frag_data.recorded)
5805 fragP->tc_frag_data.recorded = 1;
5806 switch (fragP->fr_type)
5811 mapping_state_2 (MAP_DATA, max_chars);
5814 mapping_state_2 (MAP_INSN, max_chars);
5822 /* Initialize the DWARF-2 unwind information for this procedure. */
5825 tc_aarch64_frame_initial_instructions (void)
5827 cfi_add_CFA_def_cfa (REG_SP, 0);
5829 #endif /* OBJ_ELF */
5831 /* Convert REGNAME to a DWARF-2 register number. */
5834 tc_aarch64_regname_to_dw2regnum (char *regname)
5836 const reg_entry *reg = parse_reg (®name);
5842 case REG_TYPE_SP_32:
5843 case REG_TYPE_SP_64:
5858 /* MD interface: Symbol and relocation handling. */
5860 /* Return the address within the segment that a PC-relative fixup is
5861 relative to. For AArch64 PC-relative fixups applied to instructions
5862 are generally relative to the location plus AARCH64_PCREL_OFFSET bytes. */
5865 md_pcrel_from_section (fixS * fixP, segT seg)
5867 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
5869 /* If this is pc-relative and we are going to emit a relocation
5870 then we just want to put out any pipeline compensation that the linker
5871 will need. Otherwise we want to use the calculated base. */
5873 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5874 || aarch64_force_relocation (fixP)))
5877 /* AArch64 should be consistent for all pc-relative relocations. */
5878 return base + AARCH64_PCREL_OFFSET;
5881 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5882 Otherwise we have no need to default values of symbols. */
5885 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
5888 if (name[0] == '_' && name[1] == 'G'
5889 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5893 if (symbol_find (name))
5894 as_bad (_("GOT already in the symbol table"));
5896 GOT_symbol = symbol_new (name, undefined_section,
5897 (valueT) 0, &zero_address_frag);
5907 /* Return non-zero if the indicated VALUE has overflowed the maximum
5908 range expressible by a unsigned number with the indicated number of
5912 unsigned_overflow (valueT value, unsigned bits)
5915 if (bits >= sizeof (valueT) * 8)
5917 lim = (valueT) 1 << bits;
5918 return (value >= lim);
5922 /* Return non-zero if the indicated VALUE has overflowed the maximum
5923 range expressible by an signed number with the indicated number of
5927 signed_overflow (offsetT value, unsigned bits)
5930 if (bits >= sizeof (offsetT) * 8)
5932 lim = (offsetT) 1 << (bits - 1);
5933 return (value < -lim || value >= lim);
5936 /* Given an instruction in *INST, which is expected to be a scaled, 12-bit,
5937 unsigned immediate offset load/store instruction, try to encode it as
5938 an unscaled, 9-bit, signed immediate offset load/store instruction.
5939 Return TRUE if it is successful; otherwise return FALSE.
5941 As a programmer-friendly assembler, LDUR/STUR instructions can be generated
5942 in response to the standard LDR/STR mnemonics when the immediate offset is
5943 unambiguous, i.e. when it is negative or unaligned. */
5946 try_to_encode_as_unscaled_ldst (aarch64_inst *instr)
5949 enum aarch64_op new_op;
5950 const aarch64_opcode *new_opcode;
5952 gas_assert (instr->opcode->iclass == ldst_pos);
5954 switch (instr->opcode->op)
5956 case OP_LDRB_POS:new_op = OP_LDURB; break;
5957 case OP_STRB_POS: new_op = OP_STURB; break;
5958 case OP_LDRSB_POS: new_op = OP_LDURSB; break;
5959 case OP_LDRH_POS: new_op = OP_LDURH; break;
5960 case OP_STRH_POS: new_op = OP_STURH; break;
5961 case OP_LDRSH_POS: new_op = OP_LDURSH; break;
5962 case OP_LDR_POS: new_op = OP_LDUR; break;
5963 case OP_STR_POS: new_op = OP_STUR; break;
5964 case OP_LDRF_POS: new_op = OP_LDURV; break;
5965 case OP_STRF_POS: new_op = OP_STURV; break;
5966 case OP_LDRSW_POS: new_op = OP_LDURSW; break;
5967 case OP_PRFM_POS: new_op = OP_PRFUM; break;
5968 default: new_op = OP_NIL; break;
5971 if (new_op == OP_NIL)
5974 new_opcode = aarch64_get_opcode (new_op);
5975 gas_assert (new_opcode != NULL);
5977 DEBUG_TRACE ("Check programmer-friendly STURB/LDURB -> STRB/LDRB: %d == %d",
5978 instr->opcode->op, new_opcode->op);
5980 aarch64_replace_opcode (instr, new_opcode);
5982 /* Clear up the ADDR_SIMM9's qualifier; otherwise the
5983 qualifier matching may fail because the out-of-date qualifier will
5984 prevent the operand being updated with a new and correct qualifier. */
5985 idx = aarch64_operand_index (instr->opcode->operands,
5986 AARCH64_OPND_ADDR_SIMM9);
5987 gas_assert (idx == 1);
5988 instr->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
5990 DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
5992 if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
5998 /* Called by fix_insn to fix a MOV immediate alias instruction.
6000 Operand for a generic move immediate instruction, which is an alias
6001 instruction that generates a single MOVZ, MOVN or ORR instruction to loads
6002 a 32-bit/64-bit immediate value into general register. An assembler error
6003 shall result if the immediate cannot be created by a single one of these
6004 instructions. If there is a choice, then to ensure reversability an
6005 assembler must prefer a MOVZ to MOVN, and MOVZ or MOVN to ORR. */
6008 fix_mov_imm_insn (fixS *fixP, char *buf, aarch64_inst *instr, offsetT value)
6010 const aarch64_opcode *opcode;
6012 /* Need to check if the destination is SP/ZR. The check has to be done
6013 before any aarch64_replace_opcode. */
6014 int try_mov_wide_p = !aarch64_stack_pointer_p (&instr->operands[0]);
6015 int try_mov_bitmask_p = !aarch64_zero_register_p (&instr->operands[0]);
6017 instr->operands[1].imm.value = value;
6018 instr->operands[1].skip = 0;
6022 /* Try the MOVZ alias. */
6023 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
6024 aarch64_replace_opcode (instr, opcode);
6025 if (aarch64_opcode_encode (instr->opcode, instr,
6026 &instr->value, NULL, NULL))
6028 put_aarch64_insn (buf, instr->value);
6031 /* Try the MOVK alias. */
6032 opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
6033 aarch64_replace_opcode (instr, opcode);
6034 if (aarch64_opcode_encode (instr->opcode, instr,
6035 &instr->value, NULL, NULL))
6037 put_aarch64_insn (buf, instr->value);
6042 if (try_mov_bitmask_p)
6044 /* Try the ORR alias. */
6045 opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
6046 aarch64_replace_opcode (instr, opcode);
6047 if (aarch64_opcode_encode (instr->opcode, instr,
6048 &instr->value, NULL, NULL))
6050 put_aarch64_insn (buf, instr->value);
6055 as_bad_where (fixP->fx_file, fixP->fx_line,
6056 _("immediate cannot be moved by a single instruction"));
6059 /* An instruction operand which is immediate related may have symbol used
6060 in the assembly, e.g.
6063 .set u32, 0x00ffff00
6065 At the time when the assembly instruction is parsed, a referenced symbol,
6066 like 'u32' in the above example may not have been seen; a fixS is created
6067 in such a case and is handled here after symbols have been resolved.
6068 Instruction is fixed up with VALUE using the information in *FIXP plus
6069 extra information in FLAGS.
6071 This function is called by md_apply_fix to fix up instructions that need
6072 a fix-up described above but does not involve any linker-time relocation. */
6075 fix_insn (fixS *fixP, uint32_t flags, offsetT value)
6079 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6080 enum aarch64_opnd opnd = fixP->tc_fix_data.opnd;
6081 aarch64_inst *new_inst = fixP->tc_fix_data.inst;
6085 /* Now the instruction is about to be fixed-up, so the operand that
6086 was previously marked as 'ignored' needs to be unmarked in order
6087 to get the encoding done properly. */
6088 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6089 new_inst->operands[idx].skip = 0;
6092 gas_assert (opnd != AARCH64_OPND_NIL);
6096 case AARCH64_OPND_EXCEPTION:
6097 if (unsigned_overflow (value, 16))
6098 as_bad_where (fixP->fx_file, fixP->fx_line,
6099 _("immediate out of range"));
6100 insn = get_aarch64_insn (buf);
6101 insn |= encode_svc_imm (value);
6102 put_aarch64_insn (buf, insn);
6105 case AARCH64_OPND_AIMM:
6106 /* ADD or SUB with immediate.
6107 NOTE this assumes we come here with a add/sub shifted reg encoding
6108 3 322|2222|2 2 2 21111 111111
6109 1 098|7654|3 2 1 09876 543210 98765 43210
6110 0b000000 sf 000|1011|shift 0 Rm imm6 Rn Rd ADD
6111 2b000000 sf 010|1011|shift 0 Rm imm6 Rn Rd ADDS
6112 4b000000 sf 100|1011|shift 0 Rm imm6 Rn Rd SUB
6113 6b000000 sf 110|1011|shift 0 Rm imm6 Rn Rd SUBS
6115 3 322|2222|2 2 221111111111
6116 1 098|7654|3 2 109876543210 98765 43210
6117 11000000 sf 001|0001|shift imm12 Rn Rd ADD
6118 31000000 sf 011|0001|shift imm12 Rn Rd ADDS
6119 51000000 sf 101|0001|shift imm12 Rn Rd SUB
6120 71000000 sf 111|0001|shift imm12 Rn Rd SUBS
6121 Fields sf Rn Rd are already set. */
6122 insn = get_aarch64_insn (buf);
6126 insn = reencode_addsub_switch_add_sub (insn);
6130 if ((flags & FIXUP_F_HAS_EXPLICIT_SHIFT) == 0
6131 && unsigned_overflow (value, 12))
6133 /* Try to shift the value by 12 to make it fit. */
6134 if (((value >> 12) << 12) == value
6135 && ! unsigned_overflow (value, 12 + 12))
6138 insn |= encode_addsub_imm_shift_amount (1);
6142 if (unsigned_overflow (value, 12))
6143 as_bad_where (fixP->fx_file, fixP->fx_line,
6144 _("immediate out of range"));
6146 insn |= encode_addsub_imm (value);
6148 put_aarch64_insn (buf, insn);
6151 case AARCH64_OPND_SIMD_IMM:
6152 case AARCH64_OPND_SIMD_IMM_SFT:
6153 case AARCH64_OPND_LIMM:
6154 /* Bit mask immediate. */
6155 gas_assert (new_inst != NULL);
6156 idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
6157 new_inst->operands[idx].imm.value = value;
6158 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6159 &new_inst->value, NULL, NULL))
6160 put_aarch64_insn (buf, new_inst->value);
6162 as_bad_where (fixP->fx_file, fixP->fx_line,
6163 _("invalid immediate"));
6166 case AARCH64_OPND_HALF:
6167 /* 16-bit unsigned immediate. */
6168 if (unsigned_overflow (value, 16))
6169 as_bad_where (fixP->fx_file, fixP->fx_line,
6170 _("immediate out of range"));
6171 insn = get_aarch64_insn (buf);
6172 insn |= encode_movw_imm (value & 0xffff);
6173 put_aarch64_insn (buf, insn);
6176 case AARCH64_OPND_IMM_MOV:
6177 /* Operand for a generic move immediate instruction, which is
6178 an alias instruction that generates a single MOVZ, MOVN or ORR
6179 instruction to loads a 32-bit/64-bit immediate value into general
6180 register. An assembler error shall result if the immediate cannot be
6181 created by a single one of these instructions. If there is a choice,
6182 then to ensure reversability an assembler must prefer a MOVZ to MOVN,
6183 and MOVZ or MOVN to ORR. */
6184 gas_assert (new_inst != NULL);
6185 fix_mov_imm_insn (fixP, buf, new_inst, value);
6188 case AARCH64_OPND_ADDR_SIMM7:
6189 case AARCH64_OPND_ADDR_SIMM9:
6190 case AARCH64_OPND_ADDR_SIMM9_2:
6191 case AARCH64_OPND_ADDR_UIMM12:
6192 /* Immediate offset in an address. */
6193 insn = get_aarch64_insn (buf);
6195 gas_assert (new_inst != NULL && new_inst->value == insn);
6196 gas_assert (new_inst->opcode->operands[1] == opnd
6197 || new_inst->opcode->operands[2] == opnd);
6199 /* Get the index of the address operand. */
6200 if (new_inst->opcode->operands[1] == opnd)
6201 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
6204 /* e.g. LDP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
6207 /* Update the resolved offset value. */
6208 new_inst->operands[idx].addr.offset.imm = value;
6210 /* Encode/fix-up. */
6211 if (aarch64_opcode_encode (new_inst->opcode, new_inst,
6212 &new_inst->value, NULL, NULL))
6214 put_aarch64_insn (buf, new_inst->value);
6217 else if (new_inst->opcode->iclass == ldst_pos
6218 && try_to_encode_as_unscaled_ldst (new_inst))
6220 put_aarch64_insn (buf, new_inst->value);
6224 as_bad_where (fixP->fx_file, fixP->fx_line,
6225 _("immediate offset out of range"));
6230 as_fatal (_("unhandled operand code %d"), opnd);
6234 /* Apply a fixup (fixP) to segment data, once it has been determined
6235 by our caller that we have all the info we need to fix it up.
6237 Parameter valP is the pointer to the value of the bits. */
6240 md_apply_fix (fixS * fixP, valueT * valP, segT seg)
6242 offsetT value = *valP;
6244 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
6246 unsigned flags = fixP->fx_addnumber;
6248 DEBUG_TRACE ("\n\n");
6249 DEBUG_TRACE ("~~~~~~~~~~~~~~~~~~~~~~~~~");
6250 DEBUG_TRACE ("Enter md_apply_fix");
6252 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
6254 /* Note whether this will delete the relocation. */
6256 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
6259 /* Process the relocations. */
6260 switch (fixP->fx_r_type)
6262 case BFD_RELOC_NONE:
6263 /* This will need to go in the object file. */
6268 case BFD_RELOC_8_PCREL:
6269 if (fixP->fx_done || !seg->use_rela_p)
6270 md_number_to_chars (buf, value, 1);
6274 case BFD_RELOC_16_PCREL:
6275 if (fixP->fx_done || !seg->use_rela_p)
6276 md_number_to_chars (buf, value, 2);
6280 case BFD_RELOC_32_PCREL:
6281 if (fixP->fx_done || !seg->use_rela_p)
6282 md_number_to_chars (buf, value, 4);
6286 case BFD_RELOC_64_PCREL:
6287 if (fixP->fx_done || !seg->use_rela_p)
6288 md_number_to_chars (buf, value, 8);
6291 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6292 /* We claim that these fixups have been processed here, even if
6293 in fact we generate an error because we do not have a reloc
6294 for them, so tc_gen_reloc() will reject them. */
6296 if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy))
6298 as_bad_where (fixP->fx_file, fixP->fx_line,
6299 _("undefined symbol %s used as an immediate value"),
6300 S_GET_NAME (fixP->fx_addsy));
6301 goto apply_fix_return;
6303 fix_insn (fixP, flags, value);
6306 case BFD_RELOC_AARCH64_LD_LO19_PCREL:
6308 as_bad_where (fixP->fx_file, fixP->fx_line,
6309 _("pc-relative load offset not word aligned"));
6310 if (signed_overflow (value, 21))
6311 as_bad_where (fixP->fx_file, fixP->fx_line,
6312 _("pc-relative load offset out of range"));
6313 if (fixP->fx_done || !seg->use_rela_p)
6315 insn = get_aarch64_insn (buf);
6316 insn |= encode_ld_lit_ofs_19 (value >> 2);
6317 put_aarch64_insn (buf, insn);
6321 case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
6322 if (signed_overflow (value, 21))
6323 as_bad_where (fixP->fx_file, fixP->fx_line,
6324 _("pc-relative address offset out of range"));
6325 if (fixP->fx_done || !seg->use_rela_p)
6327 insn = get_aarch64_insn (buf);
6328 insn |= encode_adr_imm (value);
6329 put_aarch64_insn (buf, insn);
6333 case BFD_RELOC_AARCH64_BRANCH19:
6335 as_bad_where (fixP->fx_file, fixP->fx_line,
6336 _("conditional branch target not word aligned"));
6337 if (signed_overflow (value, 21))
6338 as_bad_where (fixP->fx_file, fixP->fx_line,
6339 _("conditional branch out of range"));
6340 if (fixP->fx_done || !seg->use_rela_p)
6342 insn = get_aarch64_insn (buf);
6343 insn |= encode_cond_branch_ofs_19 (value >> 2);
6344 put_aarch64_insn (buf, insn);
6348 case BFD_RELOC_AARCH64_TSTBR14:
6350 as_bad_where (fixP->fx_file, fixP->fx_line,
6351 _("conditional branch target not word aligned"));
6352 if (signed_overflow (value, 16))
6353 as_bad_where (fixP->fx_file, fixP->fx_line,
6354 _("conditional branch out of range"));
6355 if (fixP->fx_done || !seg->use_rela_p)
6357 insn = get_aarch64_insn (buf);
6358 insn |= encode_tst_branch_ofs_14 (value >> 2);
6359 put_aarch64_insn (buf, insn);
6363 case BFD_RELOC_AARCH64_JUMP26:
6364 case BFD_RELOC_AARCH64_CALL26:
6366 as_bad_where (fixP->fx_file, fixP->fx_line,
6367 _("branch target not word aligned"));
6368 if (signed_overflow (value, 28))
6369 as_bad_where (fixP->fx_file, fixP->fx_line, _("branch out of range"));
6370 if (fixP->fx_done || !seg->use_rela_p)
6372 insn = get_aarch64_insn (buf);
6373 insn |= encode_branch_ofs_26 (value >> 2);
6374 put_aarch64_insn (buf, insn);
6378 case BFD_RELOC_AARCH64_MOVW_G0:
6379 case BFD_RELOC_AARCH64_MOVW_G0_S:
6380 case BFD_RELOC_AARCH64_MOVW_G0_NC:
6383 case BFD_RELOC_AARCH64_MOVW_G1:
6384 case BFD_RELOC_AARCH64_MOVW_G1_S:
6385 case BFD_RELOC_AARCH64_MOVW_G1_NC:
6388 case BFD_RELOC_AARCH64_MOVW_G2:
6389 case BFD_RELOC_AARCH64_MOVW_G2_S:
6390 case BFD_RELOC_AARCH64_MOVW_G2_NC:
6393 case BFD_RELOC_AARCH64_MOVW_G3:
6396 if (fixP->fx_done || !seg->use_rela_p)
6398 insn = get_aarch64_insn (buf);
6402 /* REL signed addend must fit in 16 bits */
6403 if (signed_overflow (value, 16))
6404 as_bad_where (fixP->fx_file, fixP->fx_line,
6405 _("offset out of range"));
6409 /* Check for overflow and scale. */
6410 switch (fixP->fx_r_type)
6412 case BFD_RELOC_AARCH64_MOVW_G0:
6413 case BFD_RELOC_AARCH64_MOVW_G1:
6414 case BFD_RELOC_AARCH64_MOVW_G2:
6415 case BFD_RELOC_AARCH64_MOVW_G3:
6416 if (unsigned_overflow (value, scale + 16))
6417 as_bad_where (fixP->fx_file, fixP->fx_line,
6418 _("unsigned value out of range"));
6420 case BFD_RELOC_AARCH64_MOVW_G0_S:
6421 case BFD_RELOC_AARCH64_MOVW_G1_S:
6422 case BFD_RELOC_AARCH64_MOVW_G2_S:
6423 /* NOTE: We can only come here with movz or movn. */
6424 if (signed_overflow (value, scale + 16))
6425 as_bad_where (fixP->fx_file, fixP->fx_line,
6426 _("signed value out of range"));
6429 /* Force use of MOVN. */
6431 insn = reencode_movzn_to_movn (insn);
6435 /* Force use of MOVZ. */
6436 insn = reencode_movzn_to_movz (insn);
6440 /* Unchecked relocations. */
6446 /* Insert value into MOVN/MOVZ/MOVK instruction. */
6447 insn |= encode_movw_imm (value & 0xffff);
6449 put_aarch64_insn (buf, insn);
6453 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6454 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6455 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6456 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6457 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6458 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6459 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6460 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6461 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6462 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6463 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6464 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6465 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE:
6466 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6467 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6468 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6469 /* Should always be exported to object file, see
6470 aarch64_force_relocation(). */
6471 gas_assert (!fixP->fx_done);
6472 gas_assert (seg->use_rela_p);
6475 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6476 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6477 case BFD_RELOC_AARCH64_ADD_LO12:
6478 case BFD_RELOC_AARCH64_LDST8_LO12:
6479 case BFD_RELOC_AARCH64_LDST16_LO12:
6480 case BFD_RELOC_AARCH64_LDST32_LO12:
6481 case BFD_RELOC_AARCH64_LDST64_LO12:
6482 case BFD_RELOC_AARCH64_LDST128_LO12:
6483 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6484 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6485 /* Should always be exported to object file, see
6486 aarch64_force_relocation(). */
6487 gas_assert (!fixP->fx_done);
6488 gas_assert (seg->use_rela_p);
6491 case BFD_RELOC_AARCH64_TLSDESC_ADD:
6492 case BFD_RELOC_AARCH64_TLSDESC_LDR:
6493 case BFD_RELOC_AARCH64_TLSDESC_CALL:
6497 as_bad_where (fixP->fx_file, fixP->fx_line,
6498 _("unexpected %s fixup"),
6499 bfd_get_reloc_code_name (fixP->fx_r_type));
6504 /* Free the allocated the struct aarch64_inst.
6505 N.B. currently there are very limited number of fix-up types actually use
6506 this field, so the impact on the performance should be minimal . */
6507 if (fixP->tc_fix_data.inst != NULL)
6508 free (fixP->tc_fix_data.inst);
6513 /* Translate internal representation of relocation info to BFD target
6517 tc_gen_reloc (asection * section, fixS * fixp)
6520 bfd_reloc_code_real_type code;
6522 reloc = xmalloc (sizeof (arelent));
6524 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
6525 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6526 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6530 if (section->use_rela_p)
6531 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
6533 fixp->fx_offset = reloc->address;
6535 reloc->addend = fixp->fx_offset;
6537 code = fixp->fx_r_type;
6542 code = BFD_RELOC_16_PCREL;
6547 code = BFD_RELOC_32_PCREL;
6552 code = BFD_RELOC_64_PCREL;
6559 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6560 if (reloc->howto == NULL)
6562 as_bad_where (fixp->fx_file, fixp->fx_line,
6564 ("cannot represent %s relocation in this object file format"),
6565 bfd_get_reloc_code_name (code));
6572 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6575 cons_fix_new_aarch64 (fragS * frag, int where, int size, expressionS * exp)
6577 bfd_reloc_code_real_type type;
6581 FIXME: @@ Should look at CPU word size. */
6588 type = BFD_RELOC_16;
6591 type = BFD_RELOC_32;
6594 type = BFD_RELOC_64;
6597 as_bad (_("cannot do %u-byte relocation"), size);
6598 type = BFD_RELOC_UNUSED;
6602 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6606 aarch64_force_relocation (struct fix *fixp)
6608 switch (fixp->fx_r_type)
6610 case BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP:
6611 /* Perform these "immediate" internal relocations
6612 even if the symbol is extern or weak. */
6615 case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
6616 case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
6617 case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
6618 case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
6619 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
6620 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
6621 case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
6622 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
6623 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
6624 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
6625 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
6626 case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
6627 case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE:
6628 case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
6629 case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
6630 case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
6631 case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
6632 case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
6633 case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
6634 case BFD_RELOC_AARCH64_ADD_LO12:
6635 case BFD_RELOC_AARCH64_LDST8_LO12:
6636 case BFD_RELOC_AARCH64_LDST16_LO12:
6637 case BFD_RELOC_AARCH64_LDST32_LO12:
6638 case BFD_RELOC_AARCH64_LDST64_LO12:
6639 case BFD_RELOC_AARCH64_LDST128_LO12:
6640 /* Always leave these relocations for the linker. */
6647 return generic_force_reloc (fixp);
6653 elf64_aarch64_target_format (void)
6655 if (target_big_endian)
6656 return "elf64-bigaarch64";
6658 return "elf64-littleaarch64";
6662 aarch64elf_frob_symbol (symbolS * symp, int *puntp)
6664 elf_frob_symbol (symp, puntp);
6668 /* MD interface: Finalization. */
6670 /* A good place to do this, although this was probably not intended
6671 for this kind of use. We need to dump the literal pool before
6672 references are made to a null symbol pointer. */
6675 aarch64_cleanup (void)
6679 for (pool = list_of_pools; pool; pool = pool->next)
6681 /* Put it at the end of the relevant section. */
6682 subseg_set (pool->section, pool->sub_section);
6688 /* Remove any excess mapping symbols generated for alignment frags in
6689 SEC. We may have created a mapping symbol before a zero byte
6690 alignment; remove it if there's a mapping symbol after the
6693 check_mapping_symbols (bfd * abfd ATTRIBUTE_UNUSED, asection * sec,
6694 void *dummy ATTRIBUTE_UNUSED)
6696 segment_info_type *seginfo = seg_info (sec);
6699 if (seginfo == NULL || seginfo->frchainP == NULL)
6702 for (fragp = seginfo->frchainP->frch_root;
6703 fragp != NULL; fragp = fragp->fr_next)
6705 symbolS *sym = fragp->tc_frag_data.last_map;
6706 fragS *next = fragp->fr_next;
6708 /* Variable-sized frags have been converted to fixed size by
6709 this point. But if this was variable-sized to start with,
6710 there will be a fixed-size frag after it. So don't handle
6712 if (sym == NULL || next == NULL)
6715 if (S_GET_VALUE (sym) < next->fr_address)
6716 /* Not at the end of this frag. */
6718 know (S_GET_VALUE (sym) == next->fr_address);
6722 if (next->tc_frag_data.first_map != NULL)
6724 /* Next frag starts with a mapping symbol. Discard this
6726 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6730 if (next->fr_next == NULL)
6732 /* This mapping symbol is at the end of the section. Discard
6734 know (next->fr_fix == 0 && next->fr_var == 0);
6735 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
6739 /* As long as we have empty frags without any mapping symbols,
6741 /* If the next frag is non-empty and does not start with a
6742 mapping symbol, then this mapping symbol is required. */
6743 if (next->fr_address != next->fr_next->fr_address)
6746 next = next->fr_next;
6748 while (next != NULL);
6753 /* Adjust the symbol table. */
6756 aarch64_adjust_symtab (void)
6759 /* Remove any overlapping mapping symbols generated by alignment frags. */
6760 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
6761 /* Now do generic ELF adjustments. */
6762 elf_adjust_symtab ();
6767 checked_hash_insert (struct hash_control *table, const char *key, void *value)
6769 const char *hash_err;
6771 hash_err = hash_insert (table, key, value);
6773 printf ("Internal Error: Can't hash %s\n", key);
6777 fill_instruction_hash_table (void)
6779 aarch64_opcode *opcode = aarch64_opcode_table;
6781 while (opcode->name != NULL)
6783 templates *templ, *new_templ;
6784 templ = hash_find (aarch64_ops_hsh, opcode->name);
6786 new_templ = (templates *) xmalloc (sizeof (templates));
6787 new_templ->opcode = opcode;
6788 new_templ->next = NULL;
6791 checked_hash_insert (aarch64_ops_hsh, opcode->name, (void *) new_templ);
6794 new_templ->next = templ->next;
6795 templ->next = new_templ;
6802 convert_to_upper (char *dst, const char *src, size_t num)
6805 for (i = 0; i < num && *src != '\0'; ++i, ++dst, ++src)
6806 *dst = TOUPPER (*src);
6810 /* Assume STR point to a lower-case string, allocate, convert and return
6811 the corresponding upper-case string. */
6812 static inline const char*
6813 get_upper_str (const char *str)
6816 size_t len = strlen (str);
6817 if ((ret = xmalloc (len + 1)) == NULL)
6819 convert_to_upper (ret, str, len);
6823 /* MD interface: Initialization. */
6831 if ((aarch64_ops_hsh = hash_new ()) == NULL
6832 || (aarch64_cond_hsh = hash_new ()) == NULL
6833 || (aarch64_shift_hsh = hash_new ()) == NULL
6834 || (aarch64_sys_regs_hsh = hash_new ()) == NULL
6835 || (aarch64_pstatefield_hsh = hash_new ()) == NULL
6836 || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
6837 || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
6838 || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
6839 || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
6840 || (aarch64_reg_hsh = hash_new ()) == NULL
6841 || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
6842 || (aarch64_nzcv_hsh = hash_new ()) == NULL
6843 || (aarch64_pldop_hsh = hash_new ()) == NULL)
6844 as_fatal (_("virtual memory exhausted"));
6846 fill_instruction_hash_table ();
6848 for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
6849 checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
6850 (void *) (aarch64_sys_regs + i));
6852 for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
6853 checked_hash_insert (aarch64_pstatefield_hsh,
6854 aarch64_pstatefields[i].name,
6855 (void *) (aarch64_pstatefields + i));
6857 for (i = 0; aarch64_sys_regs_ic[i].template != NULL; i++)
6858 checked_hash_insert (aarch64_sys_regs_ic_hsh,
6859 aarch64_sys_regs_ic[i].template,
6860 (void *) (aarch64_sys_regs_ic + i));
6862 for (i = 0; aarch64_sys_regs_dc[i].template != NULL; i++)
6863 checked_hash_insert (aarch64_sys_regs_dc_hsh,
6864 aarch64_sys_regs_dc[i].template,
6865 (void *) (aarch64_sys_regs_dc + i));
6867 for (i = 0; aarch64_sys_regs_at[i].template != NULL; i++)
6868 checked_hash_insert (aarch64_sys_regs_at_hsh,
6869 aarch64_sys_regs_at[i].template,
6870 (void *) (aarch64_sys_regs_at + i));
6872 for (i = 0; aarch64_sys_regs_tlbi[i].template != NULL; i++)
6873 checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
6874 aarch64_sys_regs_tlbi[i].template,
6875 (void *) (aarch64_sys_regs_tlbi + i));
6877 for (i = 0; i < ARRAY_SIZE (reg_names); i++)
6878 checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
6879 (void *) (reg_names + i));
6881 for (i = 0; i < ARRAY_SIZE (nzcv_names); i++)
6882 checked_hash_insert (aarch64_nzcv_hsh, nzcv_names[i].template,
6883 (void *) (nzcv_names + i));
6885 for (i = 0; aarch64_operand_modifiers[i].name != NULL; i++)
6887 const char *name = aarch64_operand_modifiers[i].name;
6888 checked_hash_insert (aarch64_shift_hsh, name,
6889 (void *) (aarch64_operand_modifiers + i));
6890 /* Also hash the name in the upper case. */
6891 checked_hash_insert (aarch64_shift_hsh, get_upper_str (name),
6892 (void *) (aarch64_operand_modifiers + i));
6895 for (i = 0; i < ARRAY_SIZE (aarch64_conds); i++)
6898 /* A condition code may have alias(es), e.g. "cc", "lo" and "ul" are
6899 the same condition code. */
6900 for (j = 0; j < ARRAY_SIZE (aarch64_conds[i].names); ++j)
6902 const char *name = aarch64_conds[i].names[j];
6905 checked_hash_insert (aarch64_cond_hsh, name,
6906 (void *) (aarch64_conds + i));
6907 /* Also hash the name in the upper case. */
6908 checked_hash_insert (aarch64_cond_hsh, get_upper_str (name),
6909 (void *) (aarch64_conds + i));
6913 for (i = 0; i < ARRAY_SIZE (aarch64_barrier_options); i++)
6915 const char *name = aarch64_barrier_options[i].name;
6916 /* Skip xx00 - the unallocated values of option. */
6919 checked_hash_insert (aarch64_barrier_opt_hsh, name,
6920 (void *) (aarch64_barrier_options + i));
6921 /* Also hash the name in the upper case. */
6922 checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
6923 (void *) (aarch64_barrier_options + i));
6926 for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
6928 const char* name = aarch64_prfops[i].name;
6929 /* Skip the unallocated hint encodings. */
6932 checked_hash_insert (aarch64_pldop_hsh, name,
6933 (void *) (aarch64_prfops + i));
6934 /* Also hash the name in the upper case. */
6935 checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
6936 (void *) (aarch64_prfops + i));
6939 /* Set the cpu variant based on the command-line options. */
6941 mcpu_cpu_opt = march_cpu_opt;
6944 mcpu_cpu_opt = &cpu_default;
6946 cpu_variant = *mcpu_cpu_opt;
6948 /* Record the CPU type. */
6949 mach = bfd_mach_aarch64;
6951 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
6954 /* Command line processing. */
6956 const char *md_shortopts = "m:";
6958 #ifdef AARCH64_BI_ENDIAN
6959 #define OPTION_EB (OPTION_MD_BASE + 0)
6960 #define OPTION_EL (OPTION_MD_BASE + 1)
6962 #if TARGET_BYTES_BIG_ENDIAN
6963 #define OPTION_EB (OPTION_MD_BASE + 0)
6965 #define OPTION_EL (OPTION_MD_BASE + 1)
6969 struct option md_longopts[] = {
6971 {"EB", no_argument, NULL, OPTION_EB},
6974 {"EL", no_argument, NULL, OPTION_EL},
6976 {NULL, no_argument, NULL, 0}
6979 size_t md_longopts_size = sizeof (md_longopts);
6981 struct aarch64_option_table
6983 char *option; /* Option name to match. */
6984 char *help; /* Help information. */
6985 int *var; /* Variable to change. */
6986 int value; /* What to change it to. */
6987 char *deprecated; /* If non-null, print this message. */
6990 static struct aarch64_option_table aarch64_opts[] = {
6991 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
6992 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
6994 #ifdef DEBUG_AARCH64
6995 {"mdebug-dump", N_("temporary switch for dumping"), &debug_dump, 1, NULL},
6996 #endif /* DEBUG_AARCH64 */
6997 {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1,
6999 {NULL, NULL, NULL, 0, NULL}
7002 struct aarch64_cpu_option_table
7005 const aarch64_feature_set value;
7006 /* The canonical name of the CPU, or NULL to use NAME converted to upper
7008 const char *canonical_name;
7011 /* This list should, at a minimum, contain all the cpu names
7012 recognized by GCC. */
7013 static const struct aarch64_cpu_option_table aarch64_cpus[] = {
7014 {"all", AARCH64_ANY, NULL},
7015 {"generic", AARCH64_ARCH_V8, NULL},
7017 /* These two are example CPUs supported in GCC, once we have real
7018 CPUs they will be removed. */
7019 {"example-1", AARCH64_ARCH_V8, NULL},
7020 {"example-2", AARCH64_ARCH_V8, NULL},
7022 {NULL, AARCH64_ARCH_NONE, NULL}
7025 struct aarch64_arch_option_table
7028 const aarch64_feature_set value;
7031 /* This list should, at a minimum, contain all the architecture names
7032 recognized by GCC. */
7033 static const struct aarch64_arch_option_table aarch64_archs[] = {
7034 {"all", AARCH64_ANY},
7035 {"armv8-a", AARCH64_ARCH_V8},
7036 {NULL, AARCH64_ARCH_NONE}
7039 /* ISA extensions. */
7040 struct aarch64_option_cpu_value_table
7043 const aarch64_feature_set value;
7046 static const struct aarch64_option_cpu_value_table aarch64_features[] = {
7047 {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
7048 {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
7049 {"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
7050 {NULL, AARCH64_ARCH_NONE}
7053 struct aarch64_long_option_table
7055 char *option; /* Substring to match. */
7056 char *help; /* Help information. */
7057 int (*func) (char *subopt); /* Function to decode sub-option. */
7058 char *deprecated; /* If non-null, print this message. */
7062 aarch64_parse_features (char *str, const aarch64_feature_set **opt_p)
7064 /* We insist on extensions being added before being removed. We achieve
7065 this by using the ADDING_VALUE variable to indicate whether we are
7066 adding an extension (1) or removing it (0) and only allowing it to
7067 change in the order -1 -> 1 -> 0. */
7068 int adding_value = -1;
7069 aarch64_feature_set *ext_set = xmalloc (sizeof (aarch64_feature_set));
7071 /* Copy the feature set, so that we can modify it. */
7075 while (str != NULL && *str != 0)
7077 const struct aarch64_option_cpu_value_table *opt;
7083 as_bad (_("invalid architectural extension"));
7088 ext = strchr (str, '+');
7093 optlen = strlen (str);
7095 if (optlen >= 2 && strncmp (str, "no", 2) == 0)
7097 if (adding_value != 0)
7102 else if (optlen > 0)
7104 if (adding_value == -1)
7106 else if (adding_value != 1)
7108 as_bad (_("must specify extensions to add before specifying "
7109 "those to remove"));
7116 as_bad (_("missing architectural extension"));
7120 gas_assert (adding_value != -1);
7122 for (opt = aarch64_features; opt->name != NULL; opt++)
7123 if (strncmp (opt->name, str, optlen) == 0)
7125 /* Add or remove the extension. */
7127 AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
7129 AARCH64_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
7133 if (opt->name == NULL)
7135 as_bad (_("unknown architectural extension `%s'"), str);
7146 aarch64_parse_cpu (char *str)
7148 const struct aarch64_cpu_option_table *opt;
7149 char *ext = strchr (str, '+');
7155 optlen = strlen (str);
7159 as_bad (_("missing cpu name `%s'"), str);
7163 for (opt = aarch64_cpus; opt->name != NULL; opt++)
7164 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7166 mcpu_cpu_opt = &opt->value;
7168 return aarch64_parse_features (ext, &mcpu_cpu_opt);
7173 as_bad (_("unknown cpu `%s'"), str);
7178 aarch64_parse_arch (char *str)
7180 const struct aarch64_arch_option_table *opt;
7181 char *ext = strchr (str, '+');
7187 optlen = strlen (str);
7191 as_bad (_("missing architecture name `%s'"), str);
7195 for (opt = aarch64_archs; opt->name != NULL; opt++)
7196 if (strlen (opt->name) == optlen && strncmp (str, opt->name, optlen) == 0)
7198 march_cpu_opt = &opt->value;
7200 return aarch64_parse_features (ext, &march_cpu_opt);
7205 as_bad (_("unknown architecture `%s'\n"), str);
7209 static struct aarch64_long_option_table aarch64_long_opts[] = {
7210 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
7211 aarch64_parse_cpu, NULL},
7212 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
7213 aarch64_parse_arch, NULL},
7214 {NULL, NULL, 0, NULL}
7218 md_parse_option (int c, char *arg)
7220 struct aarch64_option_table *opt;
7221 struct aarch64_long_option_table *lopt;
7227 target_big_endian = 1;
7233 target_big_endian = 0;
7238 /* Listing option. Just ignore these, we don't support additional
7243 for (opt = aarch64_opts; opt->option != NULL; opt++)
7245 if (c == opt->option[0]
7246 && ((arg == NULL && opt->option[1] == 0)
7247 || streq (arg, opt->option + 1)))
7249 /* If the option is deprecated, tell the user. */
7250 if (opt->deprecated != NULL)
7251 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
7252 arg ? arg : "", _(opt->deprecated));
7254 if (opt->var != NULL)
7255 *opt->var = opt->value;
7261 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7263 /* These options are expected to have an argument. */
7264 if (c == lopt->option[0]
7266 && strncmp (arg, lopt->option + 1,
7267 strlen (lopt->option + 1)) == 0)
7269 /* If the option is deprecated, tell the user. */
7270 if (lopt->deprecated != NULL)
7271 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
7272 _(lopt->deprecated));
7274 /* Call the sup-option parser. */
7275 return lopt->func (arg + strlen (lopt->option) - 1);
7286 md_show_usage (FILE * fp)
7288 struct aarch64_option_table *opt;
7289 struct aarch64_long_option_table *lopt;
7291 fprintf (fp, _(" AArch64-specific assembler options:\n"));
7293 for (opt = aarch64_opts; opt->option != NULL; opt++)
7294 if (opt->help != NULL)
7295 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
7297 for (lopt = aarch64_long_opts; lopt->option != NULL; lopt++)
7298 if (lopt->help != NULL)
7299 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
7303 -EB assemble code for a big-endian cpu\n"));
7308 -EL assemble code for a little-endian cpu\n"));
7312 /* Parse a .cpu directive. */
7315 s_aarch64_cpu (int ignored ATTRIBUTE_UNUSED)
7317 const struct aarch64_cpu_option_table *opt;
7323 name = input_line_pointer;
7324 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7325 input_line_pointer++;
7326 saved_char = *input_line_pointer;
7327 *input_line_pointer = 0;
7329 ext = strchr (name, '+');
7332 optlen = ext - name;
7334 optlen = strlen (name);
7336 /* Skip the first "all" entry. */
7337 for (opt = aarch64_cpus + 1; opt->name != NULL; opt++)
7338 if (strlen (opt->name) == optlen
7339 && strncmp (name, opt->name, optlen) == 0)
7341 mcpu_cpu_opt = &opt->value;
7343 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7346 cpu_variant = *mcpu_cpu_opt;
7348 *input_line_pointer = saved_char;
7349 demand_empty_rest_of_line ();
7352 as_bad (_("unknown cpu `%s'"), name);
7353 *input_line_pointer = saved_char;
7354 ignore_rest_of_line ();
7358 /* Parse a .arch directive. */
7361 s_aarch64_arch (int ignored ATTRIBUTE_UNUSED)
7363 const struct aarch64_arch_option_table *opt;
7369 name = input_line_pointer;
7370 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7371 input_line_pointer++;
7372 saved_char = *input_line_pointer;
7373 *input_line_pointer = 0;
7375 ext = strchr (name, '+');
7378 optlen = ext - name;
7380 optlen = strlen (name);
7382 /* Skip the first "all" entry. */
7383 for (opt = aarch64_archs + 1; opt->name != NULL; opt++)
7384 if (strlen (opt->name) == optlen
7385 && strncmp (name, opt->name, optlen) == 0)
7387 mcpu_cpu_opt = &opt->value;
7389 if (!aarch64_parse_features (ext, &mcpu_cpu_opt))
7392 cpu_variant = *mcpu_cpu_opt;
7394 *input_line_pointer = saved_char;
7395 demand_empty_rest_of_line ();
7399 as_bad (_("unknown architecture `%s'\n"), name);
7400 *input_line_pointer = saved_char;
7401 ignore_rest_of_line ();
7404 /* Copy symbol information. */
7407 aarch64_copy_symbol_attributes (symbolS * dest, symbolS * src)
7409 AARCH64_GET_FLAG (dest) = AARCH64_GET_FLAG (src);