2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
55 config BR2_ARM_CPU_ARMV7M
58 config BR2_ARM_CPU_ARMV8
62 prompt "Target Architecture Variant"
65 Specific CPU variant to use
69 select BR2_ARM_CPU_HAS_ARM
70 select BR2_ARM_CPU_HAS_THUMB
71 select BR2_ARM_CPU_ARMV4
72 select BR2_ARCH_HAS_MMU_OPTIONAL
73 depends on !BR2_ARCH_IS_64
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_HAS_THUMB
78 select BR2_ARM_CPU_ARMV4
79 select BR2_ARCH_HAS_MMU_OPTIONAL
80 depends on !BR2_ARCH_IS_64
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
85 select BR2_ARM_CPU_HAS_THUMB
86 select BR2_ARM_CPU_ARMV5
87 select BR2_ARCH_HAS_MMU_OPTIONAL
88 depends on !BR2_ARCH_IS_64
91 select BR2_ARM_CPU_HAS_ARM
92 select BR2_ARM_CPU_HAS_THUMB
93 select BR2_ARM_CPU_ARMV6
94 select BR2_ARCH_HAS_MMU_OPTIONAL
95 depends on !BR2_ARCH_IS_64
96 config BR2_arm1136jf_s
98 select BR2_ARM_CPU_HAS_ARM
99 select BR2_ARM_CPU_HAS_VFPV2
100 select BR2_ARM_CPU_HAS_THUMB
101 select BR2_ARM_CPU_ARMV6
102 select BR2_ARCH_HAS_MMU_OPTIONAL
103 depends on !BR2_ARCH_IS_64
104 config BR2_arm1176jz_s
106 select BR2_ARM_CPU_HAS_ARM
107 select BR2_ARM_CPU_HAS_THUMB
108 select BR2_ARM_CPU_ARMV6
109 select BR2_ARCH_HAS_MMU_OPTIONAL
110 depends on !BR2_ARCH_IS_64
111 config BR2_arm1176jzf_s
113 select BR2_ARM_CPU_HAS_ARM
114 select BR2_ARM_CPU_HAS_VFPV2
115 select BR2_ARM_CPU_HAS_THUMB
116 select BR2_ARM_CPU_ARMV6
117 select BR2_ARCH_HAS_MMU_OPTIONAL
118 depends on !BR2_ARCH_IS_64
119 config BR2_arm11mpcore
121 select BR2_ARM_CPU_HAS_ARM
122 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
123 select BR2_ARM_CPU_HAS_THUMB
124 select BR2_ARM_CPU_ARMV6
125 select BR2_ARCH_HAS_MMU_OPTIONAL
126 depends on !BR2_ARCH_IS_64
129 select BR2_ARM_CPU_HAS_ARM
130 select BR2_ARM_CPU_MAYBE_HAS_NEON
131 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
132 select BR2_ARM_CPU_HAS_THUMB2
133 select BR2_ARM_CPU_ARMV7A
134 select BR2_ARCH_HAS_MMU_OPTIONAL
135 depends on !BR2_ARCH_IS_64
138 select BR2_ARM_CPU_HAS_ARM
139 select BR2_ARM_CPU_HAS_NEON
140 select BR2_ARM_CPU_HAS_VFPV4
141 select BR2_ARM_CPU_HAS_THUMB2
142 select BR2_ARM_CPU_ARMV7A
143 select BR2_ARCH_HAS_MMU_OPTIONAL
144 depends on !BR2_ARCH_IS_64
147 select BR2_ARM_CPU_HAS_ARM
148 select BR2_ARM_CPU_HAS_NEON
149 select BR2_ARM_CPU_HAS_VFPV3
150 select BR2_ARM_CPU_HAS_THUMB2
151 select BR2_ARM_CPU_ARMV7A
152 select BR2_ARCH_HAS_MMU_OPTIONAL
153 depends on !BR2_ARCH_IS_64
156 select BR2_ARM_CPU_HAS_ARM
157 select BR2_ARM_CPU_MAYBE_HAS_NEON
158 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
159 select BR2_ARM_CPU_HAS_THUMB2
160 select BR2_ARM_CPU_ARMV7A
161 select BR2_ARCH_HAS_MMU_OPTIONAL
162 depends on !BR2_ARCH_IS_64
163 config BR2_cortex_a12
165 select BR2_ARM_CPU_HAS_ARM
166 select BR2_ARM_CPU_HAS_NEON
167 select BR2_ARM_CPU_HAS_VFPV4
168 select BR2_ARM_CPU_HAS_THUMB2
169 select BR2_ARM_CPU_ARMV7A
170 select BR2_ARCH_HAS_MMU_OPTIONAL
171 depends on !BR2_ARCH_IS_64
172 config BR2_cortex_a15
174 select BR2_ARM_CPU_HAS_ARM
175 select BR2_ARM_CPU_HAS_NEON
176 select BR2_ARM_CPU_HAS_VFPV4
177 select BR2_ARM_CPU_HAS_THUMB2
178 select BR2_ARM_CPU_ARMV7A
179 select BR2_ARCH_HAS_MMU_OPTIONAL
180 depends on !BR2_ARCH_IS_64
181 config BR2_cortex_a17
183 select BR2_ARM_CPU_HAS_ARM
184 select BR2_ARM_CPU_HAS_NEON
185 select BR2_ARM_CPU_HAS_VFPV4
186 select BR2_ARM_CPU_HAS_THUMB2
187 select BR2_ARM_CPU_ARMV7A
188 select BR2_ARCH_HAS_MMU_OPTIONAL
189 depends on !BR2_ARCH_IS_64
192 select BR2_ARM_CPU_HAS_THUMB2
193 select BR2_ARM_CPU_ARMV7M
194 depends on !BR2_ARCH_IS_64
197 select BR2_ARM_CPU_HAS_THUMB2
198 select BR2_ARM_CPU_ARMV7M
199 depends on !BR2_ARCH_IS_64
202 select BR2_ARM_CPU_HAS_ARM
203 select BR2_ARM_CPU_ARMV4
204 select BR2_ARCH_HAS_MMU_OPTIONAL
205 depends on !BR2_ARCH_IS_64
208 select BR2_ARM_CPU_HAS_ARM
209 select BR2_ARM_CPU_HAS_VFPV3
210 select BR2_ARM_CPU_ARMV7A
211 select BR2_ARCH_HAS_MMU_OPTIONAL
212 depends on !BR2_ARCH_IS_64
214 bool "strongarm sa110/sa1100"
215 select BR2_ARM_CPU_HAS_ARM
216 select BR2_ARM_CPU_ARMV4
217 select BR2_ARCH_HAS_MMU_OPTIONAL
218 depends on !BR2_ARCH_IS_64
221 select BR2_ARM_CPU_HAS_ARM
222 select BR2_ARM_CPU_HAS_THUMB
223 select BR2_ARM_CPU_ARMV5
224 select BR2_ARCH_HAS_MMU_OPTIONAL
225 depends on !BR2_ARCH_IS_64
228 select BR2_ARM_CPU_HAS_ARM
229 select BR2_ARM_CPU_ARMV5
230 select BR2_ARCH_HAS_MMU_OPTIONAL
231 depends on !BR2_ARCH_IS_64
234 config BR2_ARM_ENABLE_NEON
235 bool "Enable NEON SIMD extension support"
236 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
237 select BR2_ARM_CPU_HAS_NEON
239 For some CPU cores, the NEON SIMD extension is optional.
240 Select this option if you are certain your particular
241 implementation has NEON support and you want to use it.
243 config BR2_ARM_ENABLE_VFP
244 bool "Enable VFP extension support"
245 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
246 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
247 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
248 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
250 For some CPU cores, the VFP extension is optional. Select
251 this option if you are certain your particular
252 implementation has VFP support and you want to use it.
256 depends on BR2_arm || BR2_armeb
257 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
260 Application Binary Interface to use. The Application Binary
261 Interface describes the calling conventions (how arguments
262 are passed to functions, how the return value is passed, how
263 system calls are made, etc.).
268 The EABI is currently the standard ARM ABI, which is used in
269 most projects. It supports both the 'soft' floating point
270 model (in which floating point instructions are emulated in
271 software) and the 'softfp' floating point model (in which
272 floating point instructions are executed using an hardware
273 floating point unit, but floating point arguments to
274 functions are passed in integer registers).
276 The 'softfp' floating point model is link-compatible with
277 the 'soft' floating point model, i.e you can link a library
278 built 'soft' with some other code built 'softfp'.
280 However, passing the floating point arguments in integer
281 registers is a bit inefficient, so if your ARM processor has
282 a floating point unit, and you don't have pre-compiled
283 'soft' or 'softfp' code, using the EABIhf ABI will provide
284 better floating point performances.
286 If your processor does not have a floating point unit, then
287 you must use this ABI.
289 config BR2_ARM_EABIHF
291 depends on BR2_ARM_CPU_HAS_VFPV2
293 The EABIhf is an extension of EABI which supports the 'hard'
294 floating point model. This model uses the floating point
295 unit to execute floating point instructions, and passes
296 floating point arguments in floating point registers.
298 It is more efficient than EABI for floating point related
299 workload. However, it does not allow to link against code
300 that has been pre-built for the 'soft' or 'softfp' floating
303 If your processor has a floating point unit, and you don't
304 depend on existing pre-compiled code, this option is most
305 likely the best choice.
310 prompt "Floating point strategy"
311 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
312 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
313 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
314 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
315 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
317 config BR2_ARM_SOFT_FLOAT
319 depends on BR2_ARM_EABI
320 select BR2_SOFT_FLOAT
322 This option allows to use software emulated floating
323 point. It should be used for ARM cores that do not include a
324 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
325 example) or certain ARMv6 cores.
327 config BR2_ARM_FPU_VFPV2
329 depends on BR2_ARM_CPU_HAS_VFPV2
331 This option allows to use the VFPv2 floating point unit, as
332 available in some ARMv5 processors (ARM926EJ-S) and some
333 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
336 Note that this option is also safe to use for newer cores
337 such as Cortex-A, because the VFPv3 and VFPv4 units are
338 backward compatible with VFPv2.
340 config BR2_ARM_FPU_VFPV3
342 depends on BR2_ARM_CPU_HAS_VFPV3
344 This option allows to use the VFPv3 floating point unit, as
345 available in some ARMv7 processors (Cortex-A{8, 9}). This
346 option requires a VFPv3 unit that has 32 double-precision
347 registers, which is not necessarily the case in all SOCs
348 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
349 instead, which is guaranteed to work on all Cortex-A{8, 9}.
351 Note that this option is also safe to use for newer cores
352 that have a VFPv4 unit, because VFPv4 is backward compatible
353 with VFPv3. They must of course also have 32
354 double-precision registers.
356 config BR2_ARM_FPU_VFPV3D16
358 depends on BR2_ARM_CPU_HAS_VFPV3
360 This option allows to use the VFPv3 floating point unit, as
361 available in some ARMv7 processors (Cortex-A{8, 9}). This
362 option requires a VFPv3 unit that has 16 double-precision
363 registers, which is generally the case in all SOCs based on
364 Cortex-A{8, 9}, even though VFPv3 is technically optional on
365 Cortex-A9. This is the safest option for those cores.
367 Note that this option is also safe to use for newer cores
368 such that have a VFPv4 unit, because the VFPv4 is backward
369 compatible with VFPv3.
371 config BR2_ARM_FPU_VFPV4
373 depends on BR2_ARM_CPU_HAS_VFPV4
375 This option allows to use the VFPv4 floating point unit, as
376 available in some ARMv7 processors (Cortex-A{5, 7, 12,
377 15}). This option requires a VFPv4 unit that has 32
378 double-precision registers, which is not necessarily the
379 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
380 unsure, you should probably use VFPv4-D16 instead.
382 Note that if you want binary code that works on all ARMv7
383 cores, including the earlier Cortex-A{8, 9}, you should
384 instead select VFPv3.
386 config BR2_ARM_FPU_VFPV4D16
388 depends on BR2_ARM_CPU_HAS_VFPV4
390 This option allows to use the VFPv4 floating point unit, as
391 available in some ARMv7 processors (Cortex-A{5, 7, 12,
392 15}). This option requires a VFPv4 unit that has 16
393 double-precision registers, which is always available on
394 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
397 Note that if you want binary code that works on all ARMv7
398 cores, including the earlier Cortex-A{8, 9}, you should
399 instead select VFPv3-D16.
401 config BR2_ARM_FPU_NEON
403 depends on BR2_ARM_CPU_HAS_NEON
405 This option allows to use the NEON SIMD unit, as available
406 in some ARMv7 processors, as a floating-point unit. It
407 should however be noted that using NEON for floating point
408 operations doesn't provide a complete compatibility with the
411 config BR2_ARM_FPU_NEON_VFPV4
413 depends on BR2_ARM_CPU_HAS_VFPV4
414 depends on BR2_ARM_CPU_HAS_NEON
416 This option allows to use both the VFPv4 and the NEON SIMD
417 units for floating point operations. Note that some ARMv7
418 cores do not necessarily have VFPv4 and/or NEON support, for
419 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
425 prompt "ARM instruction set"
426 depends on BR2_arm || BR2_armeb
428 config BR2_ARM_INSTRUCTIONS_ARM
430 depends on BR2_ARM_CPU_HAS_ARM
432 This option instructs the compiler to generate regular ARM
433 instructions, that are all 32 bits wide.
435 config BR2_ARM_INSTRUCTIONS_THUMB
437 depends on BR2_ARM_CPU_HAS_THUMB
438 # Thumb-1 and VFP are not compatible
439 depends on BR2_ARM_SOFT_FLOAT
441 This option instructions the compiler to generate Thumb
442 instructions, which allows to mix 16 bits instructions and
443 32 bits instructions. This generally provides a much smaller
444 compiled binary size.
446 comment "Thumb1 is not compatible with VFP"
447 depends on BR2_ARM_CPU_HAS_THUMB
448 depends on !BR2_ARM_SOFT_FLOAT
450 config BR2_ARM_INSTRUCTIONS_THUMB2
452 depends on BR2_ARM_CPU_HAS_THUMB2
454 This option instructions the compiler to generate Thumb2
455 instructions, which allows to mix 16 bits instructions and
456 32 bits instructions. This generally provides a much smaller
457 compiled binary size.
462 default "arm" if BR2_arm
463 default "armeb" if BR2_armeb
464 default "aarch64" if BR2_aarch64
465 default "aarch64_be" if BR2_aarch64_be
468 default "LITTLE" if (BR2_arm || BR2_aarch64)
469 default "BIG" if (BR2_armeb || BR2_aarch64_be)
471 config BR2_GCC_TARGET_CPU
472 default "arm920t" if BR2_arm920t
473 default "arm922t" if BR2_arm922t
474 default "arm926ej-s" if BR2_arm926t
475 default "arm1136j-s" if BR2_arm1136j_s
476 default "arm1136jf-s" if BR2_arm1136jf_s
477 default "arm1176jz-s" if BR2_arm1176jz_s
478 default "arm1176jzf-s" if BR2_arm1176jzf_s
479 default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
480 default "mpcorenovfp" if BR2_arm11mpcore
481 default "cortex-a5" if BR2_cortex_a5
482 default "cortex-a7" if BR2_cortex_a7
483 default "cortex-a8" if BR2_cortex_a8
484 default "cortex-a9" if BR2_cortex_a9
485 default "cortex-a12" if BR2_cortex_a12
486 default "cortex-a15" if BR2_cortex_a15
487 default "cortex-a17" if BR2_cortex_a17
488 default "cortex-m3" if BR2_cortex_m3
489 default "cortex-m4" if BR2_cortex_m4
490 default "fa526" if BR2_fa526
491 default "marvell-pj4" if BR2_pj4
492 default "strongarm" if BR2_strongarm
493 default "xscale" if BR2_xscale
494 default "iwmmxt" if BR2_iwmmxt
496 config BR2_GCC_TARGET_ABI
497 default "aapcs-linux" if BR2_arm || BR2_armeb
499 config BR2_GCC_TARGET_FPU
500 depends on BR2_arm || BR2_armeb
501 default "vfp" if BR2_ARM_FPU_VFPV2
502 default "vfpv3" if BR2_ARM_FPU_VFPV3
503 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
504 default "vfpv4" if BR2_ARM_FPU_VFPV4
505 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
506 default "neon" if BR2_ARM_FPU_NEON
507 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
509 config BR2_GCC_TARGET_FLOAT_ABI
510 default "soft" if BR2_ARM_SOFT_FLOAT
511 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
512 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
514 config BR2_GCC_TARGET_MODE
515 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
516 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2