2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
60 Specific CPU variant to use
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
67 select BR2_ARCH_HAS_MMU_OPTIONAL
70 select BR2_ARM_CPU_HAS_ARM
71 select BR2_ARM_CPU_HAS_THUMB
72 select BR2_ARM_CPU_ARMV4
73 select BR2_ARCH_HAS_MMU_OPTIONAL
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
78 select BR2_ARM_CPU_HAS_THUMB
79 select BR2_ARM_CPU_ARMV5
80 select BR2_ARCH_HAS_MMU_OPTIONAL
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_HAS_THUMB
85 select BR2_ARM_CPU_ARMV6
86 select BR2_ARCH_HAS_MMU_OPTIONAL
87 config BR2_arm1136jf_s
89 select BR2_ARM_CPU_HAS_ARM
90 select BR2_ARM_CPU_HAS_VFPV2
91 select BR2_ARM_CPU_HAS_THUMB
92 select BR2_ARM_CPU_ARMV6
93 select BR2_ARCH_HAS_MMU_OPTIONAL
94 config BR2_arm1176jz_s
96 select BR2_ARM_CPU_HAS_ARM
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 config BR2_arm1176jzf_s
102 select BR2_ARM_CPU_HAS_ARM
103 select BR2_ARM_CPU_HAS_VFPV2
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
109 select BR2_ARM_CPU_HAS_ARM
110 select BR2_ARM_CPU_MAYBE_HAS_NEON
111 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
112 select BR2_ARM_CPU_HAS_THUMB2
113 select BR2_ARM_CPU_ARMV7A
114 select BR2_ARCH_HAS_MMU_OPTIONAL
117 select BR2_ARM_CPU_HAS_ARM
118 select BR2_ARM_CPU_HAS_NEON
119 select BR2_ARM_CPU_HAS_VFPV4
120 select BR2_ARM_CPU_HAS_THUMB2
121 select BR2_ARM_CPU_ARMV7A
122 select BR2_ARCH_HAS_MMU_OPTIONAL
125 select BR2_ARM_CPU_HAS_ARM
126 select BR2_ARM_CPU_HAS_NEON
127 select BR2_ARM_CPU_HAS_VFPV3
128 select BR2_ARM_CPU_HAS_THUMB2
129 select BR2_ARM_CPU_ARMV7A
130 select BR2_ARCH_HAS_MMU_OPTIONAL
133 select BR2_ARM_CPU_HAS_ARM
134 select BR2_ARM_CPU_MAYBE_HAS_NEON
135 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
136 select BR2_ARM_CPU_HAS_THUMB2
137 select BR2_ARM_CPU_ARMV7A
138 select BR2_ARCH_HAS_MMU_OPTIONAL
139 config BR2_cortex_a12
141 select BR2_ARM_CPU_HAS_ARM
142 select BR2_ARM_CPU_HAS_NEON
143 select BR2_ARM_CPU_HAS_VFPV4
144 select BR2_ARM_CPU_HAS_THUMB2
145 select BR2_ARM_CPU_ARMV7A
146 select BR2_ARCH_HAS_MMU_OPTIONAL
147 config BR2_cortex_a15
149 select BR2_ARM_CPU_HAS_ARM
150 select BR2_ARM_CPU_HAS_NEON
151 select BR2_ARM_CPU_HAS_VFPV4
152 select BR2_ARM_CPU_HAS_THUMB2
153 select BR2_ARM_CPU_ARMV7A
154 select BR2_ARCH_HAS_MMU_OPTIONAL
157 select BR2_ARM_CPU_HAS_THUMB
158 select BR2_ARM_CPU_HAS_THUMB2
161 select BR2_ARM_CPU_HAS_ARM
162 select BR2_ARM_CPU_ARMV4
163 select BR2_ARCH_HAS_MMU_OPTIONAL
166 select BR2_ARM_CPU_HAS_ARM
167 select BR2_ARM_CPU_HAS_VFPV3
168 select BR2_ARM_CPU_ARMV7A
169 select BR2_ARCH_HAS_MMU_OPTIONAL
171 bool "strongarm sa110/sa1100"
172 select BR2_ARM_CPU_HAS_ARM
173 select BR2_ARM_CPU_ARMV4
174 select BR2_ARCH_HAS_MMU_OPTIONAL
177 select BR2_ARM_CPU_HAS_ARM
178 select BR2_ARM_CPU_HAS_THUMB
179 select BR2_ARM_CPU_ARMV5
180 select BR2_ARCH_HAS_MMU_OPTIONAL
183 select BR2_ARM_CPU_HAS_ARM
184 select BR2_ARM_CPU_ARMV5
185 select BR2_ARCH_HAS_MMU_OPTIONAL
188 config BR2_ARM_ENABLE_NEON
189 bool "Enable NEON SIMD extension support"
190 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
191 select BR2_ARM_CPU_HAS_NEON
193 For some CPU cores, the NEON SIMD extension is optional.
194 Select this option if you are certain your particular
195 implementation has NEON support and you want to use it.
197 config BR2_ARM_ENABLE_VFP
198 bool "Enable VFP extension support"
199 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
200 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
201 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
202 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
204 For some CPU cores, the VFP extension is optional. Select
205 this option if you are certain your particular
206 implementation has VFP support and you want to use it.
210 depends on BR2_arm || BR2_armeb
211 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
214 Application Binary Interface to use. The Application Binary
215 Interface describes the calling conventions (how arguments
216 are passed to functions, how the return value is passed, how
217 system calls are made, etc.).
222 The EABI is currently the standard ARM ABI, which is used in
223 most projects. It supports both the 'soft' floating point
224 model (in which floating point instructions are emulated in
225 software) and the 'softfp' floating point model (in which
226 floating point instructions are executed using an hardware
227 floating point unit, but floating point arguments to
228 functions are passed in integer registers).
230 The 'softfp' floating point model is link-compatible with
231 the 'soft' floating point model, i.e you can link a library
232 built 'soft' with some other code built 'softfp'.
234 However, passing the floating point arguments in integer
235 registers is a bit inefficient, so if your ARM processor has
236 a floating point unit, and you don't have pre-compiled
237 'soft' or 'softfp' code, using the EABIhf ABI will provide
238 better floating point performances.
240 If your processor does not have a floating point unit, then
241 you must use this ABI.
243 config BR2_ARM_EABIHF
245 depends on BR2_ARM_CPU_HAS_VFPV2
247 The EABIhf is an extension of EABI which supports the 'hard'
248 floating point model. This model uses the floating point
249 unit to execute floating point instructions, and passes
250 floating point arguments in floating point registers.
252 It is more efficient than EABI for floating point related
253 workload. However, it does not allow to link against code
254 that has been pre-built for the 'soft' or 'softfp' floating
257 If your processor has a floating point unit, and you don't
258 depend on existing pre-compiled code, this option is most
259 likely the best choice.
264 prompt "Floating point strategy"
265 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
266 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
267 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
268 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
269 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
271 config BR2_ARM_SOFT_FLOAT
273 depends on BR2_ARM_EABI
274 select BR2_SOFT_FLOAT
276 This option allows to use software emulated floating
277 point. It should be used for ARM cores that do not include a
278 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
279 example) or certain ARMv6 cores.
281 config BR2_ARM_FPU_VFPV2
283 depends on BR2_ARM_CPU_HAS_VFPV2
285 This option allows to use the VFPv2 floating point unit, as
286 available in some ARMv5 processors (ARM926EJ-S) and some
287 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
290 Note that this option is also safe to use for newer cores
291 such as Cortex-A, because the VFPv3 and VFPv4 units are
292 backward compatible with VFPv2.
294 config BR2_ARM_FPU_VFPV3
296 depends on BR2_ARM_CPU_HAS_VFPV3
298 This option allows to use the VFPv3 floating point unit, as
299 available in some ARMv7 processors (Cortex-A{8, 9}). This
300 option requires a VFPv3 unit that has 32 double-precision
301 registers, which is not necessarily the case in all SOCs
302 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
303 instead, which is guaranteed to work on all Cortex-A{8, 9}.
305 Note that this option is also safe to use for newer cores
306 that have a VFPv4 unit, because VFPv4 is backward compatible
307 with VFPv3. They must of course also have 32
308 double-precision registers.
310 config BR2_ARM_FPU_VFPV3D16
312 depends on BR2_ARM_CPU_HAS_VFPV3
314 This option allows to use the VFPv3 floating point unit, as
315 available in some ARMv7 processors (Cortex-A{8, 9}). This
316 option requires a VFPv3 unit that has 16 double-precision
317 registers, which is generally the case in all SOCs based on
318 Cortex-A{8, 9}, even though VFPv3 is technically optional on
319 Cortex-A9. This is the safest option for those cores.
321 Note that this option is also safe to use for newer cores
322 such that have a VFPv4 unit, because the VFPv4 is backward
323 compatible with VFPv3.
325 config BR2_ARM_FPU_VFPV4
327 depends on BR2_ARM_CPU_HAS_VFPV4
329 This option allows to use the VFPv4 floating point unit, as
330 available in some ARMv7 processors (Cortex-A{5, 7, 12,
331 15}). This option requires a VFPv4 unit that has 32
332 double-precision registers, which is not necessarily the
333 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
334 unsure, you should probably use VFPv4-D16 instead.
336 Note that if you want binary code that works on all ARMv7
337 cores, including the earlier Cortex-A{8, 9}, you should
338 instead select VFPv3.
340 config BR2_ARM_FPU_VFPV4D16
342 depends on BR2_ARM_CPU_HAS_VFPV4
344 This option allows to use the VFPv4 floating point unit, as
345 available in some ARMv7 processors (Cortex-A{5, 7, 12,
346 15}). This option requires a VFPv4 unit that has 16
347 double-precision registers, which is always available on
348 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
351 Note that if you want binary code that works on all ARMv7
352 cores, including the earlier Cortex-A{8, 9}, you should
353 instead select VFPv3-D16.
355 config BR2_ARM_FPU_NEON
357 depends on BR2_ARM_CPU_HAS_NEON
359 This option allows to use the NEON SIMD unit, as available
360 in some ARMv7 processors, as a floating-point unit. It
361 should however be noted that using NEON for floating point
362 operations doesn't provide a complete compatibility with the
365 config BR2_ARM_FPU_NEON_VFPV4
367 depends on BR2_ARM_CPU_HAS_VFPV4
368 depends on BR2_ARM_CPU_HAS_NEON
370 This option allows to use both the VFPv4 and the NEON SIMD
371 units for floating point operations. Note that some ARMv7
372 cores do not necessarily have VFPv4 and/or NEON support, for
373 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
379 prompt "ARM instruction set"
381 config BR2_ARM_INSTRUCTIONS_ARM
383 depends on BR2_ARM_CPU_HAS_ARM
385 This option instructs the compiler to generate regular ARM
386 instructions, that are all 32 bits wide.
388 config BR2_ARM_INSTRUCTIONS_THUMB
390 depends on BR2_ARM_CPU_HAS_THUMB
391 # Thumb-1 and VFP are not compatible
392 depends on BR2_ARM_SOFT_FLOAT
394 This option instructions the compiler to generate Thumb
395 instructions, which allows to mix 16 bits instructions and
396 32 bits instructions. This generally provides a much smaller
397 compiled binary size.
399 comment "Thumb1 is not compatible with VFP"
400 depends on BR2_ARM_CPU_HAS_THUMB
401 depends on !BR2_ARM_SOFT_FLOAT
403 config BR2_ARM_INSTRUCTIONS_THUMB2
405 depends on BR2_ARM_CPU_HAS_THUMB2
407 This option instructions the compiler to generate Thumb2
408 instructions, which allows to mix 16 bits instructions and
409 32 bits instructions. This generally provides a much smaller
410 compiled binary size.
415 default "arm" if BR2_arm
416 default "armeb" if BR2_armeb
419 default "LITTLE" if BR2_arm
420 default "BIG" if BR2_armeb
422 config BR2_ARCH_HAS_ATOMICS
425 config BR2_GCC_TARGET_CPU
426 default "arm920t" if BR2_arm920t
427 default "arm922t" if BR2_arm922t
428 default "arm926ej-s" if BR2_arm926t
429 default "arm1136j-s" if BR2_arm1136j_s
430 default "arm1136jf-s" if BR2_arm1136jf_s
431 default "arm1176jz-s" if BR2_arm1176jz_s
432 default "arm1176jzf-s" if BR2_arm1176jzf_s
433 default "cortex-a5" if BR2_cortex_a5
434 default "cortex-a7" if BR2_cortex_a7
435 default "cortex-a8" if BR2_cortex_a8
436 default "cortex-a9" if BR2_cortex_a9
437 default "cortex-a12" if BR2_cortex_a12
438 default "cortex-a15" if BR2_cortex_a15
439 default "cortex-m3" if BR2_cortex_m3
440 default "fa526" if BR2_fa526
441 default "marvell-pj4" if BR2_pj4
442 default "strongarm" if BR2_strongarm
443 default "xscale" if BR2_xscale
444 default "iwmmxt" if BR2_iwmmxt
446 config BR2_GCC_TARGET_ABI
447 default "aapcs-linux"
449 config BR2_GCC_TARGET_FPU
450 default "vfp" if BR2_ARM_FPU_VFPV2
451 default "vfpv3" if BR2_ARM_FPU_VFPV3
452 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
453 default "vfpv4" if BR2_ARM_FPU_VFPV4
454 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
455 default "neon" if BR2_ARM_FPU_NEON
456 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
458 config BR2_GCC_TARGET_FLOAT_ABI
459 default "soft" if BR2_ARM_SOFT_FLOAT
460 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
461 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
463 config BR2_GCC_TARGET_MODE
464 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
465 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2