2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
60 Specific CPU variant to use
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
67 select BR2_ARCH_HAS_MMU_OPTIONAL
70 select BR2_ARM_CPU_HAS_ARM
71 select BR2_ARM_CPU_HAS_THUMB
72 select BR2_ARM_CPU_ARMV4
73 select BR2_ARCH_HAS_MMU_OPTIONAL
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
78 select BR2_ARM_CPU_HAS_THUMB
79 select BR2_ARM_CPU_ARMV5
80 select BR2_ARCH_HAS_MMU_OPTIONAL
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_HAS_THUMB
85 select BR2_ARM_CPU_ARMV6
86 select BR2_ARCH_HAS_MMU_OPTIONAL
87 config BR2_arm1136jf_s
89 select BR2_ARM_CPU_HAS_ARM
90 select BR2_ARM_CPU_HAS_VFPV2
91 select BR2_ARM_CPU_HAS_THUMB
92 select BR2_ARM_CPU_ARMV6
93 select BR2_ARCH_HAS_MMU_OPTIONAL
94 config BR2_arm1176jz_s
96 select BR2_ARM_CPU_HAS_ARM
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 config BR2_arm1176jzf_s
102 select BR2_ARM_CPU_HAS_ARM
103 select BR2_ARM_CPU_HAS_VFPV2
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
109 select BR2_ARM_CPU_HAS_ARM
110 select BR2_ARM_CPU_MAYBE_HAS_NEON
111 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
112 select BR2_ARM_CPU_HAS_THUMB2
113 select BR2_ARM_CPU_ARMV7A
114 select BR2_ARCH_HAS_MMU_OPTIONAL
117 select BR2_ARM_CPU_HAS_ARM
118 select BR2_ARM_CPU_HAS_NEON
119 select BR2_ARM_CPU_HAS_VFPV4
120 select BR2_ARM_CPU_HAS_THUMB2
121 select BR2_ARM_CPU_ARMV7A
122 select BR2_ARCH_HAS_MMU_OPTIONAL
125 select BR2_ARM_CPU_HAS_ARM
126 select BR2_ARM_CPU_HAS_NEON
127 select BR2_ARM_CPU_HAS_VFPV3
128 select BR2_ARM_CPU_HAS_THUMB2
129 select BR2_ARM_CPU_ARMV7A
130 select BR2_ARCH_HAS_MMU_OPTIONAL
133 select BR2_ARM_CPU_HAS_ARM
134 select BR2_ARM_CPU_MAYBE_HAS_NEON
135 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
136 select BR2_ARM_CPU_HAS_THUMB2
137 select BR2_ARM_CPU_ARMV7A
138 select BR2_ARCH_HAS_MMU_OPTIONAL
139 config BR2_cortex_a12
141 select BR2_ARM_CPU_HAS_ARM
142 select BR2_ARM_CPU_HAS_NEON
143 select BR2_ARM_CPU_HAS_VFPV4
144 select BR2_ARM_CPU_HAS_THUMB2
145 select BR2_ARM_CPU_ARMV7A
146 select BR2_ARCH_HAS_MMU_OPTIONAL
147 config BR2_cortex_a15
149 select BR2_ARM_CPU_HAS_ARM
150 select BR2_ARM_CPU_HAS_NEON
151 select BR2_ARM_CPU_HAS_VFPV4
152 select BR2_ARM_CPU_HAS_THUMB2
153 select BR2_ARM_CPU_ARMV7A
154 select BR2_ARCH_HAS_MMU_OPTIONAL
157 select BR2_ARM_CPU_HAS_THUMB
158 select BR2_ARM_CPU_HAS_THUMB2
161 select BR2_ARM_CPU_HAS_ARM
162 select BR2_ARM_CPU_ARMV4
163 select BR2_ARCH_HAS_MMU_OPTIONAL
166 select BR2_ARM_CPU_HAS_ARM
167 select BR2_ARM_CPU_HAS_VFPV3
168 select BR2_ARM_CPU_ARMV7A
169 select BR2_ARCH_HAS_MMU_OPTIONAL
171 bool "strongarm sa110/sa1100"
172 select BR2_ARM_CPU_HAS_ARM
173 select BR2_ARM_CPU_ARMV4
174 select BR2_ARCH_HAS_MMU_OPTIONAL
177 select BR2_ARM_CPU_HAS_ARM
178 select BR2_ARM_CPU_HAS_THUMB
179 select BR2_ARM_CPU_ARMV5
180 select BR2_ARCH_HAS_MMU_OPTIONAL
183 select BR2_ARM_CPU_HAS_ARM
184 select BR2_ARM_CPU_ARMV5
185 select BR2_ARCH_HAS_MMU_OPTIONAL
190 depends on BR2_arm || BR2_armeb
193 Application Binary Interface to use. The Application Binary
194 Interface describes the calling conventions (how arguments
195 are passed to functions, how the return value is passed, how
196 system calls are made, etc.).
201 The EABI is currently the standard ARM ABI, which is used in
202 most projects. It supports both the 'soft' floating point
203 model (in which floating point instructions are emulated in
204 software) and the 'softfp' floating point model (in which
205 floating point instructions are executed using an hardware
206 floating point unit, but floating point arguments to
207 functions are passed in integer registers).
209 The 'softfp' floating point model is link-compatible with
210 the 'soft' floating point model, i.e you can link a library
211 built 'soft' with some other code built 'softfp'.
213 However, passing the floating point arguments in integer
214 registers is a bit inefficient, so if your ARM processor has
215 a floating point unit, and you don't have pre-compiled
216 'soft' or 'softfp' code, using the EABIhf ABI will provide
217 better floating point performances.
219 If your processor does not have a floating point unit, then
220 you must use this ABI.
222 config BR2_ARM_EABIHF
224 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 || BR2_ARM_CPU_HAS_VFPV2
226 The EABIhf is an extension of EABI which supports the 'hard'
227 floating point model. This model uses the floating point
228 unit to execute floating point instructions, and passes
229 floating point arguments in floating point registers.
231 It is more efficient than EABI for floating point related
232 workload. However, it does not allow to link against code
233 that has been pre-built for the 'soft' or 'softfp' floating
236 If your processor has a floating point unit, and you don't
237 depend on existing pre-compiled code, this option is most
238 likely the best choice.
242 config BR2_ARM_ENABLE_NEON
243 bool "Enable NEON SIMD extension support"
244 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
245 select BR2_ARM_CPU_HAS_NEON
247 For some CPU cores, the NEON SIMD extension is optional.
248 Select this option if you are certain your particular
249 implementation has NEON support and you want to use it.
252 prompt "Floating point strategy"
253 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
254 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
255 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
256 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
257 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
259 config BR2_ARM_SOFT_FLOAT
261 depends on BR2_ARM_EABI
262 select BR2_SOFT_FLOAT
264 This option allows to use software emulated floating
265 point. It should be used for ARM cores that do not include a
266 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
267 example) or certain ARMv6 cores.
269 config BR2_ARM_FPU_VFPV2
271 depends on BR2_ARM_CPU_HAS_VFPV2 || BR2_ARM_CPU_MAYBE_HAS_VFPV2
273 This option allows to use the VFPv2 floating point unit, as
274 available in some ARMv5 processors (ARM926EJ-S) and some
275 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
278 Note that this option is also safe to use for newer cores
279 such as Cortex-A, because the VFPv3 and VFPv4 units are
280 backward compatible with VFPv2.
282 config BR2_ARM_FPU_VFPV3
284 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
286 This option allows to use the VFPv3 floating point unit, as
287 available in some ARMv7 processors (Cortex-A{8, 9}). This
288 option requires a VFPv3 unit that has 32 double-precision
289 registers, which is not necessarily the case in all SOCs
290 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
291 instead, which is guaranteed to work on all Cortex-A{8, 9}.
293 Note that this option is also safe to use for newer cores
294 that have a VFPv4 unit, because VFPv4 is backward compatible
295 with VFPv3. They must of course also have 32
296 double-precision registers.
298 config BR2_ARM_FPU_VFPV3D16
300 depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
302 This option allows to use the VFPv3 floating point unit, as
303 available in some ARMv7 processors (Cortex-A{8, 9}). This
304 option requires a VFPv3 unit that has 16 double-precision
305 registers, which is generally the case in all SOCs based on
306 Cortex-A{8, 9}, even though VFPv3 is technically optional on
307 Cortex-A9. This is the safest option for those cores.
309 Note that this option is also safe to use for newer cores
310 such that have a VFPv4 unit, because the VFPv4 is backward
311 compatible with VFPv3.
313 config BR2_ARM_FPU_VFPV4
315 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
317 This option allows to use the VFPv4 floating point unit, as
318 available in some ARMv7 processors (Cortex-A{5, 7, 12,
319 15}). This option requires a VFPv4 unit that has 32
320 double-precision registers, which is not necessarily the
321 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
322 unsure, you should probably use VFPv4-D16 instead.
324 Note that if you want binary code that works on all ARMv7
325 cores, including the earlier Cortex-A{8, 9}, you should
326 instead select VFPv3.
328 config BR2_ARM_FPU_VFPV4D16
330 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
332 This option allows to use the VFPv4 floating point unit, as
333 available in some ARMv7 processors (Cortex-A{5, 7, 12,
334 15}). This option requires a VFPv4 unit that has 16
335 double-precision registers, which is always available on
336 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
339 Note that if you want binary code that works on all ARMv7
340 cores, including the earlier Cortex-A{8, 9}, you should
341 instead select VFPv3-D16.
343 config BR2_ARM_FPU_NEON
345 depends on BR2_ARM_CPU_HAS_NEON
347 This option allows to use the NEON SIMD unit, as available
348 in some ARMv7 processors, as a floating-point unit. It
349 should however be noted that using NEON for floating point
350 operations doesn't provide a complete compatibility with the
353 config BR2_ARM_FPU_NEON_VFPV4
355 depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
356 depends on BR2_ARM_CPU_HAS_NEON
358 This option allows to use both the VFPv4 and the NEON SIMD
359 units for floating point operations. Note that some ARMv7
360 cores do not necessarily have VFPv4 and/or NEON support, for
361 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
367 prompt "ARM instruction set"
369 config BR2_ARM_INSTRUCTIONS_ARM
371 depends on BR2_ARM_CPU_HAS_ARM
373 This option instructs the compiler to generate regular ARM
374 instructions, that are all 32 bits wide.
376 config BR2_ARM_INSTRUCTIONS_THUMB
378 depends on BR2_ARM_CPU_HAS_THUMB
380 This option instructions the compiler to generate Thumb
381 instructions, which allows to mix 16 bits instructions and
382 32 bits instructions. This generally provides a much smaller
383 compiled binary size.
385 config BR2_ARM_INSTRUCTIONS_THUMB2
387 depends on BR2_ARM_CPU_HAS_THUMB2
389 This option instructions the compiler to generate Thumb2
390 instructions, which allows to mix 16 bits instructions and
391 32 bits instructions. This generally provides a much smaller
392 compiled binary size.
397 default "arm" if BR2_arm
398 default "armeb" if BR2_armeb
401 default "LITTLE" if BR2_arm
402 default "BIG" if BR2_armeb
404 config BR2_ARCH_HAS_ATOMICS
407 config BR2_GCC_TARGET_CPU
408 default "arm920t" if BR2_arm920t
409 default "arm922t" if BR2_arm922t
410 default "arm926ej-s" if BR2_arm926t
411 default "arm1136j-s" if BR2_arm1136j_s
412 default "arm1136jf-s" if BR2_arm1136jf_s
413 default "arm1176jz-s" if BR2_arm1176jz_s
414 default "arm1176jzf-s" if BR2_arm1176jzf_s
415 default "cortex-a5" if BR2_cortex_a5
416 default "cortex-a7" if BR2_cortex_a7
417 default "cortex-a8" if BR2_cortex_a8
418 default "cortex-a9" if BR2_cortex_a9
419 default "cortex-a12" if BR2_cortex_a12
420 default "cortex-a15" if BR2_cortex_a15
421 default "cortex-m3" if BR2_cortex_m3
422 default "fa526" if BR2_fa526
423 default "marvell-pj4" if BR2_pj4
424 default "strongarm" if BR2_strongarm
425 default "xscale" if BR2_xscale
426 default "iwmmxt" if BR2_iwmmxt
428 config BR2_GCC_TARGET_ABI
429 default "aapcs-linux"
431 config BR2_GCC_TARGET_FPU
432 default "vfp" if BR2_ARM_FPU_VFPV2
433 default "vfpv3" if BR2_ARM_FPU_VFPV3
434 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
435 default "vfpv4" if BR2_ARM_FPU_VFPV4
436 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
437 default "neon" if BR2_ARM_FPU_NEON
438 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
440 config BR2_GCC_TARGET_FLOAT_ABI
441 default "soft" if BR2_ARM_SOFT_FLOAT
442 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
443 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
445 config BR2_GCC_TARGET_MODE
446 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
447 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2