2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
55 config BR2_ARM_CPU_ARMV7M
59 prompt "Target Architecture Variant"
62 Specific CPU variant to use
66 select BR2_ARM_CPU_HAS_ARM
67 select BR2_ARM_CPU_HAS_THUMB
68 select BR2_ARM_CPU_ARMV4
69 select BR2_ARCH_HAS_MMU_OPTIONAL
70 depends on !BR2_ARCH_IS_64
73 select BR2_ARM_CPU_HAS_ARM
74 select BR2_ARM_CPU_HAS_THUMB
75 select BR2_ARM_CPU_ARMV4
76 select BR2_ARCH_HAS_MMU_OPTIONAL
77 depends on !BR2_ARCH_IS_64
80 select BR2_ARM_CPU_HAS_ARM
81 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
82 select BR2_ARM_CPU_HAS_THUMB
83 select BR2_ARM_CPU_ARMV5
84 select BR2_ARCH_HAS_MMU_OPTIONAL
85 depends on !BR2_ARCH_IS_64
88 select BR2_ARM_CPU_HAS_ARM
89 select BR2_ARM_CPU_HAS_THUMB
90 select BR2_ARM_CPU_ARMV6
91 select BR2_ARCH_HAS_MMU_OPTIONAL
92 depends on !BR2_ARCH_IS_64
93 config BR2_arm1136jf_s
95 select BR2_ARM_CPU_HAS_ARM
96 select BR2_ARM_CPU_HAS_VFPV2
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 depends on !BR2_ARCH_IS_64
101 config BR2_arm1176jz_s
103 select BR2_ARM_CPU_HAS_ARM
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
107 depends on !BR2_ARCH_IS_64
108 config BR2_arm1176jzf_s
110 select BR2_ARM_CPU_HAS_ARM
111 select BR2_ARM_CPU_HAS_VFPV2
112 select BR2_ARM_CPU_HAS_THUMB
113 select BR2_ARM_CPU_ARMV6
114 select BR2_ARCH_HAS_MMU_OPTIONAL
115 depends on !BR2_ARCH_IS_64
116 config BR2_arm11mpcore
118 select BR2_ARM_CPU_HAS_ARM
119 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
120 select BR2_ARM_CPU_HAS_THUMB
121 select BR2_ARM_CPU_ARMV6
122 select BR2_ARCH_HAS_MMU_OPTIONAL
123 depends on !BR2_ARCH_IS_64
126 select BR2_ARM_CPU_HAS_ARM
127 select BR2_ARM_CPU_MAYBE_HAS_NEON
128 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
129 select BR2_ARM_CPU_HAS_THUMB2
130 select BR2_ARM_CPU_ARMV7A
131 select BR2_ARCH_HAS_MMU_OPTIONAL
132 depends on !BR2_ARCH_IS_64
135 select BR2_ARM_CPU_HAS_ARM
136 select BR2_ARM_CPU_HAS_NEON
137 select BR2_ARM_CPU_HAS_VFPV4
138 select BR2_ARM_CPU_HAS_THUMB2
139 select BR2_ARM_CPU_ARMV7A
140 select BR2_ARCH_HAS_MMU_OPTIONAL
141 depends on !BR2_ARCH_IS_64
144 select BR2_ARM_CPU_HAS_ARM
145 select BR2_ARM_CPU_HAS_NEON
146 select BR2_ARM_CPU_HAS_VFPV3
147 select BR2_ARM_CPU_HAS_THUMB2
148 select BR2_ARM_CPU_ARMV7A
149 select BR2_ARCH_HAS_MMU_OPTIONAL
150 depends on !BR2_ARCH_IS_64
153 select BR2_ARM_CPU_HAS_ARM
154 select BR2_ARM_CPU_MAYBE_HAS_NEON
155 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
156 select BR2_ARM_CPU_HAS_THUMB2
157 select BR2_ARM_CPU_ARMV7A
158 select BR2_ARCH_HAS_MMU_OPTIONAL
159 depends on !BR2_ARCH_IS_64
160 config BR2_cortex_a12
162 select BR2_ARM_CPU_HAS_ARM
163 select BR2_ARM_CPU_HAS_NEON
164 select BR2_ARM_CPU_HAS_VFPV4
165 select BR2_ARM_CPU_HAS_THUMB2
166 select BR2_ARM_CPU_ARMV7A
167 select BR2_ARCH_HAS_MMU_OPTIONAL
168 depends on !BR2_ARCH_IS_64
169 config BR2_cortex_a15
171 select BR2_ARM_CPU_HAS_ARM
172 select BR2_ARM_CPU_HAS_NEON
173 select BR2_ARM_CPU_HAS_VFPV4
174 select BR2_ARM_CPU_HAS_THUMB2
175 select BR2_ARM_CPU_ARMV7A
176 select BR2_ARCH_HAS_MMU_OPTIONAL
177 depends on !BR2_ARCH_IS_64
178 config BR2_cortex_a17
180 select BR2_ARM_CPU_HAS_ARM
181 select BR2_ARM_CPU_HAS_NEON
182 select BR2_ARM_CPU_HAS_VFPV4
183 select BR2_ARM_CPU_HAS_THUMB2
184 select BR2_ARM_CPU_ARMV7A
185 select BR2_ARCH_HAS_MMU_OPTIONAL
186 depends on !BR2_ARCH_IS_64
189 select BR2_ARM_CPU_HAS_THUMB2
190 select BR2_ARM_CPU_ARMV7M
191 depends on !BR2_ARCH_IS_64
194 select BR2_ARM_CPU_HAS_THUMB2
195 select BR2_ARM_CPU_ARMV7M
196 depends on !BR2_ARCH_IS_64
199 select BR2_ARM_CPU_HAS_ARM
200 select BR2_ARM_CPU_ARMV4
201 select BR2_ARCH_HAS_MMU_OPTIONAL
202 depends on !BR2_ARCH_IS_64
205 select BR2_ARM_CPU_HAS_ARM
206 select BR2_ARM_CPU_HAS_VFPV3
207 select BR2_ARM_CPU_ARMV7A
208 select BR2_ARCH_HAS_MMU_OPTIONAL
209 depends on !BR2_ARCH_IS_64
211 bool "strongarm sa110/sa1100"
212 select BR2_ARM_CPU_HAS_ARM
213 select BR2_ARM_CPU_ARMV4
214 select BR2_ARCH_HAS_MMU_OPTIONAL
215 depends on !BR2_ARCH_IS_64
218 select BR2_ARM_CPU_HAS_ARM
219 select BR2_ARM_CPU_HAS_THUMB
220 select BR2_ARM_CPU_ARMV5
221 select BR2_ARCH_HAS_MMU_OPTIONAL
222 depends on !BR2_ARCH_IS_64
225 select BR2_ARM_CPU_HAS_ARM
226 select BR2_ARM_CPU_ARMV5
227 select BR2_ARCH_HAS_MMU_OPTIONAL
228 depends on !BR2_ARCH_IS_64
231 config BR2_ARM_ENABLE_NEON
232 bool "Enable NEON SIMD extension support"
233 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
234 select BR2_ARM_CPU_HAS_NEON
236 For some CPU cores, the NEON SIMD extension is optional.
237 Select this option if you are certain your particular
238 implementation has NEON support and you want to use it.
240 config BR2_ARM_ENABLE_VFP
241 bool "Enable VFP extension support"
242 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
243 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
244 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
245 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
247 For some CPU cores, the VFP extension is optional. Select
248 this option if you are certain your particular
249 implementation has VFP support and you want to use it.
253 depends on BR2_arm || BR2_armeb
254 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
257 Application Binary Interface to use. The Application Binary
258 Interface describes the calling conventions (how arguments
259 are passed to functions, how the return value is passed, how
260 system calls are made, etc.).
265 The EABI is currently the standard ARM ABI, which is used in
266 most projects. It supports both the 'soft' floating point
267 model (in which floating point instructions are emulated in
268 software) and the 'softfp' floating point model (in which
269 floating point instructions are executed using an hardware
270 floating point unit, but floating point arguments to
271 functions are passed in integer registers).
273 The 'softfp' floating point model is link-compatible with
274 the 'soft' floating point model, i.e you can link a library
275 built 'soft' with some other code built 'softfp'.
277 However, passing the floating point arguments in integer
278 registers is a bit inefficient, so if your ARM processor has
279 a floating point unit, and you don't have pre-compiled
280 'soft' or 'softfp' code, using the EABIhf ABI will provide
281 better floating point performances.
283 If your processor does not have a floating point unit, then
284 you must use this ABI.
286 config BR2_ARM_EABIHF
288 depends on BR2_ARM_CPU_HAS_VFPV2
290 The EABIhf is an extension of EABI which supports the 'hard'
291 floating point model. This model uses the floating point
292 unit to execute floating point instructions, and passes
293 floating point arguments in floating point registers.
295 It is more efficient than EABI for floating point related
296 workload. However, it does not allow to link against code
297 that has been pre-built for the 'soft' or 'softfp' floating
300 If your processor has a floating point unit, and you don't
301 depend on existing pre-compiled code, this option is most
302 likely the best choice.
307 prompt "Floating point strategy"
308 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
309 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
310 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
311 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
312 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
314 config BR2_ARM_SOFT_FLOAT
316 depends on BR2_ARM_EABI
317 select BR2_SOFT_FLOAT
319 This option allows to use software emulated floating
320 point. It should be used for ARM cores that do not include a
321 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
322 example) or certain ARMv6 cores.
324 config BR2_ARM_FPU_VFPV2
326 depends on BR2_ARM_CPU_HAS_VFPV2
328 This option allows to use the VFPv2 floating point unit, as
329 available in some ARMv5 processors (ARM926EJ-S) and some
330 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
333 Note that this option is also safe to use for newer cores
334 such as Cortex-A, because the VFPv3 and VFPv4 units are
335 backward compatible with VFPv2.
337 config BR2_ARM_FPU_VFPV3
339 depends on BR2_ARM_CPU_HAS_VFPV3
341 This option allows to use the VFPv3 floating point unit, as
342 available in some ARMv7 processors (Cortex-A{8, 9}). This
343 option requires a VFPv3 unit that has 32 double-precision
344 registers, which is not necessarily the case in all SOCs
345 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
346 instead, which is guaranteed to work on all Cortex-A{8, 9}.
348 Note that this option is also safe to use for newer cores
349 that have a VFPv4 unit, because VFPv4 is backward compatible
350 with VFPv3. They must of course also have 32
351 double-precision registers.
353 config BR2_ARM_FPU_VFPV3D16
355 depends on BR2_ARM_CPU_HAS_VFPV3
357 This option allows to use the VFPv3 floating point unit, as
358 available in some ARMv7 processors (Cortex-A{8, 9}). This
359 option requires a VFPv3 unit that has 16 double-precision
360 registers, which is generally the case in all SOCs based on
361 Cortex-A{8, 9}, even though VFPv3 is technically optional on
362 Cortex-A9. This is the safest option for those cores.
364 Note that this option is also safe to use for newer cores
365 such that have a VFPv4 unit, because the VFPv4 is backward
366 compatible with VFPv3.
368 config BR2_ARM_FPU_VFPV4
370 depends on BR2_ARM_CPU_HAS_VFPV4
372 This option allows to use the VFPv4 floating point unit, as
373 available in some ARMv7 processors (Cortex-A{5, 7, 12,
374 15}). This option requires a VFPv4 unit that has 32
375 double-precision registers, which is not necessarily the
376 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
377 unsure, you should probably use VFPv4-D16 instead.
379 Note that if you want binary code that works on all ARMv7
380 cores, including the earlier Cortex-A{8, 9}, you should
381 instead select VFPv3.
383 config BR2_ARM_FPU_VFPV4D16
385 depends on BR2_ARM_CPU_HAS_VFPV4
387 This option allows to use the VFPv4 floating point unit, as
388 available in some ARMv7 processors (Cortex-A{5, 7, 12,
389 15}). This option requires a VFPv4 unit that has 16
390 double-precision registers, which is always available on
391 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
394 Note that if you want binary code that works on all ARMv7
395 cores, including the earlier Cortex-A{8, 9}, you should
396 instead select VFPv3-D16.
398 config BR2_ARM_FPU_NEON
400 depends on BR2_ARM_CPU_HAS_NEON
402 This option allows to use the NEON SIMD unit, as available
403 in some ARMv7 processors, as a floating-point unit. It
404 should however be noted that using NEON for floating point
405 operations doesn't provide a complete compatibility with the
408 config BR2_ARM_FPU_NEON_VFPV4
410 depends on BR2_ARM_CPU_HAS_VFPV4
411 depends on BR2_ARM_CPU_HAS_NEON
413 This option allows to use both the VFPv4 and the NEON SIMD
414 units for floating point operations. Note that some ARMv7
415 cores do not necessarily have VFPv4 and/or NEON support, for
416 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
422 prompt "ARM instruction set"
423 depends on BR2_arm || BR2_armeb
425 config BR2_ARM_INSTRUCTIONS_ARM
427 depends on BR2_ARM_CPU_HAS_ARM
429 This option instructs the compiler to generate regular ARM
430 instructions, that are all 32 bits wide.
432 config BR2_ARM_INSTRUCTIONS_THUMB
434 depends on BR2_ARM_CPU_HAS_THUMB
435 # Thumb-1 and VFP are not compatible
436 depends on BR2_ARM_SOFT_FLOAT
438 This option instructions the compiler to generate Thumb
439 instructions, which allows to mix 16 bits instructions and
440 32 bits instructions. This generally provides a much smaller
441 compiled binary size.
443 comment "Thumb1 is not compatible with VFP"
444 depends on BR2_ARM_CPU_HAS_THUMB
445 depends on !BR2_ARM_SOFT_FLOAT
447 config BR2_ARM_INSTRUCTIONS_THUMB2
449 depends on BR2_ARM_CPU_HAS_THUMB2
451 This option instructions the compiler to generate Thumb2
452 instructions, which allows to mix 16 bits instructions and
453 32 bits instructions. This generally provides a much smaller
454 compiled binary size.
459 default "arm" if BR2_arm
460 default "armeb" if BR2_armeb
461 default "aarch64" if BR2_aarch64
462 default "aarch64_be" if BR2_aarch64_be
465 default "LITTLE" if (BR2_arm || BR2_aarch64)
466 default "BIG" if (BR2_armeb || BR2_aarch64_be)
468 config BR2_GCC_TARGET_CPU
469 default "arm920t" if BR2_arm920t
470 default "arm922t" if BR2_arm922t
471 default "arm926ej-s" if BR2_arm926t
472 default "arm1136j-s" if BR2_arm1136j_s
473 default "arm1136jf-s" if BR2_arm1136jf_s
474 default "arm1176jz-s" if BR2_arm1176jz_s
475 default "arm1176jzf-s" if BR2_arm1176jzf_s
476 default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
477 default "mpcorenovfp" if BR2_arm11mpcore
478 default "cortex-a5" if BR2_cortex_a5
479 default "cortex-a7" if BR2_cortex_a7
480 default "cortex-a8" if BR2_cortex_a8
481 default "cortex-a9" if BR2_cortex_a9
482 default "cortex-a12" if BR2_cortex_a12
483 default "cortex-a15" if BR2_cortex_a15
484 default "cortex-a17" if BR2_cortex_a17
485 default "cortex-m3" if BR2_cortex_m3
486 default "cortex-m4" if BR2_cortex_m4
487 default "fa526" if BR2_fa526
488 default "marvell-pj4" if BR2_pj4
489 default "strongarm" if BR2_strongarm
490 default "xscale" if BR2_xscale
491 default "iwmmxt" if BR2_iwmmxt
493 config BR2_GCC_TARGET_ABI
494 default "aapcs-linux" if BR2_arm || BR2_armeb
496 config BR2_GCC_TARGET_FPU
497 depends on BR2_arm || BR2_armeb
498 default "vfp" if BR2_ARM_FPU_VFPV2
499 default "vfpv3" if BR2_ARM_FPU_VFPV3
500 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
501 default "vfpv4" if BR2_ARM_FPU_VFPV4
502 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
503 default "neon" if BR2_ARM_FPU_NEON
504 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
506 config BR2_GCC_TARGET_FLOAT_ABI
507 default "soft" if BR2_ARM_SOFT_FLOAT
508 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
509 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
511 config BR2_GCC_TARGET_MODE
512 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
513 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2