2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
60 Specific CPU variant to use
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
67 select BR2_ARCH_HAS_MMU_OPTIONAL
70 select BR2_ARM_CPU_HAS_ARM
71 select BR2_ARM_CPU_HAS_THUMB
72 select BR2_ARM_CPU_ARMV4
73 select BR2_ARCH_HAS_MMU_OPTIONAL
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
78 select BR2_ARM_CPU_HAS_THUMB
79 select BR2_ARM_CPU_ARMV5
80 select BR2_ARCH_HAS_MMU_OPTIONAL
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_HAS_THUMB
85 select BR2_ARM_CPU_ARMV6
86 select BR2_ARCH_HAS_MMU_OPTIONAL
87 config BR2_arm1136jf_s
89 select BR2_ARM_CPU_HAS_ARM
90 select BR2_ARM_CPU_HAS_VFPV2
91 select BR2_ARM_CPU_HAS_THUMB
92 select BR2_ARM_CPU_ARMV6
93 select BR2_ARCH_HAS_MMU_OPTIONAL
94 config BR2_arm1176jz_s
96 select BR2_ARM_CPU_HAS_ARM
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 config BR2_arm1176jzf_s
102 select BR2_ARM_CPU_HAS_ARM
103 select BR2_ARM_CPU_HAS_VFPV2
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
109 select BR2_ARM_CPU_HAS_ARM
110 select BR2_ARM_CPU_MAYBE_HAS_NEON
111 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
112 select BR2_ARM_CPU_HAS_THUMB2
113 select BR2_ARM_CPU_ARMV7A
114 select BR2_ARCH_HAS_MMU_OPTIONAL
117 select BR2_ARM_CPU_HAS_ARM
118 select BR2_ARM_CPU_HAS_NEON
119 select BR2_ARM_CPU_HAS_VFPV4
120 select BR2_ARM_CPU_HAS_THUMB2
121 select BR2_ARM_CPU_ARMV7A
122 select BR2_ARCH_HAS_MMU_OPTIONAL
125 select BR2_ARM_CPU_HAS_ARM
126 select BR2_ARM_CPU_HAS_NEON
127 select BR2_ARM_CPU_HAS_VFPV3
128 select BR2_ARM_CPU_HAS_THUMB2
129 select BR2_ARM_CPU_ARMV7A
130 select BR2_ARCH_HAS_MMU_OPTIONAL
133 select BR2_ARM_CPU_HAS_ARM
134 select BR2_ARM_CPU_MAYBE_HAS_NEON
135 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
136 select BR2_ARM_CPU_HAS_THUMB2
137 select BR2_ARM_CPU_ARMV7A
138 select BR2_ARCH_HAS_MMU_OPTIONAL
139 config BR2_cortex_a12
141 select BR2_ARM_CPU_HAS_ARM
142 select BR2_ARM_CPU_HAS_NEON
143 select BR2_ARM_CPU_HAS_VFPV4
144 select BR2_ARM_CPU_HAS_THUMB2
145 select BR2_ARM_CPU_ARMV7A
146 select BR2_ARCH_HAS_MMU_OPTIONAL
147 config BR2_cortex_a15
149 select BR2_ARM_CPU_HAS_ARM
150 select BR2_ARM_CPU_HAS_NEON
151 select BR2_ARM_CPU_HAS_VFPV4
152 select BR2_ARM_CPU_HAS_THUMB2
153 select BR2_ARM_CPU_ARMV7A
154 select BR2_ARCH_HAS_MMU_OPTIONAL
157 select BR2_ARM_CPU_HAS_THUMB
158 select BR2_ARM_CPU_HAS_THUMB2
161 select BR2_ARM_CPU_HAS_ARM
162 select BR2_ARM_CPU_ARMV4
163 select BR2_ARCH_HAS_MMU_OPTIONAL
166 select BR2_ARM_CPU_HAS_ARM
167 select BR2_ARM_CPU_HAS_VFPV3
168 select BR2_ARM_CPU_ARMV7A
169 select BR2_ARCH_HAS_MMU_OPTIONAL
171 bool "strongarm sa110/sa1100"
172 select BR2_ARM_CPU_HAS_ARM
173 select BR2_ARM_CPU_ARMV4
174 select BR2_ARCH_HAS_MMU_OPTIONAL
177 select BR2_ARM_CPU_HAS_ARM
178 select BR2_ARM_CPU_HAS_THUMB
179 select BR2_ARM_CPU_ARMV5
180 select BR2_ARCH_HAS_MMU_OPTIONAL
183 select BR2_ARM_CPU_HAS_ARM
184 select BR2_ARM_CPU_ARMV5
185 select BR2_ARCH_HAS_MMU_OPTIONAL
188 config BR2_ARM_ENABLE_NEON
189 bool "Enable NEON SIMD extension support"
190 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
191 select BR2_ARM_CPU_HAS_NEON
193 For some CPU cores, the NEON SIMD extension is optional.
194 Select this option if you are certain your particular
195 implementation has NEON support and you want to use it.
197 config BR2_ARM_ENABLE_VFP
198 bool "Enable VFP extension support"
199 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
200 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
201 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
202 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
206 depends on BR2_arm || BR2_armeb
207 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
210 Application Binary Interface to use. The Application Binary
211 Interface describes the calling conventions (how arguments
212 are passed to functions, how the return value is passed, how
213 system calls are made, etc.).
218 The EABI is currently the standard ARM ABI, which is used in
219 most projects. It supports both the 'soft' floating point
220 model (in which floating point instructions are emulated in
221 software) and the 'softfp' floating point model (in which
222 floating point instructions are executed using an hardware
223 floating point unit, but floating point arguments to
224 functions are passed in integer registers).
226 The 'softfp' floating point model is link-compatible with
227 the 'soft' floating point model, i.e you can link a library
228 built 'soft' with some other code built 'softfp'.
230 However, passing the floating point arguments in integer
231 registers is a bit inefficient, so if your ARM processor has
232 a floating point unit, and you don't have pre-compiled
233 'soft' or 'softfp' code, using the EABIhf ABI will provide
234 better floating point performances.
236 If your processor does not have a floating point unit, then
237 you must use this ABI.
239 config BR2_ARM_EABIHF
241 depends on BR2_ARM_CPU_HAS_VFPV2
243 The EABIhf is an extension of EABI which supports the 'hard'
244 floating point model. This model uses the floating point
245 unit to execute floating point instructions, and passes
246 floating point arguments in floating point registers.
248 It is more efficient than EABI for floating point related
249 workload. However, it does not allow to link against code
250 that has been pre-built for the 'soft' or 'softfp' floating
253 If your processor has a floating point unit, and you don't
254 depend on existing pre-compiled code, this option is most
255 likely the best choice.
260 prompt "Floating point strategy"
261 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
262 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
263 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
264 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
265 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
267 config BR2_ARM_SOFT_FLOAT
269 depends on BR2_ARM_EABI
270 select BR2_SOFT_FLOAT
272 This option allows to use software emulated floating
273 point. It should be used for ARM cores that do not include a
274 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
275 example) or certain ARMv6 cores.
277 config BR2_ARM_FPU_VFPV2
279 depends on BR2_ARM_CPU_HAS_VFPV2
281 This option allows to use the VFPv2 floating point unit, as
282 available in some ARMv5 processors (ARM926EJ-S) and some
283 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
286 Note that this option is also safe to use for newer cores
287 such as Cortex-A, because the VFPv3 and VFPv4 units are
288 backward compatible with VFPv2.
290 config BR2_ARM_FPU_VFPV3
292 depends on BR2_ARM_CPU_HAS_VFPV3
294 This option allows to use the VFPv3 floating point unit, as
295 available in some ARMv7 processors (Cortex-A{8, 9}). This
296 option requires a VFPv3 unit that has 32 double-precision
297 registers, which is not necessarily the case in all SOCs
298 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
299 instead, which is guaranteed to work on all Cortex-A{8, 9}.
301 Note that this option is also safe to use for newer cores
302 that have a VFPv4 unit, because VFPv4 is backward compatible
303 with VFPv3. They must of course also have 32
304 double-precision registers.
306 config BR2_ARM_FPU_VFPV3D16
308 depends on BR2_ARM_CPU_HAS_VFPV3
310 This option allows to use the VFPv3 floating point unit, as
311 available in some ARMv7 processors (Cortex-A{8, 9}). This
312 option requires a VFPv3 unit that has 16 double-precision
313 registers, which is generally the case in all SOCs based on
314 Cortex-A{8, 9}, even though VFPv3 is technically optional on
315 Cortex-A9. This is the safest option for those cores.
317 Note that this option is also safe to use for newer cores
318 such that have a VFPv4 unit, because the VFPv4 is backward
319 compatible with VFPv3.
321 config BR2_ARM_FPU_VFPV4
323 depends on BR2_ARM_CPU_HAS_VFPV4
325 This option allows to use the VFPv4 floating point unit, as
326 available in some ARMv7 processors (Cortex-A{5, 7, 12,
327 15}). This option requires a VFPv4 unit that has 32
328 double-precision registers, which is not necessarily the
329 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
330 unsure, you should probably use VFPv4-D16 instead.
332 Note that if you want binary code that works on all ARMv7
333 cores, including the earlier Cortex-A{8, 9}, you should
334 instead select VFPv3.
336 config BR2_ARM_FPU_VFPV4D16
338 depends on BR2_ARM_CPU_HAS_VFPV4
340 This option allows to use the VFPv4 floating point unit, as
341 available in some ARMv7 processors (Cortex-A{5, 7, 12,
342 15}). This option requires a VFPv4 unit that has 16
343 double-precision registers, which is always available on
344 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
347 Note that if you want binary code that works on all ARMv7
348 cores, including the earlier Cortex-A{8, 9}, you should
349 instead select VFPv3-D16.
351 config BR2_ARM_FPU_NEON
353 depends on BR2_ARM_CPU_HAS_NEON
355 This option allows to use the NEON SIMD unit, as available
356 in some ARMv7 processors, as a floating-point unit. It
357 should however be noted that using NEON for floating point
358 operations doesn't provide a complete compatibility with the
361 config BR2_ARM_FPU_NEON_VFPV4
363 depends on BR2_ARM_CPU_HAS_VFPV4
364 depends on BR2_ARM_CPU_HAS_NEON
366 This option allows to use both the VFPv4 and the NEON SIMD
367 units for floating point operations. Note that some ARMv7
368 cores do not necessarily have VFPv4 and/or NEON support, for
369 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
375 prompt "ARM instruction set"
377 config BR2_ARM_INSTRUCTIONS_ARM
379 depends on BR2_ARM_CPU_HAS_ARM
381 This option instructs the compiler to generate regular ARM
382 instructions, that are all 32 bits wide.
384 config BR2_ARM_INSTRUCTIONS_THUMB
386 depends on BR2_ARM_CPU_HAS_THUMB
387 # Thumb-1 and VFP are not compatible
388 depends on BR2_ARM_SOFT_FLOAT
390 This option instructions the compiler to generate Thumb
391 instructions, which allows to mix 16 bits instructions and
392 32 bits instructions. This generally provides a much smaller
393 compiled binary size.
395 comment "Thumb1 is not compatible with VFP"
396 depends on BR2_ARM_CPU_HAS_THUMB
397 depends on !BR2_ARM_SOFT_FLOAT
399 config BR2_ARM_INSTRUCTIONS_THUMB2
401 depends on BR2_ARM_CPU_HAS_THUMB2
403 This option instructions the compiler to generate Thumb2
404 instructions, which allows to mix 16 bits instructions and
405 32 bits instructions. This generally provides a much smaller
406 compiled binary size.
411 default "arm" if BR2_arm
412 default "armeb" if BR2_armeb
415 default "LITTLE" if BR2_arm
416 default "BIG" if BR2_armeb
418 config BR2_ARCH_HAS_ATOMICS
421 config BR2_GCC_TARGET_CPU
422 default "arm920t" if BR2_arm920t
423 default "arm922t" if BR2_arm922t
424 default "arm926ej-s" if BR2_arm926t
425 default "arm1136j-s" if BR2_arm1136j_s
426 default "arm1136jf-s" if BR2_arm1136jf_s
427 default "arm1176jz-s" if BR2_arm1176jz_s
428 default "arm1176jzf-s" if BR2_arm1176jzf_s
429 default "cortex-a5" if BR2_cortex_a5
430 default "cortex-a7" if BR2_cortex_a7
431 default "cortex-a8" if BR2_cortex_a8
432 default "cortex-a9" if BR2_cortex_a9
433 default "cortex-a12" if BR2_cortex_a12
434 default "cortex-a15" if BR2_cortex_a15
435 default "cortex-m3" if BR2_cortex_m3
436 default "fa526" if BR2_fa526
437 default "marvell-pj4" if BR2_pj4
438 default "strongarm" if BR2_strongarm
439 default "xscale" if BR2_xscale
440 default "iwmmxt" if BR2_iwmmxt
442 config BR2_GCC_TARGET_ABI
443 default "aapcs-linux"
445 config BR2_GCC_TARGET_FPU
446 default "vfp" if BR2_ARM_FPU_VFPV2
447 default "vfpv3" if BR2_ARM_FPU_VFPV3
448 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
449 default "vfpv4" if BR2_ARM_FPU_VFPV4
450 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
451 default "neon" if BR2_ARM_FPU_NEON
452 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
454 config BR2_GCC_TARGET_FLOAT_ABI
455 default "soft" if BR2_ARM_SOFT_FLOAT
456 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
457 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
459 config BR2_GCC_TARGET_MODE
460 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
461 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2