2 config BR2_ARM_CPU_HAS_NEON
5 # for some cores, NEON support is optional
6 config BR2_ARM_CPU_MAYBE_HAS_NEON
9 # for some cores, VFPv2 is optional
10 config BR2_ARM_CPU_MAYBE_HAS_VFPV2
13 config BR2_ARM_CPU_HAS_VFPV2
16 # for some cores, VFPv3 is optional
17 config BR2_ARM_CPU_MAYBE_HAS_VFPV3
19 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
21 config BR2_ARM_CPU_HAS_VFPV3
23 select BR2_ARM_CPU_HAS_VFPV2
25 # for some cores, VFPv4 is optional
26 config BR2_ARM_CPU_MAYBE_HAS_VFPV4
28 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
30 config BR2_ARM_CPU_HAS_VFPV4
32 select BR2_ARM_CPU_HAS_VFPV3
34 config BR2_ARM_CPU_HAS_ARM
37 config BR2_ARM_CPU_HAS_THUMB
40 config BR2_ARM_CPU_HAS_THUMB2
43 config BR2_ARM_CPU_ARMV4
46 config BR2_ARM_CPU_ARMV5
49 config BR2_ARM_CPU_ARMV6
52 config BR2_ARM_CPU_ARMV7A
56 prompt "Target Architecture Variant"
57 depends on BR2_arm || BR2_armeb
60 Specific CPU variant to use
64 select BR2_ARM_CPU_HAS_ARM
65 select BR2_ARM_CPU_HAS_THUMB
66 select BR2_ARM_CPU_ARMV4
67 select BR2_ARCH_HAS_MMU_OPTIONAL
70 select BR2_ARM_CPU_HAS_ARM
71 select BR2_ARM_CPU_HAS_THUMB
72 select BR2_ARM_CPU_ARMV4
73 select BR2_ARCH_HAS_MMU_OPTIONAL
76 select BR2_ARM_CPU_HAS_ARM
77 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
78 select BR2_ARM_CPU_HAS_THUMB
79 select BR2_ARM_CPU_ARMV5
80 select BR2_ARCH_HAS_MMU_OPTIONAL
83 select BR2_ARM_CPU_HAS_ARM
84 select BR2_ARM_CPU_HAS_THUMB
85 select BR2_ARM_CPU_ARMV6
86 select BR2_ARCH_HAS_MMU_OPTIONAL
87 config BR2_arm1136jf_s
89 select BR2_ARM_CPU_HAS_ARM
90 select BR2_ARM_CPU_HAS_VFPV2
91 select BR2_ARM_CPU_HAS_THUMB
92 select BR2_ARM_CPU_ARMV6
93 select BR2_ARCH_HAS_MMU_OPTIONAL
94 config BR2_arm1176jz_s
96 select BR2_ARM_CPU_HAS_ARM
97 select BR2_ARM_CPU_HAS_THUMB
98 select BR2_ARM_CPU_ARMV6
99 select BR2_ARCH_HAS_MMU_OPTIONAL
100 config BR2_arm1176jzf_s
102 select BR2_ARM_CPU_HAS_ARM
103 select BR2_ARM_CPU_HAS_VFPV2
104 select BR2_ARM_CPU_HAS_THUMB
105 select BR2_ARM_CPU_ARMV6
106 select BR2_ARCH_HAS_MMU_OPTIONAL
107 config BR2_arm11mpcore
109 select BR2_ARM_CPU_HAS_ARM
110 select BR2_ARM_CPU_MAYBE_HAS_VFPV2
111 select BR2_ARM_CPU_HAS_THUMB
112 select BR2_ARM_CPU_ARMV6
113 select BR2_ARCH_HAS_MMU_OPTIONAL
116 select BR2_ARM_CPU_HAS_ARM
117 select BR2_ARM_CPU_MAYBE_HAS_NEON
118 select BR2_ARM_CPU_MAYBE_HAS_VFPV4
119 select BR2_ARM_CPU_HAS_THUMB2
120 select BR2_ARM_CPU_ARMV7A
121 select BR2_ARCH_HAS_MMU_OPTIONAL
124 select BR2_ARM_CPU_HAS_ARM
125 select BR2_ARM_CPU_HAS_NEON
126 select BR2_ARM_CPU_HAS_VFPV4
127 select BR2_ARM_CPU_HAS_THUMB2
128 select BR2_ARM_CPU_ARMV7A
129 select BR2_ARCH_HAS_MMU_OPTIONAL
132 select BR2_ARM_CPU_HAS_ARM
133 select BR2_ARM_CPU_HAS_NEON
134 select BR2_ARM_CPU_HAS_VFPV3
135 select BR2_ARM_CPU_HAS_THUMB2
136 select BR2_ARM_CPU_ARMV7A
137 select BR2_ARCH_HAS_MMU_OPTIONAL
140 select BR2_ARM_CPU_HAS_ARM
141 select BR2_ARM_CPU_MAYBE_HAS_NEON
142 select BR2_ARM_CPU_MAYBE_HAS_VFPV3
143 select BR2_ARM_CPU_HAS_THUMB2
144 select BR2_ARM_CPU_ARMV7A
145 select BR2_ARCH_HAS_MMU_OPTIONAL
146 config BR2_cortex_a12
148 select BR2_ARM_CPU_HAS_ARM
149 select BR2_ARM_CPU_HAS_NEON
150 select BR2_ARM_CPU_HAS_VFPV4
151 select BR2_ARM_CPU_HAS_THUMB2
152 select BR2_ARM_CPU_ARMV7A
153 select BR2_ARCH_HAS_MMU_OPTIONAL
154 config BR2_cortex_a15
156 select BR2_ARM_CPU_HAS_ARM
157 select BR2_ARM_CPU_HAS_NEON
158 select BR2_ARM_CPU_HAS_VFPV4
159 select BR2_ARM_CPU_HAS_THUMB2
160 select BR2_ARM_CPU_ARMV7A
161 select BR2_ARCH_HAS_MMU_OPTIONAL
162 config BR2_cortex_a17
164 select BR2_ARM_CPU_HAS_ARM
165 select BR2_ARM_CPU_HAS_NEON
166 select BR2_ARM_CPU_HAS_VFPV4
167 select BR2_ARM_CPU_HAS_THUMB2
168 select BR2_ARM_CPU_ARMV7A
169 select BR2_ARCH_HAS_MMU_OPTIONAL
172 select BR2_ARM_CPU_HAS_THUMB
173 select BR2_ARM_CPU_HAS_THUMB2
176 select BR2_ARM_CPU_HAS_ARM
177 select BR2_ARM_CPU_ARMV4
178 select BR2_ARCH_HAS_MMU_OPTIONAL
181 select BR2_ARM_CPU_HAS_ARM
182 select BR2_ARM_CPU_HAS_VFPV3
183 select BR2_ARM_CPU_ARMV7A
184 select BR2_ARCH_HAS_MMU_OPTIONAL
186 bool "strongarm sa110/sa1100"
187 select BR2_ARM_CPU_HAS_ARM
188 select BR2_ARM_CPU_ARMV4
189 select BR2_ARCH_HAS_MMU_OPTIONAL
192 select BR2_ARM_CPU_HAS_ARM
193 select BR2_ARM_CPU_HAS_THUMB
194 select BR2_ARM_CPU_ARMV5
195 select BR2_ARCH_HAS_MMU_OPTIONAL
198 select BR2_ARM_CPU_HAS_ARM
199 select BR2_ARM_CPU_ARMV5
200 select BR2_ARCH_HAS_MMU_OPTIONAL
203 config BR2_ARM_ENABLE_NEON
204 bool "Enable NEON SIMD extension support"
205 depends on BR2_ARM_CPU_MAYBE_HAS_NEON
206 select BR2_ARM_CPU_HAS_NEON
208 For some CPU cores, the NEON SIMD extension is optional.
209 Select this option if you are certain your particular
210 implementation has NEON support and you want to use it.
212 config BR2_ARM_ENABLE_VFP
213 bool "Enable VFP extension support"
214 depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
215 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
216 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
217 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
219 For some CPU cores, the VFP extension is optional. Select
220 this option if you are certain your particular
221 implementation has VFP support and you want to use it.
225 depends on BR2_arm || BR2_armeb
226 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
229 Application Binary Interface to use. The Application Binary
230 Interface describes the calling conventions (how arguments
231 are passed to functions, how the return value is passed, how
232 system calls are made, etc.).
237 The EABI is currently the standard ARM ABI, which is used in
238 most projects. It supports both the 'soft' floating point
239 model (in which floating point instructions are emulated in
240 software) and the 'softfp' floating point model (in which
241 floating point instructions are executed using an hardware
242 floating point unit, but floating point arguments to
243 functions are passed in integer registers).
245 The 'softfp' floating point model is link-compatible with
246 the 'soft' floating point model, i.e you can link a library
247 built 'soft' with some other code built 'softfp'.
249 However, passing the floating point arguments in integer
250 registers is a bit inefficient, so if your ARM processor has
251 a floating point unit, and you don't have pre-compiled
252 'soft' or 'softfp' code, using the EABIhf ABI will provide
253 better floating point performances.
255 If your processor does not have a floating point unit, then
256 you must use this ABI.
258 config BR2_ARM_EABIHF
260 depends on BR2_ARM_CPU_HAS_VFPV2
262 The EABIhf is an extension of EABI which supports the 'hard'
263 floating point model. This model uses the floating point
264 unit to execute floating point instructions, and passes
265 floating point arguments in floating point registers.
267 It is more efficient than EABI for floating point related
268 workload. However, it does not allow to link against code
269 that has been pre-built for the 'soft' or 'softfp' floating
272 If your processor has a floating point unit, and you don't
273 depend on existing pre-compiled code, this option is most
274 likely the best choice.
279 prompt "Floating point strategy"
280 depends on BR2_ARM_EABI || BR2_ARM_EABIHF
281 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
282 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
283 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
284 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
286 config BR2_ARM_SOFT_FLOAT
288 depends on BR2_ARM_EABI
289 select BR2_SOFT_FLOAT
291 This option allows to use software emulated floating
292 point. It should be used for ARM cores that do not include a
293 Vector Floating Point unit, such as ARMv5 cores (ARM926 for
294 example) or certain ARMv6 cores.
296 config BR2_ARM_FPU_VFPV2
298 depends on BR2_ARM_CPU_HAS_VFPV2
300 This option allows to use the VFPv2 floating point unit, as
301 available in some ARMv5 processors (ARM926EJ-S) and some
302 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
305 Note that this option is also safe to use for newer cores
306 such as Cortex-A, because the VFPv3 and VFPv4 units are
307 backward compatible with VFPv2.
309 config BR2_ARM_FPU_VFPV3
311 depends on BR2_ARM_CPU_HAS_VFPV3
313 This option allows to use the VFPv3 floating point unit, as
314 available in some ARMv7 processors (Cortex-A{8, 9}). This
315 option requires a VFPv3 unit that has 32 double-precision
316 registers, which is not necessarily the case in all SOCs
317 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16
318 instead, which is guaranteed to work on all Cortex-A{8, 9}.
320 Note that this option is also safe to use for newer cores
321 that have a VFPv4 unit, because VFPv4 is backward compatible
322 with VFPv3. They must of course also have 32
323 double-precision registers.
325 config BR2_ARM_FPU_VFPV3D16
327 depends on BR2_ARM_CPU_HAS_VFPV3
329 This option allows to use the VFPv3 floating point unit, as
330 available in some ARMv7 processors (Cortex-A{8, 9}). This
331 option requires a VFPv3 unit that has 16 double-precision
332 registers, which is generally the case in all SOCs based on
333 Cortex-A{8, 9}, even though VFPv3 is technically optional on
334 Cortex-A9. This is the safest option for those cores.
336 Note that this option is also safe to use for newer cores
337 such that have a VFPv4 unit, because the VFPv4 is backward
338 compatible with VFPv3.
340 config BR2_ARM_FPU_VFPV4
342 depends on BR2_ARM_CPU_HAS_VFPV4
344 This option allows to use the VFPv4 floating point unit, as
345 available in some ARMv7 processors (Cortex-A{5, 7, 12,
346 15}). This option requires a VFPv4 unit that has 32
347 double-precision registers, which is not necessarily the
348 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're
349 unsure, you should probably use VFPv4-D16 instead.
351 Note that if you want binary code that works on all ARMv7
352 cores, including the earlier Cortex-A{8, 9}, you should
353 instead select VFPv3.
355 config BR2_ARM_FPU_VFPV4D16
357 depends on BR2_ARM_CPU_HAS_VFPV4
359 This option allows to use the VFPv4 floating point unit, as
360 available in some ARMv7 processors (Cortex-A{5, 7, 12,
361 15}). This option requires a VFPv4 unit that has 16
362 double-precision registers, which is always available on
363 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and
366 Note that if you want binary code that works on all ARMv7
367 cores, including the earlier Cortex-A{8, 9}, you should
368 instead select VFPv3-D16.
370 config BR2_ARM_FPU_NEON
372 depends on BR2_ARM_CPU_HAS_NEON
374 This option allows to use the NEON SIMD unit, as available
375 in some ARMv7 processors, as a floating-point unit. It
376 should however be noted that using NEON for floating point
377 operations doesn't provide a complete compatibility with the
380 config BR2_ARM_FPU_NEON_VFPV4
382 depends on BR2_ARM_CPU_HAS_VFPV4
383 depends on BR2_ARM_CPU_HAS_NEON
385 This option allows to use both the VFPv4 and the NEON SIMD
386 units for floating point operations. Note that some ARMv7
387 cores do not necessarily have VFPv4 and/or NEON support, for
388 example on Cortex-A5 and Cortex-A7, support for VFPv4 and
394 prompt "ARM instruction set"
396 config BR2_ARM_INSTRUCTIONS_ARM
398 depends on BR2_ARM_CPU_HAS_ARM
400 This option instructs the compiler to generate regular ARM
401 instructions, that are all 32 bits wide.
403 config BR2_ARM_INSTRUCTIONS_THUMB
405 depends on BR2_ARM_CPU_HAS_THUMB
406 # Thumb-1 and VFP are not compatible
407 depends on BR2_ARM_SOFT_FLOAT
409 This option instructions the compiler to generate Thumb
410 instructions, which allows to mix 16 bits instructions and
411 32 bits instructions. This generally provides a much smaller
412 compiled binary size.
414 comment "Thumb1 is not compatible with VFP"
415 depends on BR2_ARM_CPU_HAS_THUMB
416 depends on !BR2_ARM_SOFT_FLOAT
418 config BR2_ARM_INSTRUCTIONS_THUMB2
420 depends on BR2_ARM_CPU_HAS_THUMB2
422 This option instructions the compiler to generate Thumb2
423 instructions, which allows to mix 16 bits instructions and
424 32 bits instructions. This generally provides a much smaller
425 compiled binary size.
430 default "arm" if BR2_arm
431 default "armeb" if BR2_armeb
434 default "LITTLE" if BR2_arm
435 default "BIG" if BR2_armeb
437 config BR2_GCC_TARGET_CPU
438 default "arm920t" if BR2_arm920t
439 default "arm922t" if BR2_arm922t
440 default "arm926ej-s" if BR2_arm926t
441 default "arm1136j-s" if BR2_arm1136j_s
442 default "arm1136jf-s" if BR2_arm1136jf_s
443 default "arm1176jz-s" if BR2_arm1176jz_s
444 default "arm1176jzf-s" if BR2_arm1176jzf_s
445 default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
446 default "mpcorenovfp" if BR2_arm11mpcore
447 default "cortex-a5" if BR2_cortex_a5
448 default "cortex-a7" if BR2_cortex_a7
449 default "cortex-a8" if BR2_cortex_a8
450 default "cortex-a9" if BR2_cortex_a9
451 default "cortex-a12" if BR2_cortex_a12
452 default "cortex-a15" if BR2_cortex_a15
453 default "cortex-a17" if BR2_cortex_a17
454 default "cortex-m3" if BR2_cortex_m3
455 default "fa526" if BR2_fa526
456 default "marvell-pj4" if BR2_pj4
457 default "strongarm" if BR2_strongarm
458 default "xscale" if BR2_xscale
459 default "iwmmxt" if BR2_iwmmxt
461 config BR2_GCC_TARGET_ABI
462 default "aapcs-linux"
464 config BR2_GCC_TARGET_FPU
465 default "vfp" if BR2_ARM_FPU_VFPV2
466 default "vfpv3" if BR2_ARM_FPU_VFPV3
467 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
468 default "vfpv4" if BR2_ARM_FPU_VFPV4
469 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
470 default "neon" if BR2_ARM_FPU_NEON
471 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
473 config BR2_GCC_TARGET_FLOAT_ABI
474 default "soft" if BR2_ARM_SOFT_FLOAT
475 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
476 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
478 config BR2_GCC_TARGET_MODE
479 default "arm" if BR2_ARM_INSTRUCTIONS_ARM
480 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2