ARM: i.MX clk pllv1: move mxc_decode_pll code to its user

The only code using mxc_decode_pll is clk-pllv1.c, so move the code
there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>

diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9ccf59086cf73ffdf22a1a290fc1f33a37..4a03c93609341d541afeae8e5a3e5e38d1887cc0 100644 (file)
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -29,8 +29,53 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
                unsigned long parent_rate)
 {
        struct clk_pllv1 *pll = to_clk_pllv1(hw);
+       long long ll;
+       int mfn_abs;
+       unsigned int mfi, mfn, mfd, pd;
+       u32 reg;
+       unsigned long rate;
 
-       return mxc_decode_pll(readl(pll->base), parent_rate);
+       reg = readl(pll->base);
+
+       /*
+        * Get the resulting clock rate from a PLL register value and the input
+        * frequency. PLLs with this register layout can be found on i.MX1,
+        * i.MX21, i.MX27 and i,MX31
+        *
+        *                  mfi + mfn / (mfd + 1)
+        *  f = 2 * f_ref * --------------------
+        *                        pd + 1
+        */
+
+       mfi = (reg >> 10) & 0xf;
+       mfn = reg & 0x3ff;
+       mfd = (reg >> 16) & 0x3ff;
+       pd =  (reg >> 26) & 0xf;
+
+       mfi = mfi <= 5 ? 5 : mfi;
+
+       mfn_abs = mfn;
+
+       /*
+        * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+        * 2's complements number
+        */
+       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+               mfn_abs = 0x400 - mfn;
+
+       rate = parent_rate * 2;
+       rate /= pd + 1;
+
+       ll = (unsigned long long)rate * mfn_abs;
+
+       do_div(ll, mfd + 1);
+
+       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+               ll = -ll;
+
+       ll = (rate * mfi) + ll;
+
+       return ll;
 }
 
 struct clk_ops clk_pllv1_ops = {

diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 5079787273d27a4ca0b54cd63bcf62008120847a..0ed09549468de934c2a919a3d8bfbb76fb1072e2 100644 (file)
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -210,48 +210,3 @@ EXPORT_SYMBOL(clk_get_parent);
 DEFINE_SPINLOCK(imx_ccm_lock);
 
 #endif /* CONFIG_COMMON_CLK */
-
-/*
- * Get the resulting clock rate from a PLL register value and the input
- * frequency. PLLs with this register layout can at least be found on
- * MX1, MX21, MX27 and MX31
- *
- *                  mfi + mfn / (mfd + 1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
-{
-       long long ll;
-       int mfn_abs;
-       unsigned int mfi, mfn, mfd, pd;
-
-       mfi = (reg_val >> 10) & 0xf;
-       mfn = reg_val & 0x3ff;
-       mfd = (reg_val >> 16) & 0x3ff;
-       pd =  (reg_val >> 26) & 0xf;
-
-       mfi = mfi <= 5 ? 5 : mfi;
-
-       mfn_abs = mfn;
-
-       /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-        * 2's complements number
-        */
-       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-               mfn_abs = 0x400 - mfn;
-
-       freq *= 2;
-       freq /= pd + 1;
-
-       ll = (unsigned long long)freq * mfn_abs;
-
-       do_div(ll, mfd + 1);
-
-       if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-               ll = -ll;
-
-       ll = (freq * mfi) + ll;
-
-       return ll;
-}

diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index bd940c795cbbff0c3a1785247e43aac1a43e7acf..0c4ad776f726a6a19e02aa982fc99c447be3022a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -64,7 +64,5 @@ void clk_unregister(struct clk *clk);
 
 extern spinlock_t imx_ccm_lock;
 
-unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
-
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MXC_CLOCK_H__ */