arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         cache-controller@50043000 {
   8                 compatible = "arm,pl310-cache";
   9                 reg = <0x50043000 0x1000>;
  10                 arm,data-latency = <5 5 2>;
  11                 arm,tag-latency = <4 4 2>;
  12                 cache-unified;
  13                 cache-level = <2>;
  14         };
  15
  16         intc: interrupt-controller {
  17                 compatible = "arm,cortex-a9-gic";
  18                 reg = <0x50041000 0x1000
  19                        0x50040100 0x0100>;
  20                 interrupt-controller;
  21                 #interrupt-cells = <3>;
  22         };
  23
  24         apbdma: dma {
  25                 compatible = "nvidia,tegra20-apbdma";
  26                 reg = <0x6000a000 0x1200>;
  27                 interrupts = <0 104 0x04
  28                               0 105 0x04
  29                               0 106 0x04
  30                               0 107 0x04
  31                               0 108 0x04
  32                               0 109 0x04
  33                               0 110 0x04
  34                               0 111 0x04
  35                               0 112 0x04
  36                               0 113 0x04
  37                               0 114 0x04
  38                               0 115 0x04
  39                               0 116 0x04
  40                               0 117 0x04
  41                               0 118 0x04
  42                               0 119 0x04>;
  43         };
  44
  45         ahb {
  46                 compatible = "nvidia,tegra20-ahb";
  47                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  48         };
  49
  50         gpio: gpio {
  51                 compatible = "nvidia,tegra20-gpio";
  52                 reg = <0x6000d000 0x1000>;
  53                 interrupts = <0 32 0x04
  54                               0 33 0x04
  55                               0 34 0x04
  56                               0 35 0x04
  57                               0 55 0x04
  58                               0 87 0x04
  59                               0 89 0x04>;
  60                 #gpio-cells = <2>;
  61                 gpio-controller;
  62                 #interrupt-cells = <2>;
  63                 interrupt-controller;
  64         };
  65
  66         pinmux: pinmux {
  67                 compatible = "nvidia,tegra20-pinmux";
  68                 reg = <0x70000014 0x10   /* Tri-state registers */
  69                        0x70000080 0x20   /* Mux registers */
  70                        0x700000a0 0x14   /* Pull-up/down registers */
  71                        0x70000868 0xa8>; /* Pad control registers */
  72         };
  73
  74         das {
  75                 compatible = "nvidia,tegra20-das";
  76                 reg = <0x70000c00 0x80>;
  77         };
  78
  79         tegra_i2s1: i2s@70002800 {
  80                 compatible = "nvidia,tegra20-i2s";
  81                 reg = <0x70002800 0x200>;
  82                 interrupts = <0 13 0x04>;
  83                 nvidia,dma-request-selector = <&apbdma 2>;
  84                 status = "disabled";
  85         };
  86
  87         tegra_i2s2: i2s@70002a00 {
  88                 compatible = "nvidia,tegra20-i2s";
  89                 reg = <0x70002a00 0x200>;
  90                 interrupts = <0 3 0x04>;
  91                 nvidia,dma-request-selector = <&apbdma 1>;
  92                 status = "disabled";
  93         };
  94
  95         serial@70006000 {
  96                 compatible = "nvidia,tegra20-uart";
  97                 reg = <0x70006000 0x40>;
  98                 reg-shift = <2>;
  99                 interrupts = <0 36 0x04>;
 100                 status = "disabled";
 101         };
 102
 103         serial@70006040 {
 104                 compatible = "nvidia,tegra20-uart";
 105                 reg = <0x70006040 0x40>;
 106                 reg-shift = <2>;
 107                 interrupts = <0 37 0x04>;
 108                 status = "disabled";
 109         };
 110
 111         serial@70006200 {
 112                 compatible = "nvidia,tegra20-uart";
 113                 reg = <0x70006200 0x100>;
 114                 reg-shift = <2>;
 115                 interrupts = <0 46 0x04>;
 116                 status = "disabled";
 117         };
 118
 119         serial@70006300 {
 120                 compatible = "nvidia,tegra20-uart";
 121                 reg = <0x70006300 0x100>;
 122                 reg-shift = <2>;
 123                 interrupts = <0 90 0x04>;
 124                 status = "disabled";
 125         };
 126
 127         serial@70006400 {
 128                 compatible = "nvidia,tegra20-uart";
 129                 reg = <0x70006400 0x100>;
 130                 reg-shift = <2>;
 131                 interrupts = <0 91 0x04>;
 132                 status = "disabled";
 133         };
 134
 135         pwm: pwm {
 136                 compatible = "nvidia,tegra20-pwm";
 137                 reg = <0x7000a000 0x100>;
 138                 #pwm-cells = <2>;
 139         };
 140
 141         i2c@7000c000 {
 142                 compatible = "nvidia,tegra20-i2c";
 143                 reg = <0x7000c000 0x100>;
 144                 interrupts = <0 38 0x04>;
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147                 status = "disabled";
 148         };
 149
 150         spi@7000c380 {
 151                 compatible = "nvidia,tegra20-sflash";
 152                 reg = <0x7000c380 0x80>;
 153                 interrupts = <0 39 0x04>;
 154                 nvidia,dma-request-selector = <&apbdma 11>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 status = "disabled";
 158         };
 159
 160         i2c@7000c400 {
 161                 compatible = "nvidia,tegra20-i2c";
 162                 reg = <0x7000c400 0x100>;
 163                 interrupts = <0 84 0x04>;
 164                 #address-cells = <1>;
 165                 #size-cells = <0>;
 166                 status = "disabled";
 167         };
 168
 169         i2c@7000c500 {
 170                 compatible = "nvidia,tegra20-i2c";
 171                 reg = <0x7000c500 0x100>;
 172                 interrupts = <0 92 0x04>;
 173                 #address-cells = <1>;
 174                 #size-cells = <0>;
 175                 status = "disabled";
 176         };
 177
 178         i2c@7000d000 {
 179                 compatible = "nvidia,tegra20-i2c-dvc";
 180                 reg = <0x7000d000 0x200>;
 181                 interrupts = <0 53 0x04>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 status = "disabled";
 185         };
 186
 187         spi@7000d400 {
 188                 compatible = "nvidia,tegra20-slink";
 189                 reg = <0x7000d400 0x200>;
 190                 interrupts = <0 59 0x04>;
 191                 nvidia,dma-request-selector = <&apbdma 15>;
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194                 status = "disabled";
 195         };
 196
 197         spi@7000d600 {
 198                 compatible = "nvidia,tegra20-slink";
 199                 reg = <0x7000d600 0x200>;
 200                 interrupts = <0 82 0x04>;
 201                 nvidia,dma-request-selector = <&apbdma 16>;
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 status = "disabled";
 205         };
 206
 207         spi@7000d800 {
 208                 compatible = "nvidia,tegra20-slink";
 209                 reg = <0x7000d480 0x200>;
 210                 interrupts = <0 83 0x04>;
 211                 nvidia,dma-request-selector = <&apbdma 17>;
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 status = "disabled";
 215         };
 216
 217         spi@7000da00 {
 218                 compatible = "nvidia,tegra20-slink";
 219                 reg = <0x7000da00 0x200>;
 220                 interrupts = <0 93 0x04>;
 221                 nvidia,dma-request-selector = <&apbdma 18>;
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 status = "disabled";
 225         };
 226
 227         pmc {
 228                 compatible = "nvidia,tegra20-pmc";
 229                 reg = <0x7000e400 0x400>;
 230         };
 231
 232         memory-controller@7000f000 {
 233                 compatible = "nvidia,tegra20-mc";
 234                 reg = <0x7000f000 0x024
 235                        0x7000f03c 0x3c4>;
 236                 interrupts = <0 77 0x04>;
 237         };
 238
 239         gart {
 240                 compatible = "nvidia,tegra20-gart";
 241                 reg = <0x7000f024 0x00000018    /* controller registers */
 242                        0x58000000 0x02000000>;  /* GART aperture */
 243         };
 244
 245         memory-controller@7000f400 {
 246                 compatible = "nvidia,tegra20-emc";
 247                 reg = <0x7000f400 0x200>;
 248                 #address-cells = <1>;
 249                 #size-cells = <0>;
 250         };
 251
 252         usb@c5000000 {
 253                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 254                 reg = <0xc5000000 0x4000>;
 255                 interrupts = <0 20 0x04>;
 256                 phy_type = "utmi";
 257                 nvidia,has-legacy-mode;
 258                 status = "disabled";
 259         };
 260
 261         usb@c5004000 {
 262                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 263                 reg = <0xc5004000 0x4000>;
 264                 interrupts = <0 21 0x04>;
 265                 phy_type = "ulpi";
 266                 status = "disabled";
 267         };
 268
 269         usb@c5008000 {
 270                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 271                 reg = <0xc5008000 0x4000>;
 272                 interrupts = <0 97 0x04>;
 273                 phy_type = "utmi";
 274                 status = "disabled";
 275         };
 276
 277         sdhci@c8000000 {
 278                 compatible = "nvidia,tegra20-sdhci";
 279                 reg = <0xc8000000 0x200>;
 280                 interrupts = <0 14 0x04>;
 281                 status = "disabled";
 282         };
 283
 284         sdhci@c8000200 {
 285                 compatible = "nvidia,tegra20-sdhci";
 286                 reg = <0xc8000200 0x200>;
 287                 interrupts = <0 15 0x04>;
 288                 status = "disabled";
 289         };
 290
 291         sdhci@c8000400 {
 292                 compatible = "nvidia,tegra20-sdhci";
 293                 reg = <0xc8000400 0x200>;
 294                 interrupts = <0 19 0x04>;
 295                 status = "disabled";
 296         };
 297
 298         sdhci@c8000600 {
 299                 compatible = "nvidia,tegra20-sdhci";
 300                 reg = <0xc8000600 0x200>;
 301                 interrupts = <0 31 0x04>;
 302                 status = "disabled";
 303         };
 304
 305         pmu {
 306                 compatible = "arm,cortex-a9-pmu";
 307                 interrupts = <0 56 0x04
 308                               0 57 0x04>;
 309         };
 310 };