arch/arm/mach-exynos/clock-exynos5.c

   1 /*
   2  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Clock support for EXYNOS5 SoCs
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos5_clock_save[] = {
  33         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
  34         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
  35         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
  36         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
  37         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
  38         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
  39         SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
  40         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
  41         SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
  42         SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
  43         SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
  44         SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
  45         SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
  46         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
  47         SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
  48         SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
  49         SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
  50         SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
  51         SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
  52         SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
  53         SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
  54         SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
  60         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
  61         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
  62         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
  63         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
  64         SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
  65         SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
  66         SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
  67         SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
  68         SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
  69         SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
  70         SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
  71         SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
  72         SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
  73         SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
  74         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
  75         SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
  76         SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
  77         SAVE_ITEM(EXYNOS5_EPLL_CON0),
  78         SAVE_ITEM(EXYNOS5_EPLL_CON1),
  79         SAVE_ITEM(EXYNOS5_EPLL_CON2),
  80         SAVE_ITEM(EXYNOS5_VPLL_CON0),
  81         SAVE_ITEM(EXYNOS5_VPLL_CON1),
  82         SAVE_ITEM(EXYNOS5_VPLL_CON2),
  83 };
  84 #endif
  85
  86 static struct clk exynos5_clk_sclk_dptxphy = {
  87         .name           = "sclk_dptx",
  88 };
  89
  90 static struct clk exynos5_clk_sclk_hdmi24m = {
  91         .name           = "sclk_hdmi24m",
  92         .rate           = 24000000,
  93 };
  94
  95 static struct clk exynos5_clk_sclk_hdmi27m = {
  96         .name           = "sclk_hdmi27m",
  97         .rate           = 27000000,
  98 };
  99
 100 static struct clk exynos5_clk_sclk_hdmiphy = {
 101         .name           = "sclk_hdmiphy",
 102 };
 103
 104 static struct clk exynos5_clk_sclk_usbphy = {
 105         .name           = "sclk_usbphy",
 106         .rate           = 48000000,
 107 };
 108
 109 static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 110 {
 111         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
 112 }
 113
 114 static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
 115 {
 116         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
 117 }
 118
 119 static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 120 {
 121         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
 122 }
 123
 124 static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
 125 {
 126         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
 127 }
 128
 129 static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
 130 {
 131         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 132 }
 133
 134 static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
 135 {
 136         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
 137 }
 138
 139 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 140 {
 141         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
 142 }
 143
 144 static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
 145 {
 146         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
 147 }
 148
 149 static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
 150 {
 151         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
 152 }
 153
 154 static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 155 {
 156         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
 157 }
 158
 159 static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
 160 {
 161         return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
 162 }
 163
 164 static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
 165 {
 166         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 167 }
 168
 169 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 170 {
 171         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
 172 }
 173
 174 static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
 175 {
 176         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
 177 }
 178
 179 static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
 180 {
 181         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
 182 }
 183
 184 static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
 185 {
 186         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
 187 }
 188
 189 static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
 190 {
 191         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
 192 }
 193
 194 static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
 195 {
 196         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 197 }
 198
 199 /* Core list of CMU_CPU side */
 200
 201 static struct clksrc_clk exynos5_clk_mout_apll = {
 202         .clk    = {
 203                 .name           = "mout_apll",
 204         },
 205         .sources = &clk_src_apll,
 206         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
 207 };
 208
 209 static struct clksrc_clk exynos5_clk_sclk_apll = {
 210         .clk    = {
 211                 .name           = "sclk_apll",
 212                 .parent         = &exynos5_clk_mout_apll.clk,
 213         },
 214         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 215 };
 216
 217 static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
 218         .clk    = {
 219                 .name           = "mout_bpll_fout",
 220         },
 221         .sources = &clk_src_bpll_fout,
 222         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
 223 };
 224
 225 static struct clk *exynos5_clk_src_bpll_list[] = {
 226         [0] = &clk_fin_bpll,
 227         [1] = &exynos5_clk_mout_bpll_fout.clk,
 228 };
 229
 230 static struct clksrc_sources exynos5_clk_src_bpll = {
 231         .sources        = exynos5_clk_src_bpll_list,
 232         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_list),
 233 };
 234
 235 static struct clksrc_clk exynos5_clk_mout_bpll = {
 236         .clk    = {
 237                 .name           = "mout_bpll",
 238         },
 239         .sources = &exynos5_clk_src_bpll,
 240         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
 241 };
 242
 243 static struct clk *exynos5_clk_src_bpll_user_list[] = {
 244         [0] = &clk_fin_mpll,
 245         [1] = &exynos5_clk_mout_bpll.clk,
 246 };
 247
 248 static struct clksrc_sources exynos5_clk_src_bpll_user = {
 249         .sources        = exynos5_clk_src_bpll_user_list,
 250         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
 251 };
 252
 253 static struct clksrc_clk exynos5_clk_mout_bpll_user = {
 254         .clk    = {
 255                 .name           = "mout_bpll_user",
 256         },
 257         .sources = &exynos5_clk_src_bpll_user,
 258         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
 259 };
 260
 261 static struct clksrc_clk exynos5_clk_mout_cpll = {
 262         .clk    = {
 263                 .name           = "mout_cpll",
 264         },
 265         .sources = &clk_src_cpll,
 266         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos5_clk_mout_epll = {
 270         .clk    = {
 271                 .name           = "mout_epll",
 272         },
 273         .sources = &clk_src_epll,
 274         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 275 };
 276
 277 static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
 278         .clk    = {
 279                 .name           = "mout_mpll_fout",
 280         },
 281         .sources = &clk_src_mpll_fout,
 282         .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
 283 };
 284
 285 static struct clk *exynos5_clk_src_mpll_list[] = {
 286         [0] = &clk_fin_mpll,
 287         [1] = &exynos5_clk_mout_mpll_fout.clk,
 288 };
 289
 290 static struct clksrc_sources exynos5_clk_src_mpll = {
 291         .sources        = exynos5_clk_src_mpll_list,
 292         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_list),
 293 };
 294
 295 struct clksrc_clk exynos5_clk_mout_mpll = {
 296         .clk = {
 297                 .name           = "mout_mpll",
 298         },
 299         .sources = &exynos5_clk_src_mpll,
 300         .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 301 };
 302
 303 static struct clk *exynos_clkset_vpllsrc_list[] = {
 304         [0] = &clk_fin_vpll,
 305         [1] = &exynos5_clk_sclk_hdmi27m,
 306 };
 307
 308 static struct clksrc_sources exynos5_clkset_vpllsrc = {
 309         .sources        = exynos_clkset_vpllsrc_list,
 310         .nr_sources     = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
 311 };
 312
 313 static struct clksrc_clk exynos5_clk_vpllsrc = {
 314         .clk    = {
 315                 .name           = "vpll_src",
 316                 .enable         = exynos5_clksrc_mask_top_ctrl,
 317                 .ctrlbit        = (1 << 0),
 318         },
 319         .sources = &exynos5_clkset_vpllsrc,
 320         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
 321 };
 322
 323 static struct clk *exynos5_clkset_sclk_vpll_list[] = {
 324         [0] = &exynos5_clk_vpllsrc.clk,
 325         [1] = &clk_fout_vpll,
 326 };
 327
 328 static struct clksrc_sources exynos5_clkset_sclk_vpll = {
 329         .sources        = exynos5_clkset_sclk_vpll_list,
 330         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
 331 };
 332
 333 static struct clksrc_clk exynos5_clk_sclk_vpll = {
 334         .clk    = {
 335                 .name           = "sclk_vpll",
 336         },
 337         .sources = &exynos5_clkset_sclk_vpll,
 338         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
 339 };
 340
 341 static struct clksrc_clk exynos5_clk_sclk_pixel = {
 342         .clk    = {
 343                 .name           = "sclk_pixel",
 344                 .parent         = &exynos5_clk_sclk_vpll.clk,
 345         },
 346         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
 347 };
 348
 349 static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
 350         [0] = &exynos5_clk_sclk_pixel.clk,
 351         [1] = &exynos5_clk_sclk_hdmiphy,
 352 };
 353
 354 static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
 355         .sources        = exynos5_clkset_sclk_hdmi_list,
 356         .nr_sources     = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
 357 };
 358
 359 static struct clksrc_clk exynos5_clk_sclk_hdmi = {
 360         .clk    = {
 361                 .name           = "sclk_hdmi",
 362                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
 363                 .ctrlbit        = (1 << 20),
 364         },
 365         .sources = &exynos5_clkset_sclk_hdmi,
 366         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
 367 };
 368
 369 static struct clksrc_clk *exynos5_sclk_tv[] = {
 370         &exynos5_clk_sclk_pixel,
 371         &exynos5_clk_sclk_hdmi,
 372 };
 373
 374 static struct clk *exynos5_clk_src_mpll_user_list[] = {
 375         [0] = &clk_fin_mpll,
 376         [1] = &exynos5_clk_mout_mpll.clk,
 377 };
 378
 379 static struct clksrc_sources exynos5_clk_src_mpll_user = {
 380         .sources        = exynos5_clk_src_mpll_user_list,
 381         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
 382 };
 383
 384 static struct clksrc_clk exynos5_clk_mout_mpll_user = {
 385         .clk    = {
 386                 .name           = "mout_mpll_user",
 387         },
 388         .sources = &exynos5_clk_src_mpll_user,
 389         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
 390 };
 391
 392 static struct clk *exynos5_clkset_mout_cpu_list[] = {
 393         [0] = &exynos5_clk_mout_apll.clk,
 394         [1] = &exynos5_clk_mout_mpll.clk,
 395 };
 396
 397 static struct clksrc_sources exynos5_clkset_mout_cpu = {
 398         .sources        = exynos5_clkset_mout_cpu_list,
 399         .nr_sources     = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
 400 };
 401
 402 static struct clksrc_clk exynos5_clk_mout_cpu = {
 403         .clk    = {
 404                 .name           = "mout_cpu",
 405         },
 406         .sources = &exynos5_clkset_mout_cpu,
 407         .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
 408 };
 409
 410 static struct clksrc_clk exynos5_clk_dout_armclk = {
 411         .clk    = {
 412                 .name           = "dout_armclk",
 413                 .parent         = &exynos5_clk_mout_cpu.clk,
 414         },
 415         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
 416 };
 417
 418 static struct clksrc_clk exynos5_clk_dout_arm2clk = {
 419         .clk    = {
 420                 .name           = "dout_arm2clk",
 421                 .parent         = &exynos5_clk_dout_armclk.clk,
 422         },
 423         .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
 424 };
 425
 426 static struct clk exynos5_clk_armclk = {
 427         .name           = "armclk",
 428         .parent         = &exynos5_clk_dout_arm2clk.clk,
 429 };
 430
 431 /* Core list of CMU_CDREX side */
 432
 433 static struct clk *exynos5_clkset_cdrex_list[] = {
 434         [0] = &exynos5_clk_mout_mpll.clk,
 435         [1] = &exynos5_clk_mout_bpll.clk,
 436 };
 437
 438 static struct clksrc_sources exynos5_clkset_cdrex = {
 439         .sources        = exynos5_clkset_cdrex_list,
 440         .nr_sources     = ARRAY_SIZE(exynos5_clkset_cdrex_list),
 441 };
 442
 443 static struct clksrc_clk exynos5_clk_cdrex = {
 444         .clk    = {
 445                 .name           = "clk_cdrex",
 446         },
 447         .sources = &exynos5_clkset_cdrex,
 448         .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
 449         .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
 450 };
 451
 452 static struct clksrc_clk exynos5_clk_aclk_acp = {
 453         .clk    = {
 454                 .name           = "aclk_acp",
 455                 .parent         = &exynos5_clk_mout_mpll.clk,
 456         },
 457         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
 458 };
 459
 460 static struct clksrc_clk exynos5_clk_pclk_acp = {
 461         .clk    = {
 462                 .name           = "pclk_acp",
 463                 .parent         = &exynos5_clk_aclk_acp.clk,
 464         },
 465         .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
 466 };
 467
 468 /* Core list of CMU_TOP side */
 469
 470 struct clk *exynos5_clkset_aclk_top_list[] = {
 471         [0] = &exynos5_clk_mout_mpll_user.clk,
 472         [1] = &exynos5_clk_mout_bpll_user.clk,
 473 };
 474
 475 struct clksrc_sources exynos5_clkset_aclk = {
 476         .sources        = exynos5_clkset_aclk_top_list,
 477         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
 478 };
 479
 480 static struct clksrc_clk exynos5_clk_aclk_400 = {
 481         .clk    = {
 482                 .name           = "aclk_400",
 483         },
 484         .sources = &exynos5_clkset_aclk,
 485         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
 486         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
 487 };
 488
 489 struct clk *exynos5_clkset_aclk_333_166_list[] = {
 490         [0] = &exynos5_clk_mout_cpll.clk,
 491         [1] = &exynos5_clk_mout_mpll_user.clk,
 492 };
 493
 494 struct clksrc_sources exynos5_clkset_aclk_333_166 = {
 495         .sources        = exynos5_clkset_aclk_333_166_list,
 496         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
 497 };
 498
 499 static struct clksrc_clk exynos5_clk_aclk_333 = {
 500         .clk    = {
 501                 .name           = "aclk_333",
 502         },
 503         .sources = &exynos5_clkset_aclk_333_166,
 504         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
 505         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
 506 };
 507
 508 static struct clksrc_clk exynos5_clk_aclk_166 = {
 509         .clk    = {
 510                 .name           = "aclk_166",
 511         },
 512         .sources = &exynos5_clkset_aclk_333_166,
 513         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
 514         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
 515 };
 516
 517 static struct clksrc_clk exynos5_clk_aclk_266 = {
 518         .clk    = {
 519                 .name           = "aclk_266",
 520                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 521         },
 522         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
 523 };
 524
 525 static struct clksrc_clk exynos5_clk_aclk_200 = {
 526         .clk    = {
 527                 .name           = "aclk_200",
 528         },
 529         .sources = &exynos5_clkset_aclk,
 530         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
 531         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
 532 };
 533
 534 static struct clksrc_clk exynos5_clk_aclk_66_pre = {
 535         .clk    = {
 536                 .name           = "aclk_66_pre",
 537                 .parent         = &exynos5_clk_mout_mpll_user.clk,
 538         },
 539         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
 540 };
 541
 542 static struct clksrc_clk exynos5_clk_aclk_66 = {
 543         .clk    = {
 544                 .name           = "aclk_66",
 545                 .parent         = &exynos5_clk_aclk_66_pre.clk,
 546         },
 547         .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 548 };
 549
 550 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
 551         .clk    = {
 552                 .name           = "mout_aclk_300_gscl_mid",
 553         },
 554         .sources = &exynos5_clkset_aclk,
 555         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
 556 };
 557
 558 static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
 559         [0] = &exynos5_clk_sclk_vpll.clk,
 560         [1] = &exynos5_clk_mout_cpll.clk,
 561 };
 562
 563 static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
 564         .sources        = exynos5_clkset_aclk_300_mid1_list,
 565         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
 566 };
 567
 568 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
 569         .clk    = {
 570                 .name           = "mout_aclk_300_gscl_mid1",
 571         },
 572         .sources = &exynos5_clkset_aclk_300_gscl_mid1,
 573         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
 574 };
 575
 576 static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
 577         [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
 578         [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
 579 };
 580
 581 static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
 582         .sources        = exynos5_clkset_aclk_300_gscl_list,
 583         .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
 584 };
 585
 586 static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
 587         .clk    = {
 588                 .name           = "mout_aclk_300_gscl",
 589         },
 590         .sources = &exynos5_clkset_aclk_300_gscl,
 591         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
 592 };
 593
 594 static struct clk *exynos5_clk_src_gscl_300_list[] = {
 595         [0] = &clk_ext_xtal_mux,
 596         [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
 597 };
 598
 599 static struct clksrc_sources exynos5_clk_src_gscl_300 = {
 600         .sources        = exynos5_clk_src_gscl_300_list,
 601         .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
 602 };
 603
 604 static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
 605         .clk    = {
 606                 .name           = "aclk_300_gscl",
 607         },
 608         .sources = &exynos5_clk_src_gscl_300,
 609         .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
 610 };
 611
 612 static struct clk exynos5_init_clocks_off[] = {
 613         {
 614                 .name           = "timers",
 615                 .parent         = &exynos5_clk_aclk_66.clk,
 616                 .enable         = exynos5_clk_ip_peric_ctrl,
 617                 .ctrlbit        = (1 << 24),
 618         }, {
 619                 .name           = "tmu_apbif",
 620                 .parent         = &exynos5_clk_aclk_66.clk,
 621                 .enable         = exynos5_clk_ip_peris_ctrl,
 622                 .ctrlbit        = (1 << 21),
 623         }, {
 624                 .name           = "rtc",
 625                 .parent         = &exynos5_clk_aclk_66.clk,
 626                 .enable         = exynos5_clk_ip_peris_ctrl,
 627                 .ctrlbit        = (1 << 20),
 628         }, {
 629                 .name           = "watchdog",
 630                 .parent         = &exynos5_clk_aclk_66.clk,
 631                 .enable         = exynos5_clk_ip_peris_ctrl,
 632                 .ctrlbit        = (1 << 19),
 633         }, {
 634                 .name           = "biu",        /* bus interface unit clock */
 635                 .devname        = "dw_mmc.0",
 636                 .parent         = &exynos5_clk_aclk_200.clk,
 637                 .enable         = exynos5_clk_ip_fsys_ctrl,
 638                 .ctrlbit        = (1 << 12),
 639         }, {
 640                 .name           = "biu",
 641                 .devname        = "dw_mmc.1",
 642                 .parent         = &exynos5_clk_aclk_200.clk,
 643                 .enable         = exynos5_clk_ip_fsys_ctrl,
 644                 .ctrlbit        = (1 << 13),
 645         }, {
 646                 .name           = "biu",
 647                 .devname        = "dw_mmc.2",
 648                 .parent         = &exynos5_clk_aclk_200.clk,
 649                 .enable         = exynos5_clk_ip_fsys_ctrl,
 650                 .ctrlbit        = (1 << 14),
 651         }, {
 652                 .name           = "biu",
 653                 .devname        = "dw_mmc.3",
 654                 .parent         = &exynos5_clk_aclk_200.clk,
 655                 .enable         = exynos5_clk_ip_fsys_ctrl,
 656                 .ctrlbit        = (1 << 15),
 657         }, {
 658                 .name           = "sata",
 659                 .devname        = "ahci",
 660                 .enable         = exynos5_clk_ip_fsys_ctrl,
 661                 .ctrlbit        = (1 << 6),
 662         }, {
 663                 .name           = "sata_phy",
 664                 .enable         = exynos5_clk_ip_fsys_ctrl,
 665                 .ctrlbit        = (1 << 24),
 666         }, {
 667                 .name           = "sata_phy_i2c",
 668                 .enable         = exynos5_clk_ip_fsys_ctrl,
 669                 .ctrlbit        = (1 << 25),
 670         }, {
 671                 .name           = "mfc",
 672                 .devname        = "s5p-mfc-v6",
 673                 .enable         = exynos5_clk_ip_mfc_ctrl,
 674                 .ctrlbit        = (1 << 0),
 675         }, {
 676                 .name           = "hdmi",
 677                 .devname        = "exynos4-hdmi",
 678                 .enable         = exynos5_clk_ip_disp1_ctrl,
 679                 .ctrlbit        = (1 << 6),
 680         }, {
 681                 .name           = "mixer",
 682                 .devname        = "s5p-mixer",
 683                 .enable         = exynos5_clk_ip_disp1_ctrl,
 684                 .ctrlbit        = (1 << 5),
 685         }, {
 686                 .name           = "jpeg",
 687                 .enable         = exynos5_clk_ip_gen_ctrl,
 688                 .ctrlbit        = (1 << 2),
 689         }, {
 690                 .name           = "dsim0",
 691                 .enable         = exynos5_clk_ip_disp1_ctrl,
 692                 .ctrlbit        = (1 << 3),
 693         }, {
 694                 .name           = "iis",
 695                 .devname        = "samsung-i2s.1",
 696                 .enable         = exynos5_clk_ip_peric_ctrl,
 697                 .ctrlbit        = (1 << 20),
 698         }, {
 699                 .name           = "iis",
 700                 .devname        = "samsung-i2s.2",
 701                 .enable         = exynos5_clk_ip_peric_ctrl,
 702                 .ctrlbit        = (1 << 21),
 703         }, {
 704                 .name           = "pcm",
 705                 .devname        = "samsung-pcm.1",
 706                 .enable         = exynos5_clk_ip_peric_ctrl,
 707                 .ctrlbit        = (1 << 22),
 708         }, {
 709                 .name           = "pcm",
 710                 .devname        = "samsung-pcm.2",
 711                 .enable         = exynos5_clk_ip_peric_ctrl,
 712                 .ctrlbit        = (1 << 23),
 713         }, {
 714                 .name           = "spdif",
 715                 .devname        = "samsung-spdif",
 716                 .enable         = exynos5_clk_ip_peric_ctrl,
 717                 .ctrlbit        = (1 << 26),
 718         }, {
 719                 .name           = "ac97",
 720                 .devname        = "samsung-ac97",
 721                 .enable         = exynos5_clk_ip_peric_ctrl,
 722                 .ctrlbit        = (1 << 27),
 723         }, {
 724                 .name           = "usbhost",
 725                 .enable         = exynos5_clk_ip_fsys_ctrl ,
 726                 .ctrlbit        = (1 << 18),
 727         }, {
 728                 .name           = "usbotg",
 729                 .enable         = exynos5_clk_ip_fsys_ctrl,
 730                 .ctrlbit        = (1 << 7),
 731         }, {
 732                 .name           = "nfcon",
 733                 .enable         = exynos5_clk_ip_fsys_ctrl,
 734                 .ctrlbit        = (1 << 22),
 735         }, {
 736                 .name           = "iop",
 737                 .enable         = exynos5_clk_ip_fsys_ctrl,
 738                 .ctrlbit        = ((1 << 30) | (1 << 26) | (1 << 23)),
 739         }, {
 740                 .name           = "core_iop",
 741                 .enable         = exynos5_clk_ip_core_ctrl,
 742                 .ctrlbit        = ((1 << 21) | (1 << 3)),
 743         }, {
 744                 .name           = "mcu_iop",
 745                 .enable         = exynos5_clk_ip_fsys_ctrl,
 746                 .ctrlbit        = (1 << 0),
 747         }, {
 748                 .name           = "i2c",
 749                 .devname        = "s3c2440-i2c.0",
 750                 .parent         = &exynos5_clk_aclk_66.clk,
 751                 .enable         = exynos5_clk_ip_peric_ctrl,
 752                 .ctrlbit        = (1 << 6),
 753         }, {
 754                 .name           = "i2c",
 755                 .devname        = "s3c2440-i2c.1",
 756                 .parent         = &exynos5_clk_aclk_66.clk,
 757                 .enable         = exynos5_clk_ip_peric_ctrl,
 758                 .ctrlbit        = (1 << 7),
 759         }, {
 760                 .name           = "i2c",
 761                 .devname        = "s3c2440-i2c.2",
 762                 .parent         = &exynos5_clk_aclk_66.clk,
 763                 .enable         = exynos5_clk_ip_peric_ctrl,
 764                 .ctrlbit        = (1 << 8),
 765         }, {
 766                 .name           = "i2c",
 767                 .devname        = "s3c2440-i2c.3",
 768                 .parent         = &exynos5_clk_aclk_66.clk,
 769                 .enable         = exynos5_clk_ip_peric_ctrl,
 770                 .ctrlbit        = (1 << 9),
 771         }, {
 772                 .name           = "i2c",
 773                 .devname        = "s3c2440-i2c.4",
 774                 .parent         = &exynos5_clk_aclk_66.clk,
 775                 .enable         = exynos5_clk_ip_peric_ctrl,
 776                 .ctrlbit        = (1 << 10),
 777         }, {
 778                 .name           = "i2c",
 779                 .devname        = "s3c2440-i2c.5",
 780                 .parent         = &exynos5_clk_aclk_66.clk,
 781                 .enable         = exynos5_clk_ip_peric_ctrl,
 782                 .ctrlbit        = (1 << 11),
 783         }, {
 784                 .name           = "i2c",
 785                 .devname        = "s3c2440-i2c.6",
 786                 .parent         = &exynos5_clk_aclk_66.clk,
 787                 .enable         = exynos5_clk_ip_peric_ctrl,
 788                 .ctrlbit        = (1 << 12),
 789         }, {
 790                 .name           = "i2c",
 791                 .devname        = "s3c2440-i2c.7",
 792                 .parent         = &exynos5_clk_aclk_66.clk,
 793                 .enable         = exynos5_clk_ip_peric_ctrl,
 794                 .ctrlbit        = (1 << 13),
 795         }, {
 796                 .name           = "i2c",
 797                 .devname        = "s3c2440-hdmiphy-i2c",
 798                 .parent         = &exynos5_clk_aclk_66.clk,
 799                 .enable         = exynos5_clk_ip_peric_ctrl,
 800                 .ctrlbit        = (1 << 14),
 801         }, {
 802                 .name           = "spi",
 803                 .devname        = "exynos4210-spi.0",
 804                 .parent         = &exynos5_clk_aclk_66.clk,
 805                 .enable         = exynos5_clk_ip_peric_ctrl,
 806                 .ctrlbit        = (1 << 16),
 807         }, {
 808                 .name           = "spi",
 809                 .devname        = "exynos4210-spi.1",
 810                 .parent         = &exynos5_clk_aclk_66.clk,
 811                 .enable         = exynos5_clk_ip_peric_ctrl,
 812                 .ctrlbit        = (1 << 17),
 813         }, {
 814                 .name           = "spi",
 815                 .devname        = "exynos4210-spi.2",
 816                 .parent         = &exynos5_clk_aclk_66.clk,
 817                 .enable         = exynos5_clk_ip_peric_ctrl,
 818                 .ctrlbit        = (1 << 18),
 819         }, {
 820                 .name           = "gscl",
 821                 .devname        = "exynos-gsc.0",
 822                 .enable         = exynos5_clk_ip_gscl_ctrl,
 823                 .ctrlbit        = (1 << 0),
 824         }, {
 825                 .name           = "gscl",
 826                 .devname        = "exynos-gsc.1",
 827                 .enable         = exynos5_clk_ip_gscl_ctrl,
 828                 .ctrlbit        = (1 << 1),
 829         }, {
 830                 .name           = "gscl",
 831                 .devname        = "exynos-gsc.2",
 832                 .enable         = exynos5_clk_ip_gscl_ctrl,
 833                 .ctrlbit        = (1 << 2),
 834         }, {
 835                 .name           = "gscl",
 836                 .devname        = "exynos-gsc.3",
 837                 .enable         = exynos5_clk_ip_gscl_ctrl,
 838                 .ctrlbit        = (1 << 3),
 839         }, {
 840                 .name           = SYSMMU_CLOCK_NAME,
 841                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 842                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 843                 .ctrlbit        = (1 << 1),
 844         }, {
 845                 .name           = SYSMMU_CLOCK_NAME,
 846                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 847                 .enable         = &exynos5_clk_ip_mfc_ctrl,
 848                 .ctrlbit        = (1 << 2),
 849         }, {
 850                 .name           = SYSMMU_CLOCK_NAME,
 851                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 852                 .enable         = &exynos5_clk_ip_disp1_ctrl,
 853                 .ctrlbit        = (1 << 9)
 854         }, {
 855                 .name           = SYSMMU_CLOCK_NAME,
 856                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 857                 .enable         = &exynos5_clk_ip_gen_ctrl,
 858                 .ctrlbit        = (1 << 7),
 859         }, {
 860                 .name           = SYSMMU_CLOCK_NAME,
 861                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 862                 .enable         = &exynos5_clk_ip_gen_ctrl,
 863                 .ctrlbit        = (1 << 6)
 864         }, {
 865                 .name           = SYSMMU_CLOCK_NAME,
 866                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
 867                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 868                 .ctrlbit        = (1 << 7),
 869         }, {
 870                 .name           = SYSMMU_CLOCK_NAME,
 871                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
 872                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 873                 .ctrlbit        = (1 << 8),
 874         }, {
 875                 .name           = SYSMMU_CLOCK_NAME,
 876                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
 877                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 878                 .ctrlbit        = (1 << 9),
 879         }, {
 880                 .name           = SYSMMU_CLOCK_NAME,
 881                 .devname        = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
 882                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 883                 .ctrlbit        = (1 << 10),
 884         }, {
 885                 .name           = SYSMMU_CLOCK_NAME,
 886                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 887                 .enable         = &exynos5_clk_ip_isp0_ctrl,
 888                 .ctrlbit        = (0x3F << 8),
 889         }, {
 890                 .name           = SYSMMU_CLOCK_NAME2,
 891                 .devname        = SYSMMU_CLOCK_DEVNAME(isp, 9),
 892                 .enable         = &exynos5_clk_ip_isp1_ctrl,
 893                 .ctrlbit        = (0xF << 4),
 894         }, {
 895                 .name           = SYSMMU_CLOCK_NAME,
 896                 .devname        = SYSMMU_CLOCK_DEVNAME(camif0, 12),
 897                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 898                 .ctrlbit        = (1 << 11),
 899         }, {
 900                 .name           = SYSMMU_CLOCK_NAME,
 901                 .devname        = SYSMMU_CLOCK_DEVNAME(camif1, 13),
 902                 .enable         = &exynos5_clk_ip_gscl_ctrl,
 903                 .ctrlbit        = (1 << 12),
 904         }, {
 905                 .name           = SYSMMU_CLOCK_NAME,
 906                 .devname        = SYSMMU_CLOCK_DEVNAME(2d, 14),
 907                 .enable         = &exynos5_clk_ip_acp_ctrl,
 908                 .ctrlbit        = (1 << 7)
 909         }
 910 };
 911
 912 static struct clk exynos5_init_clocks_on[] = {
 913         {
 914                 .name           = "uart",
 915                 .devname        = "s5pv210-uart.0",
 916                 .enable         = exynos5_clk_ip_peric_ctrl,
 917                 .ctrlbit        = (1 << 0),
 918         }, {
 919                 .name           = "uart",
 920                 .devname        = "s5pv210-uart.1",
 921                 .enable         = exynos5_clk_ip_peric_ctrl,
 922                 .ctrlbit        = (1 << 1),
 923         }, {
 924                 .name           = "uart",
 925                 .devname        = "s5pv210-uart.2",
 926                 .enable         = exynos5_clk_ip_peric_ctrl,
 927                 .ctrlbit        = (1 << 2),
 928         }, {
 929                 .name           = "uart",
 930                 .devname        = "s5pv210-uart.3",
 931                 .enable         = exynos5_clk_ip_peric_ctrl,
 932                 .ctrlbit        = (1 << 3),
 933         }, {
 934                 .name           = "uart",
 935                 .devname        = "s5pv210-uart.4",
 936                 .enable         = exynos5_clk_ip_peric_ctrl,
 937                 .ctrlbit        = (1 << 4),
 938         }, {
 939                 .name           = "uart",
 940                 .devname        = "s5pv210-uart.5",
 941                 .enable         = exynos5_clk_ip_peric_ctrl,
 942                 .ctrlbit        = (1 << 5),
 943         }
 944 };
 945
 946 static struct clk exynos5_clk_pdma0 = {
 947         .name           = "dma",
 948         .devname        = "dma-pl330.0",
 949         .enable         = exynos5_clk_ip_fsys_ctrl,
 950         .ctrlbit        = (1 << 1),
 951 };
 952
 953 static struct clk exynos5_clk_pdma1 = {
 954         .name           = "dma",
 955         .devname        = "dma-pl330.1",
 956         .enable         = exynos5_clk_ip_fsys_ctrl,
 957         .ctrlbit        = (1 << 2),
 958 };
 959
 960 static struct clk exynos5_clk_mdma1 = {
 961         .name           = "dma",
 962         .devname        = "dma-pl330.2",
 963         .enable         = exynos5_clk_ip_gen_ctrl,
 964         .ctrlbit        = (1 << 4),
 965 };
 966
 967 static struct clk exynos5_clk_fimd1 = {
 968         .name           = "fimd",
 969         .devname        = "exynos5-fb.1",
 970         .enable         = exynos5_clk_ip_disp1_ctrl,
 971         .ctrlbit        = (1 << 0),
 972 };
 973
 974 struct clk *exynos5_clkset_group_list[] = {
 975         [0] = &clk_ext_xtal_mux,
 976         [1] = NULL,
 977         [2] = &exynos5_clk_sclk_hdmi24m,
 978         [3] = &exynos5_clk_sclk_dptxphy,
 979         [4] = &exynos5_clk_sclk_usbphy,
 980         [5] = &exynos5_clk_sclk_hdmiphy,
 981         [6] = &exynos5_clk_mout_mpll_user.clk,
 982         [7] = &exynos5_clk_mout_epll.clk,
 983         [8] = &exynos5_clk_sclk_vpll.clk,
 984         [9] = &exynos5_clk_mout_cpll.clk,
 985 };
 986
 987 struct clksrc_sources exynos5_clkset_group = {
 988         .sources        = exynos5_clkset_group_list,
 989         .nr_sources     = ARRAY_SIZE(exynos5_clkset_group_list),
 990 };
 991
 992 /* Possible clock sources for aclk_266_gscl_sub Mux */
 993 static struct clk *clk_src_gscl_266_list[] = {
 994         [0] = &clk_ext_xtal_mux,
 995         [1] = &exynos5_clk_aclk_266.clk,
 996 };
 997
 998 static struct clksrc_sources clk_src_gscl_266 = {
 999         .sources        = clk_src_gscl_266_list,
1000         .nr_sources     = ARRAY_SIZE(clk_src_gscl_266_list),
1001 };
1002
1003 static struct clksrc_clk exynos5_clk_dout_mmc0 = {
1004         .clk            = {
1005                 .name           = "dout_mmc0",
1006         },
1007         .sources = &exynos5_clkset_group,
1008         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
1009         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
1010 };
1011
1012 static struct clksrc_clk exynos5_clk_dout_mmc1 = {
1013         .clk            = {
1014                 .name           = "dout_mmc1",
1015         },
1016         .sources = &exynos5_clkset_group,
1017         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
1018         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1019 };
1020
1021 static struct clksrc_clk exynos5_clk_dout_mmc2 = {
1022         .clk            = {
1023                 .name           = "dout_mmc2",
1024         },
1025         .sources = &exynos5_clkset_group,
1026         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
1027         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1028 };
1029
1030 static struct clksrc_clk exynos5_clk_dout_mmc3 = {
1031         .clk            = {
1032                 .name           = "dout_mmc3",
1033         },
1034         .sources = &exynos5_clkset_group,
1035         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
1036         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1037 };
1038
1039 static struct clksrc_clk exynos5_clk_dout_mmc4 = {
1040         .clk            = {
1041                 .name           = "dout_mmc4",
1042         },
1043         .sources = &exynos5_clkset_group,
1044         .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
1045         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1046 };
1047
1048 static struct clksrc_clk exynos5_clk_sclk_uart0 = {
1049         .clk    = {
1050                 .name           = "uclk1",
1051                 .devname        = "exynos4210-uart.0",
1052                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1053                 .ctrlbit        = (1 << 0),
1054         },
1055         .sources = &exynos5_clkset_group,
1056         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
1057         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
1058 };
1059
1060 static struct clksrc_clk exynos5_clk_sclk_uart1 = {
1061         .clk    = {
1062                 .name           = "uclk1",
1063                 .devname        = "exynos4210-uart.1",
1064                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1065                 .ctrlbit        = (1 << 4),
1066         },
1067         .sources = &exynos5_clkset_group,
1068         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
1069         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
1070 };
1071
1072 static struct clksrc_clk exynos5_clk_sclk_uart2 = {
1073         .clk    = {
1074                 .name           = "uclk1",
1075                 .devname        = "exynos4210-uart.2",
1076                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1077                 .ctrlbit        = (1 << 8),
1078         },
1079         .sources = &exynos5_clkset_group,
1080         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
1081         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
1082 };
1083
1084 static struct clksrc_clk exynos5_clk_sclk_uart3 = {
1085         .clk    = {
1086                 .name           = "uclk1",
1087                 .devname        = "exynos4210-uart.3",
1088                 .enable         = exynos5_clksrc_mask_peric0_ctrl,
1089                 .ctrlbit        = (1 << 12),
1090         },
1091         .sources = &exynos5_clkset_group,
1092         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
1093         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
1094 };
1095
1096 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
1097         .clk    = {
1098                 .name           = "ciu",        /* card interface unit clock */
1099                 .devname        = "dw_mmc.0",
1100                 .parent         = &exynos5_clk_dout_mmc0.clk,
1101                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1102                 .ctrlbit        = (1 << 0),
1103         },
1104         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1105 };
1106
1107 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
1108         .clk    = {
1109                 .name           = "ciu",
1110                 .devname        = "dw_mmc.1",
1111                 .parent         = &exynos5_clk_dout_mmc1.clk,
1112                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1113                 .ctrlbit        = (1 << 4),
1114         },
1115         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1116 };
1117
1118 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
1119         .clk    = {
1120                 .name           = "ciu",
1121                 .devname        = "dw_mmc.2",
1122                 .parent         = &exynos5_clk_dout_mmc2.clk,
1123                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1124                 .ctrlbit        = (1 << 8),
1125         },
1126         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1127 };
1128
1129 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
1130         .clk    = {
1131                 .name           = "ciu",
1132                 .devname        = "dw_mmc.3",
1133                 .parent         = &exynos5_clk_dout_mmc3.clk,
1134                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
1135                 .ctrlbit        = (1 << 12),
1136         },
1137         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1138 };
1139
1140 static struct clksrc_clk exynos5_clk_mdout_spi0 = {
1141         .clk    = {
1142                 .name           = "mdout_spi",
1143                 .devname        = "exynos4210-spi.0",
1144         },
1145         .sources = &exynos5_clkset_group,
1146         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
1147         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
1148 };
1149
1150 static struct clksrc_clk exynos5_clk_mdout_spi1 = {
1151         .clk    = {
1152                 .name           = "mdout_spi",
1153                 .devname        = "exynos4210-spi.1",
1154         },
1155         .sources = &exynos5_clkset_group,
1156         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
1157         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
1158 };
1159
1160 static struct clksrc_clk exynos5_clk_mdout_spi2 = {
1161         .clk    = {
1162                 .name           = "mdout_spi",
1163                 .devname        = "exynos4210-spi.2",
1164         },
1165         .sources = &exynos5_clkset_group,
1166         .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
1167         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
1168 };
1169
1170 static struct clksrc_clk exynos5_clk_sclk_spi0 = {
1171         .clk    = {
1172                 .name           = "sclk_spi",
1173                 .devname        = "exynos4210-spi.0",
1174                 .parent         = &exynos5_clk_mdout_spi0.clk,
1175                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1176                 .ctrlbit        = (1 << 16),
1177         },
1178         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
1179 };
1180
1181 static struct clksrc_clk exynos5_clk_sclk_spi1 = {
1182         .clk    = {
1183                 .name           = "sclk_spi",
1184                 .devname        = "exynos4210-spi.1",
1185                 .parent         = &exynos5_clk_mdout_spi1.clk,
1186                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1187                 .ctrlbit        = (1 << 20),
1188         },
1189         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
1190 };
1191
1192 static struct clksrc_clk exynos5_clk_sclk_spi2 = {
1193         .clk    = {
1194                 .name           = "sclk_spi",
1195                 .devname        = "exynos4210-spi.2",
1196                 .parent         = &exynos5_clk_mdout_spi2.clk,
1197                 .enable         = exynos5_clksrc_mask_peric1_ctrl,
1198                 .ctrlbit        = (1 << 24),
1199         },
1200         .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
1201 };
1202
1203 struct clksrc_clk exynos5_clk_sclk_fimd1 = {
1204         .clk    = {
1205                 .name           = "sclk_fimd",
1206                 .devname        = "exynos5-fb.1",
1207                 .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
1208                 .ctrlbit        = (1 << 0),
1209         },
1210         .sources = &exynos5_clkset_group,
1211         .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
1212         .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
1213 };
1214
1215 static struct clksrc_clk exynos5_clksrcs[] = {
1216         {
1217                 .clk    = {
1218                         .name           = "aclk_266_gscl",
1219                 },
1220                 .sources = &clk_src_gscl_266,
1221                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
1222         }, {
1223                 .clk    = {
1224                         .name           = "sclk_g3d",
1225                         .devname        = "mali-t604.0",
1226                         .enable         = exynos5_clk_block_ctrl,
1227                         .ctrlbit        = (1 << 1),
1228                 },
1229                 .sources = &exynos5_clkset_aclk,
1230                 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
1231                 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
1232         }, {
1233                 .clk    = {
1234                         .name           = "sclk_gscl_wrap",
1235                         .devname        = "s5p-mipi-csis.0",
1236                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1237                         .ctrlbit        = (1 << 24),
1238                 },
1239                 .sources = &exynos5_clkset_group,
1240                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
1241                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
1242         }, {
1243                 .clk    = {
1244                         .name           = "sclk_gscl_wrap",
1245                         .devname        = "s5p-mipi-csis.1",
1246                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1247                         .ctrlbit        = (1 << 28),
1248                 },
1249                 .sources = &exynos5_clkset_group,
1250                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
1251                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
1252         }, {
1253                 .clk    = {
1254                         .name           = "sclk_cam0",
1255                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1256                         .ctrlbit        = (1 << 16),
1257                 },
1258                 .sources = &exynos5_clkset_group,
1259                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
1260                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
1261         }, {
1262                 .clk    = {
1263                         .name           = "sclk_cam1",
1264                         .enable         = exynos5_clksrc_mask_gscl_ctrl,
1265                         .ctrlbit        = (1 << 20),
1266                 },
1267                 .sources = &exynos5_clkset_group,
1268                 .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
1269                 .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
1270         }, {
1271                 .clk    = {
1272                         .name           = "sclk_jpeg",
1273                         .parent         = &exynos5_clk_mout_cpll.clk,
1274                 },
1275                 .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
1276         },
1277 };
1278
1279 /* Clock initialization code */
1280 static struct clksrc_clk *exynos5_sysclks[] = {
1281         &exynos5_clk_mout_apll,
1282         &exynos5_clk_sclk_apll,
1283         &exynos5_clk_mout_bpll,
1284         &exynos5_clk_mout_bpll_fout,
1285         &exynos5_clk_mout_bpll_user,
1286         &exynos5_clk_mout_cpll,
1287         &exynos5_clk_mout_epll,
1288         &exynos5_clk_mout_mpll,
1289         &exynos5_clk_mout_mpll_fout,
1290         &exynos5_clk_mout_mpll_user,
1291         &exynos5_clk_vpllsrc,
1292         &exynos5_clk_sclk_vpll,
1293         &exynos5_clk_mout_cpu,
1294         &exynos5_clk_dout_armclk,
1295         &exynos5_clk_dout_arm2clk,
1296         &exynos5_clk_cdrex,
1297         &exynos5_clk_aclk_400,
1298         &exynos5_clk_aclk_333,
1299         &exynos5_clk_aclk_266,
1300         &exynos5_clk_aclk_200,
1301         &exynos5_clk_aclk_166,
1302         &exynos5_clk_aclk_300_gscl,
1303         &exynos5_clk_mout_aclk_300_gscl,
1304         &exynos5_clk_mout_aclk_300_gscl_mid,
1305         &exynos5_clk_mout_aclk_300_gscl_mid1,
1306         &exynos5_clk_aclk_66_pre,
1307         &exynos5_clk_aclk_66,
1308         &exynos5_clk_dout_mmc0,
1309         &exynos5_clk_dout_mmc1,
1310         &exynos5_clk_dout_mmc2,
1311         &exynos5_clk_dout_mmc3,
1312         &exynos5_clk_dout_mmc4,
1313         &exynos5_clk_aclk_acp,
1314         &exynos5_clk_pclk_acp,
1315         &exynos5_clk_sclk_spi0,
1316         &exynos5_clk_sclk_spi1,
1317         &exynos5_clk_sclk_spi2,
1318         &exynos5_clk_mdout_spi0,
1319         &exynos5_clk_mdout_spi1,
1320         &exynos5_clk_mdout_spi2,
1321         &exynos5_clk_sclk_fimd1,
1322 };
1323
1324 static struct clk *exynos5_clk_cdev[] = {
1325         &exynos5_clk_pdma0,
1326         &exynos5_clk_pdma1,
1327         &exynos5_clk_mdma1,
1328         &exynos5_clk_fimd1,
1329 };
1330
1331 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
1332         &exynos5_clk_sclk_uart0,
1333         &exynos5_clk_sclk_uart1,
1334         &exynos5_clk_sclk_uart2,
1335         &exynos5_clk_sclk_uart3,
1336         &exynos5_clk_sclk_mmc0,
1337         &exynos5_clk_sclk_mmc1,
1338         &exynos5_clk_sclk_mmc2,
1339         &exynos5_clk_sclk_mmc3,
1340 };
1341
1342 static struct clk_lookup exynos5_clk_lookup[] = {
1343         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
1344         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
1345         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
1346         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
1347         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
1348         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
1349         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
1350         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
1351         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
1352         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
1353         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
1354         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
1355         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
1356         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
1357         CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
1358 };
1359
1360 static unsigned long exynos5_epll_get_rate(struct clk *clk)
1361 {
1362         return clk->rate;
1363 }
1364
1365 static struct clk *exynos5_clks[] __initdata = {
1366         &exynos5_clk_sclk_hdmi27m,
1367         &exynos5_clk_sclk_hdmiphy,
1368         &clk_fout_bpll,
1369         &clk_fout_bpll_div2,
1370         &clk_fout_cpll,
1371         &clk_fout_mpll_div2,
1372         &exynos5_clk_armclk,
1373 };
1374
1375 static u32 epll_div[][6] = {
1376         { 192000000, 0, 48, 3, 1, 0 },
1377         { 180000000, 0, 45, 3, 1, 0 },
1378         {  73728000, 1, 73, 3, 3, 47710 },
1379         {  67737600, 1, 90, 4, 3, 20762 },
1380         {  49152000, 0, 49, 3, 3, 9961 },
1381         {  45158400, 0, 45, 3, 3, 10381 },
1382         { 180633600, 0, 45, 3, 1, 10381 },
1383 };
1384
1385 static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
1386 {
1387         unsigned int epll_con, epll_con_k;
1388         unsigned int i;
1389         unsigned int tmp;
1390         unsigned int epll_rate;
1391         unsigned int locktime;
1392         unsigned int lockcnt;
1393
1394         /* Return if nothing changed */
1395         if (clk->rate == rate)
1396                 return 0;
1397
1398         if (clk->parent)
1399                 epll_rate = clk_get_rate(clk->parent);
1400         else
1401                 epll_rate = clk_ext_xtal_mux.rate;
1402
1403         if (epll_rate != 24000000) {
1404                 pr_err("Invalid Clock : recommended clock is 24MHz.\n");
1405                 return -EINVAL;
1406         }
1407
1408         epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
1409         epll_con &= ~(0x1 << 27 | \
1410                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |   \
1411                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1412                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1413
1414         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1415                 if (epll_div[i][0] == rate) {
1416                         epll_con_k = epll_div[i][5] << 0;
1417                         epll_con |= epll_div[i][1] << 27;
1418                         epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
1419                         epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
1420                         epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
1421                         break;
1422                 }
1423         }
1424
1425         if (i == ARRAY_SIZE(epll_div)) {
1426                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1427                                 __func__);
1428                 return -EINVAL;
1429         }
1430
1431         epll_rate /= 1000000;
1432
1433         /* 3000 max_cycls : specification data */
1434         locktime = 3000 / epll_rate * epll_div[i][3];
1435         lockcnt = locktime * 10000 / (10000 / epll_rate);
1436
1437         __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
1438
1439         __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
1440         __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
1441
1442         do {
1443                 tmp = __raw_readl(EXYNOS5_EPLL_CON0);
1444         } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
1445
1446         clk->rate = rate;
1447
1448         return 0;
1449 }
1450
1451 static struct clk_ops exynos5_epll_ops = {
1452         .get_rate = exynos5_epll_get_rate,
1453         .set_rate = exynos5_epll_set_rate,
1454 };
1455
1456 static int xtal_rate;
1457
1458 static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
1459 {
1460         return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
1461 }
1462
1463 static struct clk_ops exynos5_fout_apll_ops = {
1464         .get_rate = exynos5_fout_apll_get_rate,
1465 };
1466
1467 #ifdef CONFIG_PM
1468 static int exynos5_clock_suspend(void)
1469 {
1470         s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1471
1472         return 0;
1473 }
1474
1475 static void exynos5_clock_resume(void)
1476 {
1477         s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
1478 }
1479 #else
1480 #define exynos5_clock_suspend NULL
1481 #define exynos5_clock_resume NULL
1482 #endif
1483
1484 struct syscore_ops exynos5_clock_syscore_ops = {
1485         .suspend        = exynos5_clock_suspend,
1486         .resume         = exynos5_clock_resume,
1487 };
1488
1489 void __init_or_cpufreq exynos5_setup_clocks(void)
1490 {
1491         struct clk *xtal_clk;
1492         unsigned long apll;
1493         unsigned long bpll;
1494         unsigned long cpll;
1495         unsigned long mpll;
1496         unsigned long epll;
1497         unsigned long vpll;
1498         unsigned long vpllsrc;
1499         unsigned long xtal;
1500         unsigned long armclk;
1501         unsigned long mout_cdrex;
1502         unsigned long aclk_400;
1503         unsigned long aclk_333;
1504         unsigned long aclk_266;
1505         unsigned long aclk_200;
1506         unsigned long aclk_166;
1507         unsigned long aclk_66;
1508         unsigned int ptr;
1509
1510         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1511
1512         xtal_clk = clk_get(NULL, "xtal");
1513         BUG_ON(IS_ERR(xtal_clk));
1514
1515         xtal = clk_get_rate(xtal_clk);
1516
1517         xtal_rate = xtal;
1518
1519         clk_put(xtal_clk);
1520
1521         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1522
1523         apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
1524         bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
1525         cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
1526         mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
1527         epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
1528                         __raw_readl(EXYNOS5_EPLL_CON1));
1529
1530         vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
1531         vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
1532                         __raw_readl(EXYNOS5_VPLL_CON1));
1533
1534         clk_fout_apll.ops = &exynos5_fout_apll_ops;
1535         clk_fout_bpll.rate = bpll;
1536         clk_fout_bpll_div2.rate = bpll >> 1;
1537         clk_fout_cpll.rate = cpll;
1538         clk_fout_mpll.rate = mpll;
1539         clk_fout_mpll_div2.rate = mpll >> 1;
1540         clk_fout_epll.rate = epll;
1541         clk_fout_vpll.rate = vpll;
1542
1543         printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
1544                         "M=%ld, E=%ld V=%ld",
1545                         apll, bpll, cpll, mpll, epll, vpll);
1546
1547         armclk = clk_get_rate(&exynos5_clk_armclk);
1548         mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
1549
1550         aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
1551         aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
1552         aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
1553         aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
1554         aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
1555         aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
1556
1557         printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
1558                         "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
1559                         "ACLK166=%ld, ACLK66=%ld\n",
1560                         armclk, mout_cdrex, aclk_400,
1561                         aclk_333, aclk_266, aclk_200,
1562                         aclk_166, aclk_66);
1563
1564
1565         clk_fout_epll.ops = &exynos5_epll_ops;
1566
1567         if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
1568                 printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
1569                                 clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
1570
1571         clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
1572         clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
1573
1574         clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
1575         clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
1576
1577         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
1578                 s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
1579 }
1580
1581 void __init exynos5_register_clocks(void)
1582 {
1583         int ptr;
1584
1585         s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
1586
1587         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
1588                 s3c_register_clksrc(exynos5_sysclks[ptr], 1);
1589
1590         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
1591                 s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
1592
1593         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
1594                 s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
1595
1596         s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
1597         s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
1598
1599         s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
1600         for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
1601                 s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
1602
1603         s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1604         s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
1605         clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
1606
1607         register_syscore_ops(&exynos5_clock_syscore_ops);
1608         s3c_pwmclk_init();
1609 }