4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
86 config SYS_SUPPORTS_APM_EMULATION
94 select GENERIC_ALLOCATOR
105 The Extended Industry Standard Architecture (EISA) bus was
106 developed as an open alternative to the IBM MicroChannel bus.
108 The EISA bus provided some of the features of the IBM MicroChannel
109 bus while maintaining backward compatibility with cards made for
110 the older ISA bus. The EISA bus saw limited use between 1988 and
111 1995 when it was made obsolete by the PCI bus.
113 Say Y here if you are building a kernel for an EISA-based machine.
120 config STACKTRACE_SUPPORT
124 config HAVE_LATENCYTOP_SUPPORT
129 config LOCKDEP_SUPPORT
133 config TRACE_IRQFLAGS_SUPPORT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config GENERIC_HWEIGHT
161 config GENERIC_CALIBRATE_DELAY
165 config ARCH_MAY_HAVE_PC_FDC
171 config NEED_DMA_MAP_STATE
174 config ARCH_HAS_DMA_SET_COHERENT_MASK
177 config GENERIC_ISA_DMA
183 config NEED_RET_TO_USER
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_GPIO_H
217 Select this when mach/gpio.h is required to provide special
218 definitions for this platform. The need for mach/gpio.h should
219 be avoided when possible.
221 config NEED_MACH_IO_H
224 Select this when mach/io.h is required to provide special
225 definitions for this platform. The need for mach/io.h should
226 be avoided when possible.
228 config NEED_MACH_MEMORY_H
231 Select this when mach/memory.h is required to provide special
232 definitions for this platform. The need for mach/memory.h should
233 be avoided when possible.
236 hex "Physical address of main memory" if MMU
237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
238 default DRAM_BASE if !MMU
240 Please provide the physical address corresponding to the
241 location of main memory in your system.
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
254 bool "MMU-based Paged Memory Management Support"
257 Select if you want MMU-based virtualised addressing space
258 support by paged memory management. If unsure, say 'Y'.
261 # The "ARM system type" choice list is ordered alphabetically by option
262 # text. Please add new entries in the option alphabetic order.
265 prompt "ARM system type"
266 default ARCH_MULTIPLATFORM
268 config ARCH_MULTIPLATFORM
269 bool "Allow multiple platforms to be selected"
271 select ARM_PATCH_PHYS_VIRT
274 select MULTI_IRQ_HANDLER
278 config ARCH_INTEGRATOR
279 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
283 select COMMON_CLK_VERSATILE
284 select GENERIC_CLOCKEVENTS
287 select MULTI_IRQ_HANDLER
288 select NEED_MACH_MEMORY_H
289 select PLAT_VERSATILE
291 select VERSATILE_FPGA_IRQ
293 Support for ARM's Integrator platform.
296 bool "ARM Ltd. RealView family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select COMMON_CLK_VERSATILE
302 select GENERIC_CLOCKEVENTS
303 select GPIO_PL061 if GPIOLIB
305 select NEED_MACH_MEMORY_H
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for ARM Ltd RealView boards.
311 config ARCH_VERSATILE
312 bool "ARM Ltd. Versatile family"
313 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_TIMER_SP804
318 select GENERIC_CLOCKEVENTS
319 select HAVE_MACH_CLKDEV
321 select PLAT_VERSATILE
322 select PLAT_VERSATILE_CLCD
323 select PLAT_VERSATILE_CLOCK
324 select VERSATILE_FPGA_IRQ
326 This enables support for ARM Ltd Versatile board.
330 select ARCH_REQUIRE_GPIOLIB
334 select NEED_MACH_GPIO_H
335 select NEED_MACH_IO_H if PCCARD
337 select PINCTRL_AT91 if USE_OF
339 This enables support for systems based on Atmel
340 AT91RM9200 and AT91SAM9* processors.
343 bool "Broadcom BCM2835 family"
344 select ARCH_REQUIRE_GPIOLIB
346 select ARM_ERRATA_411920
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
353 select MULTI_IRQ_HANDLER
355 select PINCTRL_BCM2835
359 This enables support for the Broadcom BCM2835 SoC. This SoC is
360 use in the Raspberry Pi, and Roku 2 devices.
363 bool "Cavium Networks CNS3XXX family"
366 select GENERIC_CLOCKEVENTS
367 select MIGHT_HAVE_CACHE_L2X0
368 select MIGHT_HAVE_PCI
369 select PCI_DOMAINS if PCI
371 Support for Cavium Networks CNS3XXX platform.
374 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
375 select ARCH_REQUIRE_GPIOLIB
376 select ARCH_USES_GETTIMEOFFSET
381 select GENERIC_CLOCKEVENTS
382 select MULTI_IRQ_HANDLER
383 select NEED_MACH_MEMORY_H
386 Support for Cirrus Logic 711x/721x/731x based boards.
389 bool "Cortina Systems Gemini"
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_USES_GETTIMEOFFSET
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_REQUIRE_GPIOLIB
400 select GENERIC_CLOCKEVENTS
401 select GENERIC_IRQ_CHIP
402 select MIGHT_HAVE_CACHE_L2X0
408 Support for CSR SiRFprimaII/Marco/Polo platforms
412 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_IO_H
416 select NEED_MACH_MEMORY_H
419 This is an evaluation board for the StrongARM processor available
420 from Digital. It has limited hardware on-board, including an
421 Ethernet interface, two PCMCIA sockets, two serial ports and a
426 select ARCH_HAS_HOLES_MEMORYMODEL
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_USES_GETTIMEOFFSET
433 select NEED_MACH_MEMORY_H
435 This enables support for the Cirrus EP93xx series of CPUs.
437 config ARCH_FOOTBRIDGE
441 select GENERIC_CLOCKEVENTS
443 select NEED_MACH_IO_H if !MMU
444 select NEED_MACH_MEMORY_H
446 Support for systems based on the DC21285 companion chip
447 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
450 bool "Freescale MXS-based"
451 select ARCH_REQUIRE_GPIOLIB
455 select GENERIC_CLOCKEVENTS
456 select HAVE_CLK_PREPARE
457 select MULTI_IRQ_HANDLER
462 Support for Freescale MXS-based family of processors
465 bool "Hilscher NetX based"
469 select GENERIC_CLOCKEVENTS
471 This enables support for systems based on the Hilscher NetX Soc
474 bool "Hynix HMS720x-based"
475 select ARCH_USES_GETTIMEOFFSET
479 This enables support for systems based on the Hynix HMS720x
484 select ARCH_SUPPORTS_MSI
486 select NEED_MACH_MEMORY_H
487 select NEED_RET_TO_USER
492 Support for Intel's IOP13XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
499 select NEED_MACH_GPIO_H
500 select NEED_RET_TO_USER
504 Support for Intel's 80219 and IOP32X (XScale) family of
510 select ARCH_REQUIRE_GPIOLIB
512 select NEED_MACH_GPIO_H
513 select NEED_RET_TO_USER
517 Support for Intel's IOP33X (XScale) family of processors.
522 select ARCH_HAS_DMA_SET_COHERENT_MASK
523 select ARCH_REQUIRE_GPIOLIB
526 select DMABOUNCE if PCI
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
529 select NEED_MACH_IO_H
531 Support for Intel's IXP4XX (XScale) family of processors.
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 select PLAT_ORION_LEGACY
553 Support for the following Marvell Kirkwood series SoCs:
554 88F6180, 88F6192 and 88F6281.
557 bool "Marvell MV78xx0"
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
574 select PLAT_ORION_LEGACY
576 Support for the following Marvell Orion 5x series SoCs:
577 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
578 Orion-2 (5281), Orion-1-90 (6183).
581 bool "Marvell PXA168/910/MMP2"
583 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_ALLOCATOR
586 select GENERIC_CLOCKEVENTS
589 select NEED_MACH_GPIO_H
594 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
597 bool "Micrel/Kendin KS8695"
598 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
602 select NEED_MACH_MEMORY_H
604 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
605 System-on-Chip devices.
608 bool "Nuvoton W90X900 CPU"
609 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_CLOCKEVENTS
615 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
616 At present, the w90x900 has been renamed nuc900, regarding
617 the ARM series product line, you can login the following
618 link address to know more.
620 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
621 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
633 select USB_ARCH_HAS_OHCI
636 Support for the NXP LPC32XX family of processors
640 select ARCH_HAS_CPUFREQ
644 select GENERIC_CLOCKEVENTS
648 select MIGHT_HAVE_CACHE_L2X0
651 This enables support for NVIDIA Tegra based systems (Tegra APX,
652 Tegra 6xx and Tegra 2 series).
655 bool "PXA2xx/PXA3xx-based"
657 select ARCH_HAS_CPUFREQ
659 select ARCH_REQUIRE_GPIOLIB
660 select ARM_CPU_SUSPEND if PM
664 select GENERIC_CLOCKEVENTS
667 select MULTI_IRQ_HANDLER
668 select NEED_MACH_GPIO_H
672 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
676 select ARCH_REQUIRE_GPIOLIB
678 select GENERIC_CLOCKEVENTS
681 Support for Qualcomm MSM/QSD based systems. This runs on the
682 apps processor of the MSM/QSD and depends on a shared memory
683 interface to the modem processor which runs the baseband
684 stack and controls some vital subsystems
685 (clock and power control, etc).
688 bool "Renesas SH-Mobile / R-Mobile"
690 select GENERIC_CLOCKEVENTS
692 select HAVE_MACH_CLKDEV
694 select MIGHT_HAVE_CACHE_L2X0
695 select MULTI_IRQ_HANDLER
696 select NEED_MACH_MEMORY_H
698 select PM_GENERIC_DOMAINS if PM
701 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
706 select ARCH_MAY_HAVE_PC_FDC
707 select ARCH_SPARSEMEM_ENABLE
708 select ARCH_USES_GETTIMEOFFSET
711 select HAVE_PATA_PLATFORM
713 select NEED_MACH_IO_H
714 select NEED_MACH_MEMORY_H
717 On the Acorn Risc-PC, Linux can support the internal IDE disk and
718 CD-ROM interface, serial and parallel port, and the floppy drive.
722 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
725 select ARCH_SPARSEMEM_ENABLE
730 select GENERIC_CLOCKEVENTS
733 select NEED_MACH_GPIO_H
734 select NEED_MACH_MEMORY_H
737 Support for StrongARM 11x0 based boards.
740 bool "Samsung S3C24XX SoCs"
741 select ARCH_HAS_CPUFREQ
742 select ARCH_USES_GETTIMEOFFSET
746 select HAVE_S3C2410_I2C if I2C
747 select HAVE_S3C2410_WATCHDOG if WATCHDOG
748 select HAVE_S3C_RTC if RTC_CLASS
749 select NEED_MACH_GPIO_H
750 select NEED_MACH_IO_H
752 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
753 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
754 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
755 Samsung SMDK2410 development board (and derivatives).
758 bool "Samsung S3C64XX"
759 select ARCH_HAS_CPUFREQ
760 select ARCH_REQUIRE_GPIOLIB
761 select ARCH_USES_GETTIMEOFFSET
766 select HAVE_S3C2410_I2C if I2C
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
769 select NEED_MACH_GPIO_H
773 select S3C_GPIO_TRACK
774 select SAMSUNG_CLKSRC
775 select SAMSUNG_GPIOLIB_4BIT
776 select SAMSUNG_IRQ_VIC_TIMER
777 select USB_ARCH_HAS_OHCI
779 Samsung S3C64XX series based systems
782 bool "Samsung S5P6440 S5P6450"
786 select GENERIC_CLOCKEVENTS
789 select HAVE_S3C2410_I2C if I2C
790 select HAVE_S3C2410_WATCHDOG if WATCHDOG
791 select HAVE_S3C_RTC if RTC_CLASS
792 select NEED_MACH_GPIO_H
794 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
798 bool "Samsung S5PC100"
799 select ARCH_USES_GETTIMEOFFSET
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
809 Samsung S5PC100 series based systems
812 bool "Samsung S5PV210/S5PC110"
813 select ARCH_HAS_CPUFREQ
814 select ARCH_HAS_HOLES_MEMORYMODEL
815 select ARCH_SPARSEMEM_ENABLE
819 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C2410_I2C if I2C
823 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 select HAVE_S3C_RTC if RTC_CLASS
825 select NEED_MACH_GPIO_H
826 select NEED_MACH_MEMORY_H
828 Samsung S5PV210/S5PC110 series based systems
831 bool "Samsung EXYNOS"
832 select ARCH_HAS_CPUFREQ
833 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARCH_SPARSEMEM_ENABLE
837 select GENERIC_CLOCKEVENTS
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
842 select HAVE_S3C_RTC if RTC_CLASS
843 select NEED_MACH_GPIO_H
844 select NEED_MACH_MEMORY_H
846 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
850 select ARCH_USES_GETTIMEOFFSET
854 select NEED_MACH_MEMORY_H
858 Support for the StrongARM based Digital DNARD machine, also known
859 as "Shark" (<http://www.shark-linux.de/shark.html>).
862 bool "ST-Ericsson U300 Series"
864 select ARCH_REQUIRE_GPIOLIB
866 select ARM_PATCH_PHYS_VIRT
872 select GENERIC_CLOCKEVENTS
877 Support for ST-Ericsson U300 series mobile platforms.
880 bool "ST-Ericsson U8500 Series"
882 select ARCH_HAS_CPUFREQ
883 select ARCH_REQUIRE_GPIOLIB
887 select GENERIC_CLOCKEVENTS
889 select MIGHT_HAVE_CACHE_L2X0
891 Support for ST-Ericsson's Ux500 architecture
894 bool "STMicroelectronics Nomadik"
895 select ARCH_REQUIRE_GPIOLIB
900 select GENERIC_CLOCKEVENTS
901 select MIGHT_HAVE_CACHE_L2X0
903 select PINCTRL_STN8815
905 Support for the Nomadik platform by ST-Ericsson
909 select ARCH_HAS_CPUFREQ
910 select ARCH_REQUIRE_GPIOLIB
915 select GENERIC_CLOCKEVENTS
918 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
922 select ARCH_HAS_HOLES_MEMORYMODEL
923 select ARCH_REQUIRE_GPIOLIB
925 select GENERIC_ALLOCATOR
926 select GENERIC_CLOCKEVENTS
927 select GENERIC_IRQ_CHIP
929 select NEED_MACH_GPIO_H
933 Support for TI's DaVinci platform.
938 select ARCH_HAS_CPUFREQ
939 select ARCH_HAS_HOLES_MEMORYMODEL
940 select ARCH_REQUIRE_GPIOLIB
942 select GENERIC_CLOCKEVENTS
945 Support for TI's OMAP platform (OMAP1/2/3/4).
948 bool "VIA/WonderMedia 85xx"
949 select ARCH_HAS_CPUFREQ
950 select ARCH_REQUIRE_GPIOLIB
954 select GENERIC_CLOCKEVENTS
959 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
962 bool "Xilinx Zynq ARM Cortex A9 Platform"
966 select GENERIC_CLOCKEVENTS
968 select MIGHT_HAVE_CACHE_L2X0
971 Support for Xilinx Zynq ARM Cortex A9 Platform
974 menu "Multiple platform selection"
975 depends on ARCH_MULTIPLATFORM
977 comment "CPU Core family selection"
980 bool "ARMv4 based platforms (FA526, StrongARM)"
981 depends on !ARCH_MULTI_V6_V7
982 select ARCH_MULTI_V4_V5
984 config ARCH_MULTI_V4T
985 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
986 depends on !ARCH_MULTI_V6_V7
987 select ARCH_MULTI_V4_V5
990 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
991 depends on !ARCH_MULTI_V6_V7
992 select ARCH_MULTI_V4_V5
994 config ARCH_MULTI_V4_V5
998 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
999 select ARCH_MULTI_V6_V7
1002 config ARCH_MULTI_V7
1003 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1005 select ARCH_MULTI_V6_V7
1006 select ARCH_VEXPRESS
1009 config ARCH_MULTI_V6_V7
1012 config ARCH_MULTI_CPU_AUTO
1013 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1014 select ARCH_MULTI_V5
1019 # This is sorted alphabetically by mach-* pathname. However, plat-*
1020 # Kconfigs may be included either alphabetically (according to the
1021 # plat- suffix) or along side the corresponding mach-* source.
1023 source "arch/arm/mach-mvebu/Kconfig"
1025 source "arch/arm/mach-at91/Kconfig"
1027 source "arch/arm/mach-bcm/Kconfig"
1029 source "arch/arm/mach-clps711x/Kconfig"
1031 source "arch/arm/mach-cns3xxx/Kconfig"
1033 source "arch/arm/mach-davinci/Kconfig"
1035 source "arch/arm/mach-dove/Kconfig"
1037 source "arch/arm/mach-ep93xx/Kconfig"
1039 source "arch/arm/mach-footbridge/Kconfig"
1041 source "arch/arm/mach-gemini/Kconfig"
1043 source "arch/arm/mach-h720x/Kconfig"
1045 source "arch/arm/mach-highbank/Kconfig"
1047 source "arch/arm/mach-integrator/Kconfig"
1049 source "arch/arm/mach-iop32x/Kconfig"
1051 source "arch/arm/mach-iop33x/Kconfig"
1053 source "arch/arm/mach-iop13xx/Kconfig"
1055 source "arch/arm/mach-ixp4xx/Kconfig"
1057 source "arch/arm/mach-kirkwood/Kconfig"
1059 source "arch/arm/mach-ks8695/Kconfig"
1061 source "arch/arm/mach-msm/Kconfig"
1063 source "arch/arm/mach-mv78xx0/Kconfig"
1065 source "arch/arm/mach-imx/Kconfig"
1067 source "arch/arm/mach-mxs/Kconfig"
1069 source "arch/arm/mach-netx/Kconfig"
1071 source "arch/arm/mach-nomadik/Kconfig"
1072 source "arch/arm/plat-nomadik/Kconfig"
1074 source "arch/arm/plat-omap/Kconfig"
1076 source "arch/arm/mach-omap1/Kconfig"
1078 source "arch/arm/mach-omap2/Kconfig"
1080 source "arch/arm/mach-orion5x/Kconfig"
1082 source "arch/arm/mach-picoxcell/Kconfig"
1084 source "arch/arm/mach-pxa/Kconfig"
1085 source "arch/arm/plat-pxa/Kconfig"
1087 source "arch/arm/mach-mmp/Kconfig"
1089 source "arch/arm/mach-realview/Kconfig"
1091 source "arch/arm/mach-sa1100/Kconfig"
1093 source "arch/arm/plat-samsung/Kconfig"
1094 source "arch/arm/plat-s3c24xx/Kconfig"
1096 source "arch/arm/mach-socfpga/Kconfig"
1098 source "arch/arm/plat-spear/Kconfig"
1100 source "arch/arm/mach-s3c24xx/Kconfig"
1102 source "arch/arm/mach-s3c2412/Kconfig"
1103 source "arch/arm/mach-s3c2440/Kconfig"
1107 source "arch/arm/mach-s3c64xx/Kconfig"
1110 source "arch/arm/mach-s5p64x0/Kconfig"
1112 source "arch/arm/mach-s5pc100/Kconfig"
1114 source "arch/arm/mach-s5pv210/Kconfig"
1116 source "arch/arm/mach-exynos/Kconfig"
1118 source "arch/arm/mach-shmobile/Kconfig"
1120 source "arch/arm/mach-sunxi/Kconfig"
1122 source "arch/arm/mach-prima2/Kconfig"
1124 source "arch/arm/mach-tegra/Kconfig"
1126 source "arch/arm/mach-u300/Kconfig"
1128 source "arch/arm/mach-ux500/Kconfig"
1130 source "arch/arm/mach-versatile/Kconfig"
1132 source "arch/arm/mach-vexpress/Kconfig"
1133 source "arch/arm/plat-versatile/Kconfig"
1135 source "arch/arm/mach-w90x900/Kconfig"
1137 # Definitions to make life easier
1143 select GENERIC_CLOCKEVENTS
1149 select GENERIC_IRQ_CHIP
1152 config PLAT_ORION_LEGACY
1159 config PLAT_VERSATILE
1162 config ARM_TIMER_SP804
1165 select HAVE_SCHED_CLOCK
1167 source arch/arm/mm/Kconfig
1171 default 16 if ARCH_EP93XX
1175 bool "Enable iWMMXt support"
1176 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1177 default y if PXA27x || PXA3xx || ARCH_MMP
1179 Enable support for iWMMXt context switching at run time if
1180 running on a CPU that supports it.
1184 depends on CPU_XSCALE
1187 config MULTI_IRQ_HANDLER
1190 Allow each machine to specify it's own IRQ handler at run time.
1193 source "arch/arm/Kconfig-nommu"
1196 config ARM_ERRATA_326103
1197 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1200 Executing a SWP instruction to read-only memory does not set bit 11
1201 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1202 treat the access as a read, preventing a COW from occurring and
1203 causing the faulting task to livelock.
1205 config ARM_ERRATA_411920
1206 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1207 depends on CPU_V6 || CPU_V6K
1209 Invalidation of the Instruction Cache operation can
1210 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1211 It does not affect the MPCore. This option enables the ARM Ltd.
1212 recommended workaround.
1214 config ARM_ERRATA_430973
1215 bool "ARM errata: Stale prediction on replaced interworking branch"
1218 This option enables the workaround for the 430973 Cortex-A8
1219 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1220 interworking branch is replaced with another code sequence at the
1221 same virtual address, whether due to self-modifying code or virtual
1222 to physical address re-mapping, Cortex-A8 does not recover from the
1223 stale interworking branch prediction. This results in Cortex-A8
1224 executing the new code sequence in the incorrect ARM or Thumb state.
1225 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1226 and also flushes the branch target cache at every context switch.
1227 Note that setting specific bits in the ACTLR register may not be
1228 available in non-secure mode.
1230 config ARM_ERRATA_458693
1231 bool "ARM errata: Processor deadlock when a false hazard is created"
1234 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1235 erratum. For very specific sequences of memory operations, it is
1236 possible for a hazard condition intended for a cache line to instead
1237 be incorrectly associated with a different cache line. This false
1238 hazard might then cause a processor deadlock. The workaround enables
1239 the L1 caching of the NEON accesses and disables the PLD instruction
1240 in the ACTLR register. Note that setting specific bits in the ACTLR
1241 register may not be available in non-secure mode.
1243 config ARM_ERRATA_460075
1244 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1247 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1248 erratum. Any asynchronous access to the L2 cache may encounter a
1249 situation in which recent store transactions to the L2 cache are lost
1250 and overwritten with stale memory contents from external memory. The
1251 workaround disables the write-allocate mode for the L2 cache via the
1252 ACTLR register. Note that setting specific bits in the ACTLR register
1253 may not be available in non-secure mode.
1255 config ARM_ERRATA_742230
1256 bool "ARM errata: DMB operation may be faulty"
1257 depends on CPU_V7 && SMP
1259 This option enables the workaround for the 742230 Cortex-A9
1260 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1261 between two write operations may not ensure the correct visibility
1262 ordering of the two writes. This workaround sets a specific bit in
1263 the diagnostic register of the Cortex-A9 which causes the DMB
1264 instruction to behave as a DSB, ensuring the correct behaviour of
1267 config ARM_ERRATA_742231
1268 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1269 depends on CPU_V7 && SMP
1271 This option enables the workaround for the 742231 Cortex-A9
1272 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1273 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1274 accessing some data located in the same cache line, may get corrupted
1275 data due to bad handling of the address hazard when the line gets
1276 replaced from one of the CPUs at the same time as another CPU is
1277 accessing it. This workaround sets specific bits in the diagnostic
1278 register of the Cortex-A9 which reduces the linefill issuing
1279 capabilities of the processor.
1281 config PL310_ERRATA_588369
1282 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1283 depends on CACHE_L2X0
1285 The PL310 L2 cache controller implements three types of Clean &
1286 Invalidate maintenance operations: by Physical Address
1287 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1288 They are architecturally defined to behave as the execution of a
1289 clean operation followed immediately by an invalidate operation,
1290 both performing to the same memory location. This functionality
1291 is not correctly implemented in PL310 as clean lines are not
1292 invalidated as a result of these operations.
1294 config ARM_ERRATA_720789
1295 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1298 This option enables the workaround for the 720789 Cortex-A9 (prior to
1299 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1300 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1301 As a consequence of this erratum, some TLB entries which should be
1302 invalidated are not, resulting in an incoherency in the system page
1303 tables. The workaround changes the TLB flushing routines to invalidate
1304 entries regardless of the ASID.
1306 config PL310_ERRATA_727915
1307 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1308 depends on CACHE_L2X0
1310 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1311 operation (offset 0x7FC). This operation runs in background so that
1312 PL310 can handle normal accesses while it is in progress. Under very
1313 rare circumstances, due to this erratum, write data can be lost when
1314 PL310 treats a cacheable write transaction during a Clean &
1315 Invalidate by Way operation.
1317 config ARM_ERRATA_743622
1318 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1321 This option enables the workaround for the 743622 Cortex-A9
1322 (r2p*) erratum. Under very rare conditions, a faulty
1323 optimisation in the Cortex-A9 Store Buffer may lead to data
1324 corruption. This workaround sets a specific bit in the diagnostic
1325 register of the Cortex-A9 which disables the Store Buffer
1326 optimisation, preventing the defect from occurring. This has no
1327 visible impact on the overall performance or power consumption of the
1330 config ARM_ERRATA_751472
1331 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1334 This option enables the workaround for the 751472 Cortex-A9 (prior
1335 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1336 completion of a following broadcasted operation if the second
1337 operation is received by a CPU before the ICIALLUIS has completed,
1338 potentially leading to corrupted entries in the cache or TLB.
1340 config PL310_ERRATA_753970
1341 bool "PL310 errata: cache sync operation may be faulty"
1342 depends on CACHE_PL310
1344 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1346 Under some condition the effect of cache sync operation on
1347 the store buffer still remains when the operation completes.
1348 This means that the store buffer is always asked to drain and
1349 this prevents it from merging any further writes. The workaround
1350 is to replace the normal offset of cache sync operation (0x730)
1351 by another offset targeting an unmapped PL310 register 0x740.
1352 This has the same effect as the cache sync operation: store buffer
1353 drain and waiting for all buffers empty.
1355 config ARM_ERRATA_754322
1356 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1359 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1360 r3p*) erratum. A speculative memory access may cause a page table walk
1361 which starts prior to an ASID switch but completes afterwards. This
1362 can populate the micro-TLB with a stale entry which may be hit with
1363 the new ASID. This workaround places two dsb instructions in the mm
1364 switching code so that no page table walks can cross the ASID switch.
1366 config ARM_ERRATA_754327
1367 bool "ARM errata: no automatic Store Buffer drain"
1368 depends on CPU_V7 && SMP
1370 This option enables the workaround for the 754327 Cortex-A9 (prior to
1371 r2p0) erratum. The Store Buffer does not have any automatic draining
1372 mechanism and therefore a livelock may occur if an external agent
1373 continuously polls a memory location waiting to observe an update.
1374 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1375 written polling loops from denying visibility of updates to memory.
1377 config ARM_ERRATA_364296
1378 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1379 depends on CPU_V6 && !SMP
1381 This options enables the workaround for the 364296 ARM1136
1382 r0p2 erratum (possible cache data corruption with
1383 hit-under-miss enabled). It sets the undocumented bit 31 in
1384 the auxiliary control register and the FI bit in the control
1385 register, thus disabling hit-under-miss without putting the
1386 processor into full low interrupt latency mode. ARM11MPCore
1389 config ARM_ERRATA_764369
1390 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1391 depends on CPU_V7 && SMP
1393 This option enables the workaround for erratum 764369
1394 affecting Cortex-A9 MPCore with two or more processors (all
1395 current revisions). Under certain timing circumstances, a data
1396 cache line maintenance operation by MVA targeting an Inner
1397 Shareable memory region may fail to proceed up to either the
1398 Point of Coherency or to the Point of Unification of the
1399 system. This workaround adds a DSB instruction before the
1400 relevant cache maintenance functions and sets a specific bit
1401 in the diagnostic control register of the SCU.
1403 config PL310_ERRATA_769419
1404 bool "PL310 errata: no automatic Store Buffer drain"
1405 depends on CACHE_L2X0
1407 On revisions of the PL310 prior to r3p2, the Store Buffer does
1408 not automatically drain. This can cause normal, non-cacheable
1409 writes to be retained when the memory system is idle, leading
1410 to suboptimal I/O performance for drivers using coherent DMA.
1411 This option adds a write barrier to the cpu_idle loop so that,
1412 on systems with an outer cache, the store buffer is drained
1415 config ARM_ERRATA_775420
1416 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1419 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1420 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1421 operation aborts with MMU exception, it might cause the processor
1422 to deadlock. This workaround puts DSB before executing ISB if
1423 an abort may occur on cache maintenance.
1427 source "arch/arm/common/Kconfig"
1437 Find out whether you have ISA slots on your motherboard. ISA is the
1438 name of a bus system, i.e. the way the CPU talks to the other stuff
1439 inside your box. Other bus systems are PCI, EISA, MicroChannel
1440 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1441 newer boards don't support it. If you have ISA, say Y, otherwise N.
1443 # Select ISA DMA controller support
1448 # Select ISA DMA interface
1453 bool "PCI support" if MIGHT_HAVE_PCI
1455 Find out whether you have a PCI motherboard. PCI is the name of a
1456 bus system, i.e. the way the CPU talks to the other stuff inside
1457 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1458 VESA. If you have PCI, say Y, otherwise N.
1464 config PCI_NANOENGINE
1465 bool "BSE nanoEngine PCI support"
1466 depends on SA1100_NANOENGINE
1468 Enable PCI on the BSE nanoEngine board.
1473 # Select the host bridge type
1474 config PCI_HOST_VIA82C505
1476 depends on PCI && ARCH_SHARK
1479 config PCI_HOST_ITE8152
1481 depends on PCI && MACH_ARMCORE
1485 source "drivers/pci/Kconfig"
1487 source "drivers/pcmcia/Kconfig"
1491 menu "Kernel Features"
1496 This option should be selected by machines which have an SMP-
1499 The only effect of this option is to make the SMP-related
1500 options available to the user for configuration.
1503 bool "Symmetric Multi-Processing"
1504 depends on CPU_V6K || CPU_V7
1505 depends on GENERIC_CLOCKEVENTS
1508 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1509 select USE_GENERIC_SMP_HELPERS
1511 This enables support for systems with more than one CPU. If you have
1512 a system with only one CPU, like most personal computers, say N. If
1513 you have a system with more than one CPU, say Y.
1515 If you say N here, the kernel will run on single and multiprocessor
1516 machines, but will use only one CPU of a multiprocessor machine. If
1517 you say Y here, the kernel will run on many, but not all, single
1518 processor machines. On a single processor machine, the kernel will
1519 run faster if you say N here.
1521 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1522 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1523 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1525 If you don't know what to do here, say N.
1528 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1529 depends on EXPERIMENTAL
1530 depends on SMP && !XIP_KERNEL
1533 SMP kernels contain instructions which fail on non-SMP processors.
1534 Enabling this option allows the kernel to modify itself to make
1535 these instructions safe. Disabling it allows about 1K of space
1538 If you don't know what to do here, say Y.
1540 config ARM_CPU_TOPOLOGY
1541 bool "Support cpu topology definition"
1542 depends on SMP && CPU_V7
1545 Support ARM cpu topology definition. The MPIDR register defines
1546 affinity between processors which is then used to describe the cpu
1547 topology of an ARM System.
1550 bool "Multi-core scheduler support"
1551 depends on ARM_CPU_TOPOLOGY
1553 Multi-core scheduler support improves the CPU scheduler's decision
1554 making when dealing with multi-core CPU chips at a cost of slightly
1555 increased overhead in some places. If unsure say N here.
1558 bool "SMT scheduler support"
1559 depends on ARM_CPU_TOPOLOGY
1561 Improves the CPU scheduler's decision making when dealing with
1562 MultiThreading at a cost of slightly increased overhead in some
1563 places. If unsure say N here.
1568 This option enables support for the ARM system coherency unit
1570 config ARM_ARCH_TIMER
1571 bool "Architected timer support"
1574 This option enables support for the ARM architected timer
1580 This options enables support for the ARM timer and watchdog unit
1583 prompt "Memory split"
1586 Select the desired split between kernel and user memory.
1588 If you are not absolutely sure what you are doing, leave this
1592 bool "3G/1G user/kernel split"
1594 bool "2G/2G user/kernel split"
1596 bool "1G/3G user/kernel split"
1601 default 0x40000000 if VMSPLIT_1G
1602 default 0x80000000 if VMSPLIT_2G
1606 int "Maximum number of CPUs (2-32)"
1612 bool "Support for hot-pluggable CPUs"
1613 depends on SMP && HOTPLUG
1615 Say Y here to experiment with turning CPUs off and on. CPUs
1616 can be controlled through /sys/devices/system/cpu.
1619 bool "Use local timer interrupts"
1622 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1624 Enable support for local timers on SMP platforms, rather then the
1625 legacy IPI broadcast method. Local timers allows the system
1626 accounting to be spread across the timer interval, preventing a
1627 "thundering herd" at every timer tick.
1631 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1632 default 355 if ARCH_U8500
1633 default 264 if MACH_H4700
1634 default 512 if SOC_OMAP5
1635 default 288 if ARCH_VT8500
1638 Maximum number of GPIOs in the system.
1640 If unsure, leave the default value.
1642 source kernel/Kconfig.preempt
1646 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1647 ARCH_S5PV210 || ARCH_EXYNOS4
1648 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1649 default AT91_TIMER_HZ if ARCH_AT91
1650 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1653 config THUMB2_KERNEL
1654 bool "Compile the kernel in Thumb-2 mode"
1655 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1657 select ARM_ASM_UNIFIED
1660 By enabling this option, the kernel will be compiled in
1661 Thumb-2 mode. A compiler/assembler that understand the unified
1662 ARM-Thumb syntax is needed.
1666 config THUMB2_AVOID_R_ARM_THM_JUMP11
1667 bool "Work around buggy Thumb-2 short branch relocations in gas"
1668 depends on THUMB2_KERNEL && MODULES
1671 Various binutils versions can resolve Thumb-2 branches to
1672 locally-defined, preemptible global symbols as short-range "b.n"
1673 branch instructions.
1675 This is a problem, because there's no guarantee the final
1676 destination of the symbol, or any candidate locations for a
1677 trampoline, are within range of the branch. For this reason, the
1678 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1679 relocation in modules at all, and it makes little sense to add
1682 The symptom is that the kernel fails with an "unsupported
1683 relocation" error when loading some modules.
1685 Until fixed tools are available, passing
1686 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1687 code which hits this problem, at the cost of a bit of extra runtime
1688 stack usage in some cases.
1690 The problem is described in more detail at:
1691 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1693 Only Thumb-2 kernels are affected.
1695 Unless you are sure your tools don't have this problem, say Y.
1697 config ARM_ASM_UNIFIED
1701 bool "Use the ARM EABI to compile the kernel"
1703 This option allows for the kernel to be compiled using the latest
1704 ARM ABI (aka EABI). This is only useful if you are using a user
1705 space environment that is also compiled with EABI.
1707 Since there are major incompatibilities between the legacy ABI and
1708 EABI, especially with regard to structure member alignment, this
1709 option also changes the kernel syscall calling convention to
1710 disambiguate both ABIs and allow for backward compatibility support
1711 (selected with CONFIG_OABI_COMPAT).
1713 To use this you need GCC version 4.0.0 or later.
1716 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1717 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1720 This option preserves the old syscall interface along with the
1721 new (ARM EABI) one. It also provides a compatibility layer to
1722 intercept syscalls that have structure arguments which layout
1723 in memory differs between the legacy ABI and the new ARM EABI
1724 (only for non "thumb" binaries). This option adds a tiny
1725 overhead to all syscalls and produces a slightly larger kernel.
1726 If you know you'll be using only pure EABI user space then you
1727 can say N here. If this option is not selected and you attempt
1728 to execute a legacy ABI binary then the result will be
1729 UNPREDICTABLE (in fact it can be predicted that it won't work
1730 at all). If in doubt say Y.
1732 config ARCH_HAS_HOLES_MEMORYMODEL
1735 config ARCH_SPARSEMEM_ENABLE
1738 config ARCH_SPARSEMEM_DEFAULT
1739 def_bool ARCH_SPARSEMEM_ENABLE
1741 config ARCH_SELECT_MEMORY_MODEL
1742 def_bool ARCH_SPARSEMEM_ENABLE
1744 config HAVE_ARCH_PFN_VALID
1745 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1748 bool "High Memory Support"
1751 The address space of ARM processors is only 4 Gigabytes large
1752 and it has to accommodate user address space, kernel address
1753 space as well as some memory mapped IO. That means that, if you
1754 have a large amount of physical memory and/or IO, not all of the
1755 memory can be "permanently mapped" by the kernel. The physical
1756 memory that is not permanently mapped is called "high memory".
1758 Depending on the selected kernel/user memory split, minimum
1759 vmalloc space and actual amount of RAM, you may not need this
1760 option which should result in a slightly faster kernel.
1765 bool "Allocate 2nd-level pagetables from highmem"
1768 config HW_PERF_EVENTS
1769 bool "Enable hardware performance counter support for perf events"
1770 depends on PERF_EVENTS
1773 Enable hardware performance counter support for perf events. If
1774 disabled, perf events will use software events only.
1778 config FORCE_MAX_ZONEORDER
1779 int "Maximum zone order" if ARCH_SHMOBILE
1780 range 11 64 if ARCH_SHMOBILE
1781 default "12" if SOC_AM33XX
1782 default "9" if SA1111
1785 The kernel memory allocator divides physically contiguous memory
1786 blocks into "zones", where each zone is a power of two number of
1787 pages. This option selects the largest power of two that the kernel
1788 keeps in the memory allocator. If you need to allocate very large
1789 blocks of physically contiguous memory, then you may need to
1790 increase this value.
1792 This config option is actually maximum order plus one. For example,
1793 a value of 11 means that the largest free memory block is 2^10 pages.
1795 config ALIGNMENT_TRAP
1797 depends on CPU_CP15_MMU
1798 default y if !ARCH_EBSA110
1799 select HAVE_PROC_CPU if PROC_FS
1801 ARM processors cannot fetch/store information which is not
1802 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1803 address divisible by 4. On 32-bit ARM processors, these non-aligned
1804 fetch/store instructions will be emulated in software if you say
1805 here, which has a severe performance impact. This is necessary for
1806 correct operation of some network protocols. With an IP-only
1807 configuration it is safe to say N, otherwise say Y.
1809 config UACCESS_WITH_MEMCPY
1810 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1812 default y if CPU_FEROCEON
1814 Implement faster copy_to_user and clear_user methods for CPU
1815 cores where a 8-word STM instruction give significantly higher
1816 memory write throughput than a sequence of individual 32bit stores.
1818 A possible side effect is a slight increase in scheduling latency
1819 between threads sharing the same address space if they invoke
1820 such copy operations with large buffers.
1822 However, if the CPU data cache is using a write-allocate mode,
1823 this option is unlikely to provide any performance gain.
1827 prompt "Enable seccomp to safely compute untrusted bytecode"
1829 This kernel feature is useful for number crunching applications
1830 that may need to compute untrusted bytecode during their
1831 execution. By using pipes or other transports made available to
1832 the process as file descriptors supporting the read/write
1833 syscalls, it's possible to isolate those applications in
1834 their own address space using seccomp. Once seccomp is
1835 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1836 and the task is only allowed to execute a few safe syscalls
1837 defined by each seccomp mode.
1839 config CC_STACKPROTECTOR
1840 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1841 depends on EXPERIMENTAL
1843 This option turns on the -fstack-protector GCC feature. This
1844 feature puts, at the beginning of functions, a canary value on
1845 the stack just before the return address, and validates
1846 the value just before actually returning. Stack based buffer
1847 overflows (that need to overwrite this return address) now also
1848 overwrite the canary, which gets detected and the attack is then
1849 neutralized via a kernel panic.
1850 This feature requires gcc version 4.2 or above.
1857 bool "Xen guest support on ARM (EXPERIMENTAL)"
1858 depends on EXPERIMENTAL && ARM && OF
1859 depends on CPU_V7 && !CPU_V6
1861 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1868 bool "Flattened Device Tree support"
1871 select OF_EARLY_FLATTREE
1873 Include support for flattened device tree machine descriptions.
1876 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1879 This is the traditional way of passing data to the kernel at boot
1880 time. If you are solely relying on the flattened device tree (or
1881 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1882 to remove ATAGS support from your kernel binary. If unsure,
1885 config DEPRECATED_PARAM_STRUCT
1886 bool "Provide old way to pass kernel parameters"
1889 This was deprecated in 2001 and announced to live on for 5 years.
1890 Some old boot loaders still use this way.
1892 # Compressed boot loader in ROM. Yes, we really want to ask about
1893 # TEXT and BSS so we preserve their values in the config files.
1894 config ZBOOT_ROM_TEXT
1895 hex "Compressed ROM boot loader base address"
1898 The physical address at which the ROM-able zImage is to be
1899 placed in the target. Platforms which normally make use of
1900 ROM-able zImage formats normally set this to a suitable
1901 value in their defconfig file.
1903 If ZBOOT_ROM is not enabled, this has no effect.
1905 config ZBOOT_ROM_BSS
1906 hex "Compressed ROM boot loader BSS address"
1909 The base address of an area of read/write memory in the target
1910 for the ROM-able zImage which must be available while the
1911 decompressor is running. It must be large enough to hold the
1912 entire decompressed kernel plus an additional 128 KiB.
1913 Platforms which normally make use of ROM-able zImage formats
1914 normally set this to a suitable value in their defconfig file.
1916 If ZBOOT_ROM is not enabled, this has no effect.
1919 bool "Compressed boot loader in ROM/flash"
1920 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1922 Say Y here if you intend to execute your compressed kernel image
1923 (zImage) directly from ROM or flash. If unsure, say N.
1926 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1927 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1928 default ZBOOT_ROM_NONE
1930 Include experimental SD/MMC loading code in the ROM-able zImage.
1931 With this enabled it is possible to write the ROM-able zImage
1932 kernel image to an MMC or SD card and boot the kernel straight
1933 from the reset vector. At reset the processor Mask ROM will load
1934 the first part of the ROM-able zImage which in turn loads the
1935 rest the kernel image to RAM.
1937 config ZBOOT_ROM_NONE
1938 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1940 Do not load image from SD or MMC
1942 config ZBOOT_ROM_MMCIF
1943 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1945 Load image from MMCIF hardware block.
1947 config ZBOOT_ROM_SH_MOBILE_SDHI
1948 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1950 Load image from SDHI hardware block
1954 config ARM_APPENDED_DTB
1955 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1956 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1958 With this option, the boot code will look for a device tree binary
1959 (DTB) appended to zImage
1960 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1962 This is meant as a backward compatibility convenience for those
1963 systems with a bootloader that can't be upgraded to accommodate
1964 the documented boot protocol using a device tree.
1966 Beware that there is very little in terms of protection against
1967 this option being confused by leftover garbage in memory that might
1968 look like a DTB header after a reboot if no actual DTB is appended
1969 to zImage. Do not leave this option active in a production kernel
1970 if you don't intend to always append a DTB. Proper passing of the
1971 location into r2 of a bootloader provided DTB is always preferable
1974 config ARM_ATAG_DTB_COMPAT
1975 bool "Supplement the appended DTB with traditional ATAG information"
1976 depends on ARM_APPENDED_DTB
1978 Some old bootloaders can't be updated to a DTB capable one, yet
1979 they provide ATAGs with memory configuration, the ramdisk address,
1980 the kernel cmdline string, etc. Such information is dynamically
1981 provided by the bootloader and can't always be stored in a static
1982 DTB. To allow a device tree enabled kernel to be used with such
1983 bootloaders, this option allows zImage to extract the information
1984 from the ATAG list and store it at run time into the appended DTB.
1987 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1988 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1990 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1991 bool "Use bootloader kernel arguments if available"
1993 Uses the command-line options passed by the boot loader instead of
1994 the device tree bootargs property. If the boot loader doesn't provide
1995 any, the device tree bootargs property will be used.
1997 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1998 bool "Extend with bootloader kernel arguments"
2000 The command-line arguments provided by the boot loader will be
2001 appended to the the device tree bootargs property.
2006 string "Default kernel command string"
2009 On some architectures (EBSA110 and CATS), there is currently no way
2010 for the boot loader to pass arguments to the kernel. For these
2011 architectures, you should supply some command-line options at build
2012 time by entering them here. As a minimum, you should specify the
2013 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2016 prompt "Kernel command line type" if CMDLINE != ""
2017 default CMDLINE_FROM_BOOTLOADER
2020 config CMDLINE_FROM_BOOTLOADER
2021 bool "Use bootloader kernel arguments if available"
2023 Uses the command-line options passed by the boot loader. If
2024 the boot loader doesn't provide any, the default kernel command
2025 string provided in CMDLINE will be used.
2027 config CMDLINE_EXTEND
2028 bool "Extend bootloader kernel arguments"
2030 The command-line arguments provided by the boot loader will be
2031 appended to the default kernel command string.
2033 config CMDLINE_FORCE
2034 bool "Always use the default kernel command string"
2036 Always use the default kernel command string, even if the boot
2037 loader passes other arguments to the kernel.
2038 This is useful if you cannot or don't want to change the
2039 command-line options your boot loader passes to the kernel.
2043 bool "Kernel Execute-In-Place from ROM"
2044 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2046 Execute-In-Place allows the kernel to run from non-volatile storage
2047 directly addressable by the CPU, such as NOR flash. This saves RAM
2048 space since the text section of the kernel is not loaded from flash
2049 to RAM. Read-write sections, such as the data section and stack,
2050 are still copied to RAM. The XIP kernel is not compressed since
2051 it has to run directly from flash, so it will take more space to
2052 store it. The flash address used to link the kernel object files,
2053 and for storing it, is configuration dependent. Therefore, if you
2054 say Y here, you must know the proper physical address where to
2055 store the kernel image depending on your own flash memory usage.
2057 Also note that the make target becomes "make xipImage" rather than
2058 "make zImage" or "make Image". The final kernel binary to put in
2059 ROM memory will be arch/arm/boot/xipImage.
2063 config XIP_PHYS_ADDR
2064 hex "XIP Kernel Physical Location"
2065 depends on XIP_KERNEL
2066 default "0x00080000"
2068 This is the physical address in your flash memory the kernel will
2069 be linked for and stored to. This address is dependent on your
2073 bool "Kexec system call (EXPERIMENTAL)"
2074 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2076 kexec is a system call that implements the ability to shutdown your
2077 current kernel, and to start another kernel. It is like a reboot
2078 but it is independent of the system firmware. And like a reboot
2079 you can start any kernel with it, not just Linux.
2081 It is an ongoing process to be certain the hardware in a machine
2082 is properly shutdown, so do not be surprised if this code does not
2083 initially work for you. It may help to enable device hotplugging
2087 bool "Export atags in procfs"
2088 depends on ATAGS && KEXEC
2091 Should the atags used to boot the kernel be exported in an "atags"
2092 file in procfs. Useful with kexec.
2095 bool "Build kdump crash kernel (EXPERIMENTAL)"
2096 depends on EXPERIMENTAL
2098 Generate crash dump after being started by kexec. This should
2099 be normally only set in special crash dump kernels which are
2100 loaded in the main kernel with kexec-tools into a specially
2101 reserved region and then later executed after a crash by
2102 kdump/kexec. The crash dump kernel must be compiled to a
2103 memory address not used by the main kernel
2105 For more details see Documentation/kdump/kdump.txt
2107 config AUTO_ZRELADDR
2108 bool "Auto calculation of the decompressed kernel image address"
2109 depends on !ZBOOT_ROM && !ARCH_U300
2111 ZRELADDR is the physical address where the decompressed kernel
2112 image will be placed. If AUTO_ZRELADDR is selected, the address
2113 will be determined at run-time by masking the current IP with
2114 0xf8000000. This assumes the zImage being placed in the first 128MB
2115 from start of memory.
2119 menu "CPU Power Management"
2123 source "drivers/cpufreq/Kconfig"
2126 tristate "CPUfreq driver for i.MX CPUs"
2127 depends on ARCH_MXC && CPU_FREQ
2128 select CPU_FREQ_TABLE
2130 This enables the CPUfreq driver for i.MX CPUs.
2132 config CPU_FREQ_SA1100
2135 config CPU_FREQ_SA1110
2138 config CPU_FREQ_INTEGRATOR
2139 tristate "CPUfreq driver for ARM Integrator CPUs"
2140 depends on ARCH_INTEGRATOR && CPU_FREQ
2143 This enables the CPUfreq driver for ARM Integrator CPUs.
2145 For details, take a look at <file:Documentation/cpu-freq>.
2151 depends on CPU_FREQ && ARCH_PXA && PXA25x
2153 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2154 select CPU_FREQ_TABLE
2159 Internal configuration node for common cpufreq on Samsung SoC
2161 config CPU_FREQ_S3C24XX
2162 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2163 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2166 This enables the CPUfreq driver for the Samsung S3C24XX family
2169 For details, take a look at <file:Documentation/cpu-freq>.
2173 config CPU_FREQ_S3C24XX_PLL
2174 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2175 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2177 Compile in support for changing the PLL frequency from the
2178 S3C24XX series CPUfreq driver. The PLL takes time to settle
2179 after a frequency change, so by default it is not enabled.
2181 This also means that the PLL tables for the selected CPU(s) will
2182 be built which may increase the size of the kernel image.
2184 config CPU_FREQ_S3C24XX_DEBUG
2185 bool "Debug CPUfreq Samsung driver core"
2186 depends on CPU_FREQ_S3C24XX
2188 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2190 config CPU_FREQ_S3C24XX_IODEBUG
2191 bool "Debug CPUfreq Samsung driver IO timing"
2192 depends on CPU_FREQ_S3C24XX
2194 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2196 config CPU_FREQ_S3C24XX_DEBUGFS
2197 bool "Export debugfs for CPUFreq"
2198 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2200 Export status information via debugfs.
2204 source "drivers/cpuidle/Kconfig"
2208 menu "Floating point emulation"
2210 comment "At least one emulation must be selected"
2213 bool "NWFPE math emulation"
2214 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2216 Say Y to include the NWFPE floating point emulator in the kernel.
2217 This is necessary to run most binaries. Linux does not currently
2218 support floating point hardware so you need to say Y here even if
2219 your machine has an FPA or floating point co-processor podule.
2221 You may say N here if you are going to load the Acorn FPEmulator
2222 early in the bootup.
2225 bool "Support extended precision"
2226 depends on FPE_NWFPE
2228 Say Y to include 80-bit support in the kernel floating-point
2229 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2230 Note that gcc does not generate 80-bit operations by default,
2231 so in most cases this option only enlarges the size of the
2232 floating point emulator without any good reason.
2234 You almost surely want to say N here.
2237 bool "FastFPE math emulation (EXPERIMENTAL)"
2238 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2240 Say Y here to include the FAST floating point emulator in the kernel.
2241 This is an experimental much faster emulator which now also has full
2242 precision for the mantissa. It does not support any exceptions.
2243 It is very simple, and approximately 3-6 times faster than NWFPE.
2245 It should be sufficient for most programs. It may be not suitable
2246 for scientific calculations, but you have to check this for yourself.
2247 If you do not feel you need a faster FP emulation you should better
2251 bool "VFP-format floating point maths"
2252 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2254 Say Y to include VFP support code in the kernel. This is needed
2255 if your hardware includes a VFP unit.
2257 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2258 release notes and additional status information.
2260 Say N if your target does not have VFP hardware.
2268 bool "Advanced SIMD (NEON) Extension support"
2269 depends on VFPv3 && CPU_V7
2271 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2276 menu "Userspace binary formats"
2278 source "fs/Kconfig.binfmt"
2281 tristate "RISC OS personality"
2284 Say Y here to include the kernel code necessary if you want to run
2285 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2286 experimental; if this sounds frightening, say N and sleep in peace.
2287 You can also say M here to compile this support as a module (which
2288 will be called arthur).
2292 menu "Power management options"
2294 source "kernel/power/Kconfig"
2296 config ARCH_SUSPEND_POSSIBLE
2297 depends on !ARCH_S5PC100
2298 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2299 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2302 config ARM_CPU_SUSPEND
2307 source "net/Kconfig"
2309 source "drivers/Kconfig"
2313 source "arch/arm/Kconfig.debug"
2315 source "security/Kconfig"
2317 source "crypto/Kconfig"
2319 source "lib/Kconfig"