arch/arm/mach-tegra/tegra30_clocks_data.c

   1 /*
   2  * arch/arm/mach-tegra/tegra30_clocks.c
   3  *
   4  * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  18  *
  19  */
  20
  21 #include <linux/clk-private.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/delay.h>
  27 #include <linux/err.h>
  28 #include <linux/io.h>
  29 #include <linux/clk.h>
  30 #include <linux/cpufreq.h>
  31
  32 #include "clock.h"
  33 #include "fuse.h"
  34 #include "tegra30_clocks.h"
  35 #include "tegra_cpu_car.h"
  36
  37 #define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags,            \
  38                    _parent_names, _parents, _parent)            \
  39         static struct clk tegra_##_name = {                     \
  40                 .hw = &tegra_##_name##_hw.hw,                   \
  41                 .name = #_name,                                 \
  42                 .rate = _rate,                                  \
  43                 .ops = _ops,                                    \
  44                 .flags = _flags,                                \
  45                 .parent_names = _parent_names,                  \
  46                 .parents = _parents,                            \
  47                 .num_parents = ARRAY_SIZE(_parent_names),       \
  48                 .parent = _parent,                              \
  49         };
  50
  51 static struct clk tegra_clk_32k;
  52 static struct clk_tegra tegra_clk_32k_hw = {
  53         .hw = {
  54                 .clk = &tegra_clk_32k,
  55         },
  56         .fixed_rate = 32768,
  57 };
  58 static struct clk tegra_clk_32k = {
  59         .name = "clk_32k",
  60         .hw = &tegra_clk_32k_hw.hw,
  61         .ops = &tegra30_clk_32k_ops,
  62         .flags = CLK_IS_ROOT,
  63 };
  64
  65 static struct clk tegra_clk_m;
  66 static struct clk_tegra tegra_clk_m_hw = {
  67         .hw = {
  68                 .clk = &tegra_clk_m,
  69         },
  70         .flags = ENABLE_ON_INIT,
  71         .reg = 0x1fc,
  72         .reg_shift = 28,
  73         .max_rate = 48000000,
  74 };
  75 static struct clk tegra_clk_m = {
  76         .name = "clk_m",
  77         .hw = &tegra_clk_m_hw.hw,
  78         .ops = &tegra30_clk_m_ops,
  79         .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
  80 };
  81
  82 static const char *clk_m_div_parent_names[] = {
  83         "clk_m",
  84 };
  85
  86 static struct clk *clk_m_div_parents[] = {
  87         &tegra_clk_m,
  88 };
  89
  90 static struct clk tegra_clk_m_div2;
  91 static struct clk_tegra tegra_clk_m_div2_hw = {
  92         .hw = {
  93                 .clk = &tegra_clk_m_div2,
  94         },
  95         .mul = 1,
  96         .div = 2,
  97         .max_rate = 24000000,
  98 };
  99 DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
 100                 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
 101
 102 static struct clk tegra_clk_m_div4;
 103 static struct clk_tegra tegra_clk_m_div4_hw = {
 104         .hw = {
 105                 .clk = &tegra_clk_m_div4,
 106         },
 107         .mul = 1,
 108         .div = 4,
 109         .max_rate = 12000000,
 110 };
 111 DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
 112                 clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
 113
 114 static struct clk tegra_pll_ref;
 115 static struct clk_tegra tegra_pll_ref_hw = {
 116         .hw = {
 117                 .clk = &tegra_pll_ref,
 118         },
 119         .flags = ENABLE_ON_INIT,
 120         .max_rate = 26000000,
 121 };
 122 DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
 123                 clk_m_div_parents, &tegra_clk_m);
 124
 125 #define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min,  \
 126                    _input_max, _cf_min, _cf_max, _vco_min,      \
 127                    _vco_max, _freq_table, _lock_delay, _ops,    \
 128                    _fixed_rate, _clk_cfg_ex, _parent)           \
 129         static struct clk tegra_##_name;                        \
 130         static const char *_name##_parent_names[] = {           \
 131                 #_parent,                                       \
 132         };                                                      \
 133         static struct clk *_name##_parents[] = {                \
 134                 &tegra_##_parent,                               \
 135         };                                                      \
 136         static struct clk_tegra tegra_##_name##_hw = {          \
 137                 .hw = {                                         \
 138                         .clk = &tegra_##_name,                  \
 139                 },                                              \
 140                 .flags = _flags,                                \
 141                 .reg = _reg,                                    \
 142                 .max_rate = _max_rate,                          \
 143                 .u.pll = {                                      \
 144                         .input_min = _input_min,                \
 145                         .input_max = _input_max,                \
 146                         .cf_min = _cf_min,                      \
 147                         .cf_max = _cf_max,                      \
 148                         .vco_min = _vco_min,                    \
 149                         .vco_max = _vco_max,                    \
 150                         .freq_table = _freq_table,              \
 151                         .lock_delay = _lock_delay,              \
 152                         .fixed_rate = _fixed_rate,              \
 153                 },                                              \
 154                 .clk_cfg_ex = _clk_cfg_ex,                      \
 155         };                                                      \
 156         DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED,    \
 157                          _name##_parent_names, _name##_parents, \
 158                         &tegra_##_parent);
 159
 160 #define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift,         \
 161                 _max_rate, _ops, _parent, _clk_flags)           \
 162         static const char *_name##_parent_names[] = {           \
 163                 #_parent,                                       \
 164         };                                                      \
 165         static struct clk *_name##_parents[] = {                \
 166                 &tegra_##_parent,                               \
 167         };                                                      \
 168         static struct clk tegra_##_name;                        \
 169         static struct clk_tegra tegra_##_name##_hw = {          \
 170                 .hw = {                                         \
 171                         .clk = &tegra_##_name,                  \
 172                 },                                              \
 173                 .flags = _flags,                                \
 174                 .reg = _reg,                                    \
 175                 .max_rate = _max_rate,                          \
 176                 .reg_shift = _reg_shift,                        \
 177         };                                                      \
 178         DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops,        \
 179                 _clk_flags,  _name##_parent_names,              \
 180                 _name##_parents, &tegra_##_parent);
 181
 182 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
 183         { 12000000, 1040000000, 520,  6, 1, 8},
 184         { 13000000, 1040000000, 480,  6, 1, 8},
 185         { 16800000, 1040000000, 495,  8, 1, 8}, /* actual: 1039.5 MHz */
 186         { 19200000, 1040000000, 325,  6, 1, 6},
 187         { 26000000, 1040000000, 520, 13, 1, 8},
 188
 189         { 12000000, 832000000, 416,  6, 1, 8},
 190         { 13000000, 832000000, 832, 13, 1, 8},
 191         { 16800000, 832000000, 396,  8, 1, 8},  /* actual: 831.6 MHz */
 192         { 19200000, 832000000, 260,  6, 1, 8},
 193         { 26000000, 832000000, 416, 13, 1, 8},
 194
 195         { 12000000, 624000000, 624, 12, 1, 8},
 196         { 13000000, 624000000, 624, 13, 1, 8},
 197         { 16800000, 600000000, 520, 14, 1, 8},
 198         { 19200000, 624000000, 520, 16, 1, 8},
 199         { 26000000, 624000000, 624, 26, 1, 8},
 200
 201         { 12000000, 600000000, 600, 12, 1, 8},
 202         { 13000000, 600000000, 600, 13, 1, 8},
 203         { 16800000, 600000000, 500, 14, 1, 8},
 204         { 19200000, 600000000, 375, 12, 1, 6},
 205         { 26000000, 600000000, 600, 26, 1, 8},
 206
 207         { 12000000, 520000000, 520, 12, 1, 8},
 208         { 13000000, 520000000, 520, 13, 1, 8},
 209         { 16800000, 520000000, 495, 16, 1, 8},  /* actual: 519.75 MHz */
 210         { 19200000, 520000000, 325, 12, 1, 6},
 211         { 26000000, 520000000, 520, 26, 1, 8},
 212
 213         { 12000000, 416000000, 416, 12, 1, 8},
 214         { 13000000, 416000000, 416, 13, 1, 8},
 215         { 16800000, 416000000, 396, 16, 1, 8},  /* actual: 415.8 MHz */
 216         { 19200000, 416000000, 260, 12, 1, 6},
 217         { 26000000, 416000000, 416, 26, 1, 8},
 218         { 0, 0, 0, 0, 0, 0 },
 219 };
 220
 221 DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
 222                 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
 223                 tegra30_pll_ops, 0, NULL, pll_ref);
 224
 225 DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
 226                 tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
 227
 228 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
 229         { 12000000, 666000000, 666, 12, 1, 8},
 230         { 13000000, 666000000, 666, 13, 1, 8},
 231         { 16800000, 666000000, 555, 14, 1, 8},
 232         { 19200000, 666000000, 555, 16, 1, 8},
 233         { 26000000, 666000000, 666, 26, 1, 8},
 234         { 12000000, 600000000, 600, 12, 1, 8},
 235         { 13000000, 600000000, 600, 13, 1, 8},
 236         { 16800000, 600000000, 500, 14, 1, 8},
 237         { 19200000, 600000000, 375, 12, 1, 6},
 238         { 26000000, 600000000, 600, 26, 1, 8},
 239         { 0, 0, 0, 0, 0, 0 },
 240 };
 241
 242 DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
 243                 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
 244                 300, tegra30_pll_ops, 0, NULL, pll_ref);
 245
 246 DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
 247                 tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
 248
 249 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
 250         { 12000000, 216000000, 432, 12, 2, 8},
 251         { 13000000, 216000000, 432, 13, 2, 8},
 252         { 16800000, 216000000, 360, 14, 2, 8},
 253         { 19200000, 216000000, 360, 16, 2, 8},
 254         { 26000000, 216000000, 432, 26, 2, 8},
 255         { 0, 0, 0, 0, 0, 0 },
 256 };
 257
 258 DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
 259                 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
 260                 tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
 261                 pll_ref);
 262
 263 DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
 264                 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
 265 DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
 266                 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
 267 DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
 268                 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
 269 DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
 270                 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
 271
 272 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
 273         { 9600000, 564480000, 294, 5, 1, 4},
 274         { 9600000, 552960000, 288, 5, 1, 4},
 275         { 9600000, 24000000,  5,   2, 1, 1},
 276
 277         { 28800000, 56448000, 49, 25, 1, 1},
 278         { 28800000, 73728000, 64, 25, 1, 1},
 279         { 28800000, 24000000,  5,  6, 1, 1},
 280         { 0, 0, 0, 0, 0, 0 },
 281 };
 282
 283 DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
 284                 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
 285                 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
 286
 287 DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
 288                 pll_a, CLK_IGNORE_UNUSED);
 289
 290 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 291         { 12000000, 216000000, 216, 12, 1, 4},
 292         { 13000000, 216000000, 216, 13, 1, 4},
 293         { 16800000, 216000000, 180, 14, 1, 4},
 294         { 19200000, 216000000, 180, 16, 1, 4},
 295         { 26000000, 216000000, 216, 26, 1, 4},
 296
 297         { 12000000, 594000000, 594, 12, 1, 8},
 298         { 13000000, 594000000, 594, 13, 1, 8},
 299         { 16800000, 594000000, 495, 14, 1, 8},
 300         { 19200000, 594000000, 495, 16, 1, 8},
 301         { 26000000, 594000000, 594, 26, 1, 8},
 302
 303         { 12000000, 1000000000, 1000, 12, 1, 12},
 304         { 13000000, 1000000000, 1000, 13, 1, 12},
 305         { 19200000, 1000000000, 625,  12, 1, 8},
 306         { 26000000, 1000000000, 1000, 26, 1, 12},
 307
 308         { 0, 0, 0, 0, 0, 0 },
 309 };
 310
 311 DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
 312                 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
 313                 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
 314
 315 DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
 316                 pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 317
 318 DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
 319                 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
 320                 tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
 321                 pll_ref);
 322
 323 DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
 324                 pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 325
 326 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
 327         { 12000000, 480000000, 960, 12, 2, 12},
 328         { 13000000, 480000000, 960, 13, 2, 12},
 329         { 16800000, 480000000, 400, 7,  2, 5},
 330         { 19200000, 480000000, 200, 4,  2, 3},
 331         { 26000000, 480000000, 960, 26, 2, 12},
 332         { 0, 0, 0, 0, 0, 0 },
 333 };
 334
 335 DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
 336                 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
 337                 1000, tegra30_pll_ops, 0, NULL, pll_ref);
 338
 339 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 340         /* 1.7 GHz */
 341         { 12000000, 1700000000, 850,  6,  1, 8},
 342         { 13000000, 1700000000, 915,  7,  1, 8},        /* actual: 1699.2 MHz */
 343         { 16800000, 1700000000, 708,  7,  1, 8},        /* actual: 1699.2 MHz */
 344         { 19200000, 1700000000, 885,  10, 1, 8},        /* actual: 1699.2 MHz */
 345         { 26000000, 1700000000, 850,  13, 1, 8},
 346
 347         /* 1.6 GHz */
 348         { 12000000, 1600000000, 800,  6,  1, 8},
 349         { 13000000, 1600000000, 738,  6,  1, 8},        /* actual: 1599.0 MHz */
 350         { 16800000, 1600000000, 857,  9,  1, 8},        /* actual: 1599.7 MHz */
 351         { 19200000, 1600000000, 500,  6,  1, 8},
 352         { 26000000, 1600000000, 800,  13, 1, 8},
 353
 354         /* 1.5 GHz */
 355         { 12000000, 1500000000, 750,  6,  1, 8},
 356         { 13000000, 1500000000, 923,  8,  1, 8},        /* actual: 1499.8 MHz */
 357         { 16800000, 1500000000, 625,  7,  1, 8},
 358         { 19200000, 1500000000, 625,  8,  1, 8},
 359         { 26000000, 1500000000, 750,  13, 1, 8},
 360
 361         /* 1.4 GHz */
 362         { 12000000, 1400000000, 700,  6,  1, 8},
 363         { 13000000, 1400000000, 969,  9,  1, 8},        /* actual: 1399.7 MHz */
 364         { 16800000, 1400000000, 1000, 12, 1, 8},
 365         { 19200000, 1400000000, 875,  12, 1, 8},
 366         { 26000000, 1400000000, 700,  13, 1, 8},
 367
 368         /* 1.3 GHz */
 369         { 12000000, 1300000000, 975,  9,  1, 8},
 370         { 13000000, 1300000000, 1000, 10, 1, 8},
 371         { 16800000, 1300000000, 928,  12, 1, 8},        /* actual: 1299.2 MHz */
 372         { 19200000, 1300000000, 812,  12, 1, 8},        /* actual: 1299.2 MHz */
 373         { 26000000, 1300000000, 650,  13, 1, 8},
 374
 375         /* 1.2 GHz */
 376         { 12000000, 1200000000, 1000, 10, 1, 8},
 377         { 13000000, 1200000000, 923,  10, 1, 8},        /* actual: 1199.9 MHz */
 378         { 16800000, 1200000000, 1000, 14, 1, 8},
 379         { 19200000, 1200000000, 1000, 16, 1, 8},
 380         { 26000000, 1200000000, 600,  13, 1, 8},
 381
 382         /* 1.1 GHz */
 383         { 12000000, 1100000000, 825,  9,  1, 8},
 384         { 13000000, 1100000000, 846,  10, 1, 8},        /* actual: 1099.8 MHz */
 385         { 16800000, 1100000000, 982,  15, 1, 8},        /* actual: 1099.8 MHz */
 386         { 19200000, 1100000000, 859,  15, 1, 8},        /* actual: 1099.5 MHz */
 387         { 26000000, 1100000000, 550,  13, 1, 8},
 388
 389         /* 1 GHz */
 390         { 12000000, 1000000000, 1000, 12, 1, 8},
 391         { 13000000, 1000000000, 1000, 13, 1, 8},
 392         { 16800000, 1000000000, 833,  14, 1, 8},        /* actual: 999.6 MHz */
 393         { 19200000, 1000000000, 625,  12, 1, 8},
 394         { 26000000, 1000000000, 1000, 26, 1, 8},
 395
 396         { 0, 0, 0, 0, 0, 0 },
 397 };
 398
 399 DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
 400                 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
 401                 tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
 402
 403 DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
 404                 pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
 405
 406 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
 407         /* PLLE special case: use cpcon field to store cml divider value */
 408         { 12000000,  100000000, 150, 1,  18, 11},
 409         { 216000000, 100000000, 200, 18, 24, 13},
 410         { 0, 0, 0, 0, 0, 0 },
 411 };
 412
 413 DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
 414                 12000000, 12000000, 1200000000, 2400000000U,
 415                 tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
 416                 pll_ref);
 417
 418 static const char *mux_plle[] = {
 419         "pll_e",
 420 };
 421
 422 static struct clk *mux_plle_p[] = {
 423         &tegra_pll_e,
 424 };
 425
 426 static struct clk tegra_cml0;
 427 static struct clk_tegra tegra_cml0_hw = {
 428         .hw = {
 429                 .clk = &tegra_cml0,
 430         },
 431         .reg = 0x48c,
 432         .fixed_rate = 100000000,
 433         .u.periph = {
 434                 .clk_num = 0,
 435         },
 436 };
 437 DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
 438                 mux_plle_p, &tegra_pll_e);
 439
 440 static struct clk tegra_cml1;
 441 static struct clk_tegra tegra_cml1_hw = {
 442         .hw = {
 443                 .clk = &tegra_cml1,
 444         },
 445         .reg = 0x48c,
 446         .fixed_rate = 100000000,
 447         .u.periph = {
 448                 .clk_num = 1,
 449         },
 450 };
 451 DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
 452                 mux_plle_p, &tegra_pll_e);
 453
 454 static struct clk tegra_pciex;
 455 static struct clk_tegra tegra_pciex_hw = {
 456         .hw = {
 457                 .clk = &tegra_pciex,
 458         },
 459         .reg = 0x48c,
 460         .fixed_rate = 100000000,
 461         .reset = tegra30_periph_clk_reset,
 462         .u.periph = {
 463                 .clk_num = 74,
 464         },
 465 };
 466 DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
 467                 mux_plle_p, &tegra_pll_e);
 468
 469 #define SYNC_SOURCE(_name)                                      \
 470         static struct clk tegra_##_name##_sync;                 \
 471         static struct clk_tegra tegra_##_name##_sync_hw = {     \
 472                 .hw = {                                         \
 473                         .clk = &tegra_##_name##_sync,           \
 474                 },                                              \
 475                 .max_rate = 24000000,                           \
 476                 .fixed_rate = 24000000,                         \
 477         };                                                      \
 478         static struct clk tegra_##_name##_sync = {              \
 479                 .name = #_name "_sync",                         \
 480                 .hw = &tegra_##_name##_sync_hw.hw,              \
 481                 .ops = &tegra_sync_source_ops,                  \
 482                 .flags = CLK_IS_ROOT,                           \
 483         };
 484
 485 SYNC_SOURCE(spdif_in);
 486 SYNC_SOURCE(i2s0);
 487 SYNC_SOURCE(i2s1);
 488 SYNC_SOURCE(i2s2);
 489 SYNC_SOURCE(i2s3);
 490 SYNC_SOURCE(i2s4);
 491 SYNC_SOURCE(vimclk);
 492
 493 static struct clk *tegra_sync_source_list[] = {
 494         &tegra_spdif_in_sync,
 495         &tegra_i2s0_sync,
 496         &tegra_i2s1_sync,
 497         &tegra_i2s2_sync,
 498         &tegra_i2s3_sync,
 499         &tegra_i2s4_sync,
 500         &tegra_vimclk_sync,
 501 };
 502
 503 static const char *mux_audio_sync_clk[] = {
 504         "spdif_in_sync",
 505         "i2s0_sync",
 506         "i2s1_sync",
 507         "i2s2_sync",
 508         "i2s3_sync",
 509         "i2s4_sync",
 510         "vimclk_sync",
 511 };
 512
 513 #define AUDIO_SYNC_CLK(_name, _index)                           \
 514         static struct clk tegra_##_name;                        \
 515         static struct clk_tegra tegra_##_name##_hw = {          \
 516                 .hw = {                                         \
 517                         .clk = &tegra_##_name,                  \
 518                 },                                              \
 519                 .max_rate = 24000000,                           \
 520                 .reg = 0x4A0 + (_index) * 4,                    \
 521         };                                                      \
 522         static struct clk tegra_##_name = {                     \
 523                 .name = #_name,                                 \
 524                 .ops = &tegra30_audio_sync_clk_ops,             \
 525                 .hw = &tegra_##_name##_hw.hw,                   \
 526                 .parent_names = mux_audio_sync_clk,             \
 527                 .parents = tegra_sync_source_list,              \
 528                 .num_parents = ARRAY_SIZE(mux_audio_sync_clk),  \
 529         };
 530
 531 AUDIO_SYNC_CLK(audio0, 0);
 532 AUDIO_SYNC_CLK(audio1, 1);
 533 AUDIO_SYNC_CLK(audio2, 2);
 534 AUDIO_SYNC_CLK(audio3, 3);
 535 AUDIO_SYNC_CLK(audio4, 4);
 536 AUDIO_SYNC_CLK(audio5, 5);
 537
 538 static struct clk *tegra_clk_audio_list[] = {
 539         &tegra_audio0,
 540         &tegra_audio1,
 541         &tegra_audio2,
 542         &tegra_audio3,
 543         &tegra_audio4,
 544         &tegra_audio5,  /* SPDIF */
 545 };
 546
 547 #define AUDIO_SYNC_2X_CLK(_name, _index)                        \
 548         static const char *_name##_parent_names[] = {           \
 549                 "tegra_" #_name,                                \
 550         };                                                      \
 551         static struct clk *_name##_parents[] = {                \
 552                 &tegra_##_name,                                 \
 553         };                                                      \
 554         static struct clk tegra_##_name##_2x;                   \
 555         static struct clk_tegra tegra_##_name##_2x_hw = {       \
 556                 .hw = {                                         \
 557                         .clk = &tegra_##_name##_2x,             \
 558                 },                                              \
 559                 .flags = PERIPH_NO_RESET,                       \
 560                 .max_rate = 48000000,                           \
 561                 .reg = 0x49C,                                   \
 562                 .reg_shift = 24 + (_index),                     \
 563                 .u.periph = {                                   \
 564                         .clk_num = 113 + (_index),              \
 565                 },                                              \
 566         };                                                      \
 567         static struct clk tegra_##_name##_2x = {                \
 568                 .name = #_name "_2x",                           \
 569                 .ops = &tegra30_clk_double_ops,                 \
 570                 .hw = &tegra_##_name##_2x_hw.hw,                \
 571                 .parent_names = _name##_parent_names,           \
 572                 .parents = _name##_parents,                     \
 573                 .parent = &tegra_##_name,                       \
 574                 .num_parents = 1,                               \
 575         };
 576
 577 AUDIO_SYNC_2X_CLK(audio0, 0);
 578 AUDIO_SYNC_2X_CLK(audio1, 1);
 579 AUDIO_SYNC_2X_CLK(audio2, 2);
 580 AUDIO_SYNC_2X_CLK(audio3, 3);
 581 AUDIO_SYNC_2X_CLK(audio4, 4);
 582 AUDIO_SYNC_2X_CLK(audio5, 5);   /* SPDIF */
 583
 584 static struct clk *tegra_clk_audio_2x_list[] = {
 585         &tegra_audio0_2x,
 586         &tegra_audio1_2x,
 587         &tegra_audio2_2x,
 588         &tegra_audio3_2x,
 589         &tegra_audio4_2x,
 590         &tegra_audio5_2x,       /* SPDIF */
 591 };
 592
 593 #define MUX_I2S_SPDIF(_id)                                      \
 594 static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = {      \
 595         "pll_a_out0",                                           \
 596         #_id "_2x",                                             \
 597         "pll_p",                                                \
 598         "clk_m",                                                \
 599 };                                                              \
 600 static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = {    \
 601         &tegra_pll_a_out0,                                      \
 602         &tegra_##_id##_2x,                                      \
 603         &tegra_pll_p,                                           \
 604         &tegra_clk_m,                                           \
 605 };
 606
 607 MUX_I2S_SPDIF(audio0);
 608 MUX_I2S_SPDIF(audio1);
 609 MUX_I2S_SPDIF(audio2);
 610 MUX_I2S_SPDIF(audio3);
 611 MUX_I2S_SPDIF(audio4);
 612 MUX_I2S_SPDIF(audio5);          /* SPDIF */
 613
 614 static struct clk tegra_extern1;
 615 static struct clk tegra_extern2;
 616 static struct clk tegra_extern3;
 617
 618 /* External clock outputs (through PMC) */
 619 #define MUX_EXTERN_OUT(_id)                                     \
 620 static const char *mux_clkm_clkm2_clkm4_extern##_id[] = {       \
 621         "clk_m",                                                \
 622         "clk_m_div2",                                           \
 623         "clk_m_div4",                                           \
 624         "extern" #_id,                                          \
 625 };                                                              \
 626 static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = {   \
 627         &tegra_clk_m,                                           \
 628         &tegra_clk_m_div2,                                      \
 629         &tegra_clk_m_div4,                                      \
 630         &tegra_extern##_id,                                     \
 631 };
 632
 633 MUX_EXTERN_OUT(1);
 634 MUX_EXTERN_OUT(2);
 635 MUX_EXTERN_OUT(3);
 636
 637 #define CLK_OUT_CLK(_name, _index)                                      \
 638         static struct clk tegra_##_name;                                \
 639         static struct clk_tegra tegra_##_name##_hw = {                  \
 640                 .hw = {                                                 \
 641                         .clk = &tegra_##_name,                          \
 642                 },                                                      \
 643                 .lookup = {                                             \
 644                         .dev_id = #_name,                               \
 645                         .con_id = "extern" #_index,                     \
 646                 },                                                      \
 647                 .flags = MUX_CLK_OUT,                                   \
 648                 .fixed_rate = 216000000,                                        \
 649                 .reg = 0x1a8,                                           \
 650                 .u.periph = {                                           \
 651                         .clk_num = (_index - 1) * 8 + 2,                \
 652                 },                                                      \
 653         };                                                              \
 654         static struct clk tegra_##_name = {                             \
 655                 .name = #_name,                                         \
 656                 .ops = &tegra_clk_out_ops,                              \
 657                 .hw = &tegra_##_name##_hw.hw,                           \
 658                 .parent_names = mux_clkm_clkm2_clkm4_extern##_index,    \
 659                 .parents = mux_clkm_clkm2_clkm4_extern##_index##_p,     \
 660                 .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
 661         };
 662
 663 CLK_OUT_CLK(clk_out_1, 1);
 664 CLK_OUT_CLK(clk_out_2, 2);
 665 CLK_OUT_CLK(clk_out_3, 3);
 666
 667 static struct clk *tegra_clk_out_list[] = {
 668         &tegra_clk_out_1,
 669         &tegra_clk_out_2,
 670         &tegra_clk_out_3,
 671 };
 672
 673 static const char *mux_sclk[] = {
 674         "clk_m",
 675         "pll_c_out1",
 676         "pll_p_out4",
 677         "pll_p_out3",
 678         "pll_p_out2",
 679         "dummy",
 680         "clk_32k",
 681         "pll_m_out1",
 682 };
 683
 684 static struct clk *mux_sclk_p[] = {
 685         &tegra_clk_m,
 686         &tegra_pll_c_out1,
 687         &tegra_pll_p_out4,
 688         &tegra_pll_p_out3,
 689         &tegra_pll_p_out2,
 690         NULL,
 691         &tegra_clk_32k,
 692         &tegra_pll_m_out1,
 693 };
 694
 695 static struct clk tegra_clk_sclk;
 696 static struct clk_tegra tegra_clk_sclk_hw = {
 697         .hw = {
 698                 .clk = &tegra_clk_sclk,
 699         },
 700         .reg = 0x28,
 701         .max_rate = 334000000,
 702         .min_rate = 40000000,
 703 };
 704
 705 static struct clk tegra_clk_sclk = {
 706         .name = "sclk",
 707         .ops = &tegra30_super_ops,
 708         .hw = &tegra_clk_sclk_hw.hw,
 709         .parent_names = mux_sclk,
 710         .parents = mux_sclk_p,
 711         .num_parents = ARRAY_SIZE(mux_sclk),
 712 };
 713
 714 static const char *tegra_hclk_parent_names[] = {
 715         "tegra_sclk",
 716 };
 717
 718 static struct clk *tegra_hclk_parents[] = {
 719         &tegra_clk_sclk,
 720 };
 721
 722 static struct clk tegra_hclk;
 723 static struct clk_tegra tegra_hclk_hw = {
 724         .hw = {
 725                 .clk = &tegra_hclk,
 726         },
 727         .flags = DIV_BUS,
 728         .reg = 0x30,
 729         .reg_shift = 4,
 730         .max_rate = 378000000,
 731         .min_rate = 12000000,
 732 };
 733 DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
 734                 tegra_hclk_parents, &tegra_clk_sclk);
 735
 736 static const char *tegra_pclk_parent_names[] = {
 737         "tegra_hclk",
 738 };
 739
 740 static struct clk *tegra_pclk_parents[] = {
 741         &tegra_hclk,
 742 };
 743
 744 static struct clk tegra_pclk;
 745 static struct clk_tegra tegra_pclk_hw = {
 746         .hw = {
 747                 .clk = &tegra_pclk,
 748         },
 749         .flags = DIV_BUS,
 750         .reg = 0x30,
 751         .reg_shift = 0,
 752         .max_rate = 167000000,
 753         .min_rate = 12000000,
 754 };
 755 DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
 756                 tegra_pclk_parents, &tegra_hclk);
 757
 758 static const char *mux_blink[] = {
 759         "clk_32k",
 760 };
 761
 762 static struct clk *mux_blink_p[] = {
 763         &tegra_clk_32k,
 764 };
 765
 766 static struct clk tegra_clk_blink;
 767 static struct clk_tegra tegra_clk_blink_hw = {
 768         .hw = {
 769                 .clk = &tegra_clk_blink,
 770         },
 771         .reg = 0x40,
 772         .max_rate = 32768,
 773 };
 774 static struct clk tegra_clk_blink = {
 775         .name = "blink",
 776         .ops = &tegra30_blink_clk_ops,
 777         .hw = &tegra_clk_blink_hw.hw,
 778         .parent = &tegra_clk_32k,
 779         .parent_names = mux_blink,
 780         .parents = mux_blink_p,
 781         .num_parents = ARRAY_SIZE(mux_blink),
 782 };
 783
 784 static const char *mux_pllm_pllc_pllp_plla[] = {
 785         "pll_m",
 786         "pll_c",
 787         "pll_p",
 788         "pll_a_out0",
 789 };
 790
 791 static const char *mux_pllp_pllc_pllm_clkm[] = {
 792         "pll_p",
 793         "pll_c",
 794         "pll_m",
 795         "clk_m",
 796 };
 797
 798 static const char *mux_pllp_clkm[] = {
 799         "pll_p",
 800         "dummy",
 801         "dummy",
 802         "clk_m",
 803 };
 804
 805 static const char *mux_pllp_plld_pllc_clkm[] = {
 806         "pll_p",
 807         "pll_d_out0",
 808         "pll_c",
 809         "clk_m",
 810 };
 811
 812 static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
 813         "pll_p",
 814         "pll_m",
 815         "pll_d_out0",
 816         "pll_a_out0",
 817         "pll_c",
 818         "pll_d2_out0",
 819         "clk_m",
 820 };
 821
 822 static const char *mux_plla_pllc_pllp_clkm[] = {
 823         "pll_a_out0",
 824         "dummy",
 825         "pll_p",
 826         "clk_m"
 827 };
 828
 829 static const char *mux_pllp_pllc_clk32_clkm[] = {
 830         "pll_p",
 831         "pll_c",
 832         "clk_32k",
 833         "clk_m",
 834 };
 835
 836 static const char *mux_pllp_pllc_clkm_clk32[] = {
 837         "pll_p",
 838         "pll_c",
 839         "clk_m",
 840         "clk_32k",
 841 };
 842
 843 static const char *mux_pllp_pllc_pllm[] = {
 844         "pll_p",
 845         "pll_c",
 846         "pll_m",
 847 };
 848
 849 static const char *mux_clk_m[] = {
 850         "clk_m",
 851 };
 852
 853 static const char *mux_pllp_out3[] = {
 854         "pll_p_out3",
 855 };
 856
 857 static const char *mux_plld_out0[] = {
 858         "pll_d_out0",
 859 };
 860
 861 static const char *mux_plld_out0_plld2_out0[] = {
 862         "pll_d_out0",
 863         "pll_d2_out0",
 864 };
 865
 866 static const char *mux_clk_32k[] = {
 867         "clk_32k",
 868 };
 869
 870 static const char *mux_plla_clk32_pllp_clkm_plle[] = {
 871         "pll_a_out0",
 872         "clk_32k",
 873         "pll_p",
 874         "clk_m",
 875         "pll_e",
 876 };
 877
 878 static const char *mux_cclk_g[] = {
 879         "clk_m",
 880         "pll_c",
 881         "clk_32k",
 882         "pll_m",
 883         "pll_p",
 884         "pll_p_out4",
 885         "pll_p_out3",
 886         "dummy",
 887         "pll_x",
 888 };
 889
 890 static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
 891         &tegra_pll_m,
 892         &tegra_pll_c,
 893         &tegra_pll_p,
 894         &tegra_pll_a_out0,
 895 };
 896
 897 static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
 898         &tegra_pll_p,
 899         &tegra_pll_c,
 900         &tegra_pll_m,
 901         &tegra_clk_m,
 902 };
 903
 904 static struct clk *mux_pllp_clkm_p[] = {
 905         &tegra_pll_p,
 906         NULL,
 907         NULL,
 908         &tegra_clk_m,
 909 };
 910
 911 static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
 912         &tegra_pll_p,
 913         &tegra_pll_d_out0,
 914         &tegra_pll_c,
 915         &tegra_clk_m,
 916 };
 917
 918 static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
 919         &tegra_pll_p,
 920         &tegra_pll_m,
 921         &tegra_pll_d_out0,
 922         &tegra_pll_a_out0,
 923         &tegra_pll_c,
 924         &tegra_pll_d2_out0,
 925         &tegra_clk_m,
 926 };
 927
 928 static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
 929         &tegra_pll_a_out0,
 930         NULL,
 931         &tegra_pll_p,
 932         &tegra_clk_m,
 933 };
 934
 935 static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
 936         &tegra_pll_p,
 937         &tegra_pll_c,
 938         &tegra_clk_32k,
 939         &tegra_clk_m,
 940 };
 941
 942 static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
 943         &tegra_pll_p,
 944         &tegra_pll_c,
 945         &tegra_clk_m,
 946         &tegra_clk_32k,
 947 };
 948
 949 static struct clk *mux_pllp_pllc_pllm_p[] = {
 950         &tegra_pll_p,
 951         &tegra_pll_c,
 952         &tegra_pll_m,
 953 };
 954
 955 static struct clk *mux_clk_m_p[] = {
 956         &tegra_clk_m,
 957 };
 958
 959 static struct clk *mux_pllp_out3_p[] = {
 960         &tegra_pll_p_out3,
 961 };
 962
 963 static struct clk *mux_plld_out0_p[] = {
 964         &tegra_pll_d_out0,
 965 };
 966
 967 static struct clk *mux_plld_out0_plld2_out0_p[] = {
 968         &tegra_pll_d_out0,
 969         &tegra_pll_d2_out0,
 970 };
 971
 972 static struct clk *mux_clk_32k_p[] = {
 973         &tegra_clk_32k,
 974 };
 975
 976 static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
 977         &tegra_pll_a_out0,
 978         &tegra_clk_32k,
 979         &tegra_pll_p,
 980         &tegra_clk_m,
 981         &tegra_pll_e,
 982 };
 983
 984 static struct clk *mux_cclk_g_p[] = {
 985         &tegra_clk_m,
 986         &tegra_pll_c,
 987         &tegra_clk_32k,
 988         &tegra_pll_m,
 989         &tegra_pll_p,
 990         &tegra_pll_p_out4,
 991         &tegra_pll_p_out3,
 992         NULL,
 993         &tegra_pll_x,
 994 };
 995
 996 static struct clk tegra_clk_cclk_g;
 997 static struct clk_tegra tegra_clk_cclk_g_hw = {
 998         .hw = {
 999                 .clk = &tegra_clk_cclk_g,
1000         },
1001         .flags = DIV_U71 | DIV_U71_INT,
1002         .reg = 0x368,
1003         .max_rate = 1700000000,
1004 };
1005 static struct clk tegra_clk_cclk_g = {
1006         .name = "cclk_g",
1007         .ops = &tegra30_super_ops,
1008         .hw = &tegra_clk_cclk_g_hw.hw,
1009         .parent_names = mux_cclk_g,
1010         .parents = mux_cclk_g_p,
1011         .num_parents = ARRAY_SIZE(mux_cclk_g),
1012 };
1013
1014 static const char *mux_twd[] = {
1015         "cclk_g",
1016 };
1017
1018 static struct clk *mux_twd_p[] = {
1019         &tegra_clk_cclk_g,
1020 };
1021
1022 static struct clk tegra30_clk_twd;
1023 static struct clk_tegra tegra30_clk_twd_hw = {
1024         .hw = {
1025                 .clk = &tegra30_clk_twd,
1026         },
1027         .max_rate = 1400000000,
1028         .mul = 1,
1029         .div = 2,
1030 };
1031
1032 static struct clk tegra30_clk_twd = {
1033         .name = "twd",
1034         .ops = &tegra30_twd_ops,
1035         .hw = &tegra30_clk_twd_hw.hw,
1036         .parent = &tegra_clk_cclk_g,
1037         .parent_names = mux_twd,
1038         .parents = mux_twd_p,
1039         .num_parents = ARRAY_SIZE(mux_twd),
1040 };
1041
1042 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg,   \
1043                 _max, _inputs, _flags)                  \
1044         static struct clk tegra_##_name;                \
1045         static struct clk_tegra tegra_##_name##_hw = {  \
1046                 .hw = {                                 \
1047                         .clk = &tegra_##_name,          \
1048                 },                                      \
1049                 .lookup = {                             \
1050                         .dev_id = _dev,                 \
1051                         .con_id = _con,                 \
1052                 },                                      \
1053                 .reg = _reg,                            \
1054                 .flags = _flags,                        \
1055                 .max_rate = _max,                       \
1056                 .u.periph = {                           \
1057                         .clk_num = _clk_num,            \
1058                 },                                      \
1059                 .reset = &tegra30_periph_clk_reset,     \
1060         };                                              \
1061         static struct clk tegra_##_name = {             \
1062                 .name = #_name,                         \
1063                 .ops = &tegra30_periph_clk_ops,         \
1064                 .hw = &tegra_##_name##_hw.hw,           \
1065                 .parent_names = _inputs,                \
1066                 .parents = _inputs##_p,                 \
1067                 .num_parents = ARRAY_SIZE(_inputs),     \
1068         };
1069
1070 PERIPH_CLK(apbdma,      "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0);
1071 PERIPH_CLK(rtc,         "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
1072 PERIPH_CLK(kbc,         "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB);
1073 PERIPH_CLK(timer,       "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0);
1074 PERIPH_CLK(kfuse,       "kfuse-tegra",          NULL,   40,     0,      26000000,  mux_clk_m,                   0);
1075 PERIPH_CLK(fuse,        "fuse-tegra",           "fuse", 39,     0,      26000000,  mux_clk_m,                   PERIPH_ON_APB);
1076 PERIPH_CLK(fuse_burn,   "fuse-tegra",           "fuse_burn",    39,     0,      26000000,  mux_clk_m,           PERIPH_ON_APB);
1077 PERIPH_CLK(apbif,       "tegra30-ahub",         "apbif", 107,   0,      26000000,  mux_clk_m,                   0);
1078 PERIPH_CLK(i2s0,        "tegra30-i2s.0",        NULL,   30,     0x1d8,  26000000,  mux_pllaout0_audio0_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1079 PERIPH_CLK(i2s1,        "tegra30-i2s.1",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio1_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1080 PERIPH_CLK(i2s2,        "tegra30-i2s.2",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1081 PERIPH_CLK(i2s3,        "tegra30-i2s.3",        NULL,   101,    0x3bc,  26000000,  mux_pllaout0_audio3_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1082 PERIPH_CLK(i2s4,        "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1083 PERIPH_CLK(spdif_out,   "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio5_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1084 PERIPH_CLK(spdif_in,    "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB);
1085 PERIPH_CLK(pwm,         "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
1086 PERIPH_CLK(d_audio,     "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
1087 PERIPH_CLK(dam0,        "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
1088 PERIPH_CLK(dam1,        "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
1089 PERIPH_CLK(dam2,        "tegra30-dam.2",        NULL,   110,    0x3e0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71);
1090 PERIPH_CLK(hda,         "tegra30-hda",          "hda",  125,    0x428,  108000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1091 PERIPH_CLK(hda2codec_2x,        "tegra30-hda",  "hda2codec",    111,    0x3e4,  48000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1092 PERIPH_CLK(hda2hdmi,    "tegra30-hda",          "hda2hdmi",     128,    0,      48000000,  mux_clk_m,                   0);
1093 PERIPH_CLK(sbc1,        "spi_tegra.0",          NULL,   41,     0x134,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1094 PERIPH_CLK(sbc2,        "spi_tegra.1",          NULL,   44,     0x118,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1095 PERIPH_CLK(sbc3,        "spi_tegra.2",          NULL,   46,     0x11c,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1096 PERIPH_CLK(sbc4,        "spi_tegra.3",          NULL,   68,     0x1b4,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1097 PERIPH_CLK(sbc5,        "spi_tegra.4",          NULL,   104,    0x3c8,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1098 PERIPH_CLK(sbc6,        "spi_tegra.5",          NULL,   105,    0x3cc,  160000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1099 PERIPH_CLK(sata_oob,    "tegra_sata_oob",       NULL,   123,    0x420,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1100 PERIPH_CLK(sata,        "tegra_sata",           NULL,   124,    0x424,  216000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1101 PERIPH_CLK(sata_cold,   "tegra_sata_cold",      NULL,   129,    0,      48000000,  mux_clk_m,                   0);
1102 PERIPH_CLK(ndflash,     "tegra_nand",           NULL,   13,     0x160,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1103 PERIPH_CLK(ndspeed,     "tegra_nand_speed",     NULL,   80,     0x3f8,  240000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1104 PERIPH_CLK(vfir,        "vfir",                 NULL,   7,      0x168,  72000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1105 PERIPH_CLK(sdmmc1,      "sdhci-tegra.0",        NULL,   14,     0x150,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
1106 PERIPH_CLK(sdmmc2,      "sdhci-tegra.1",        NULL,   9,      0x154,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
1107 PERIPH_CLK(sdmmc3,      "sdhci-tegra.2",        NULL,   69,     0x1bc,  208000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
1108 PERIPH_CLK(sdmmc4,      "sdhci-tegra.3",        NULL,   15,     0x164,  104000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* scales with voltage */
1109 PERIPH_CLK(vcp,         "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0);
1110 PERIPH_CLK(bsea,        "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0);
1111 PERIPH_CLK(bsev,        "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0);
1112 PERIPH_CLK(vde,         "vde",                  NULL,   61,     0x1c8,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
1113 PERIPH_CLK(csite,       "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* max rate ??? */
1114 PERIPH_CLK(la,          "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71);
1115 PERIPH_CLK(owr,         "tegra_w1",             NULL,   71,     0x1cc,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB);
1116 PERIPH_CLK(nor,         "nor",                  NULL,   42,     0x1d0,  127000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71); /* requires min voltage */
1117 PERIPH_CLK(mipi,        "mipi",                 NULL,   50,     0x174,  60000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
1118 PERIPH_CLK(i2c1,        "tegra-i2c.0",          "div-clk", 12,  0x124,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
1119 PERIPH_CLK(i2c2,        "tegra-i2c.1",          "div-clk", 54,  0x198,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
1120 PERIPH_CLK(i2c3,        "tegra-i2c.2",          "div-clk", 67,  0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
1121 PERIPH_CLK(i2c4,        "tegra-i2c.3",          "div-clk", 103, 0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
1122 PERIPH_CLK(i2c5,        "tegra-i2c.4",          "div-clk", 47,  0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB);
1123 PERIPH_CLK(uarta,       "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1124 PERIPH_CLK(uartb,       "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1125 PERIPH_CLK(uartc,       "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1126 PERIPH_CLK(uartd,       "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1127 PERIPH_CLK(uarte,       "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
1128 PERIPH_CLK(vi,          "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
1129 PERIPH_CLK(3d,          "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1130 PERIPH_CLK(3d2,         "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
1131 PERIPH_CLK(2d,          "2d",                   NULL,   21,     0x15c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
1132 PERIPH_CLK(vi_sensor,   "tegra_camera",         "vi_sensor",    20,     0x1a8,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_NO_RESET);
1133 PERIPH_CLK(epp,         "epp",                  NULL,   19,     0x16c,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
1134 PERIPH_CLK(mpe,         "mpe",                  NULL,   60,     0x170,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
1135 PERIPH_CLK(host1x,      "host1x",               NULL,   28,     0x180,  260000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT);
1136 PERIPH_CLK(cve,         "cve",                  NULL,   49,     0x140,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
1137 PERIPH_CLK(tvo,         "tvo",                  NULL,   49,     0x188,  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
1138 PERIPH_CLK(dtv,         "dtv",                  NULL,   79,     0x1dc,  250000000, mux_clk_m,                   0);
1139 PERIPH_CLK(hdmi,        "hdmi",                 NULL,   51,     0x18c,  148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8 | DIV_U71);
1140 PERIPH_CLK(tvdac,       "tvdac",                NULL,   53,     0x194,  220000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71); /* requires min voltage */
1141 PERIPH_CLK(disp1,       "tegradc.0",            NULL,   27,     0x138,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
1142 PERIPH_CLK(disp2,       "tegradc.1",            NULL,   26,     0x13c,  600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm,     MUX | MUX8);
1143 PERIPH_CLK(usbd,        "fsl-tegra-udc",        NULL,   22,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
1144 PERIPH_CLK(usb2,        "tegra-ehci.1",         NULL,   58,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
1145 PERIPH_CLK(usb3,        "tegra-ehci.2",         NULL,   59,     0,      480000000, mux_clk_m,                   0); /* requires min voltage */
1146 PERIPH_CLK(dsia,        "tegradc.0",            "dsia", 48,     0,      500000000, mux_plld_out0,               0);
1147 PERIPH_CLK(csi,         "tegra_camera",         "csi",  52,     0,      102000000, mux_pllp_out3,               0);
1148 PERIPH_CLK(isp,         "tegra_camera",         "isp",  23,     0,      150000000, mux_clk_m,                   0); /* same frequency as VI */
1149 PERIPH_CLK(csus,        "tegra_camera",         "csus", 92,     0,      150000000, mux_clk_m,                   PERIPH_NO_RESET);
1150 PERIPH_CLK(tsensor,     "tegra-tsensor",        NULL,   100,    0x3b8,  216000000, mux_pllp_pllc_clkm_clk32,    MUX | DIV_U71);
1151 PERIPH_CLK(actmon,      "actmon",               NULL,   119,    0x3e8,  216000000, mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71);
1152 PERIPH_CLK(extern1,     "extern1",              NULL,   120,    0x3ec,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
1153 PERIPH_CLK(extern2,     "extern2",              NULL,   121,    0x3f0,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
1154 PERIPH_CLK(extern3,     "extern3",              NULL,   122,    0x3f4,  216000000, mux_plla_clk32_pllp_clkm_plle,       MUX | MUX8 | DIV_U71);
1155 PERIPH_CLK(i2cslow,     "i2cslow",              NULL,   81,     0x3fc,  26000000,  mux_pllp_pllc_clk32_clkm,    MUX | DIV_U71 | PERIPH_ON_APB);
1156 PERIPH_CLK(pcie,        "tegra-pcie",           "pcie", 70,     0,      250000000, mux_clk_m,                   0);
1157 PERIPH_CLK(afi,         "tegra-pcie",           "afi",  72,     0,      250000000, mux_clk_m,                   0);
1158 PERIPH_CLK(se,          "se",                   NULL,   127,    0x42c,  520000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT);
1159
1160 static struct clk tegra_dsib;
1161 static struct clk_tegra tegra_dsib_hw = {
1162         .hw = {
1163                 .clk = &tegra_dsib,
1164         },
1165         .lookup = {
1166                 .dev_id = "tegradc.1",
1167                 .con_id = "dsib",
1168         },
1169         .reg = 0xd0,
1170         .flags = MUX | PLLD,
1171         .max_rate = 500000000,
1172         .u.periph = {
1173                 .clk_num = 82,
1174         },
1175         .reset = &tegra30_periph_clk_reset,
1176 };
1177 static struct clk tegra_dsib = {
1178         .name = "dsib",
1179         .ops = &tegra30_dsib_clk_ops,
1180         .hw = &tegra_dsib_hw.hw,
1181         .parent_names = mux_plld_out0_plld2_out0,
1182         .parents = mux_plld_out0_plld2_out0_p,
1183         .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
1184 };
1185
1186 struct clk *tegra_list_clks[] = {
1187         &tegra_apbdma,
1188         &tegra_rtc,
1189         &tegra_kbc,
1190         &tegra_timer,
1191         &tegra_kfuse,
1192         &tegra_fuse,
1193         &tegra_fuse_burn,
1194         &tegra_apbif,
1195         &tegra_i2s0,
1196         &tegra_i2s1,
1197         &tegra_i2s2,
1198         &tegra_i2s3,
1199         &tegra_i2s4,
1200         &tegra_spdif_out,
1201         &tegra_spdif_in,
1202         &tegra_pwm,
1203         &tegra_d_audio,
1204         &tegra_dam0,
1205         &tegra_dam1,
1206         &tegra_dam2,
1207         &tegra_hda,
1208         &tegra_hda2codec_2x,
1209         &tegra_hda2hdmi,
1210         &tegra_sbc1,
1211         &tegra_sbc2,
1212         &tegra_sbc3,
1213         &tegra_sbc4,
1214         &tegra_sbc5,
1215         &tegra_sbc6,
1216         &tegra_sata_oob,
1217         &tegra_sata,
1218         &tegra_sata_cold,
1219         &tegra_ndflash,
1220         &tegra_ndspeed,
1221         &tegra_vfir,
1222         &tegra_sdmmc1,
1223         &tegra_sdmmc2,
1224         &tegra_sdmmc3,
1225         &tegra_sdmmc4,
1226         &tegra_vcp,
1227         &tegra_bsea,
1228         &tegra_bsev,
1229         &tegra_vde,
1230         &tegra_csite,
1231         &tegra_la,
1232         &tegra_owr,
1233         &tegra_nor,
1234         &tegra_mipi,
1235         &tegra_i2c1,
1236         &tegra_i2c2,
1237         &tegra_i2c3,
1238         &tegra_i2c4,
1239         &tegra_i2c5,
1240         &tegra_uarta,
1241         &tegra_uartb,
1242         &tegra_uartc,
1243         &tegra_uartd,
1244         &tegra_uarte,
1245         &tegra_vi,
1246         &tegra_3d,
1247         &tegra_3d2,
1248         &tegra_2d,
1249         &tegra_vi_sensor,
1250         &tegra_epp,
1251         &tegra_mpe,
1252         &tegra_host1x,
1253         &tegra_cve,
1254         &tegra_tvo,
1255         &tegra_dtv,
1256         &tegra_hdmi,
1257         &tegra_tvdac,
1258         &tegra_disp1,
1259         &tegra_disp2,
1260         &tegra_usbd,
1261         &tegra_usb2,
1262         &tegra_usb3,
1263         &tegra_dsia,
1264         &tegra_dsib,
1265         &tegra_csi,
1266         &tegra_isp,
1267         &tegra_csus,
1268         &tegra_tsensor,
1269         &tegra_actmon,
1270         &tegra_extern1,
1271         &tegra_extern2,
1272         &tegra_extern3,
1273         &tegra_i2cslow,
1274         &tegra_pcie,
1275         &tegra_afi,
1276         &tegra_se,
1277 };
1278
1279 #define CLK_DUPLICATE(_name, _dev, _con)        \
1280         {                                       \
1281                 .name   = _name,                \
1282                 .lookup = {                     \
1283                         .dev_id = _dev,         \
1284                         .con_id = _con,         \
1285                 },                              \
1286         }
1287
1288 /* Some clocks may be used by different drivers depending on the board
1289  * configuration.  List those here to register them twice in the clock lookup
1290  * table under two names.
1291  */
1292 struct clk_duplicate tegra_clk_duplicates[] = {
1293         CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
1294         CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
1295         CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
1296         CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
1297         CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
1298         CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1299         CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1300         CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1301         CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
1302         CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
1303         CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
1304         CLK_DUPLICATE("bsev", "nvavp", "bsev"),
1305         CLK_DUPLICATE("vde", "tegra-aes", "vde"),
1306         CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
1307         CLK_DUPLICATE("bsea", "nvavp", "bsea"),
1308         CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
1309         CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
1310         CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
1311         CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
1312         CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
1313         CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
1314         CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
1315         CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
1316         CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
1317         CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
1318         CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
1319         CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
1320         CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
1321         CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
1322         CLK_DUPLICATE("twd", "smp_twd", NULL),
1323         CLK_DUPLICATE("vcp", "nvavp", "vcp"),
1324         CLK_DUPLICATE("i2s0", NULL, "i2s0"),
1325         CLK_DUPLICATE("i2s1", NULL, "i2s1"),
1326         CLK_DUPLICATE("i2s2", NULL, "i2s2"),
1327         CLK_DUPLICATE("i2s3", NULL, "i2s3"),
1328         CLK_DUPLICATE("i2s4", NULL, "i2s4"),
1329         CLK_DUPLICATE("dam0", NULL, "dam0"),
1330         CLK_DUPLICATE("dam1", NULL, "dam1"),
1331         CLK_DUPLICATE("dam2", NULL, "dam2"),
1332         CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
1333         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.0", "fast-clk"),
1334         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
1335         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
1336         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
1337         CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
1338         CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
1339         CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
1340         CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
1341 };
1342
1343 struct clk *tegra_ptr_clks[] = {
1344         &tegra_clk_32k,
1345         &tegra_clk_m,
1346         &tegra_clk_m_div2,
1347         &tegra_clk_m_div4,
1348         &tegra_pll_ref,
1349         &tegra_pll_m,
1350         &tegra_pll_m_out1,
1351         &tegra_pll_c,
1352         &tegra_pll_c_out1,
1353         &tegra_pll_p,
1354         &tegra_pll_p_out1,
1355         &tegra_pll_p_out2,
1356         &tegra_pll_p_out3,
1357         &tegra_pll_p_out4,
1358         &tegra_pll_a,
1359         &tegra_pll_a_out0,
1360         &tegra_pll_d,
1361         &tegra_pll_d_out0,
1362         &tegra_pll_d2,
1363         &tegra_pll_d2_out0,
1364         &tegra_pll_u,
1365         &tegra_pll_x,
1366         &tegra_pll_x_out0,
1367         &tegra_pll_e,
1368         &tegra_clk_cclk_g,
1369         &tegra_cml0,
1370         &tegra_cml1,
1371         &tegra_pciex,
1372         &tegra_clk_sclk,
1373         &tegra_hclk,
1374         &tegra_pclk,
1375         &tegra_clk_blink,
1376         &tegra30_clk_twd,
1377 };
1378
1379 static void tegra30_init_one_clock(struct clk *c)
1380 {
1381         struct clk_tegra *clk = to_clk_tegra(c->hw);
1382         __clk_init(NULL, c);
1383         INIT_LIST_HEAD(&clk->shared_bus_list);
1384         if (!clk->lookup.dev_id && !clk->lookup.con_id)
1385                 clk->lookup.con_id = c->name;
1386         clk->lookup.clk = c;
1387         clkdev_add(&clk->lookup);
1388         tegra_clk_add(c);
1389 }
1390
1391 void __init tegra30_init_clocks(void)
1392 {
1393         int i;
1394         struct clk *c;
1395
1396         for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
1397                 tegra30_init_one_clock(tegra_ptr_clks[i]);
1398
1399         for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
1400                 tegra30_init_one_clock(tegra_list_clks[i]);
1401
1402         for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1403                 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
1404                 if (!c) {
1405                         pr_err("%s: Unknown duplicate clock %s\n", __func__,
1406                                 tegra_clk_duplicates[i].name);
1407                         continue;
1408                 }
1409
1410                 tegra_clk_duplicates[i].lookup.clk = c;
1411                 clkdev_add(&tegra_clk_duplicates[i].lookup);
1412         }
1413
1414         for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
1415                 tegra30_init_one_clock(tegra_sync_source_list[i]);
1416         for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
1417                 tegra30_init_one_clock(tegra_clk_audio_list[i]);
1418         for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
1419                 tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
1420
1421         for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
1422                 tegra30_init_one_clock(tegra_clk_out_list[i]);
1423
1424         tegra30_cpu_car_ops_init();
1425 }