2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/clk.h>
26 #include <asm/mach/map.h>
28 #include <plat-omap/dma-omap.h>
30 #include "../plat-omap/sram.h"
32 #include "omap_hwmod.h"
36 #include "powerdomain.h"
37 #include "clockdomain.h"
40 #include "clock2xxx.h"
41 #include "clock3xxx.h"
42 #include "clock44xx.h"
51 #include "prcm_mpu44xx.h"
52 #include "prminst44xx.h"
53 #include "cminst44xx.h"
55 * The machine specific code may provide the extra mapping besides the
56 * default mapping provided here.
59 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
60 static struct map_desc omap24xx_io_desc[] __initdata = {
62 .virtual = L3_24XX_VIRT,
63 .pfn = __phys_to_pfn(L3_24XX_PHYS),
64 .length = L3_24XX_SIZE,
68 .virtual = L4_24XX_VIRT,
69 .pfn = __phys_to_pfn(L4_24XX_PHYS),
70 .length = L4_24XX_SIZE,
75 #ifdef CONFIG_SOC_OMAP2420
76 static struct map_desc omap242x_io_desc[] __initdata = {
78 .virtual = DSP_MEM_2420_VIRT,
79 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
80 .length = DSP_MEM_2420_SIZE,
84 .virtual = DSP_IPI_2420_VIRT,
85 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
86 .length = DSP_IPI_2420_SIZE,
90 .virtual = DSP_MMU_2420_VIRT,
91 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
92 .length = DSP_MMU_2420_SIZE,
99 #ifdef CONFIG_SOC_OMAP2430
100 static struct map_desc omap243x_io_desc[] __initdata = {
102 .virtual = L4_WK_243X_VIRT,
103 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
104 .length = L4_WK_243X_SIZE,
108 .virtual = OMAP243X_GPMC_VIRT,
109 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
110 .length = OMAP243X_GPMC_SIZE,
114 .virtual = OMAP243X_SDRC_VIRT,
115 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
116 .length = OMAP243X_SDRC_SIZE,
120 .virtual = OMAP243X_SMS_VIRT,
121 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
122 .length = OMAP243X_SMS_SIZE,
129 #ifdef CONFIG_ARCH_OMAP3
130 static struct map_desc omap34xx_io_desc[] __initdata = {
132 .virtual = L3_34XX_VIRT,
133 .pfn = __phys_to_pfn(L3_34XX_PHYS),
134 .length = L3_34XX_SIZE,
138 .virtual = L4_34XX_VIRT,
139 .pfn = __phys_to_pfn(L4_34XX_PHYS),
140 .length = L4_34XX_SIZE,
144 .virtual = OMAP34XX_GPMC_VIRT,
145 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
146 .length = OMAP34XX_GPMC_SIZE,
150 .virtual = OMAP343X_SMS_VIRT,
151 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
152 .length = OMAP343X_SMS_SIZE,
156 .virtual = OMAP343X_SDRC_VIRT,
157 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
158 .length = OMAP343X_SDRC_SIZE,
162 .virtual = L4_PER_34XX_VIRT,
163 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
164 .length = L4_PER_34XX_SIZE,
168 .virtual = L4_EMU_34XX_VIRT,
169 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
170 .length = L4_EMU_34XX_SIZE,
173 #if defined(CONFIG_DEBUG_LL) && \
174 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
176 .virtual = ZOOM_UART_VIRT,
177 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
185 #ifdef CONFIG_SOC_TI81XX
186 static struct map_desc omapti81xx_io_desc[] __initdata = {
188 .virtual = L4_34XX_VIRT,
189 .pfn = __phys_to_pfn(L4_34XX_PHYS),
190 .length = L4_34XX_SIZE,
196 #ifdef CONFIG_SOC_AM33XX
197 static struct map_desc omapam33xx_io_desc[] __initdata = {
199 .virtual = L4_34XX_VIRT,
200 .pfn = __phys_to_pfn(L4_34XX_PHYS),
201 .length = L4_34XX_SIZE,
205 .virtual = L4_WK_AM33XX_VIRT,
206 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
207 .length = L4_WK_AM33XX_SIZE,
213 #ifdef CONFIG_ARCH_OMAP4
214 static struct map_desc omap44xx_io_desc[] __initdata = {
216 .virtual = L3_44XX_VIRT,
217 .pfn = __phys_to_pfn(L3_44XX_PHYS),
218 .length = L3_44XX_SIZE,
222 .virtual = L4_44XX_VIRT,
223 .pfn = __phys_to_pfn(L4_44XX_PHYS),
224 .length = L4_44XX_SIZE,
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
233 #ifdef CONFIG_OMAP4_ERRATA_I688
235 .virtual = OMAP4_SRAM_VA,
236 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
238 .type = MT_MEMORY_SO,
245 #ifdef CONFIG_SOC_OMAP5
246 static struct map_desc omap54xx_io_desc[] __initdata = {
248 .virtual = L3_54XX_VIRT,
249 .pfn = __phys_to_pfn(L3_54XX_PHYS),
250 .length = L3_54XX_SIZE,
254 .virtual = L4_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_54XX_PHYS),
256 .length = L4_54XX_SIZE,
260 .virtual = L4_WK_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
262 .length = L4_WK_54XX_SIZE,
266 .virtual = L4_PER_54XX_VIRT,
267 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
268 .length = L4_PER_54XX_SIZE,
274 #ifdef CONFIG_SOC_OMAP2420
275 void __init omap242x_map_io(void)
277 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
278 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
282 #ifdef CONFIG_SOC_OMAP2430
283 void __init omap243x_map_io(void)
285 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
286 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
290 #ifdef CONFIG_ARCH_OMAP3
291 void __init omap3_map_io(void)
293 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
297 #ifdef CONFIG_SOC_TI81XX
298 void __init ti81xx_map_io(void)
300 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
304 #ifdef CONFIG_SOC_AM33XX
305 void __init am33xx_map_io(void)
307 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
311 #ifdef CONFIG_ARCH_OMAP4
312 void __init omap4_map_io(void)
314 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
315 omap_barriers_init();
319 #ifdef CONFIG_SOC_OMAP5
320 void __init omap5_map_io(void)
322 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
326 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
328 * Sets the CORE DPLL3 M2 divider to the same value that it's at
329 * currently. This has the effect of setting the SDRC SDRAM AC timing
330 * registers to the values currently defined by the kernel. Currently
331 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
332 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
333 * or passes along the return value of clk_set_rate().
335 static int __init _omap2_init_reprogram_sdrc(void)
337 struct clk *dpll3_m2_ck;
341 if (!cpu_is_omap34xx())
344 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
345 if (IS_ERR(dpll3_m2_ck))
348 rate = clk_get_rate(dpll3_m2_ck);
349 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
350 v = clk_set_rate(dpll3_m2_ck, rate);
352 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
354 clk_put(dpll3_m2_ck);
359 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
361 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
364 static void __init omap_common_init_early(void)
366 omap_init_consistent_dma_size();
369 static void __init omap_hwmod_init_postsetup(void)
373 /* Set the default postsetup state for all hwmods */
374 #ifdef CONFIG_PM_RUNTIME
375 postsetup_state = _HWMOD_STATE_IDLE;
377 postsetup_state = _HWMOD_STATE_ENABLED;
379 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
381 omap_pm_if_early_init();
384 #ifdef CONFIG_SOC_OMAP2420
385 void __init omap2420_init_early(void)
387 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
388 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
389 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
390 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
392 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
393 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
394 omap2xxx_check_revision();
396 omap_common_init_early();
397 omap2xxx_voltagedomains_init();
398 omap242x_powerdomains_init();
399 omap242x_clockdomains_init();
400 omap2420_hwmod_init();
401 omap_hwmod_init_postsetup();
405 void __init omap2420_init_late(void)
407 omap_mux_late_init();
408 omap2_common_pm_late_init();
413 #ifdef CONFIG_SOC_OMAP2430
414 void __init omap2430_init_early(void)
416 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
417 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
418 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
419 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
421 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
422 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
423 omap2xxx_check_revision();
425 omap_common_init_early();
426 omap2xxx_voltagedomains_init();
427 omap243x_powerdomains_init();
428 omap243x_clockdomains_init();
429 omap2430_hwmod_init();
430 omap_hwmod_init_postsetup();
434 void __init omap2430_init_late(void)
436 omap_mux_late_init();
437 omap2_common_pm_late_init();
443 * Currently only board-omap3beagle.c should call this because of the
444 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
446 #ifdef CONFIG_ARCH_OMAP3
447 void __init omap3_init_early(void)
449 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
450 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
451 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
452 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
454 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
455 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
456 omap3xxx_check_revision();
457 omap3xxx_check_features();
459 omap_common_init_early();
460 omap3xxx_voltagedomains_init();
461 omap3xxx_powerdomains_init();
462 omap3xxx_clockdomains_init();
463 omap3xxx_hwmod_init();
464 omap_hwmod_init_postsetup();
468 void __init omap3430_init_early(void)
473 void __init omap35xx_init_early(void)
478 void __init omap3630_init_early(void)
483 void __init am35xx_init_early(void)
488 void __init ti81xx_init_early(void)
490 omap2_set_globals_tap(OMAP343X_CLASS,
491 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
492 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
494 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
495 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
496 omap3xxx_check_revision();
497 ti81xx_check_features();
498 omap_common_init_early();
499 omap3xxx_voltagedomains_init();
500 omap3xxx_powerdomains_init();
501 omap3xxx_clockdomains_init();
502 omap3xxx_hwmod_init();
503 omap_hwmod_init_postsetup();
507 void __init omap3_init_late(void)
509 omap_mux_late_init();
510 omap2_common_pm_late_init();
514 void __init omap3430_init_late(void)
516 omap_mux_late_init();
517 omap2_common_pm_late_init();
521 void __init omap35xx_init_late(void)
523 omap_mux_late_init();
524 omap2_common_pm_late_init();
528 void __init omap3630_init_late(void)
530 omap_mux_late_init();
531 omap2_common_pm_late_init();
535 void __init am35xx_init_late(void)
537 omap_mux_late_init();
538 omap2_common_pm_late_init();
542 void __init ti81xx_init_late(void)
544 omap_mux_late_init();
545 omap2_common_pm_late_init();
550 #ifdef CONFIG_SOC_AM33XX
551 void __init am33xx_init_early(void)
553 omap2_set_globals_tap(AM335X_CLASS,
554 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
555 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
557 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
558 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
559 omap3xxx_check_revision();
560 ti81xx_check_features();
561 omap_common_init_early();
562 am33xx_voltagedomains_init();
563 am33xx_powerdomains_init();
564 am33xx_clockdomains_init();
566 omap_hwmod_init_postsetup();
571 #ifdef CONFIG_ARCH_OMAP4
572 void __init omap4430_init_early(void)
574 omap2_set_globals_tap(OMAP443X_CLASS,
575 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
576 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
577 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
578 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
579 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
580 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
581 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
582 omap_prm_base_init();
584 omap4xxx_check_revision();
585 omap4xxx_check_features();
586 omap_common_init_early();
587 omap44xx_voltagedomains_init();
588 omap44xx_powerdomains_init();
589 omap44xx_clockdomains_init();
590 omap44xx_hwmod_init();
591 omap_hwmod_init_postsetup();
595 void __init omap4430_init_late(void)
597 omap_mux_late_init();
598 omap2_common_pm_late_init();
603 #ifdef CONFIG_SOC_OMAP5
604 void __init omap5_init_early(void)
606 omap2_set_globals_tap(OMAP54XX_CLASS,
607 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
608 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
609 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
610 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
611 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
612 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
614 omap_prm_base_init();
616 omap5xxx_check_revision();
617 omap_common_init_early();
621 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
622 struct omap_sdrc_params *sdrc_cs1)
626 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
627 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
628 _omap2_init_reprogram_sdrc();