2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/module.h>
14 #include <linux/gfp.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-contiguous.h>
21 #include <linux/highmem.h>
22 #include <linux/memblock.h>
23 #include <linux/slab.h>
25 #include <asm/memory.h>
26 #include <asm/highmem.h>
27 #include <asm/cacheflush.h>
28 #include <asm/tlbflush.h>
29 #include <asm/sizes.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/system_info.h>
33 #include <asm/dma-contiguous.h>
37 static u64 get_coherent_dma_mask(struct device *dev)
39 u64 mask = (u64)arm_dma_limit;
42 mask = dev->coherent_dma_mask;
45 * Sanity check the DMA mask - it must be non-zero, and
46 * must be able to be satisfied by a DMA allocation.
49 dev_warn(dev, "coherent DMA mask is unset\n");
53 if ((~mask) & (u64)arm_dma_limit) {
54 dev_warn(dev, "coherent DMA mask %#llx is smaller "
55 "than system GFP_DMA mask %#llx\n",
56 mask, (u64)arm_dma_limit);
64 static void __dma_clear_buffer(struct page *page, size_t size)
68 * Ensure that the allocated pages are zeroed, and that any data
69 * lurking in the kernel direct-mapped region is invalidated.
71 ptr = page_address(page);
73 dmac_flush_range(ptr, ptr + size);
74 outer_flush_range(__pa(ptr), __pa(ptr) + size);
78 * Allocate a DMA buffer for 'dev' of size 'size' using the
79 * specified gfp mask. Note that 'size' must be page aligned.
81 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
83 unsigned long order = get_order(size);
84 struct page *page, *p, *e;
86 page = alloc_pages(gfp, order);
91 * Now split the huge page and free the excess pages
93 split_page(page, order);
94 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
97 __dma_clear_buffer(page, size);
103 * Free a DMA buffer. 'size' must be page aligned.
105 static void __dma_free_buffer(struct page *page, size_t size)
107 struct page *e = page + (size >> PAGE_SHIFT);
117 #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
118 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
121 * These are the page tables (2MB each) covering uncached, DMA consistent allocations
123 static pte_t **consistent_pte;
125 #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
127 unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
129 void __init init_consistent_dma_size(unsigned long size)
131 unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
133 BUG_ON(consistent_pte); /* Check we're called before DMA region init */
134 BUG_ON(base < VMALLOC_END);
136 /* Grow region to accommodate specified size */
137 if (base < consistent_base)
138 consistent_base = base;
141 #include "vmregion.h"
143 static struct arm_vmregion_head consistent_head = {
144 .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
145 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
146 .vm_end = CONSISTENT_END,
149 #ifdef CONFIG_HUGETLB_PAGE
150 #error ARM Coherent DMA allocator does not (yet) support huge TLB
154 * Initialise the consistent memory allocation.
156 static int __init consistent_init(void)
164 unsigned long base = consistent_base;
165 unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
167 if (cpu_architecture() >= CPU_ARCH_ARMv6)
170 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
171 if (!consistent_pte) {
172 pr_err("%s: no memory\n", __func__);
176 pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
177 consistent_head.vm_start = base;
180 pgd = pgd_offset(&init_mm, base);
182 pud = pud_alloc(&init_mm, pgd, base);
184 printk(KERN_ERR "%s: no pud tables\n", __func__);
189 pmd = pmd_alloc(&init_mm, pud, base);
191 printk(KERN_ERR "%s: no pmd tables\n", __func__);
195 WARN_ON(!pmd_none(*pmd));
197 pte = pte_alloc_kernel(pmd, base);
199 printk(KERN_ERR "%s: no pte tables\n", __func__);
204 consistent_pte[i++] = pte;
206 } while (base < CONSISTENT_END);
210 core_initcall(consistent_init);
212 static void *__alloc_from_contiguous(struct device *dev, size_t size,
213 pgprot_t prot, struct page **ret_page);
215 static struct arm_vmregion_head coherent_head = {
216 .vm_lock = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock),
217 .vm_list = LIST_HEAD_INIT(coherent_head.vm_list),
220 size_t coherent_pool_size = DEFAULT_CONSISTENT_DMA_SIZE / 8;
222 static int __init early_coherent_pool(char *p)
224 coherent_pool_size = memparse(p, &p);
227 early_param("coherent_pool", early_coherent_pool);
230 * Initialise the coherent pool for atomic allocations.
232 static int __init coherent_init(void)
234 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
235 size_t size = coherent_pool_size;
239 if (cpu_architecture() < CPU_ARCH_ARMv6)
242 ptr = __alloc_from_contiguous(NULL, size, prot, &page);
244 coherent_head.vm_start = (unsigned long) ptr;
245 coherent_head.vm_end = (unsigned long) ptr + size;
246 printk(KERN_INFO "DMA: preallocated %u KiB pool for atomic coherent allocations\n",
247 (unsigned)size / 1024);
250 printk(KERN_ERR "DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
251 (unsigned)size / 1024);
255 * CMA is activated by core_initcall, so we must be called after it.
257 postcore_initcall(coherent_init);
259 struct dma_contig_early_reserve {
264 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
266 static int dma_mmu_remap_num __initdata;
268 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
270 dma_mmu_remap[dma_mmu_remap_num].base = base;
271 dma_mmu_remap[dma_mmu_remap_num].size = size;
275 void __init dma_contiguous_remap(void)
278 for (i = 0; i < dma_mmu_remap_num; i++) {
279 phys_addr_t start = dma_mmu_remap[i].base;
280 phys_addr_t end = start + dma_mmu_remap[i].size;
284 if (end > arm_lowmem_limit)
285 end = arm_lowmem_limit;
289 map.pfn = __phys_to_pfn(start);
290 map.virtual = __phys_to_virt(start);
291 map.length = end - start;
292 map.type = MT_MEMORY_DMA_READY;
295 * Clear previous low-memory mapping
297 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
299 pmd_clear(pmd_off_k(addr));
301 iotable_init(&map, 1);
306 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
309 struct arm_vmregion *c;
313 if (!consistent_pte) {
314 printk(KERN_ERR "%s: not initialised\n", __func__);
320 * Align the virtual region allocation - maximum alignment is
321 * a section size, minimum is a page size. This helps reduce
322 * fragmentation of the DMA space, and also prevents allocations
323 * smaller than a section from crossing a section boundary.
326 if (bit > SECTION_SHIFT)
331 * Allocate a virtual address in the consistent mapping region.
333 c = arm_vmregion_alloc(&consistent_head, align, size,
334 gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller);
337 int idx = CONSISTENT_PTE_INDEX(c->vm_start);
338 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
340 pte = consistent_pte[idx] + off;
344 BUG_ON(!pte_none(*pte));
346 set_pte_ext(pte, mk_pte(page, prot), 0);
350 if (off >= PTRS_PER_PTE) {
352 pte = consistent_pte[++idx];
354 } while (size -= PAGE_SIZE);
358 return (void *)c->vm_start;
363 static void __dma_free_remap(void *cpu_addr, size_t size)
365 struct arm_vmregion *c;
371 c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr);
373 printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n",
379 if ((c->vm_end - c->vm_start) != size) {
380 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
381 __func__, c->vm_end - c->vm_start, size);
383 size = c->vm_end - c->vm_start;
386 idx = CONSISTENT_PTE_INDEX(c->vm_start);
387 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
388 ptep = consistent_pte[idx] + off;
391 pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
396 if (off >= PTRS_PER_PTE) {
398 ptep = consistent_pte[++idx];
401 if (pte_none(pte) || !pte_present(pte))
402 printk(KERN_CRIT "%s: bad page in kernel page table\n",
404 } while (size -= PAGE_SIZE);
406 flush_tlb_kernel_range(c->vm_start, c->vm_end);
408 arm_vmregion_free(&consistent_head, c);
411 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
414 struct page *page = virt_to_page(addr);
415 pgprot_t prot = *(pgprot_t *)data;
417 set_pte_ext(pte, mk_pte(page, prot), 0);
421 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
423 unsigned long start = (unsigned long) page_address(page);
424 unsigned end = start + size;
426 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
428 flush_tlb_kernel_range(start, end);
431 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
432 pgprot_t prot, struct page **ret_page,
437 page = __dma_alloc_buffer(dev, size, gfp);
441 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
443 __dma_free_buffer(page, size);
451 static void *__alloc_from_pool(struct device *dev, size_t size,
452 struct page **ret_page, const void *caller)
454 struct arm_vmregion *c;
457 if (!coherent_head.vm_start) {
458 printk(KERN_ERR "%s: coherent pool not initialised!\n",
465 * Align the region allocation - allocations from pool are rather
466 * small, so align them to their order in pages, minimum is a page
467 * size. This helps reduce fragmentation of the DMA space.
469 align = PAGE_SIZE << get_order(size);
470 c = arm_vmregion_alloc(&coherent_head, align, size, 0, caller);
472 void *ptr = (void *)c->vm_start;
473 struct page *page = virt_to_page(ptr);
480 static int __free_from_pool(void *cpu_addr, size_t size)
482 unsigned long start = (unsigned long)cpu_addr;
483 unsigned long end = start + size;
484 struct arm_vmregion *c;
486 if (start < coherent_head.vm_start || end > coherent_head.vm_end)
489 c = arm_vmregion_find_remove(&coherent_head, (unsigned long)start);
491 if ((c->vm_end - c->vm_start) != size) {
492 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
493 __func__, c->vm_end - c->vm_start, size);
495 size = c->vm_end - c->vm_start;
498 arm_vmregion_free(&coherent_head, c);
502 static void *__alloc_from_contiguous(struct device *dev, size_t size,
503 pgprot_t prot, struct page **ret_page)
505 unsigned long order = get_order(size);
506 size_t count = size >> PAGE_SHIFT;
509 page = dma_alloc_from_contiguous(dev, count, order);
513 __dma_clear_buffer(page, size);
514 __dma_remap(page, size, prot);
517 return page_address(page);
520 static void __free_from_contiguous(struct device *dev, struct page *page,
523 __dma_remap(page, size, pgprot_kernel);
524 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
529 #else /* !CONFIG_MMU */
533 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
534 #define __alloc_from_pool(dev, size, ret_page, c) NULL
535 #define __alloc_from_contiguous(dev, size, prot, ret) NULL
536 #define __free_from_pool(cpu_addr, size) 0
537 #define __free_from_contiguous(dev, page, size) do { } while (0)
538 #define __dma_free_remap(cpu_addr, size) do { } while (0)
540 #endif /* CONFIG_MMU */
542 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
543 struct page **ret_page)
546 page = __dma_alloc_buffer(dev, size, gfp);
551 return page_address(page);
556 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
557 gfp_t gfp, pgprot_t prot, const void *caller)
559 u64 mask = get_coherent_dma_mask(dev);
563 #ifdef CONFIG_DMA_API_DEBUG
564 u64 limit = (mask + 1) & ~mask;
565 if (limit && size >= limit) {
566 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
575 if (mask < 0xffffffffULL)
579 * Following is a work-around (a.k.a. hack) to prevent pages
580 * with __GFP_COMP being passed to split_page() which cannot
581 * handle them. The real problem is that this flag probably
582 * should be 0 on ARM as it is not supported on this
583 * platform; see CONFIG_HUGETLBFS.
585 gfp &= ~(__GFP_COMP);
588 size = PAGE_ALIGN(size);
590 if (arch_is_coherent() || nommu())
591 addr = __alloc_simple_buffer(dev, size, gfp, &page);
592 else if (cpu_architecture() < CPU_ARCH_ARMv6)
593 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
594 else if (gfp & GFP_ATOMIC)
595 addr = __alloc_from_pool(dev, size, &page, caller);
597 addr = __alloc_from_contiguous(dev, size, prot, &page);
600 *handle = pfn_to_dma(dev, page_to_pfn(page));
606 * Allocate DMA-coherent memory space and return both the kernel remapped
607 * virtual and bus address for that space.
609 void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle,
614 if (dma_alloc_from_coherent(dev, size, handle, &memory))
617 return __dma_alloc(dev, size, handle, gfp,
618 pgprot_dmacoherent(pgprot_kernel),
619 __builtin_return_address(0));
621 EXPORT_SYMBOL(dma_alloc_coherent);
624 * Allocate a writecombining region, in much the same way as
625 * dma_alloc_coherent above.
628 dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
630 return __dma_alloc(dev, size, handle, gfp,
631 pgprot_writecombine(pgprot_kernel),
632 __builtin_return_address(0));
634 EXPORT_SYMBOL(dma_alloc_writecombine);
636 static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
637 void *cpu_addr, dma_addr_t dma_addr, size_t size)
641 unsigned long pfn = dma_to_pfn(dev, dma_addr);
642 ret = remap_pfn_range(vma, vma->vm_start,
644 vma->vm_end - vma->vm_start,
646 #endif /* CONFIG_MMU */
651 int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
652 void *cpu_addr, dma_addr_t dma_addr, size_t size)
654 vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot);
655 return dma_mmap(dev, vma, cpu_addr, dma_addr, size);
657 EXPORT_SYMBOL(dma_mmap_coherent);
659 int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
660 void *cpu_addr, dma_addr_t dma_addr, size_t size)
662 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
663 return dma_mmap(dev, vma, cpu_addr, dma_addr, size);
665 EXPORT_SYMBOL(dma_mmap_writecombine);
669 * Free a buffer as defined by the above mapping.
671 void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
673 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
675 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
678 size = PAGE_ALIGN(size);
680 if (arch_is_coherent() || nommu()) {
681 __dma_free_buffer(page, size);
682 } else if (cpu_architecture() < CPU_ARCH_ARMv6) {
683 __dma_free_remap(cpu_addr, size);
684 __dma_free_buffer(page, size);
686 if (__free_from_pool(cpu_addr, size))
689 * Non-atomic allocations cannot be freed with IRQs disabled
691 WARN_ON(irqs_disabled());
692 __free_from_contiguous(dev, page, size);
695 EXPORT_SYMBOL(dma_free_coherent);
698 * Make an area consistent for devices.
699 * Note: Drivers should NOT use this function directly, as it will break
700 * platforms with CONFIG_DMABOUNCE.
701 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
703 void ___dma_single_cpu_to_dev(const void *kaddr, size_t size,
704 enum dma_data_direction dir)
708 BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
710 dmac_map_area(kaddr, size, dir);
713 if (dir == DMA_FROM_DEVICE) {
714 outer_inv_range(paddr, paddr + size);
716 outer_clean_range(paddr, paddr + size);
718 /* FIXME: non-speculating: flush on bidirectional mappings? */
720 EXPORT_SYMBOL(___dma_single_cpu_to_dev);
722 void ___dma_single_dev_to_cpu(const void *kaddr, size_t size,
723 enum dma_data_direction dir)
725 BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
727 /* FIXME: non-speculating: not required */
728 /* don't bother invalidating if DMA to device */
729 if (dir != DMA_TO_DEVICE) {
730 unsigned long paddr = __pa(kaddr);
731 outer_inv_range(paddr, paddr + size);
734 dmac_unmap_area(kaddr, size, dir);
736 EXPORT_SYMBOL(___dma_single_dev_to_cpu);
738 static void dma_cache_maint_page(struct page *page, unsigned long offset,
739 size_t size, enum dma_data_direction dir,
740 void (*op)(const void *, size_t, int))
743 * A single sg entry may refer to multiple physically contiguous
744 * pages. But we still need to process highmem pages individually.
745 * If highmem is not configured then the bulk of this loop gets
753 if (PageHighMem(page)) {
754 if (len + offset > PAGE_SIZE) {
755 if (offset >= PAGE_SIZE) {
756 page += offset / PAGE_SIZE;
759 len = PAGE_SIZE - offset;
761 vaddr = kmap_high_get(page);
766 } else if (cache_is_vipt()) {
767 /* unmapped pages might still be cached */
768 vaddr = kmap_atomic(page);
769 op(vaddr + offset, len, dir);
770 kunmap_atomic(vaddr);
773 vaddr = page_address(page) + offset;
782 void ___dma_page_cpu_to_dev(struct page *page, unsigned long off,
783 size_t size, enum dma_data_direction dir)
787 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
789 paddr = page_to_phys(page) + off;
790 if (dir == DMA_FROM_DEVICE) {
791 outer_inv_range(paddr, paddr + size);
793 outer_clean_range(paddr, paddr + size);
795 /* FIXME: non-speculating: flush on bidirectional mappings? */
797 EXPORT_SYMBOL(___dma_page_cpu_to_dev);
799 void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
800 size_t size, enum dma_data_direction dir)
802 unsigned long paddr = page_to_phys(page) + off;
804 /* FIXME: non-speculating: not required */
805 /* don't bother invalidating if DMA to device */
806 if (dir != DMA_TO_DEVICE)
807 outer_inv_range(paddr, paddr + size);
809 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
812 * Mark the D-cache clean for this page to avoid extra flushing.
814 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
815 set_bit(PG_dcache_clean, &page->flags);
817 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
820 * dma_map_sg - map a set of SG buffers for streaming mode DMA
821 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
822 * @sg: list of buffers
823 * @nents: number of buffers to map
824 * @dir: DMA transfer direction
826 * Map a set of buffers described by scatterlist in streaming mode for DMA.
827 * This is the scatter-gather version of the dma_map_single interface.
828 * Here the scatter gather list elements are each tagged with the
829 * appropriate dma address and length. They are obtained via
830 * sg_dma_{address,length}.
832 * Device ownership issues as mentioned for dma_map_single are the same
835 int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
836 enum dma_data_direction dir)
838 struct scatterlist *s;
841 BUG_ON(!valid_dma_direction(dir));
843 for_each_sg(sg, s, nents, i) {
844 s->dma_address = __dma_map_page(dev, sg_page(s), s->offset,
846 if (dma_mapping_error(dev, s->dma_address))
849 debug_dma_map_sg(dev, sg, nents, nents, dir);
853 for_each_sg(sg, s, i, j)
854 __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
857 EXPORT_SYMBOL(dma_map_sg);
860 * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
861 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
862 * @sg: list of buffers
863 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
864 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
866 * Unmap a set of streaming mode DMA translations. Again, CPU access
867 * rules concerning calls here are the same as for dma_unmap_single().
869 void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
870 enum dma_data_direction dir)
872 struct scatterlist *s;
875 debug_dma_unmap_sg(dev, sg, nents, dir);
877 for_each_sg(sg, s, nents, i)
878 __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
880 EXPORT_SYMBOL(dma_unmap_sg);
883 * dma_sync_sg_for_cpu
884 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
885 * @sg: list of buffers
886 * @nents: number of buffers to map (returned from dma_map_sg)
887 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
889 void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
890 int nents, enum dma_data_direction dir)
892 struct scatterlist *s;
895 for_each_sg(sg, s, nents, i) {
896 if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
900 __dma_page_dev_to_cpu(sg_page(s), s->offset,
904 debug_dma_sync_sg_for_cpu(dev, sg, nents, dir);
906 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
909 * dma_sync_sg_for_device
910 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
911 * @sg: list of buffers
912 * @nents: number of buffers to map (returned from dma_map_sg)
913 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
915 void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
916 int nents, enum dma_data_direction dir)
918 struct scatterlist *s;
921 for_each_sg(sg, s, nents, i) {
922 if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0,
926 __dma_page_cpu_to_dev(sg_page(s), s->offset,
930 debug_dma_sync_sg_for_device(dev, sg, nents, dir);
932 EXPORT_SYMBOL(dma_sync_sg_for_device);
935 * Return whether the given device DMA address mask can be supported
936 * properly. For example, if your device can only drive the low 24-bits
937 * during bus mastering, then you would pass 0x00ffffff as the mask
940 int dma_supported(struct device *dev, u64 mask)
942 if (mask < (u64)arm_dma_limit)
946 EXPORT_SYMBOL(dma_supported);
948 int dma_set_mask(struct device *dev, u64 dma_mask)
950 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
953 #ifndef CONFIG_DMABOUNCE
954 *dev->dma_mask = dma_mask;
959 EXPORT_SYMBOL(dma_set_mask);
961 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
963 static int __init dma_debug_do_init(void)
966 arm_vmregion_create_proc("dma-mappings", &consistent_head);
968 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
971 fs_initcall(dma_debug_do_init);