2 * arch/arm/mach-tegra/fuse.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@android.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
22 #include <linux/export.h>
28 #define FUSE_UID_LOW 0x108
29 #define FUSE_UID_HIGH 0x10c
30 #define FUSE_SKU_INFO 0x110
32 #define TEGRA20_FUSE_SPARE_BIT 0x200
35 int tegra_cpu_process_id;
36 int tegra_core_process_id;
38 enum tegra_revision tegra_revision;
40 static int tegra_fuse_spare_bit;
42 /* The BCT to use at boot is specified by board straps that can be read
43 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
45 int tegra_bct_strapping;
47 #define STRAP_OPT 0x008
48 #define GMI_AD0 (1 << 4)
49 #define GMI_AD1 (1 << 5)
50 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
51 #define RAM_CODE_SHIFT 4
53 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
54 [TEGRA_REVISION_UNKNOWN] = "unknown",
55 [TEGRA_REVISION_A01] = "A01",
56 [TEGRA_REVISION_A02] = "A02",
57 [TEGRA_REVISION_A03] = "A03",
58 [TEGRA_REVISION_A03p] = "A03 prime",
59 [TEGRA_REVISION_A04] = "A04",
62 u32 tegra_fuse_readl(unsigned long offset)
64 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
67 bool tegra_spare_fuse(int bit)
69 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
72 static enum tegra_revision tegra_get_revision(u32 id)
74 u32 minor_rev = (id >> 16) & 0xf;
78 return TEGRA_REVISION_A01;
80 return TEGRA_REVISION_A02;
82 if (tegra_chip_id == TEGRA20 &&
83 (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
84 return TEGRA_REVISION_A03p;
86 return TEGRA_REVISION_A03;
88 return TEGRA_REVISION_A04;
90 return TEGRA_REVISION_UNKNOWN;
94 void tegra_init_fuse(void)
98 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
100 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
102 reg = tegra_fuse_readl(FUSE_SKU_INFO);
103 tegra_sku_id = reg & 0xFF;
105 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
107 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
108 tegra_cpu_process_id = (reg >> 6) & 3;
110 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
111 tegra_core_process_id = (reg >> 12) & 3;
113 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
114 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
116 id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
117 tegra_chip_id = (id >> 8) & 0xff;
119 tegra_revision = tegra_get_revision(id);
121 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
122 tegra_revision_name[tegra_revision],
123 tegra_sku_id, tegra_cpu_process_id,
124 tegra_core_process_id);
127 unsigned long long tegra_chip_uid(void)
129 unsigned long long lo, hi;
131 lo = tegra_fuse_readl(FUSE_UID_LOW);
132 hi = tegra_fuse_readl(FUSE_UID_HIGH);
133 return (hi << 32ull) | lo;
135 EXPORT_SYMBOL(tegra_chip_uid);