drivers/staging/tidspbridge/core/tiomap3430.c

   1 /*
   2  * tiomap.c
   3  *
   4  * DSP-BIOS Bridge driver support functions for TI OMAP processors.
   5  *
   6  * Processor Manager Driver for TI OMAP3430 EVM.
   7  *
   8  * Copyright (C) 2005-2006 Texas Instruments, Inc.
   9  *
  10  * This package is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  16  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  17  */
  18
  19 #include <linux/platform_data/dsp-omap.h>
  20
  21 #include <linux/types.h>
  22 /*  ----------------------------------- Host OS */
  23 #include <dspbridge/host_os.h>
  24 #include <linux/mm.h>
  25 #include <linux/mmzone.h>
  26
  27 /*  ----------------------------------- DSP/BIOS Bridge */
  28 #include <dspbridge/dbdefs.h>
  29
  30 /*  ----------------------------------- OS Adaptation Layer */
  31 #include <dspbridge/drv.h>
  32 #include <dspbridge/sync.h>
  33
  34 /* ------------------------------------ Hardware Abstraction Layer */
  35 #include <hw_defs.h>
  36 #include <hw_mmu.h>
  37
  38 /*  ----------------------------------- Link Driver */
  39 #include <dspbridge/dspdefs.h>
  40 #include <dspbridge/dspchnl.h>
  41 #include <dspbridge/dspdeh.h>
  42 #include <dspbridge/dspio.h>
  43 #include <dspbridge/dspmsg.h>
  44 #include <dspbridge/pwr.h>
  45 #include <dspbridge/io_sm.h>
  46
  47 /*  ----------------------------------- Platform Manager */
  48 #include <dspbridge/dev.h>
  49 #include <dspbridge/dspapi.h>
  50 #include <dspbridge/dmm.h>
  51 #include <dspbridge/wdt.h>
  52
  53 /*  ----------------------------------- Local */
  54 #include "_tiomap.h"
  55 #include "_tiomap_pwr.h"
  56 #include "tiomap_io.h"
  57
  58 /* Offset in shared mem to write to in order to synchronize start with DSP */
  59 #define SHMSYNCOFFSET 4         /* GPP byte offset */
  60
  61 #define BUFFERSIZE 1024
  62
  63 #define TIHELEN_ACKTIMEOUT  10000
  64
  65 #define MMU_SECTION_ADDR_MASK    0xFFF00000
  66 #define MMU_SSECTION_ADDR_MASK   0xFF000000
  67 #define MMU_LARGE_PAGE_MASK      0xFFFF0000
  68 #define MMU_SMALL_PAGE_MASK      0xFFFFF000
  69 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
  70 #define PAGES_II_LVL_TABLE   512
  71 #define PHYS_TO_PAGE(phys)      pfn_to_page((phys) >> PAGE_SHIFT)
  72
  73 /*
  74  * This is a totally ugly layer violation, but needed until
  75  * omap_ctrl_set_dsp_boot*() are provided.
  76  */
  77 #define OMAP3_IVA2_BOOTMOD_IDLE 1
  78 #define OMAP2_CONTROL_GENERAL 0x270
  79 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
  80 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
  81
  82 /* Forward Declarations: */
  83 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
  84 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
  85                                   u8 *host_buff,
  86                                   u32 dsp_addr, u32 ul_num_bytes,
  87                                   u32 mem_type);
  88 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
  89                                    u32 dsp_addr);
  90 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
  91                                     int *board_state);
  92 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
  93 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
  94                                    u8 *host_buff,
  95                                    u32 dsp_addr, u32 ul_num_bytes,
  96                                    u32 mem_type);
  97 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
  98                                     u32 brd_state);
  99 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
 100                                    u32 dsp_dest_addr, u32 dsp_src_addr,
 101                                    u32 ul_num_bytes, u32 mem_type);
 102 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
 103                                     u8 *host_buff, u32 dsp_addr,
 104                                     u32 ul_num_bytes, u32 mem_type);
 105 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
 106                                   u32 ul_mpu_addr, u32 virt_addr,
 107                                   u32 ul_num_bytes, u32 ul_map_attr,
 108                                   struct page **mapped_pages);
 109 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
 110                                      u32 virt_addr, u32 ul_num_bytes);
 111 static int bridge_dev_create(struct bridge_dev_context
 112                                         **dev_cntxt,
 113                                         struct dev_object *hdev_obj,
 114                                         struct cfg_hostres *config_param);
 115 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 116                                   u32 dw_cmd, void *pargs);
 117 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
 118 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
 119 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
 120                              u32 va, u32 size,
 121                              struct hw_mmu_map_attrs_t *map_attrs);
 122 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
 123                           u32 size, struct hw_mmu_map_attrs_t *attrs);
 124 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
 125                                   u32 ul_mpu_addr, u32 virt_addr,
 126                                   u32 ul_num_bytes,
 127                                   struct hw_mmu_map_attrs_t *hw_attrs);
 128
 129 bool wait_for_start(struct bridge_dev_context *dev_context,
 130                         void __iomem *sync_addr);
 131
 132 /*  ----------------------------------- Globals */
 133
 134 /* Attributes of L2 page tables for DSP MMU */
 135 struct page_info {
 136         u32 num_entries;        /* Number of valid PTEs in the L2 PT */
 137 };
 138
 139 /* Attributes used to manage the DSP MMU page tables */
 140 struct pg_table_attrs {
 141         spinlock_t pg_lock;     /* Critical section object handle */
 142
 143         u32 l1_base_pa;         /* Physical address of the L1 PT */
 144         u32 l1_base_va;         /* Virtual  address of the L1 PT */
 145         u32 l1_size;            /* Size of the L1 PT */
 146         u32 l1_tbl_alloc_pa;
 147         /* Physical address of Allocated mem for L1 table. May not be aligned */
 148         u32 l1_tbl_alloc_va;
 149         /* Virtual address of Allocated mem for L1 table. May not be aligned */
 150         u32 l1_tbl_alloc_sz;
 151         /* Size of consistent memory allocated for L1 table.
 152          * May not be aligned */
 153
 154         u32 l2_base_pa;         /* Physical address of the L2 PT */
 155         u32 l2_base_va;         /* Virtual  address of the L2 PT */
 156         u32 l2_size;            /* Size of the L2 PT */
 157         u32 l2_tbl_alloc_pa;
 158         /* Physical address of Allocated mem for L2 table. May not be aligned */
 159         u32 l2_tbl_alloc_va;
 160         /* Virtual address of Allocated mem for L2 table. May not be aligned */
 161         u32 l2_tbl_alloc_sz;
 162         /* Size of consistent memory allocated for L2 table.
 163          * May not be aligned */
 164
 165         u32 l2_num_pages;       /* Number of allocated L2 PT */
 166         /* Array [l2_num_pages] of L2 PT info structs */
 167         struct page_info *pg_info;
 168 };
 169
 170 /*
 171  *  This Bridge driver's function interface table.
 172  */
 173 static struct bridge_drv_interface drv_interface_fxns = {
 174         /* Bridge API ver. for which this bridge driver is built. */
 175         BRD_API_MAJOR_VERSION,
 176         BRD_API_MINOR_VERSION,
 177         bridge_dev_create,
 178         bridge_dev_destroy,
 179         bridge_dev_ctrl,
 180         bridge_brd_monitor,
 181         bridge_brd_start,
 182         bridge_brd_stop,
 183         bridge_brd_status,
 184         bridge_brd_read,
 185         bridge_brd_write,
 186         bridge_brd_set_state,
 187         bridge_brd_mem_copy,
 188         bridge_brd_mem_write,
 189         bridge_brd_mem_map,
 190         bridge_brd_mem_un_map,
 191         /* The following CHNL functions are provided by chnl_io.lib: */
 192         bridge_chnl_create,
 193         bridge_chnl_destroy,
 194         bridge_chnl_open,
 195         bridge_chnl_close,
 196         bridge_chnl_add_io_req,
 197         bridge_chnl_get_ioc,
 198         bridge_chnl_cancel_io,
 199         bridge_chnl_flush_io,
 200         bridge_chnl_get_info,
 201         bridge_chnl_get_mgr_info,
 202         bridge_chnl_idle,
 203         bridge_chnl_register_notify,
 204         /* The following IO functions are provided by chnl_io.lib: */
 205         bridge_io_create,
 206         bridge_io_destroy,
 207         bridge_io_on_loaded,
 208         bridge_io_get_proc_load,
 209         /* The following msg_ctrl functions are provided by chnl_io.lib: */
 210         bridge_msg_create,
 211         bridge_msg_create_queue,
 212         bridge_msg_delete,
 213         bridge_msg_delete_queue,
 214         bridge_msg_get,
 215         bridge_msg_put,
 216         bridge_msg_register_notify,
 217         bridge_msg_set_queue_id,
 218 };
 219
 220 static struct notifier_block dsp_mbox_notifier = {
 221         .notifier_call = io_mbox_msg,
 222 };
 223
 224 static inline void flush_all(struct bridge_dev_context *dev_context)
 225 {
 226         if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
 227             dev_context->brd_state == BRD_HIBERNATION)
 228                 wake_dsp(dev_context, NULL);
 229
 230         hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
 231 }
 232
 233 static void bad_page_dump(u32 pa, struct page *pg)
 234 {
 235         pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
 236         pr_emerg("Bad page state in process '%s'\n"
 237                  "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
 238                  "Backtrace:\n",
 239                  current->comm, pg, (int)(2 * sizeof(unsigned long)),
 240                  (unsigned long)pg->flags, pg->mapping,
 241                  page_mapcount(pg), page_count(pg));
 242         dump_stack();
 243 }
 244
 245 /*
 246  *  ======== bridge_drv_entry ========
 247  *  purpose:
 248  *      Bridge Driver entry point.
 249  */
 250 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
 251                    const char *driver_file_name)
 252 {
 253         if (strcmp(driver_file_name, "UMA") == 0)
 254                 *drv_intf = &drv_interface_fxns;
 255         else
 256                 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
 257
 258 }
 259
 260 /*
 261  *  ======== bridge_brd_monitor ========
 262  *  purpose:
 263  *      This bridge_brd_monitor puts DSP into a Loadable state.
 264  *      i.e Application can load and start the device.
 265  *
 266  *  Preconditions:
 267  *      Device in 'OFF' state.
 268  */
 269 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
 270 {
 271         struct bridge_dev_context *dev_context = dev_ctxt;
 272         u32 temp;
 273         struct omap_dsp_platform_data *pdata =
 274                 omap_dspbridge_dev->dev.platform_data;
 275
 276         temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 277                                         OMAP_POWERSTATEST_MASK;
 278         if (!(temp & 0x02)) {
 279                 /* IVA2 is not in ON state */
 280                 /* Read and set PM_PWSTCTRL_IVA2  to ON */
 281                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 282                         PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 283                 /* Set the SW supervised state transition */
 284                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
 285                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 286
 287                 /* Wait until the state has moved to ON */
 288                 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 289                                                 OMAP_INTRANSITION_MASK)
 290                         ;
 291                 /* Disable Automatic transition */
 292                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
 293                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 294         }
 295         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 296                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 297         dsp_clk_enable(DSP_CLK_IVA2);
 298
 299         /* set the device state to IDLE */
 300         dev_context->brd_state = BRD_IDLE;
 301
 302         return 0;
 303 }
 304
 305 /*
 306  *  ======== bridge_brd_read ========
 307  *  purpose:
 308  *      Reads buffers for DSP memory.
 309  */
 310 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
 311                                   u8 *host_buff, u32 dsp_addr,
 312                                   u32 ul_num_bytes, u32 mem_type)
 313 {
 314         int status = 0;
 315         struct bridge_dev_context *dev_context = dev_ctxt;
 316         u32 offset;
 317         u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
 318
 319         if (dsp_addr < dev_context->dsp_start_add) {
 320                 status = -EPERM;
 321                 return status;
 322         }
 323         /* change here to account for the 3 bands of the DSP internal memory */
 324         if ((dsp_addr - dev_context->dsp_start_add) <
 325             dev_context->internal_size) {
 326                 offset = dsp_addr - dev_context->dsp_start_add;
 327         } else {
 328                 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
 329                                            ul_num_bytes, mem_type);
 330                 return status;
 331         }
 332         /* copy the data from DSP memory */
 333         memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
 334         return status;
 335 }
 336
 337 /*
 338  *  ======== bridge_brd_set_state ========
 339  *  purpose:
 340  *      This routine updates the Board status.
 341  */
 342 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
 343                                     u32 brd_state)
 344 {
 345         int status = 0;
 346         struct bridge_dev_context *dev_context = dev_ctxt;
 347
 348         dev_context->brd_state = brd_state;
 349         return status;
 350 }
 351
 352 /*
 353  *  ======== bridge_brd_start ========
 354  *  purpose:
 355  *      Initializes DSP MMU and Starts DSP.
 356  *
 357  *  Preconditions:
 358  *  a) DSP domain is 'ACTIVE'.
 359  *  b) DSP_RST1 is asserted.
 360  *  b) DSP_RST2 is released.
 361  */
 362 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
 363                                    u32 dsp_addr)
 364 {
 365         int status = 0;
 366         struct bridge_dev_context *dev_context = dev_ctxt;
 367         void __iomem *sync_addr;
 368         u32 ul_shm_base;        /* Gpp Phys SM base addr(byte) */
 369         u32 ul_shm_base_virt;   /* Dsp Virt SM base addr */
 370         u32 ul_tlb_base_virt;   /* Base of MMU TLB entry */
 371         u32 shm_sync_pa;
 372         /* Offset of shm_base_virt from tlb_base_virt */
 373         u32 ul_shm_offset_virt;
 374         s32 entry_ndx;
 375         s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
 376         struct cfg_hostres *resources = NULL;
 377         u32 temp;
 378         u32 ul_dsp_clk_rate;
 379         u32 ul_dsp_clk_addr;
 380         u32 ul_bios_gp_timer;
 381         u32 clk_cmd;
 382         struct io_mgr *hio_mgr;
 383         u32 ul_load_monitor_timer;
 384         u32 wdt_en = 0;
 385         struct omap_dsp_platform_data *pdata =
 386                 omap_dspbridge_dev->dev.platform_data;
 387
 388         /* The device context contains all the mmu setup info from when the
 389          * last dsp base image was loaded. The first entry is always
 390          * SHMMEM base. */
 391         /* Get SHM_BEG - convert to byte address */
 392         (void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
 393                              &ul_shm_base_virt);
 394         ul_shm_base_virt *= DSPWORDSIZE;
 395         /* DSP Virtual address */
 396         ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
 397         ul_shm_offset_virt =
 398             ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
 399         /* Kernel logical address */
 400         ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
 401
 402         /* SHM physical sync address */
 403         shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
 404                         SHMSYNCOFFSET;
 405
 406         /* 2nd wd is used as sync field */
 407         sync_addr = ioremap(shm_sync_pa, SZ_32);
 408         if (!sync_addr)
 409                 return -ENOMEM;
 410
 411         /* Write a signature into the shm base + offset; this will
 412          * get cleared when the DSP program starts. */
 413         if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
 414                 pr_err("%s: Illegal SM base\n", __func__);
 415                 status = -EPERM;
 416         } else
 417                 __raw_writel(0xffffffff, sync_addr);
 418
 419         if (!status) {
 420                 resources = dev_context->resources;
 421                 if (!resources)
 422                         status = -EPERM;
 423
 424                 /* Assert RST1 i.e only the RST only for DSP megacell */
 425                 if (!status) {
 426                         /*
 427                          * XXX: OMAP343X_CTRL_BASE ioremapping  MUST be removed once ctrl
 428                          * function is made available.
 429                          */
 430                         void __iomem *ctrl = ioremap(0x48002000, SZ_4K);
 431                         if (!ctrl) {
 432                                 iounmap(sync_addr);
 433                                 return -ENOMEM;
 434                         }
 435
 436                         (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
 437                                         OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
 438                                         OMAP2_RM_RSTCTRL);
 439                         /* Mask address with 1K for compatibility */
 440                         __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
 441                                         ctrl + OMAP343X_CONTROL_IVA2_BOOTADDR);
 442                         /*
 443                          * Set bootmode to self loop if dsp_debug flag is true
 444                          */
 445                         __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
 446                                         ctrl + OMAP343X_CONTROL_IVA2_BOOTMOD);
 447
 448                         iounmap(ctrl);
 449                 }
 450         }
 451         if (!status) {
 452                 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
 453                  * IVA2 SYSC register */
 454                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
 455                         OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 456                 udelay(100);
 457                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 458                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 459                 udelay(100);
 460
 461                 /* Disbale the DSP MMU */
 462                 hw_mmu_disable(resources->dmmu_base);
 463                 /* Disable TWL */
 464                 hw_mmu_twl_disable(resources->dmmu_base);
 465
 466                 /* Only make TLB entry if both addresses are non-zero */
 467                 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
 468                      entry_ndx++) {
 469                         struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
 470                         struct hw_mmu_map_attrs_t map_attrs = {
 471                                 .endianism = e->endianism,
 472                                 .element_size = e->elem_size,
 473                                 .mixed_size = e->mixed_mode,
 474                         };
 475
 476                         if (!e->gpp_pa || !e->dsp_va)
 477                                 continue;
 478
 479                         dev_dbg(bridge,
 480                                         "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
 481                                         itmp_entry_ndx,
 482                                         e->gpp_pa,
 483                                         e->dsp_va,
 484                                         e->size);
 485
 486                         hw_mmu_tlb_add(dev_context->dsp_mmu_base,
 487                                         e->gpp_pa,
 488                                         e->dsp_va,
 489                                         e->size,
 490                                         itmp_entry_ndx,
 491                                         &map_attrs, 1, 1);
 492
 493                         itmp_entry_ndx++;
 494                 }
 495         }
 496
 497         /* Lock the above TLB entries and get the BIOS and load monitor timer
 498          * information */
 499         if (!status) {
 500                 hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
 501                 hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
 502                 hw_mmu_ttb_set(resources->dmmu_base,
 503                                dev_context->pt_attrs->l1_base_pa);
 504                 hw_mmu_twl_enable(resources->dmmu_base);
 505                 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
 506
 507                 temp = __raw_readl((resources->dmmu_base) + 0x10);
 508                 temp = (temp & 0xFFFFFFEF) | 0x11;
 509                 __raw_writel(temp, (resources->dmmu_base) + 0x10);
 510
 511                 /* Let the DSP MMU run */
 512                 hw_mmu_enable(resources->dmmu_base);
 513
 514                 /* Enable the BIOS clock */
 515                 (void)dev_get_symbol(dev_context->dev_obj,
 516                                      BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
 517                 (void)dev_get_symbol(dev_context->dev_obj,
 518                                      BRIDGEINIT_LOADMON_GPTIMER,
 519                                      &ul_load_monitor_timer);
 520         }
 521
 522         if (!status) {
 523                 if (ul_load_monitor_timer != 0xFFFF) {
 524                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 525                             ul_load_monitor_timer;
 526                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 527                 } else {
 528                         dev_dbg(bridge, "Not able to get the symbol for Load "
 529                                 "Monitor Timer\n");
 530                 }
 531         }
 532
 533         if (!status) {
 534                 if (ul_bios_gp_timer != 0xFFFF) {
 535                         clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 536                             ul_bios_gp_timer;
 537                         dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
 538                 } else {
 539                         dev_dbg(bridge,
 540                                 "Not able to get the symbol for BIOS Timer\n");
 541                 }
 542         }
 543
 544         if (!status) {
 545                 /* Set the DSP clock rate */
 546                 (void)dev_get_symbol(dev_context->dev_obj,
 547                                      "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
 548                 /*Set Autoidle Mode for IVA2 PLL */
 549                 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 550                                 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 551
 552                 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 553                         /* Get the clock rate */
 554                         ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
 555                         dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 556                                 __func__, ul_dsp_clk_rate);
 557                         (void)bridge_brd_write(dev_context,
 558                                                (u8 *) &ul_dsp_clk_rate,
 559                                                ul_dsp_clk_addr, sizeof(u32), 0);
 560                 }
 561                 /*
 562                  * Enable Mailbox events and also drain any pending
 563                  * stale messages.
 564                  */
 565                 dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
 566                 if (IS_ERR(dev_context->mbox)) {
 567                         dev_context->mbox = NULL;
 568                         pr_err("%s: Failed to get dsp mailbox handle\n",
 569                                                                 __func__);
 570                         status = -EPERM;
 571                 }
 572
 573         }
 574         if (!status) {
 575 /*PM_IVA2GRPSEL_PER = 0xC0;*/
 576                 temp = readl(resources->per_pm_base + 0xA8);
 577                 temp = (temp & 0xFFFFFF30) | 0xC0;
 578                 writel(temp, resources->per_pm_base + 0xA8);
 579
 580 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
 581                 temp = readl(resources->per_pm_base + 0xA4);
 582                 temp = (temp & 0xFFFFFF3F);
 583                 writel(temp, resources->per_pm_base + 0xA4);
 584 /*CM_SLEEPDEP_PER |= 0x04; */
 585                 temp = readl(resources->per_base + 0x44);
 586                 temp = (temp & 0xFFFFFFFB) | 0x04;
 587                 writel(temp, resources->per_base + 0x44);
 588
 589 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
 590                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
 591                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 592
 593                 /* Let DSP go */
 594                 dev_dbg(bridge, "%s Unreset\n", __func__);
 595                 /* Enable DSP MMU Interrupts */
 596                 hw_mmu_event_enable(resources->dmmu_base,
 597                                     HW_MMU_ALL_INTERRUPTS);
 598                 /* release the RST1, DSP starts executing now .. */
 599                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
 600                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 601
 602                 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
 603                 dev_dbg(bridge, "DSP c_int00 Address =  0x%x\n", dsp_addr);
 604                 if (dsp_debug)
 605                         while (__raw_readw(sync_addr))
 606                                 ;
 607
 608                 /* Wait for DSP to clear word in shared memory */
 609                 /* Read the Location */
 610                 if (!wait_for_start(dev_context, sync_addr))
 611                         status = -ETIMEDOUT;
 612
 613                 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
 614                 if (wdt_en) {
 615                         /* Start wdt */
 616                         dsp_wdt_sm_set((void *)ul_shm_base);
 617                         dsp_wdt_enable(true);
 618                 }
 619
 620                 status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
 621                 if (hio_mgr) {
 622                         io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
 623                         /* Write the synchronization bit to indicate the
 624                          * completion of OPP table update to DSP
 625                          */
 626                         __raw_writel(0XCAFECAFE, sync_addr);
 627
 628                         /* update board state */
 629                         dev_context->brd_state = BRD_RUNNING;
 630                         /* (void)chnlsm_enable_interrupt(dev_context); */
 631                 } else {
 632                         dev_context->brd_state = BRD_UNKNOWN;
 633                 }
 634         }
 635
 636         iounmap(sync_addr);
 637
 638         return status;
 639 }
 640
 641 /*
 642  *  ======== bridge_brd_stop ========
 643  *  purpose:
 644  *      Puts DSP in self loop.
 645  *
 646  *  Preconditions :
 647  *  a) None
 648  */
 649 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
 650 {
 651         int status = 0;
 652         struct bridge_dev_context *dev_context = dev_ctxt;
 653         struct pg_table_attrs *pt_attrs;
 654         u32 dsp_pwr_state;
 655         struct omap_dsp_platform_data *pdata =
 656                 omap_dspbridge_dev->dev.platform_data;
 657
 658         if (dev_context->brd_state == BRD_STOPPED)
 659                 return status;
 660
 661         /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
 662          * before turning off the clocks.. This is to ensure that there are no
 663          * pending L3 or other transactons from IVA2 */
 664         dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
 665                                         OMAP_POWERSTATEST_MASK;
 666         if (dsp_pwr_state != PWRDM_POWER_OFF) {
 667                 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
 668                                         OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 669                 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 670                 mdelay(10);
 671
 672                 /* IVA2 is not in OFF state */
 673                 /* Set PM_PWSTCTRL_IVA2  to OFF */
 674                 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
 675                         PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
 676                 /* Set the SW supervised state transition for Sleep */
 677                 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 678                                         OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 679         }
 680         udelay(10);
 681         /* Release the Ext Base virtual Address as the next DSP Program
 682          * may have a different load address */
 683         if (dev_context->dsp_ext_base_addr)
 684                 dev_context->dsp_ext_base_addr = 0;
 685
 686         dev_context->brd_state = BRD_STOPPED;   /* update board state */
 687
 688         dsp_wdt_enable(false);
 689
 690         /* This is a good place to clear the MMU page tables as well */
 691         if (dev_context->pt_attrs) {
 692                 pt_attrs = dev_context->pt_attrs;
 693                 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
 694                 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
 695                 memset((u8 *) pt_attrs->pg_info, 0x00,
 696                        (pt_attrs->l2_num_pages * sizeof(struct page_info)));
 697         }
 698         /* Disable the mailbox interrupts */
 699         if (dev_context->mbox) {
 700                 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
 701                 omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
 702                 dev_context->mbox = NULL;
 703         }
 704         /* Reset IVA2 clocks*/
 705         (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
 706                         OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 707
 708         dsp_clock_disable_all(dev_context->dsp_per_clks);
 709         dsp_clk_disable(DSP_CLK_IVA2);
 710
 711         return status;
 712 }
 713
 714 /*
 715  *  ======== bridge_brd_status ========
 716  *      Returns the board status.
 717  */
 718 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
 719                                     int *board_state)
 720 {
 721         struct bridge_dev_context *dev_context = dev_ctxt;
 722         *board_state = dev_context->brd_state;
 723         return 0;
 724 }
 725
 726 /*
 727  *  ======== bridge_brd_write ========
 728  *      Copies the buffers to DSP internal or external memory.
 729  */
 730 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
 731                                    u8 *host_buff, u32 dsp_addr,
 732                                    u32 ul_num_bytes, u32 mem_type)
 733 {
 734         int status = 0;
 735         struct bridge_dev_context *dev_context = dev_ctxt;
 736
 737         if (dsp_addr < dev_context->dsp_start_add) {
 738                 status = -EPERM;
 739                 return status;
 740         }
 741         if ((dsp_addr - dev_context->dsp_start_add) <
 742             dev_context->internal_size) {
 743                 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
 744                                         ul_num_bytes, mem_type);
 745         } else {
 746                 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
 747                                             ul_num_bytes, mem_type, false);
 748         }
 749
 750         return status;
 751 }
 752
 753 /*
 754  *  ======== bridge_dev_create ========
 755  *      Creates a driver object. Puts DSP in self loop.
 756  */
 757 static int bridge_dev_create(struct bridge_dev_context
 758                                         **dev_cntxt,
 759                                         struct dev_object *hdev_obj,
 760                                         struct cfg_hostres *config_param)
 761 {
 762         int status = 0;
 763         struct bridge_dev_context *dev_context = NULL;
 764         s32 entry_ndx;
 765         struct cfg_hostres *resources = config_param;
 766         struct pg_table_attrs *pt_attrs;
 767         u32 pg_tbl_pa;
 768         u32 pg_tbl_va;
 769         u32 align_size;
 770         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 771
 772         /* Allocate and initialize a data structure to contain the bridge driver
 773          *  state, which becomes the context for later calls into this driver */
 774         dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
 775         if (!dev_context) {
 776                 status = -ENOMEM;
 777                 goto func_end;
 778         }
 779
 780         dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
 781         dev_context->self_loop = (u32) NULL;
 782         dev_context->dsp_per_clks = 0;
 783         dev_context->internal_size = OMAP_DSP_SIZE;
 784         /*  Clear dev context MMU table entries.
 785          *  These get set on bridge_io_on_loaded() call after program loaded. */
 786         for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
 787                 dev_context->atlb_entry[entry_ndx].gpp_pa =
 788                     dev_context->atlb_entry[entry_ndx].dsp_va = 0;
 789         }
 790         dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
 791                                                                  (config_param->
 792                                                                   mem_base
 793                                                                   [3]),
 794                                                                  config_param->
 795                                                                  mem_length
 796                                                                  [3]);
 797         if (!dev_context->dsp_base_addr)
 798                 status = -EPERM;
 799
 800         pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
 801         if (pt_attrs != NULL) {
 802                 pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
 803                 align_size = pt_attrs->l1_size;
 804                 /* Align sizes are expected to be power of 2 */
 805                 /* we like to get aligned on L1 table size */
 806                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
 807                                                      align_size, &pg_tbl_pa);
 808
 809                 /* Check if the PA is aligned for us */
 810                 if ((pg_tbl_pa) & (align_size - 1)) {
 811                         /* PA not aligned to page table size ,
 812                          * try with more allocation and align */
 813                         mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
 814                                           pt_attrs->l1_size);
 815                         /* we like to get aligned on L1 table size */
 816                         pg_tbl_va =
 817                             (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
 818                                                      align_size, &pg_tbl_pa);
 819                         /* We should be able to get aligned table now */
 820                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 821                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 822                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
 823                         /* Align the PA to the next 'align'  boundary */
 824                         pt_attrs->l1_base_pa =
 825                             ((pg_tbl_pa) +
 826                              (align_size - 1)) & (~(align_size - 1));
 827                         pt_attrs->l1_base_va =
 828                             pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
 829                 } else {
 830                         /* We got aligned PA, cool */
 831                         pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
 832                         pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
 833                         pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
 834                         pt_attrs->l1_base_pa = pg_tbl_pa;
 835                         pt_attrs->l1_base_va = pg_tbl_va;
 836                 }
 837                 if (pt_attrs->l1_base_va)
 838                         memset((u8 *) pt_attrs->l1_base_va, 0x00,
 839                                pt_attrs->l1_size);
 840
 841                 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
 842                  * L4 pages */
 843                 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
 844                 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
 845                     pt_attrs->l2_num_pages;
 846                 align_size = 4; /* Make it u32 aligned */
 847                 /* we like to get aligned on L1 table size */
 848                 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
 849                                                      align_size, &pg_tbl_pa);
 850                 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
 851                 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
 852                 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
 853                 pt_attrs->l2_base_pa = pg_tbl_pa;
 854                 pt_attrs->l2_base_va = pg_tbl_va;
 855
 856                 if (pt_attrs->l2_base_va)
 857                         memset((u8 *) pt_attrs->l2_base_va, 0x00,
 858                                pt_attrs->l2_size);
 859
 860                 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
 861                                         sizeof(struct page_info), GFP_KERNEL);
 862                 dev_dbg(bridge,
 863                         "L1 pa %x, va %x, size %x\n L2 pa %x, va "
 864                         "%x, size %x\n", pt_attrs->l1_base_pa,
 865                         pt_attrs->l1_base_va, pt_attrs->l1_size,
 866                         pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
 867                         pt_attrs->l2_size);
 868                 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
 869                         pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
 870         }
 871         if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
 872             (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
 873                 dev_context->pt_attrs = pt_attrs;
 874         else
 875                 status = -ENOMEM;
 876
 877         if (!status) {
 878                 spin_lock_init(&pt_attrs->pg_lock);
 879                 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
 880
 881                 /* Set the Clock Divisor for the DSP module */
 882                 udelay(5);
 883                 /* MMU address is obtained from the host
 884                  * resources struct */
 885                 dev_context->dsp_mmu_base = resources->dmmu_base;
 886         }
 887         if (!status) {
 888                 dev_context->dev_obj = hdev_obj;
 889                 /* Store current board state. */
 890                 dev_context->brd_state = BRD_UNKNOWN;
 891                 dev_context->resources = resources;
 892                 dsp_clk_enable(DSP_CLK_IVA2);
 893                 bridge_brd_stop(dev_context);
 894                 /* Return ptr to our device state to the DSP API for storage */
 895                 *dev_cntxt = dev_context;
 896         } else {
 897                 if (pt_attrs != NULL) {
 898                         kfree(pt_attrs->pg_info);
 899
 900                         if (pt_attrs->l2_tbl_alloc_va) {
 901                                 mem_free_phys_mem((void *)
 902                                                   pt_attrs->l2_tbl_alloc_va,
 903                                                   pt_attrs->l2_tbl_alloc_pa,
 904                                                   pt_attrs->l2_tbl_alloc_sz);
 905                         }
 906                         if (pt_attrs->l1_tbl_alloc_va) {
 907                                 mem_free_phys_mem((void *)
 908                                                   pt_attrs->l1_tbl_alloc_va,
 909                                                   pt_attrs->l1_tbl_alloc_pa,
 910                                                   pt_attrs->l1_tbl_alloc_sz);
 911                         }
 912                 }
 913                 kfree(pt_attrs);
 914                 kfree(dev_context);
 915         }
 916 func_end:
 917         return status;
 918 }
 919
 920 /*
 921  *  ======== bridge_dev_ctrl ========
 922  *      Receives device specific commands.
 923  */
 924 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
 925                                   u32 dw_cmd, void *pargs)
 926 {
 927         int status = 0;
 928         struct bridge_ioctl_extproc *pa_ext_proc =
 929                                         (struct bridge_ioctl_extproc *)pargs;
 930         s32 ndx;
 931
 932         switch (dw_cmd) {
 933         case BRDIOCTL_CHNLREAD:
 934                 break;
 935         case BRDIOCTL_CHNLWRITE:
 936                 break;
 937         case BRDIOCTL_SETMMUCONFIG:
 938                 /* store away dsp-mmu setup values for later use */
 939                 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
 940                         dev_context->atlb_entry[ndx] = *pa_ext_proc;
 941                 break;
 942         case BRDIOCTL_DEEPSLEEP:
 943         case BRDIOCTL_EMERGENCYSLEEP:
 944                 /* Currently only DSP Idle is supported Need to update for
 945                  * later releases */
 946                 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
 947                 break;
 948         case BRDIOCTL_WAKEUP:
 949                 status = wake_dsp(dev_context, pargs);
 950                 break;
 951         case BRDIOCTL_CLK_CTRL:
 952                 status = 0;
 953                 /* Looking For Baseport Fix for Clocks */
 954                 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
 955                 break;
 956         case BRDIOCTL_PWR_HIBERNATE:
 957                 status = handle_hibernation_from_dsp(dev_context);
 958                 break;
 959         case BRDIOCTL_PRESCALE_NOTIFY:
 960                 status = pre_scale_dsp(dev_context, pargs);
 961                 break;
 962         case BRDIOCTL_POSTSCALE_NOTIFY:
 963                 status = post_scale_dsp(dev_context, pargs);
 964                 break;
 965         case BRDIOCTL_CONSTRAINT_REQUEST:
 966                 status = handle_constraints_set(dev_context, pargs);
 967                 break;
 968         default:
 969                 status = -EPERM;
 970                 break;
 971         }
 972         return status;
 973 }
 974
 975 /*
 976  *  ======== bridge_dev_destroy ========
 977  *      Destroys the driver object.
 978  */
 979 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
 980 {
 981         struct pg_table_attrs *pt_attrs;
 982         int status = 0;
 983         struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
 984             dev_ctxt;
 985         struct cfg_hostres *host_res;
 986         u32 shm_size;
 987         struct drv_data *drv_datap = dev_get_drvdata(bridge);
 988
 989         /* It should never happen */
 990         if (!dev_ctxt)
 991                 return -EFAULT;
 992
 993         /* first put the device to stop state */
 994         bridge_brd_stop(dev_context);
 995         if (dev_context->pt_attrs) {
 996                 pt_attrs = dev_context->pt_attrs;
 997                 kfree(pt_attrs->pg_info);
 998
 999                 if (pt_attrs->l2_tbl_alloc_va) {
1000                         mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
1001                                           pt_attrs->l2_tbl_alloc_pa,
1002                                           pt_attrs->l2_tbl_alloc_sz);
1003                 }
1004                 if (pt_attrs->l1_tbl_alloc_va) {
1005                         mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
1006                                           pt_attrs->l1_tbl_alloc_pa,
1007                                           pt_attrs->l1_tbl_alloc_sz);
1008                 }
1009                 kfree(pt_attrs);
1010
1011         }
1012
1013         if (dev_context->resources) {
1014                 host_res = dev_context->resources;
1015                 shm_size = drv_datap->shm_size;
1016                 if (shm_size >= 0x10000) {
1017                         if ((host_res->mem_base[1]) &&
1018                             (host_res->mem_phys[1])) {
1019                                 mem_free_phys_mem((void *)
1020                                                   host_res->mem_base
1021                                                   [1],
1022                                                   host_res->mem_phys
1023                                                   [1], shm_size);
1024                         }
1025                 } else {
1026                         dev_dbg(bridge, "%s: Error getting shm size "
1027                                 "from registry: %x. Not calling "
1028                                 "mem_free_phys_mem\n", __func__,
1029                                 status);
1030                 }
1031                 host_res->mem_base[1] = 0;
1032                 host_res->mem_phys[1] = 0;
1033
1034                 if (host_res->mem_base[0])
1035                         iounmap((void *)host_res->mem_base[0]);
1036                 if (host_res->mem_base[2])
1037                         iounmap((void *)host_res->mem_base[2]);
1038                 if (host_res->mem_base[3])
1039                         iounmap((void *)host_res->mem_base[3]);
1040                 if (host_res->mem_base[4])
1041                         iounmap((void *)host_res->mem_base[4]);
1042                 if (host_res->dmmu_base)
1043                         iounmap(host_res->dmmu_base);
1044                 if (host_res->per_base)
1045                         iounmap(host_res->per_base);
1046                 if (host_res->per_pm_base)
1047                         iounmap((void *)host_res->per_pm_base);
1048                 if (host_res->core_pm_base)
1049                         iounmap((void *)host_res->core_pm_base);
1050
1051                 host_res->mem_base[0] = (u32) NULL;
1052                 host_res->mem_base[2] = (u32) NULL;
1053                 host_res->mem_base[3] = (u32) NULL;
1054                 host_res->mem_base[4] = (u32) NULL;
1055                 host_res->dmmu_base = NULL;
1056
1057                 kfree(host_res);
1058         }
1059
1060         /* Free the driver's device context: */
1061         kfree(drv_datap->base_img);
1062         kfree((void *)dev_ctxt);
1063         return status;
1064 }
1065
1066 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1067                                    u32 dsp_dest_addr, u32 dsp_src_addr,
1068                                    u32 ul_num_bytes, u32 mem_type)
1069 {
1070         int status = 0;
1071         u32 src_addr = dsp_src_addr;
1072         u32 dest_addr = dsp_dest_addr;
1073         u32 copy_bytes = 0;
1074         u32 total_bytes = ul_num_bytes;
1075         u8 host_buf[BUFFERSIZE];
1076         struct bridge_dev_context *dev_context = dev_ctxt;
1077         while (total_bytes > 0 && !status) {
1078                 copy_bytes =
1079                     total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1080                 /* Read from External memory */
1081                 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1082                                            copy_bytes, mem_type);
1083                 if (!status) {
1084                         if (dest_addr < (dev_context->dsp_start_add +
1085                                          dev_context->internal_size)) {
1086                                 /* Write to Internal memory */
1087                                 status = write_dsp_data(dev_ctxt, host_buf,
1088                                                         dest_addr, copy_bytes,
1089                                                         mem_type);
1090                         } else {
1091                                 /* Write to External memory */
1092                                 status =
1093                                     write_ext_dsp_data(dev_ctxt, host_buf,
1094                                                        dest_addr, copy_bytes,
1095                                                        mem_type, false);
1096                         }
1097                 }
1098                 total_bytes -= copy_bytes;
1099                 src_addr += copy_bytes;
1100                 dest_addr += copy_bytes;
1101         }
1102         return status;
1103 }
1104
1105 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1106 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1107                                     u8 *host_buff, u32 dsp_addr,
1108                                     u32 ul_num_bytes, u32 mem_type)
1109 {
1110         int status = 0;
1111         struct bridge_dev_context *dev_context = dev_ctxt;
1112         u32 ul_remain_bytes = 0;
1113         u32 ul_bytes = 0;
1114         ul_remain_bytes = ul_num_bytes;
1115         while (ul_remain_bytes > 0 && !status) {
1116                 ul_bytes =
1117                     ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1118                 if (dsp_addr < (dev_context->dsp_start_add +
1119                                  dev_context->internal_size)) {
1120                         status =
1121                             write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1122                                            ul_bytes, mem_type);
1123                 } else {
1124                         status = write_ext_dsp_data(dev_ctxt, host_buff,
1125                                                     dsp_addr, ul_bytes,
1126                                                     mem_type, true);
1127                 }
1128                 ul_remain_bytes -= ul_bytes;
1129                 dsp_addr += ul_bytes;
1130                 host_buff = host_buff + ul_bytes;
1131         }
1132         return status;
1133 }
1134
1135 /*
1136  *  ======== bridge_brd_mem_map ========
1137  *      This function maps MPU buffer to the DSP address space. It performs
1138  *  linear to physical address translation if required. It translates each
1139  *  page since linear addresses can be physically non-contiguous
1140  *  All address & size arguments are assumed to be page aligned (in proc.c)
1141  *
1142  *  TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1143  */
1144 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1145                                   u32 ul_mpu_addr, u32 virt_addr,
1146                                   u32 ul_num_bytes, u32 ul_map_attr,
1147                                   struct page **mapped_pages)
1148 {
1149         u32 attrs;
1150         int status = 0;
1151         struct bridge_dev_context *dev_context = dev_ctxt;
1152         struct hw_mmu_map_attrs_t hw_attrs;
1153         struct vm_area_struct *vma;
1154         struct mm_struct *mm = current->mm;
1155         u32 write = 0;
1156         u32 num_usr_pgs = 0;
1157         struct page *mapped_page, *pg;
1158         s32 pg_num;
1159         u32 va = virt_addr;
1160         struct task_struct *curr_task = current;
1161         u32 pg_i = 0;
1162         u32 mpu_addr, pa;
1163
1164         dev_dbg(bridge,
1165                 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1166                 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1167                 ul_map_attr);
1168         if (ul_num_bytes == 0)
1169                 return -EINVAL;
1170
1171         if (ul_map_attr & DSP_MAP_DIR_MASK) {
1172                 attrs = ul_map_attr;
1173         } else {
1174                 /* Assign default attributes */
1175                 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1176         }
1177         /* Take mapping properties */
1178         if (attrs & DSP_MAPBIGENDIAN)
1179                 hw_attrs.endianism = HW_BIG_ENDIAN;
1180         else
1181                 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1182
1183         hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1184             ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1185         /* Ignore element_size if mixed_size is enabled */
1186         if (hw_attrs.mixed_size == 0) {
1187                 if (attrs & DSP_MAPELEMSIZE8) {
1188                         /* Size is 8 bit */
1189                         hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1190                 } else if (attrs & DSP_MAPELEMSIZE16) {
1191                         /* Size is 16 bit */
1192                         hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1193                 } else if (attrs & DSP_MAPELEMSIZE32) {
1194                         /* Size is 32 bit */
1195                         hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1196                 } else if (attrs & DSP_MAPELEMSIZE64) {
1197                         /* Size is 64 bit */
1198                         hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1199                 } else {
1200                         /*
1201                          * Mixedsize isn't enabled, so size can't be
1202                          * zero here
1203                          */
1204                         return -EINVAL;
1205                 }
1206         }
1207         if (attrs & DSP_MAPDONOTLOCK)
1208                 hw_attrs.donotlockmpupage = 1;
1209         else
1210                 hw_attrs.donotlockmpupage = 0;
1211
1212         if (attrs & DSP_MAPVMALLOCADDR) {
1213                 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1214                                        ul_num_bytes, &hw_attrs);
1215         }
1216         /*
1217          * Do OS-specific user-va to pa translation.
1218          * Combine physically contiguous regions to reduce TLBs.
1219          * Pass the translated pa to pte_update.
1220          */
1221         if ((attrs & DSP_MAPPHYSICALADDR)) {
1222                 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1223                                     ul_num_bytes, &hw_attrs);
1224                 goto func_cont;
1225         }
1226
1227         /*
1228          * Important Note: ul_mpu_addr is mapped from user application process
1229          * to current process - it must lie completely within the current
1230          * virtual memory address space in order to be of use to us here!
1231          */
1232         down_read(&mm->mmap_sem);
1233         vma = find_vma(mm, ul_mpu_addr);
1234         if (vma)
1235                 dev_dbg(bridge,
1236                         "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1237                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1238                         ul_num_bytes, vma->vm_start, vma->vm_end,
1239                         vma->vm_flags);
1240
1241         /*
1242          * It is observed that under some circumstances, the user buffer is
1243          * spread across several VMAs. So loop through and check if the entire
1244          * user buffer is covered
1245          */
1246         while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1247                 /* jump to the next VMA region */
1248                 vma = find_vma(mm, vma->vm_end + 1);
1249                 dev_dbg(bridge,
1250                         "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1251                         "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1252                         ul_num_bytes, vma->vm_start, vma->vm_end,
1253                         vma->vm_flags);
1254         }
1255         if (!vma) {
1256                 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1257                        __func__, ul_mpu_addr, ul_num_bytes);
1258                 status = -EINVAL;
1259                 up_read(&mm->mmap_sem);
1260                 goto func_cont;
1261         }
1262
1263         if (vma->vm_flags & VM_IO) {
1264                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1265                 mpu_addr = ul_mpu_addr;
1266
1267                 /* Get the physical addresses for user buffer */
1268                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1269                         pa = user_va2_pa(mm, mpu_addr);
1270                         if (!pa) {
1271                                 status = -EPERM;
1272                                 pr_err("DSPBRIDGE: VM_IO mapping physical"
1273                                        "address is invalid\n");
1274                                 break;
1275                         }
1276                         if (pfn_valid(__phys_to_pfn(pa))) {
1277                                 pg = PHYS_TO_PAGE(pa);
1278                                 get_page(pg);
1279                                 if (page_count(pg) < 1) {
1280                                         pr_err("Bad page in VM_IO buffer\n");
1281                                         bad_page_dump(pa, pg);
1282                                 }
1283                         }
1284                         status = pte_set(dev_context->pt_attrs, pa,
1285                                          va, HW_PAGE_SIZE4KB, &hw_attrs);
1286                         if (status)
1287                                 break;
1288
1289                         va += HW_PAGE_SIZE4KB;
1290                         mpu_addr += HW_PAGE_SIZE4KB;
1291                         pa += HW_PAGE_SIZE4KB;
1292                 }
1293         } else {
1294                 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1295                 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1296                         write = 1;
1297
1298                 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1299                         pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1300                                                 write, 1, &mapped_page, NULL);
1301                         if (pg_num > 0) {
1302                                 if (page_count(mapped_page) < 1) {
1303                                         pr_err("Bad page count after doing"
1304                                                "get_user_pages on"
1305                                                "user buffer\n");
1306                                         bad_page_dump(page_to_phys(mapped_page),
1307                                                       mapped_page);
1308                                 }
1309                                 status = pte_set(dev_context->pt_attrs,
1310                                                  page_to_phys(mapped_page), va,
1311                                                  HW_PAGE_SIZE4KB, &hw_attrs);
1312                                 if (status)
1313                                         break;
1314
1315                                 if (mapped_pages)
1316                                         mapped_pages[pg_i] = mapped_page;
1317
1318                                 va += HW_PAGE_SIZE4KB;
1319                                 ul_mpu_addr += HW_PAGE_SIZE4KB;
1320                         } else {
1321                                 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1322                                        "MPU addr = 0x%x,"
1323                                        "vma->vm_flags = 0x%lx,"
1324                                        "get_user_pages Err"
1325                                        "Value = %d, Buffer"
1326                                        "size=0x%x\n", ul_mpu_addr,
1327                                        vma->vm_flags, pg_num, ul_num_bytes);
1328                                 status = -EPERM;
1329                                 break;
1330                         }
1331                 }
1332         }
1333         up_read(&mm->mmap_sem);
1334 func_cont:
1335         if (status) {
1336                 /*
1337                  * Roll out the mapped pages incase it failed in middle of
1338                  * mapping
1339                  */
1340                 if (pg_i) {
1341                         bridge_brd_mem_un_map(dev_context, virt_addr,
1342                                            (pg_i * PG_SIZE4K));
1343                 }
1344                 status = -EPERM;
1345         }
1346         /*
1347          * In any case, flush the TLB
1348          * This is called from here instead from pte_update to avoid unnecessary
1349          * repetition while mapping non-contiguous physical regions of a virtual
1350          * region
1351          */
1352         flush_all(dev_context);
1353         dev_dbg(bridge, "%s status %x\n", __func__, status);
1354         return status;
1355 }
1356
1357 /*
1358  *  ======== bridge_brd_mem_un_map ========
1359  *      Invalidate the PTEs for the DSP VA block to be unmapped.
1360  *
1361  *      PTEs of a mapped memory block are contiguous in any page table
1362  *      So, instead of looking up the PTE address for every 4K block,
1363  *      we clear consecutive PTEs until we unmap all the bytes
1364  */
1365 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1366                                      u32 virt_addr, u32 ul_num_bytes)
1367 {
1368         u32 l1_base_va;
1369         u32 l2_base_va;
1370         u32 l2_base_pa;
1371         u32 l2_page_num;
1372         u32 pte_val;
1373         u32 pte_size;
1374         u32 pte_count;
1375         u32 pte_addr_l1;
1376         u32 pte_addr_l2 = 0;
1377         u32 rem_bytes;
1378         u32 rem_bytes_l2;
1379         u32 va_curr;
1380         struct page *pg = NULL;
1381         int status = 0;
1382         struct bridge_dev_context *dev_context = dev_ctxt;
1383         struct pg_table_attrs *pt = dev_context->pt_attrs;
1384         u32 temp;
1385         u32 paddr;
1386         u32 numof4k_pages = 0;
1387
1388         va_curr = virt_addr;
1389         rem_bytes = ul_num_bytes;
1390         rem_bytes_l2 = 0;
1391         l1_base_va = pt->l1_base_va;
1392         pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1393         dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1394                 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1395                 ul_num_bytes, l1_base_va, pte_addr_l1);
1396
1397         while (rem_bytes && !status) {
1398                 u32 va_curr_orig = va_curr;
1399                 /* Find whether the L1 PTE points to a valid L2 PT */
1400                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1401                 pte_val = *(u32 *) pte_addr_l1;
1402                 pte_size = hw_mmu_pte_size_l1(pte_val);
1403
1404                 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1405                         goto skip_coarse_page;
1406
1407                 /*
1408                  * Get the L2 PA from the L1 PTE, and find
1409                  * corresponding L2 VA
1410                  */
1411                 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1412                 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1413                 l2_page_num =
1414                     (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1415                 /*
1416                  * Find the L2 PTE address from which we will start
1417                  * clearing, the number of PTEs to be cleared on this
1418                  * page, and the size of VA space that needs to be
1419                  * cleared on this L2 page
1420                  */
1421                 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1422                 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1423                 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1424                 if (rem_bytes < (pte_count * PG_SIZE4K))
1425                         pte_count = rem_bytes / PG_SIZE4K;
1426                 rem_bytes_l2 = pte_count * PG_SIZE4K;
1427
1428                 /*
1429                  * Unmap the VA space on this L2 PT. A quicker way
1430                  * would be to clear pte_count entries starting from
1431                  * pte_addr_l2. However, below code checks that we don't
1432                  * clear invalid entries or less than 64KB for a 64KB
1433                  * entry. Similar checking is done for L1 PTEs too
1434                  * below
1435                  */
1436                 while (rem_bytes_l2 && !status) {
1437                         pte_val = *(u32 *) pte_addr_l2;
1438                         pte_size = hw_mmu_pte_size_l2(pte_val);
1439                         /* va_curr aligned to pte_size? */
1440                         if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1441                             va_curr & (pte_size - 1)) {
1442                                 status = -EPERM;
1443                                 break;
1444                         }
1445
1446                         /* Collect Physical addresses from VA */
1447                         paddr = (pte_val & ~(pte_size - 1));
1448                         if (pte_size == HW_PAGE_SIZE64KB)
1449                                 numof4k_pages = 16;
1450                         else
1451                                 numof4k_pages = 1;
1452                         temp = 0;
1453                         while (temp++ < numof4k_pages) {
1454                                 if (!pfn_valid(__phys_to_pfn(paddr))) {
1455                                         paddr += HW_PAGE_SIZE4KB;
1456                                         continue;
1457                                 }
1458                                 pg = PHYS_TO_PAGE(paddr);
1459                                 if (page_count(pg) < 1) {
1460                                         pr_info("DSPBRIDGE: UNMAP function: "
1461                                                 "COUNT 0 FOR PA 0x%x, size = "
1462                                                 "0x%x\n", paddr, ul_num_bytes);
1463                                         bad_page_dump(paddr, pg);
1464                                 } else {
1465                                         set_page_dirty(pg);
1466                                         page_cache_release(pg);
1467                                 }
1468                                 paddr += HW_PAGE_SIZE4KB;
1469                         }
1470                         if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1471                                 status = -EPERM;
1472                                 goto EXIT_LOOP;
1473                         }
1474
1475                         status = 0;
1476                         rem_bytes_l2 -= pte_size;
1477                         va_curr += pte_size;
1478                         pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1479                 }
1480                 spin_lock(&pt->pg_lock);
1481                 if (rem_bytes_l2 == 0) {
1482                         pt->pg_info[l2_page_num].num_entries -= pte_count;
1483                         if (pt->pg_info[l2_page_num].num_entries == 0) {
1484                                 /*
1485                                  * Clear the L1 PTE pointing to the L2 PT
1486                                  */
1487                                 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1488                                                      HW_MMU_COARSE_PAGE_SIZE))
1489                                         status = 0;
1490                                 else {
1491                                         status = -EPERM;
1492                                         spin_unlock(&pt->pg_lock);
1493                                         goto EXIT_LOOP;
1494                                 }
1495                         }
1496                         rem_bytes -= pte_count * PG_SIZE4K;
1497                 } else
1498                         status = -EPERM;
1499
1500                 spin_unlock(&pt->pg_lock);
1501                 continue;
1502 skip_coarse_page:
1503                 /* va_curr aligned to pte_size? */
1504                 /* pte_size = 1 MB or 16 MB */
1505                 if (pte_size == 0 || rem_bytes < pte_size ||
1506                     va_curr & (pte_size - 1)) {
1507                         status = -EPERM;
1508                         break;
1509                 }
1510
1511                 if (pte_size == HW_PAGE_SIZE1MB)
1512                         numof4k_pages = 256;
1513                 else
1514                         numof4k_pages = 4096;
1515                 temp = 0;
1516                 /* Collect Physical addresses from VA */
1517                 paddr = (pte_val & ~(pte_size - 1));
1518                 while (temp++ < numof4k_pages) {
1519                         if (pfn_valid(__phys_to_pfn(paddr))) {
1520                                 pg = PHYS_TO_PAGE(paddr);
1521                                 if (page_count(pg) < 1) {
1522                                         pr_info("DSPBRIDGE: UNMAP function: "
1523                                                 "COUNT 0 FOR PA 0x%x, size = "
1524                                                 "0x%x\n", paddr, ul_num_bytes);
1525                                         bad_page_dump(paddr, pg);
1526                                 } else {
1527                                         set_page_dirty(pg);
1528                                         page_cache_release(pg);
1529                                 }
1530                         }
1531                         paddr += HW_PAGE_SIZE4KB;
1532                 }
1533                 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1534                         status = 0;
1535                         rem_bytes -= pte_size;
1536                         va_curr += pte_size;
1537                 } else {
1538                         status = -EPERM;
1539                         goto EXIT_LOOP;
1540                 }
1541         }
1542         /*
1543          * It is better to flush the TLB here, so that any stale old entries
1544          * get flushed
1545          */
1546 EXIT_LOOP:
1547         flush_all(dev_context);
1548         dev_dbg(bridge,
1549                 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1550                 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1551                 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1552         return status;
1553 }
1554
1555 /*
1556  *  ======== user_va2_pa ========
1557  *  Purpose:
1558  *      This function walks through the page tables to convert a userland
1559  *      virtual address to physical address
1560  */
1561 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1562 {
1563         pgd_t *pgd;
1564         pud_t *pud;
1565         pmd_t *pmd;
1566         pte_t *ptep, pte;
1567
1568         pgd = pgd_offset(mm, address);
1569         if (pgd_none(*pgd) || pgd_bad(*pgd))
1570                 return 0;
1571
1572         pud = pud_offset(pgd, address);
1573         if (pud_none(*pud) || pud_bad(*pud))
1574                 return 0;
1575
1576         pmd = pmd_offset(pud, address);
1577         if (pmd_none(*pmd) || pmd_bad(*pmd))
1578                 return 0;
1579
1580         ptep = pte_offset_map(pmd, address);
1581         if (ptep) {
1582                 pte = *ptep;
1583                 if (pte_present(pte))
1584                         return pte & PAGE_MASK;
1585         }
1586
1587         return 0;
1588 }
1589
1590 /*
1591  *  ======== pte_update ========
1592  *      This function calculates the optimum page-aligned addresses and sizes
1593  *      Caller must pass page-aligned values
1594  */
1595 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1596                              u32 va, u32 size,
1597                              struct hw_mmu_map_attrs_t *map_attrs)
1598 {
1599         u32 i;
1600         u32 all_bits;
1601         u32 pa_curr = pa;
1602         u32 va_curr = va;
1603         u32 num_bytes = size;
1604         struct bridge_dev_context *dev_context = dev_ctxt;
1605         int status = 0;
1606         u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1607                 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1608         };
1609
1610         while (num_bytes && !status) {
1611                 /* To find the max. page size with which both PA & VA are
1612                  * aligned */
1613                 all_bits = pa_curr | va_curr;
1614
1615                 for (i = 0; i < 4; i++) {
1616                         if ((num_bytes >= page_size[i]) && ((all_bits &
1617                                                              (page_size[i] -
1618                                                               1)) == 0)) {
1619                                 status =
1620                                     pte_set(dev_context->pt_attrs, pa_curr,
1621                                             va_curr, page_size[i], map_attrs);
1622                                 pa_curr += page_size[i];
1623                                 va_curr += page_size[i];
1624                                 num_bytes -= page_size[i];
1625                                 /* Don't try smaller sizes. Hopefully we have
1626                                  * reached an address aligned to a bigger page
1627                                  * size */
1628                                 break;
1629                         }
1630                 }
1631         }
1632
1633         return status;
1634 }
1635
1636 /*
1637  *  ======== pte_set ========
1638  *      This function calculates PTE address (MPU virtual) to be updated
1639  *      It also manages the L2 page tables
1640  */
1641 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1642                           u32 size, struct hw_mmu_map_attrs_t *attrs)
1643 {
1644         u32 i;
1645         u32 pte_val;
1646         u32 pte_addr_l1;
1647         u32 pte_size;
1648         /* Base address of the PT that will be updated */
1649         u32 pg_tbl_va;
1650         u32 l1_base_va;
1651         /* Compiler warns that the next three variables might be used
1652          * uninitialized in this function. Doesn't seem so. Working around,
1653          * anyways. */
1654         u32 l2_base_va = 0;
1655         u32 l2_base_pa = 0;
1656         u32 l2_page_num = 0;
1657         int status = 0;
1658
1659         l1_base_va = pt->l1_base_va;
1660         pg_tbl_va = l1_base_va;
1661         if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1662                 /* Find whether the L1 PTE points to a valid L2 PT */
1663                 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1664                 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1665                         pte_val = *(u32 *) pte_addr_l1;
1666                         pte_size = hw_mmu_pte_size_l1(pte_val);
1667                 } else {
1668                         return -EPERM;
1669                 }
1670                 spin_lock(&pt->pg_lock);
1671                 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1672                         /* Get the L2 PA from the L1 PTE, and find
1673                          * corresponding L2 VA */
1674                         l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1675                         l2_base_va =
1676                             l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1677                         l2_page_num =
1678                             (l2_base_pa -
1679                              pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1680                 } else if (pte_size == 0) {
1681                         /* L1 PTE is invalid. Allocate a L2 PT and
1682                          * point the L1 PTE to it */
1683                         /* Find a free L2 PT. */
1684                         for (i = 0; (i < pt->l2_num_pages) &&
1685                              (pt->pg_info[i].num_entries != 0); i++)
1686                                 ;
1687                         if (i < pt->l2_num_pages) {
1688                                 l2_page_num = i;
1689                                 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1690                                                 HW_MMU_COARSE_PAGE_SIZE);
1691                                 l2_base_va = pt->l2_base_va + (l2_page_num *
1692                                                 HW_MMU_COARSE_PAGE_SIZE);
1693                                 /* Endianness attributes are ignored for
1694                                  * HW_MMU_COARSE_PAGE_SIZE */
1695                                 status =
1696                                     hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1697                                                    HW_MMU_COARSE_PAGE_SIZE,
1698                                                    attrs);
1699                         } else {
1700                                 status = -ENOMEM;
1701                         }
1702                 } else {
1703                         /* Found valid L1 PTE of another size.
1704                          * Should not overwrite it. */
1705                         status = -EPERM;
1706                 }
1707                 if (!status) {
1708                         pg_tbl_va = l2_base_va;
1709                         if (size == HW_PAGE_SIZE64KB)
1710                                 pt->pg_info[l2_page_num].num_entries += 16;
1711                         else
1712                                 pt->pg_info[l2_page_num].num_entries++;
1713                         dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1714                                 "%x, num_entries %x\n", l2_base_va,
1715                                 l2_base_pa, l2_page_num,
1716                                 pt->pg_info[l2_page_num].num_entries);
1717                 }
1718                 spin_unlock(&pt->pg_lock);
1719         }
1720         if (!status) {
1721                 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1722                         pg_tbl_va, pa, va, size);
1723                 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1724                         "mixed_size %x\n", attrs->endianism,
1725                         attrs->element_size, attrs->mixed_size);
1726                 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1727         }
1728
1729         return status;
1730 }
1731
1732 /* Memory map kernel VA -- memory allocated with vmalloc */
1733 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1734                                   u32 ul_mpu_addr, u32 virt_addr,
1735                                   u32 ul_num_bytes,
1736                                   struct hw_mmu_map_attrs_t *hw_attrs)
1737 {
1738         int status = 0;
1739         struct page *page[1];
1740         u32 i;
1741         u32 pa_curr;
1742         u32 pa_next;
1743         u32 va_curr;
1744         u32 size_curr;
1745         u32 num_pages;
1746         u32 pa;
1747         u32 num_of4k_pages;
1748         u32 temp = 0;
1749
1750         /*
1751          * Do Kernel va to pa translation.
1752          * Combine physically contiguous regions to reduce TLBs.
1753          * Pass the translated pa to pte_update.
1754          */
1755         num_pages = ul_num_bytes / PAGE_SIZE;   /* PAGE_SIZE = OS page size */
1756         i = 0;
1757         va_curr = ul_mpu_addr;
1758         page[0] = vmalloc_to_page((void *)va_curr);
1759         pa_next = page_to_phys(page[0]);
1760         while (!status && (i < num_pages)) {
1761                 /*
1762                  * Reuse pa_next from the previous iteration to avoid
1763                  * an extra va2pa call
1764                  */
1765                 pa_curr = pa_next;
1766                 size_curr = PAGE_SIZE;
1767                 /*
1768                  * If the next page is physically contiguous,
1769                  * map it with the current one by increasing
1770                  * the size of the region to be mapped
1771                  */
1772                 while (++i < num_pages) {
1773                         page[0] =
1774                             vmalloc_to_page((void *)(va_curr + size_curr));
1775                         pa_next = page_to_phys(page[0]);
1776
1777                         if (pa_next == (pa_curr + size_curr))
1778                                 size_curr += PAGE_SIZE;
1779                         else
1780                                 break;
1781
1782                 }
1783                 if (pa_next == 0) {
1784                         status = -ENOMEM;
1785                         break;
1786                 }
1787                 pa = pa_curr;
1788                 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1789                 while (temp++ < num_of4k_pages) {
1790                         get_page(PHYS_TO_PAGE(pa));
1791                         pa += HW_PAGE_SIZE4KB;
1792                 }
1793                 status = pte_update(dev_context, pa_curr, virt_addr +
1794                                     (va_curr - ul_mpu_addr), size_curr,
1795                                     hw_attrs);
1796                 va_curr += size_curr;
1797         }
1798         /*
1799          * In any case, flush the TLB
1800          * This is called from here instead from pte_update to avoid unnecessary
1801          * repetition while mapping non-contiguous physical regions of a virtual
1802          * region
1803          */
1804         flush_all(dev_context);
1805         dev_dbg(bridge, "%s status %x\n", __func__, status);
1806         return status;
1807 }
1808
1809 /*
1810  *  ======== wait_for_start ========
1811  *      Wait for the singal from DSP that it has started, or time out.
1812  */
1813 bool wait_for_start(struct bridge_dev_context *dev_context,
1814                         void __iomem *sync_addr)
1815 {
1816         u16 timeout = TIHELEN_ACKTIMEOUT;
1817
1818         /*  Wait for response from board */
1819         while (__raw_readw(sync_addr) && --timeout)
1820                 udelay(10);
1821
1822         /*  If timed out: return false */
1823         if (!timeout) {
1824                 pr_err("%s: Timed out waiting DSP to Start\n", __func__);
1825                 return false;
1826         }
1827         return true;
1828 }