arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/omap_ocp2scp.h>
  30 #include <linux/platform_data/spi-omap2-mcspi.h>
  31 #include <linux/platform_data/asoc-ti-mcbsp.h>
  32 #include <linux/platform_data/iommu-omap.h>
  33 #include <plat/dmtimer.h>
  34
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "i2c.h"
  42 #include "mmc.h"
  43 #include "wd_timer.h"
  44
  45 /* Base offset for all OMAP4 interrupts external to MPUSS */
  46 #define OMAP44XX_IRQ_GIC_START  32
  47
  48 /* Base offset for all OMAP4 dma requests */
  49 #define OMAP44XX_DMA_REQ_START  1
  50
  51 /*
  52  * IP blocks
  53  */
  54
  55 /*
  56  * 'c2c_target_fw' class
  57  * instance(s): c2c_target_fw
  58  */
  59 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  60         .name   = "c2c_target_fw",
  61 };
  62
  63 /* c2c_target_fw */
  64 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  65         .name           = "c2c_target_fw",
  66         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  67         .clkdm_name     = "d2d_clkdm",
  68         .prcm = {
  69                 .omap4 = {
  70                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  71                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  72                 },
  73         },
  74 };
  75
  76 /*
  77  * 'dmm' class
  78  * instance(s): dmm
  79  */
  80 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  81         .name   = "dmm",
  82 };
  83
  84 /* dmm */
  85 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  86         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  87         { .irq = -1 }
  88 };
  89
  90 static struct omap_hwmod omap44xx_dmm_hwmod = {
  91         .name           = "dmm",
  92         .class          = &omap44xx_dmm_hwmod_class,
  93         .clkdm_name     = "l3_emif_clkdm",
  94         .mpu_irqs       = omap44xx_dmm_irqs,
  95         .prcm = {
  96                 .omap4 = {
  97                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  98                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  99                 },
 100         },
 101 };
 102
 103 /*
 104  * 'emif_fw' class
 105  * instance(s): emif_fw
 106  */
 107 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 108         .name   = "emif_fw",
 109 };
 110
 111 /* emif_fw */
 112 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 113         .name           = "emif_fw",
 114         .class          = &omap44xx_emif_fw_hwmod_class,
 115         .clkdm_name     = "l3_emif_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 119                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /*
 125  * 'l3' class
 126  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 127  */
 128 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 129         .name   = "l3",
 130 };
 131
 132 /* l3_instr */
 133 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 134         .name           = "l3_instr",
 135         .class          = &omap44xx_l3_hwmod_class,
 136         .clkdm_name     = "l3_instr_clkdm",
 137         .prcm = {
 138                 .omap4 = {
 139                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 140                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 141                         .modulemode   = MODULEMODE_HWCTRL,
 142                 },
 143         },
 144 };
 145
 146 /* l3_main_1 */
 147 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 148         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 149         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 150         { .irq = -1 }
 151 };
 152
 153 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 154         .name           = "l3_main_1",
 155         .class          = &omap44xx_l3_hwmod_class,
 156         .clkdm_name     = "l3_1_clkdm",
 157         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 158         .prcm = {
 159                 .omap4 = {
 160                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 161                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 162                 },
 163         },
 164 };
 165
 166 /* l3_main_2 */
 167 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 168         .name           = "l3_main_2",
 169         .class          = &omap44xx_l3_hwmod_class,
 170         .clkdm_name     = "l3_2_clkdm",
 171         .prcm = {
 172                 .omap4 = {
 173                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 174                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 175                 },
 176         },
 177 };
 178
 179 /* l3_main_3 */
 180 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 181         .name           = "l3_main_3",
 182         .class          = &omap44xx_l3_hwmod_class,
 183         .clkdm_name     = "l3_instr_clkdm",
 184         .prcm = {
 185                 .omap4 = {
 186                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 187                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 188                         .modulemode   = MODULEMODE_HWCTRL,
 189                 },
 190         },
 191 };
 192
 193 /*
 194  * 'l4' class
 195  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 196  */
 197 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 198         .name   = "l4",
 199 };
 200
 201 /* l4_abe */
 202 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 203         .name           = "l4_abe",
 204         .class          = &omap44xx_l4_hwmod_class,
 205         .clkdm_name     = "abe_clkdm",
 206         .prcm = {
 207                 .omap4 = {
 208                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 209                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 210                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 211                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 212                 },
 213         },
 214 };
 215
 216 /* l4_cfg */
 217 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 218         .name           = "l4_cfg",
 219         .class          = &omap44xx_l4_hwmod_class,
 220         .clkdm_name     = "l4_cfg_clkdm",
 221         .prcm = {
 222                 .omap4 = {
 223                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 224                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 225                 },
 226         },
 227 };
 228
 229 /* l4_per */
 230 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 231         .name           = "l4_per",
 232         .class          = &omap44xx_l4_hwmod_class,
 233         .clkdm_name     = "l4_per_clkdm",
 234         .prcm = {
 235                 .omap4 = {
 236                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 237                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 238                 },
 239         },
 240 };
 241
 242 /* l4_wkup */
 243 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 244         .name           = "l4_wkup",
 245         .class          = &omap44xx_l4_hwmod_class,
 246         .clkdm_name     = "l4_wkup_clkdm",
 247         .prcm = {
 248                 .omap4 = {
 249                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 250                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 251                 },
 252         },
 253 };
 254
 255 /*
 256  * 'mpu_bus' class
 257  * instance(s): mpu_private
 258  */
 259 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 260         .name   = "mpu_bus",
 261 };
 262
 263 /* mpu_private */
 264 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 265         .name           = "mpu_private",
 266         .class          = &omap44xx_mpu_bus_hwmod_class,
 267         .clkdm_name     = "mpuss_clkdm",
 268         .prcm = {
 269                 .omap4 = {
 270                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 271                 },
 272         },
 273 };
 274
 275 /*
 276  * 'ocp_wp_noc' class
 277  * instance(s): ocp_wp_noc
 278  */
 279 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 280         .name   = "ocp_wp_noc",
 281 };
 282
 283 /* ocp_wp_noc */
 284 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 285         .name           = "ocp_wp_noc",
 286         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 287         .clkdm_name     = "l3_instr_clkdm",
 288         .prcm = {
 289                 .omap4 = {
 290                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 291                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 292                         .modulemode   = MODULEMODE_HWCTRL,
 293                 },
 294         },
 295 };
 296
 297 /*
 298  * Modules omap_hwmod structures
 299  *
 300  * The following IPs are excluded for the moment because:
 301  * - They do not need an explicit SW control using omap_hwmod API.
 302  * - They still need to be validated with the driver
 303  *   properly adapted to omap_hwmod / omap_device
 304  *
 305  * usim
 306  */
 307
 308 /*
 309  * 'aess' class
 310  * audio engine sub system
 311  */
 312
 313 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 314         .rev_offs       = 0x0000,
 315         .sysc_offs      = 0x0010,
 316         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 317         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 318                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 319                            MSTANDBY_SMART_WKUP),
 320         .sysc_fields    = &omap_hwmod_sysc_type2,
 321 };
 322
 323 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 324         .name   = "aess",
 325         .sysc   = &omap44xx_aess_sysc,
 326 };
 327
 328 /* aess */
 329 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 330         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 331         { .irq = -1 }
 332 };
 333
 334 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 335         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 343         { .dma_req = -1 }
 344 };
 345
 346 static struct omap_hwmod omap44xx_aess_hwmod = {
 347         .name           = "aess",
 348         .class          = &omap44xx_aess_hwmod_class,
 349         .clkdm_name     = "abe_clkdm",
 350         .mpu_irqs       = omap44xx_aess_irqs,
 351         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 352         .main_clk       = "aess_fck",
 353         .prcm = {
 354                 .omap4 = {
 355                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 356                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 357                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 358                         .modulemode   = MODULEMODE_SWCTRL,
 359                 },
 360         },
 361 };
 362
 363 /*
 364  * 'c2c' class
 365  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 366  * soc
 367  */
 368
 369 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 370         .name   = "c2c",
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap44xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap44xx_c2c_hwmod_class,
 387         .clkdm_name     = "d2d_clkdm",
 388         .mpu_irqs       = omap44xx_c2c_irqs,
 389         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 390         .prcm = {
 391                 .omap4 = {
 392                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 393                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 394                 },
 395         },
 396 };
 397
 398 /*
 399  * 'counter' class
 400  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 404         .rev_offs       = 0x0000,
 405         .sysc_offs      = 0x0004,
 406         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 408         .sysc_fields    = &omap_hwmod_sysc_type1,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 412         .name   = "counter",
 413         .sysc   = &omap44xx_counter_sysc,
 414 };
 415
 416 /* counter_32k */
 417 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 418         .name           = "counter_32k",
 419         .class          = &omap44xx_counter_hwmod_class,
 420         .clkdm_name     = "l4_wkup_clkdm",
 421         .flags          = HWMOD_SWSUP_SIDLE,
 422         .main_clk       = "sys_32k_ck",
 423         .prcm = {
 424                 .omap4 = {
 425                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 426                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'ctrl_module' class
 433  * attila core control module + core pad control module + wkup pad control
 434  * module + attila wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 441         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 442                            SIDLE_SMART_WKUP),
 443         .sysc_fields    = &omap_hwmod_sysc_type2,
 444 };
 445
 446 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 447         .name   = "ctrl_module",
 448         .sysc   = &omap44xx_ctrl_module_sysc,
 449 };
 450
 451 /* ctrl_module_core */
 452 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 453         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 454         { .irq = -1 }
 455 };
 456
 457 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 458         .name           = "ctrl_module_core",
 459         .class          = &omap44xx_ctrl_module_hwmod_class,
 460         .clkdm_name     = "l4_cfg_clkdm",
 461         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 462         .prcm = {
 463                 .omap4 = {
 464                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 465                 },
 466         },
 467 };
 468
 469 /* ctrl_module_pad_core */
 470 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 471         .name           = "ctrl_module_pad_core",
 472         .class          = &omap44xx_ctrl_module_hwmod_class,
 473         .clkdm_name     = "l4_cfg_clkdm",
 474         .prcm = {
 475                 .omap4 = {
 476                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 477                 },
 478         },
 479 };
 480
 481 /* ctrl_module_wkup */
 482 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 483         .name           = "ctrl_module_wkup",
 484         .class          = &omap44xx_ctrl_module_hwmod_class,
 485         .clkdm_name     = "l4_wkup_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 489                 },
 490         },
 491 };
 492
 493 /* ctrl_module_pad_wkup */
 494 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 495         .name           = "ctrl_module_pad_wkup",
 496         .class          = &omap44xx_ctrl_module_hwmod_class,
 497         .clkdm_name     = "l4_wkup_clkdm",
 498         .prcm = {
 499                 .omap4 = {
 500                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 501                 },
 502         },
 503 };
 504
 505 /*
 506  * 'debugss' class
 507  * debug and emulation sub system
 508  */
 509
 510 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 511         .name   = "debugss",
 512 };
 513
 514 /* debugss */
 515 static struct omap_hwmod omap44xx_debugss_hwmod = {
 516         .name           = "debugss",
 517         .class          = &omap44xx_debugss_hwmod_class,
 518         .clkdm_name     = "emu_sys_clkdm",
 519         .main_clk       = "trace_clk_div_ck",
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 524                 },
 525         },
 526 };
 527
 528 /*
 529  * 'dma' class
 530  * dma controller for data exchange between memory to memory (i.e. internal or
 531  * external memory) and gp peripherals to memory or memory to gp peripherals
 532  */
 533
 534 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x002c,
 537         .syss_offs      = 0x0028,
 538         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 539                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 540                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 541                            SYSS_HAS_RESET_STATUS),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 544         .sysc_fields    = &omap_hwmod_sysc_type1,
 545 };
 546
 547 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 548         .name   = "dma",
 549         .sysc   = &omap44xx_dma_sysc,
 550 };
 551
 552 /* dma dev_attr */
 553 static struct omap_dma_dev_attr dma_dev_attr = {
 554         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 555                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 556         .lch_count      = 32,
 557 };
 558
 559 /* dma_system */
 560 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 561         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 565         { .irq = -1 }
 566 };
 567
 568 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 569         .name           = "dma_system",
 570         .class          = &omap44xx_dma_hwmod_class,
 571         .clkdm_name     = "l3_dma_clkdm",
 572         .mpu_irqs       = omap44xx_dma_system_irqs,
 573         .main_clk       = "l3_div_ck",
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 577                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 578                 },
 579         },
 580         .dev_attr       = &dma_dev_attr,
 581 };
 582
 583 /*
 584  * 'dmic' class
 585  * digital microphone controller
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 592                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 593         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 594                            SIDLE_SMART_WKUP),
 595         .sysc_fields    = &omap_hwmod_sysc_type2,
 596 };
 597
 598 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 599         .name   = "dmic",
 600         .sysc   = &omap44xx_dmic_sysc,
 601 };
 602
 603 /* dmic */
 604 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 605         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 606         { .irq = -1 }
 607 };
 608
 609 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 610         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 611         { .dma_req = -1 }
 612 };
 613
 614 static struct omap_hwmod omap44xx_dmic_hwmod = {
 615         .name           = "dmic",
 616         .class          = &omap44xx_dmic_hwmod_class,
 617         .clkdm_name     = "abe_clkdm",
 618         .mpu_irqs       = omap44xx_dmic_irqs,
 619         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 620         .main_clk       = "dmic_fck",
 621         .prcm = {
 622                 .omap4 = {
 623                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 624                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 625                         .modulemode   = MODULEMODE_SWCTRL,
 626                 },
 627         },
 628 };
 629
 630 /*
 631  * 'dsp' class
 632  * dsp sub-system
 633  */
 634
 635 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 636         .name   = "dsp",
 637 };
 638
 639 /* dsp */
 640 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 641         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 642         { .irq = -1 }
 643 };
 644
 645 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 646         { .name = "dsp", .rst_shift = 0 },
 647 };
 648
 649 static struct omap_hwmod omap44xx_dsp_hwmod = {
 650         .name           = "dsp",
 651         .class          = &omap44xx_dsp_hwmod_class,
 652         .clkdm_name     = "tesla_clkdm",
 653         .mpu_irqs       = omap44xx_dsp_irqs,
 654         .rst_lines      = omap44xx_dsp_resets,
 655         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 656         .main_clk       = "dsp_fck",
 657         .prcm = {
 658                 .omap4 = {
 659                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 660                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 661                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 662                         .modulemode   = MODULEMODE_HWCTRL,
 663                 },
 664         },
 665 };
 666
 667 /*
 668  * 'dss' class
 669  * display sub-system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 673         .rev_offs       = 0x0000,
 674         .syss_offs      = 0x0014,
 675         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 676 };
 677
 678 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 679         .name   = "dss",
 680         .sysc   = &omap44xx_dss_sysc,
 681         .reset  = omap_dss_reset,
 682 };
 683
 684 /* dss */
 685 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 686         { .role = "sys_clk", .clk = "dss_sys_clk" },
 687         { .role = "tv_clk", .clk = "dss_tv_clk" },
 688         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 689 };
 690
 691 static struct omap_hwmod omap44xx_dss_hwmod = {
 692         .name           = "dss_core",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .class          = &omap44xx_dss_hwmod_class,
 695         .clkdm_name     = "l3_dss_clkdm",
 696         .main_clk       = "dss_dss_clk",
 697         .prcm = {
 698                 .omap4 = {
 699                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 700                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 701                 },
 702         },
 703         .opt_clks       = dss_opt_clks,
 704         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 705 };
 706
 707 /*
 708  * 'dispc' class
 709  * display controller
 710  */
 711
 712 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 713         .rev_offs       = 0x0000,
 714         .sysc_offs      = 0x0010,
 715         .syss_offs      = 0x0014,
 716         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 717                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 719                            SYSS_HAS_RESET_STATUS),
 720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 721                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 722         .sysc_fields    = &omap_hwmod_sysc_type1,
 723 };
 724
 725 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 726         .name   = "dispc",
 727         .sysc   = &omap44xx_dispc_sysc,
 728 };
 729
 730 /* dss_dispc */
 731 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 732         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 733         { .irq = -1 }
 734 };
 735
 736 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 737         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 738         { .dma_req = -1 }
 739 };
 740
 741 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 742         .manager_count          = 3,
 743         .has_framedonetv_irq    = 1
 744 };
 745
 746 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 747         .name           = "dss_dispc",
 748         .class          = &omap44xx_dispc_hwmod_class,
 749         .clkdm_name     = "l3_dss_clkdm",
 750         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 751         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 752         .main_clk       = "dss_dss_clk",
 753         .prcm = {
 754                 .omap4 = {
 755                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 756                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 757                 },
 758         },
 759         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 760 };
 761
 762 /*
 763  * 'dsi' class
 764  * display serial interface controller
 765  */
 766
 767 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 768         .rev_offs       = 0x0000,
 769         .sysc_offs      = 0x0010,
 770         .syss_offs      = 0x0014,
 771         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 772                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 773                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 774         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 775         .sysc_fields    = &omap_hwmod_sysc_type1,
 776 };
 777
 778 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 779         .name   = "dsi",
 780         .sysc   = &omap44xx_dsi_sysc,
 781 };
 782
 783 /* dss_dsi1 */
 784 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 785         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 786         { .irq = -1 }
 787 };
 788
 789 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 790         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 791         { .dma_req = -1 }
 792 };
 793
 794 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 795         { .role = "sys_clk", .clk = "dss_sys_clk" },
 796 };
 797
 798 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 799         .name           = "dss_dsi1",
 800         .class          = &omap44xx_dsi_hwmod_class,
 801         .clkdm_name     = "l3_dss_clkdm",
 802         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 803         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 804         .main_clk       = "dss_dss_clk",
 805         .prcm = {
 806                 .omap4 = {
 807                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 808                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 809                 },
 810         },
 811         .opt_clks       = dss_dsi1_opt_clks,
 812         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 813 };
 814
 815 /* dss_dsi2 */
 816 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 817         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 818         { .irq = -1 }
 819 };
 820
 821 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 822         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 823         { .dma_req = -1 }
 824 };
 825
 826 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 827         { .role = "sys_clk", .clk = "dss_sys_clk" },
 828 };
 829
 830 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 831         .name           = "dss_dsi2",
 832         .class          = &omap44xx_dsi_hwmod_class,
 833         .clkdm_name     = "l3_dss_clkdm",
 834         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 835         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 836         .main_clk       = "dss_dss_clk",
 837         .prcm = {
 838                 .omap4 = {
 839                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 840                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 841                 },
 842         },
 843         .opt_clks       = dss_dsi2_opt_clks,
 844         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 845 };
 846
 847 /*
 848  * 'hdmi' class
 849  * hdmi controller
 850  */
 851
 852 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 853         .rev_offs       = 0x0000,
 854         .sysc_offs      = 0x0010,
 855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            SIDLE_SMART_WKUP),
 859         .sysc_fields    = &omap_hwmod_sysc_type2,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 863         .name   = "hdmi",
 864         .sysc   = &omap44xx_hdmi_sysc,
 865 };
 866
 867 /* dss_hdmi */
 868 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 869         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 870         { .irq = -1 }
 871 };
 872
 873 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 874         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 875         { .dma_req = -1 }
 876 };
 877
 878 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 879         { .role = "sys_clk", .clk = "dss_sys_clk" },
 880 };
 881
 882 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 883         .name           = "dss_hdmi",
 884         .class          = &omap44xx_hdmi_hwmod_class,
 885         .clkdm_name     = "l3_dss_clkdm",
 886         /*
 887          * HDMI audio requires to use no-idle mode. Hence,
 888          * set idle mode by software.
 889          */
 890         .flags          = HWMOD_SWSUP_SIDLE,
 891         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 892         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 893         .main_clk       = "dss_48mhz_clk",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 897                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 898                 },
 899         },
 900         .opt_clks       = dss_hdmi_opt_clks,
 901         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 902 };
 903
 904 /*
 905  * 'rfbi' class
 906  * remote frame buffer interface
 907  */
 908
 909 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 910         .rev_offs       = 0x0000,
 911         .sysc_offs      = 0x0010,
 912         .syss_offs      = 0x0014,
 913         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 914                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 916         .sysc_fields    = &omap_hwmod_sysc_type1,
 917 };
 918
 919 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 920         .name   = "rfbi",
 921         .sysc   = &omap44xx_rfbi_sysc,
 922 };
 923
 924 /* dss_rfbi */
 925 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 926         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 927         { .dma_req = -1 }
 928 };
 929
 930 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 931         { .role = "ick", .clk = "dss_fck" },
 932 };
 933
 934 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 935         .name           = "dss_rfbi",
 936         .class          = &omap44xx_rfbi_hwmod_class,
 937         .clkdm_name     = "l3_dss_clkdm",
 938         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 939         .main_clk       = "dss_dss_clk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 943                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 944                 },
 945         },
 946         .opt_clks       = dss_rfbi_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 948 };
 949
 950 /*
 951  * 'venc' class
 952  * video encoder
 953  */
 954
 955 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 956         .name   = "venc",
 957 };
 958
 959 /* dss_venc */
 960 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 961         .name           = "dss_venc",
 962         .class          = &omap44xx_venc_hwmod_class,
 963         .clkdm_name     = "l3_dss_clkdm",
 964         .main_clk       = "dss_tv_clk",
 965         .prcm = {
 966                 .omap4 = {
 967                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 968                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 969                 },
 970         },
 971 };
 972
 973 /*
 974  * 'elm' class
 975  * bch error location module
 976  */
 977
 978 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 979         .rev_offs       = 0x0000,
 980         .sysc_offs      = 0x0010,
 981         .syss_offs      = 0x0014,
 982         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 983                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 984                            SYSS_HAS_RESET_STATUS),
 985         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 986         .sysc_fields    = &omap_hwmod_sysc_type1,
 987 };
 988
 989 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 990         .name   = "elm",
 991         .sysc   = &omap44xx_elm_sysc,
 992 };
 993
 994 /* elm */
 995 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 996         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 997         { .irq = -1 }
 998 };
 999
1000 static struct omap_hwmod omap44xx_elm_hwmod = {
1001         .name           = "elm",
1002         .class          = &omap44xx_elm_hwmod_class,
1003         .clkdm_name     = "l4_per_clkdm",
1004         .mpu_irqs       = omap44xx_elm_irqs,
1005         .prcm = {
1006                 .omap4 = {
1007                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1008                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1009                 },
1010         },
1011 };
1012
1013 /*
1014  * 'emif' class
1015  * external memory interface no1
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019         .rev_offs       = 0x0000,
1020 };
1021
1022 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1023         .name   = "emif",
1024         .sysc   = &omap44xx_emif_sysc,
1025 };
1026
1027 /* emif1 */
1028 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1029         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030         { .irq = -1 }
1031 };
1032
1033 static struct omap_hwmod omap44xx_emif1_hwmod = {
1034         .name           = "emif1",
1035         .class          = &omap44xx_emif_hwmod_class,
1036         .clkdm_name     = "l3_emif_clkdm",
1037         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1038         .mpu_irqs       = omap44xx_emif1_irqs,
1039         .main_clk       = "ddrphy_ck",
1040         .prcm = {
1041                 .omap4 = {
1042                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1043                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1044                         .modulemode   = MODULEMODE_HWCTRL,
1045                 },
1046         },
1047 };
1048
1049 /* emif2 */
1050 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1051         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052         { .irq = -1 }
1053 };
1054
1055 static struct omap_hwmod omap44xx_emif2_hwmod = {
1056         .name           = "emif2",
1057         .class          = &omap44xx_emif_hwmod_class,
1058         .clkdm_name     = "l3_emif_clkdm",
1059         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1060         .mpu_irqs       = omap44xx_emif2_irqs,
1061         .main_clk       = "ddrphy_ck",
1062         .prcm = {
1063                 .omap4 = {
1064                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1065                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1066                         .modulemode   = MODULEMODE_HWCTRL,
1067                 },
1068         },
1069 };
1070
1071 /*
1072  * 'fdif' class
1073  * face detection hw accelerator module
1074  */
1075
1076 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1077         .rev_offs       = 0x0000,
1078         .sysc_offs      = 0x0010,
1079         /*
1080          * FDIF needs 100 OCP clk cycles delay after a softreset before
1081          * accessing sysconfig again.
1082          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1083          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1084          *
1085          * TODO: Indicate errata when available.
1086          */
1087         .srst_udelay    = 2,
1088         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1089                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type2,
1093 };
1094
1095 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1096         .name   = "fdif",
1097         .sysc   = &omap44xx_fdif_sysc,
1098 };
1099
1100 /* fdif */
1101 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1102         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod omap44xx_fdif_hwmod = {
1107         .name           = "fdif",
1108         .class          = &omap44xx_fdif_hwmod_class,
1109         .clkdm_name     = "iss_clkdm",
1110         .mpu_irqs       = omap44xx_fdif_irqs,
1111         .main_clk       = "fdif_fck",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1115                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1116                         .modulemode   = MODULEMODE_SWCTRL,
1117                 },
1118         },
1119 };
1120
1121 /*
1122  * 'gpio' class
1123  * general purpose io module
1124  */
1125
1126 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1127         .rev_offs       = 0x0000,
1128         .sysc_offs      = 0x0010,
1129         .syss_offs      = 0x0114,
1130         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1131                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1132                            SYSS_HAS_RESET_STATUS),
1133         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1134                            SIDLE_SMART_WKUP),
1135         .sysc_fields    = &omap_hwmod_sysc_type1,
1136 };
1137
1138 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1139         .name   = "gpio",
1140         .sysc   = &omap44xx_gpio_sysc,
1141         .rev    = 2,
1142 };
1143
1144 /* gpio dev_attr */
1145 static struct omap_gpio_dev_attr gpio_dev_attr = {
1146         .bank_width     = 32,
1147         .dbck_flag      = true,
1148 };
1149
1150 /* gpio1 */
1151 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1152         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153         { .irq = -1 }
1154 };
1155
1156 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1157         { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 };
1159
1160 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161         .name           = "gpio1",
1162         .class          = &omap44xx_gpio_hwmod_class,
1163         .clkdm_name     = "l4_wkup_clkdm",
1164         .mpu_irqs       = omap44xx_gpio1_irqs,
1165         .main_clk       = "gpio1_ick",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1169                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1170                         .modulemode   = MODULEMODE_HWCTRL,
1171                 },
1172         },
1173         .opt_clks       = gpio1_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1175         .dev_attr       = &gpio_dev_attr,
1176 };
1177
1178 /* gpio2 */
1179 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1180         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181         { .irq = -1 }
1182 };
1183
1184 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1185         { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 };
1187
1188 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1189         .name           = "gpio2",
1190         .class          = &omap44xx_gpio_hwmod_class,
1191         .clkdm_name     = "l4_per_clkdm",
1192         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1193         .mpu_irqs       = omap44xx_gpio2_irqs,
1194         .main_clk       = "gpio2_ick",
1195         .prcm = {
1196                 .omap4 = {
1197                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1198                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1199                         .modulemode   = MODULEMODE_HWCTRL,
1200                 },
1201         },
1202         .opt_clks       = gpio2_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1204         .dev_attr       = &gpio_dev_attr,
1205 };
1206
1207 /* gpio3 */
1208 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1209         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210         { .irq = -1 }
1211 };
1212
1213 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1214         { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 };
1216
1217 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1218         .name           = "gpio3",
1219         .class          = &omap44xx_gpio_hwmod_class,
1220         .clkdm_name     = "l4_per_clkdm",
1221         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1222         .mpu_irqs       = omap44xx_gpio3_irqs,
1223         .main_clk       = "gpio3_ick",
1224         .prcm = {
1225                 .omap4 = {
1226                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1227                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1228                         .modulemode   = MODULEMODE_HWCTRL,
1229                 },
1230         },
1231         .opt_clks       = gpio3_opt_clks,
1232         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1233         .dev_attr       = &gpio_dev_attr,
1234 };
1235
1236 /* gpio4 */
1237 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1238         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239         { .irq = -1 }
1240 };
1241
1242 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1243         { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1247         .name           = "gpio4",
1248         .class          = &omap44xx_gpio_hwmod_class,
1249         .clkdm_name     = "l4_per_clkdm",
1250         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1251         .mpu_irqs       = omap44xx_gpio4_irqs,
1252         .main_clk       = "gpio4_ick",
1253         .prcm = {
1254                 .omap4 = {
1255                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1256                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1257                         .modulemode   = MODULEMODE_HWCTRL,
1258                 },
1259         },
1260         .opt_clks       = gpio4_opt_clks,
1261         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1262         .dev_attr       = &gpio_dev_attr,
1263 };
1264
1265 /* gpio5 */
1266 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1267         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268         { .irq = -1 }
1269 };
1270
1271 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1272         { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 };
1274
1275 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1276         .name           = "gpio5",
1277         .class          = &omap44xx_gpio_hwmod_class,
1278         .clkdm_name     = "l4_per_clkdm",
1279         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1280         .mpu_irqs       = omap44xx_gpio5_irqs,
1281         .main_clk       = "gpio5_ick",
1282         .prcm = {
1283                 .omap4 = {
1284                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1285                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1286                         .modulemode   = MODULEMODE_HWCTRL,
1287                 },
1288         },
1289         .opt_clks       = gpio5_opt_clks,
1290         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1291         .dev_attr       = &gpio_dev_attr,
1292 };
1293
1294 /* gpio6 */
1295 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1296         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297         { .irq = -1 }
1298 };
1299
1300 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1301         { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 };
1303
1304 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1305         .name           = "gpio6",
1306         .class          = &omap44xx_gpio_hwmod_class,
1307         .clkdm_name     = "l4_per_clkdm",
1308         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1309         .mpu_irqs       = omap44xx_gpio6_irqs,
1310         .main_clk       = "gpio6_ick",
1311         .prcm = {
1312                 .omap4 = {
1313                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1314                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1315                         .modulemode   = MODULEMODE_HWCTRL,
1316                 },
1317         },
1318         .opt_clks       = gpio6_opt_clks,
1319         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1320         .dev_attr       = &gpio_dev_attr,
1321 };
1322
1323 /*
1324  * 'gpmc' class
1325  * general purpose memory controller
1326  */
1327
1328 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1329         .rev_offs       = 0x0000,
1330         .sysc_offs      = 0x0010,
1331         .syss_offs      = 0x0014,
1332         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1333                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1334         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1335         .sysc_fields    = &omap_hwmod_sysc_type1,
1336 };
1337
1338 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1339         .name   = "gpmc",
1340         .sysc   = &omap44xx_gpmc_sysc,
1341 };
1342
1343 /* gpmc */
1344 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1345         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346         { .irq = -1 }
1347 };
1348
1349 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1350         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351         { .dma_req = -1 }
1352 };
1353
1354 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1355         .name           = "gpmc",
1356         .class          = &omap44xx_gpmc_hwmod_class,
1357         .clkdm_name     = "l3_2_clkdm",
1358         /*
1359          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1360          * block.  It is not being added due to any known bugs with
1361          * resetting the GPMC IP block, but rather because any timings
1362          * set by the bootloader are not being correctly programmed by
1363          * the kernel from the board file or DT data.
1364          * HWMOD_INIT_NO_RESET should be removed ASAP.
1365          */
1366         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1367         .mpu_irqs       = omap44xx_gpmc_irqs,
1368         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1369         .prcm = {
1370                 .omap4 = {
1371                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1372                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1373                         .modulemode   = MODULEMODE_HWCTRL,
1374                 },
1375         },
1376 };
1377
1378 /*
1379  * 'gpu' class
1380  * 2d/3d graphics accelerator
1381  */
1382
1383 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1384         .rev_offs       = 0x1fc00,
1385         .sysc_offs      = 0x1fc10,
1386         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1387         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1388                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1389                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1390         .sysc_fields    = &omap_hwmod_sysc_type2,
1391 };
1392
1393 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1394         .name   = "gpu",
1395         .sysc   = &omap44xx_gpu_sysc,
1396 };
1397
1398 /* gpu */
1399 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1400         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401         { .irq = -1 }
1402 };
1403
1404 static struct omap_hwmod omap44xx_gpu_hwmod = {
1405         .name           = "gpu",
1406         .class          = &omap44xx_gpu_hwmod_class,
1407         .clkdm_name     = "l3_gfx_clkdm",
1408         .mpu_irqs       = omap44xx_gpu_irqs,
1409         .main_clk       = "gpu_fck",
1410         .prcm = {
1411                 .omap4 = {
1412                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1413                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1414                         .modulemode   = MODULEMODE_SWCTRL,
1415                 },
1416         },
1417 };
1418
1419 /*
1420  * 'hdq1w' class
1421  * hdq / 1-wire serial interface controller
1422  */
1423
1424 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1425         .rev_offs       = 0x0000,
1426         .sysc_offs      = 0x0014,
1427         .syss_offs      = 0x0018,
1428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1429                            SYSS_HAS_RESET_STATUS),
1430         .sysc_fields    = &omap_hwmod_sysc_type1,
1431 };
1432
1433 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1434         .name   = "hdq1w",
1435         .sysc   = &omap44xx_hdq1w_sysc,
1436 };
1437
1438 /* hdq1w */
1439 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1440         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441         { .irq = -1 }
1442 };
1443
1444 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1445         .name           = "hdq1w",
1446         .class          = &omap44xx_hdq1w_hwmod_class,
1447         .clkdm_name     = "l4_per_clkdm",
1448         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1449         .mpu_irqs       = omap44xx_hdq1w_irqs,
1450         .main_clk       = "hdq1w_fck",
1451         .prcm = {
1452                 .omap4 = {
1453                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1454                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1455                         .modulemode   = MODULEMODE_SWCTRL,
1456                 },
1457         },
1458 };
1459
1460 /*
1461  * 'hsi' class
1462  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463  * serial if)
1464  */
1465
1466 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1467         .rev_offs       = 0x0000,
1468         .sysc_offs      = 0x0010,
1469         .syss_offs      = 0x0014,
1470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1471                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1472                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1474                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1475                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1476         .sysc_fields    = &omap_hwmod_sysc_type1,
1477 };
1478
1479 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1480         .name   = "hsi",
1481         .sysc   = &omap44xx_hsi_sysc,
1482 };
1483
1484 /* hsi */
1485 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1486         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489         { .irq = -1 }
1490 };
1491
1492 static struct omap_hwmod omap44xx_hsi_hwmod = {
1493         .name           = "hsi",
1494         .class          = &omap44xx_hsi_hwmod_class,
1495         .clkdm_name     = "l3_init_clkdm",
1496         .mpu_irqs       = omap44xx_hsi_irqs,
1497         .main_clk       = "hsi_fck",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1501                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_HWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /*
1508  * 'i2c' class
1509  * multimaster high-speed i2c controller
1510  */
1511
1512 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1513         .sysc_offs      = 0x0010,
1514         .syss_offs      = 0x0090,
1515         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1516                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1517                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1518         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1519                            SIDLE_SMART_WKUP),
1520         .clockact       = CLOCKACT_TEST_ICLK,
1521         .sysc_fields    = &omap_hwmod_sysc_type1,
1522 };
1523
1524 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1525         .name   = "i2c",
1526         .sysc   = &omap44xx_i2c_sysc,
1527         .rev    = OMAP_I2C_IP_VERSION_2,
1528         .reset  = &omap_i2c_reset,
1529 };
1530
1531 static struct omap_i2c_dev_attr i2c_dev_attr = {
1532         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1533                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1534 };
1535
1536 /* i2c1 */
1537 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1538         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1539         { .irq = -1 }
1540 };
1541
1542 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1543         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1544         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1545         { .dma_req = -1 }
1546 };
1547
1548 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1549         .name           = "i2c1",
1550         .class          = &omap44xx_i2c_hwmod_class,
1551         .clkdm_name     = "l4_per_clkdm",
1552         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1553         .mpu_irqs       = omap44xx_i2c1_irqs,
1554         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1555         .main_clk       = "i2c1_fck",
1556         .prcm = {
1557                 .omap4 = {
1558                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1559                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1560                         .modulemode   = MODULEMODE_SWCTRL,
1561                 },
1562         },
1563         .dev_attr       = &i2c_dev_attr,
1564 };
1565
1566 /* i2c2 */
1567 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1568         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1569         { .irq = -1 }
1570 };
1571
1572 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1573         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1574         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1575         { .dma_req = -1 }
1576 };
1577
1578 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1579         .name           = "i2c2",
1580         .class          = &omap44xx_i2c_hwmod_class,
1581         .clkdm_name     = "l4_per_clkdm",
1582         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1583         .mpu_irqs       = omap44xx_i2c2_irqs,
1584         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1585         .main_clk       = "i2c2_fck",
1586         .prcm = {
1587                 .omap4 = {
1588                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1589                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1590                         .modulemode   = MODULEMODE_SWCTRL,
1591                 },
1592         },
1593         .dev_attr       = &i2c_dev_attr,
1594 };
1595
1596 /* i2c3 */
1597 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1598         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1599         { .irq = -1 }
1600 };
1601
1602 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1603         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1604         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1605         { .dma_req = -1 }
1606 };
1607
1608 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1609         .name           = "i2c3",
1610         .class          = &omap44xx_i2c_hwmod_class,
1611         .clkdm_name     = "l4_per_clkdm",
1612         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1613         .mpu_irqs       = omap44xx_i2c3_irqs,
1614         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1615         .main_clk       = "i2c3_fck",
1616         .prcm = {
1617                 .omap4 = {
1618                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1619                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1620                         .modulemode   = MODULEMODE_SWCTRL,
1621                 },
1622         },
1623         .dev_attr       = &i2c_dev_attr,
1624 };
1625
1626 /* i2c4 */
1627 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1628         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1629         { .irq = -1 }
1630 };
1631
1632 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1633         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1634         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1635         { .dma_req = -1 }
1636 };
1637
1638 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1639         .name           = "i2c4",
1640         .class          = &omap44xx_i2c_hwmod_class,
1641         .clkdm_name     = "l4_per_clkdm",
1642         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1643         .mpu_irqs       = omap44xx_i2c4_irqs,
1644         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1645         .main_clk       = "i2c4_fck",
1646         .prcm = {
1647                 .omap4 = {
1648                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1649                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1650                         .modulemode   = MODULEMODE_SWCTRL,
1651                 },
1652         },
1653         .dev_attr       = &i2c_dev_attr,
1654 };
1655
1656 /*
1657  * 'ipu' class
1658  * imaging processor unit
1659  */
1660
1661 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1662         .name   = "ipu",
1663 };
1664
1665 /* ipu */
1666 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1667         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1668         { .irq = -1 }
1669 };
1670
1671 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1672         { .name = "cpu0", .rst_shift = 0 },
1673         { .name = "cpu1", .rst_shift = 1 },
1674 };
1675
1676 static struct omap_hwmod omap44xx_ipu_hwmod = {
1677         .name           = "ipu",
1678         .class          = &omap44xx_ipu_hwmod_class,
1679         .clkdm_name     = "ducati_clkdm",
1680         .mpu_irqs       = omap44xx_ipu_irqs,
1681         .rst_lines      = omap44xx_ipu_resets,
1682         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1683         .main_clk       = "ipu_fck",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1687                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1688                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1689                         .modulemode   = MODULEMODE_HWCTRL,
1690                 },
1691         },
1692 };
1693
1694 /*
1695  * 'iss' class
1696  * external images sensor pixel data processor
1697  */
1698
1699 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1700         .rev_offs       = 0x0000,
1701         .sysc_offs      = 0x0010,
1702         /*
1703          * ISS needs 100 OCP clk cycles delay after a softreset before
1704          * accessing sysconfig again.
1705          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1706          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1707          *
1708          * TODO: Indicate errata when available.
1709          */
1710         .srst_udelay    = 2,
1711         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1712                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1713         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1714                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1715                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1716         .sysc_fields    = &omap_hwmod_sysc_type2,
1717 };
1718
1719 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1720         .name   = "iss",
1721         .sysc   = &omap44xx_iss_sysc,
1722 };
1723
1724 /* iss */
1725 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1726         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1727         { .irq = -1 }
1728 };
1729
1730 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1731         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1732         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1733         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1734         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1735         { .dma_req = -1 }
1736 };
1737
1738 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1739         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1740 };
1741
1742 static struct omap_hwmod omap44xx_iss_hwmod = {
1743         .name           = "iss",
1744         .class          = &omap44xx_iss_hwmod_class,
1745         .clkdm_name     = "iss_clkdm",
1746         .mpu_irqs       = omap44xx_iss_irqs,
1747         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1748         .main_clk       = "iss_fck",
1749         .prcm = {
1750                 .omap4 = {
1751                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1752                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1753                         .modulemode   = MODULEMODE_SWCTRL,
1754                 },
1755         },
1756         .opt_clks       = iss_opt_clks,
1757         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1758 };
1759
1760 /*
1761  * 'iva' class
1762  * multi-standard video encoder/decoder hardware accelerator
1763  */
1764
1765 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1766         .name   = "iva",
1767 };
1768
1769 /* iva */
1770 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1771         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1773         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1774         { .irq = -1 }
1775 };
1776
1777 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1778         { .name = "seq0", .rst_shift = 0 },
1779         { .name = "seq1", .rst_shift = 1 },
1780         { .name = "logic", .rst_shift = 2 },
1781 };
1782
1783 static struct omap_hwmod omap44xx_iva_hwmod = {
1784         .name           = "iva",
1785         .class          = &omap44xx_iva_hwmod_class,
1786         .clkdm_name     = "ivahd_clkdm",
1787         .mpu_irqs       = omap44xx_iva_irqs,
1788         .rst_lines      = omap44xx_iva_resets,
1789         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1790         .main_clk       = "iva_fck",
1791         .prcm = {
1792                 .omap4 = {
1793                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1794                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1795                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1796                         .modulemode   = MODULEMODE_HWCTRL,
1797                 },
1798         },
1799 };
1800
1801 /*
1802  * 'kbd' class
1803  * keyboard controller
1804  */
1805
1806 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1807         .rev_offs       = 0x0000,
1808         .sysc_offs      = 0x0010,
1809         .syss_offs      = 0x0014,
1810         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1811                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1813                            SYSS_HAS_RESET_STATUS),
1814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1815         .sysc_fields    = &omap_hwmod_sysc_type1,
1816 };
1817
1818 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1819         .name   = "kbd",
1820         .sysc   = &omap44xx_kbd_sysc,
1821 };
1822
1823 /* kbd */
1824 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1825         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1828
1829 static struct omap_hwmod omap44xx_kbd_hwmod = {
1830         .name           = "kbd",
1831         .class          = &omap44xx_kbd_hwmod_class,
1832         .clkdm_name     = "l4_wkup_clkdm",
1833         .mpu_irqs       = omap44xx_kbd_irqs,
1834         .main_clk       = "kbd_fck",
1835         .prcm = {
1836                 .omap4 = {
1837                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1838                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1839                         .modulemode   = MODULEMODE_SWCTRL,
1840                 },
1841         },
1842 };
1843
1844 /*
1845  * 'mailbox' class
1846  * mailbox module allowing communication between the on-chip processors using a
1847  * queued mailbox-interrupt mechanism.
1848  */
1849
1850 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1851         .rev_offs       = 0x0000,
1852         .sysc_offs      = 0x0010,
1853         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1854                            SYSC_HAS_SOFTRESET),
1855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1856         .sysc_fields    = &omap_hwmod_sysc_type2,
1857 };
1858
1859 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1860         .name   = "mailbox",
1861         .sysc   = &omap44xx_mailbox_sysc,
1862 };
1863
1864 /* mailbox */
1865 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1866         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1867         { .irq = -1 }
1868 };
1869
1870 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1871         .name           = "mailbox",
1872         .class          = &omap44xx_mailbox_hwmod_class,
1873         .clkdm_name     = "l4_cfg_clkdm",
1874         .mpu_irqs       = omap44xx_mailbox_irqs,
1875         .prcm = {
1876                 .omap4 = {
1877                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1878                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1879                 },
1880         },
1881 };
1882
1883 /*
1884  * 'mcasp' class
1885  * multi-channel audio serial port controller
1886  */
1887
1888 /* The IP is not compliant to type1 / type2 scheme */
1889 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1890         .sidle_shift    = 0,
1891 };
1892
1893 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1894         .sysc_offs      = 0x0004,
1895         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1896         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1897                            SIDLE_SMART_WKUP),
1898         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1899 };
1900
1901 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1902         .name   = "mcasp",
1903         .sysc   = &omap44xx_mcasp_sysc,
1904 };
1905
1906 /* mcasp */
1907 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1908         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1909         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1910         { .irq = -1 }
1911 };
1912
1913 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1914         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1915         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1916         { .dma_req = -1 }
1917 };
1918
1919 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1920         .name           = "mcasp",
1921         .class          = &omap44xx_mcasp_hwmod_class,
1922         .clkdm_name     = "abe_clkdm",
1923         .mpu_irqs       = omap44xx_mcasp_irqs,
1924         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1925         .main_clk       = "mcasp_fck",
1926         .prcm = {
1927                 .omap4 = {
1928                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1929                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1930                         .modulemode   = MODULEMODE_SWCTRL,
1931                 },
1932         },
1933 };
1934
1935 /*
1936  * 'mcbsp' class
1937  * multi channel buffered serial port controller
1938  */
1939
1940 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1941         .sysc_offs      = 0x008c,
1942         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1943                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1944         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1945         .sysc_fields    = &omap_hwmod_sysc_type1,
1946 };
1947
1948 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1949         .name   = "mcbsp",
1950         .sysc   = &omap44xx_mcbsp_sysc,
1951         .rev    = MCBSP_CONFIG_TYPE4,
1952 };
1953
1954 /* mcbsp1 */
1955 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1956         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1957         { .irq = -1 }
1958 };
1959
1960 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1961         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1962         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1963         { .dma_req = -1 }
1964 };
1965
1966 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1967         { .role = "pad_fck", .clk = "pad_clks_ck" },
1968         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1972         .name           = "mcbsp1",
1973         .class          = &omap44xx_mcbsp_hwmod_class,
1974         .clkdm_name     = "abe_clkdm",
1975         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1976         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1977         .main_clk       = "mcbsp1_fck",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1981                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1982                         .modulemode   = MODULEMODE_SWCTRL,
1983                 },
1984         },
1985         .opt_clks       = mcbsp1_opt_clks,
1986         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1987 };
1988
1989 /* mcbsp2 */
1990 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1991         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1992         { .irq = -1 }
1993 };
1994
1995 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1996         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1997         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1998         { .dma_req = -1 }
1999 };
2000
2001 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2002         { .role = "pad_fck", .clk = "pad_clks_ck" },
2003         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2004 };
2005
2006 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2007         .name           = "mcbsp2",
2008         .class          = &omap44xx_mcbsp_hwmod_class,
2009         .clkdm_name     = "abe_clkdm",
2010         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2011         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2012         .main_clk       = "mcbsp2_fck",
2013         .prcm = {
2014                 .omap4 = {
2015                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2016                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2017                         .modulemode   = MODULEMODE_SWCTRL,
2018                 },
2019         },
2020         .opt_clks       = mcbsp2_opt_clks,
2021         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2022 };
2023
2024 /* mcbsp3 */
2025 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2026         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2027         { .irq = -1 }
2028 };
2029
2030 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2031         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2032         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2033         { .dma_req = -1 }
2034 };
2035
2036 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2037         { .role = "pad_fck", .clk = "pad_clks_ck" },
2038         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2039 };
2040
2041 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2042         .name           = "mcbsp3",
2043         .class          = &omap44xx_mcbsp_hwmod_class,
2044         .clkdm_name     = "abe_clkdm",
2045         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2046         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2047         .main_clk       = "mcbsp3_fck",
2048         .prcm = {
2049                 .omap4 = {
2050                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2051                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2052                         .modulemode   = MODULEMODE_SWCTRL,
2053                 },
2054         },
2055         .opt_clks       = mcbsp3_opt_clks,
2056         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2057 };
2058
2059 /* mcbsp4 */
2060 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2061         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2062         { .irq = -1 }
2063 };
2064
2065 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2066         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2067         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2068         { .dma_req = -1 }
2069 };
2070
2071 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2072         { .role = "pad_fck", .clk = "pad_clks_ck" },
2073         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2074 };
2075
2076 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2077         .name           = "mcbsp4",
2078         .class          = &omap44xx_mcbsp_hwmod_class,
2079         .clkdm_name     = "l4_per_clkdm",
2080         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2081         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2082         .main_clk       = "mcbsp4_fck",
2083         .prcm = {
2084                 .omap4 = {
2085                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2086                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2087                         .modulemode   = MODULEMODE_SWCTRL,
2088                 },
2089         },
2090         .opt_clks       = mcbsp4_opt_clks,
2091         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2092 };
2093
2094 /*
2095  * 'mcpdm' class
2096  * multi channel pdm controller (proprietary interface with phoenix power
2097  * ic)
2098  */
2099
2100 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2101         .rev_offs       = 0x0000,
2102         .sysc_offs      = 0x0010,
2103         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2104                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2106                            SIDLE_SMART_WKUP),
2107         .sysc_fields    = &omap_hwmod_sysc_type2,
2108 };
2109
2110 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2111         .name   = "mcpdm",
2112         .sysc   = &omap44xx_mcpdm_sysc,
2113 };
2114
2115 /* mcpdm */
2116 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2117         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2118         { .irq = -1 }
2119 };
2120
2121 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2122         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2123         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2124         { .dma_req = -1 }
2125 };
2126
2127 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2128         .name           = "mcpdm",
2129         .class          = &omap44xx_mcpdm_hwmod_class,
2130         .clkdm_name     = "abe_clkdm",
2131         /*
2132          * It's suspected that the McPDM requires an off-chip main
2133          * functional clock, controlled via I2C.  This IP block is
2134          * currently reset very early during boot, before I2C is
2135          * available, so it doesn't seem that we have any choice in
2136          * the kernel other than to avoid resetting it.
2137          */
2138         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2139         .mpu_irqs       = omap44xx_mcpdm_irqs,
2140         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2141         .main_clk       = "mcpdm_fck",
2142         .prcm = {
2143                 .omap4 = {
2144                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2145                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2146                         .modulemode   = MODULEMODE_SWCTRL,
2147                 },
2148         },
2149 };
2150
2151 /*
2152  * 'mcspi' class
2153  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2154  * bus
2155  */
2156
2157 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2158         .rev_offs       = 0x0000,
2159         .sysc_offs      = 0x0010,
2160         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2161                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2162         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2163                            SIDLE_SMART_WKUP),
2164         .sysc_fields    = &omap_hwmod_sysc_type2,
2165 };
2166
2167 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2168         .name   = "mcspi",
2169         .sysc   = &omap44xx_mcspi_sysc,
2170         .rev    = OMAP4_MCSPI_REV,
2171 };
2172
2173 /* mcspi1 */
2174 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2175         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2176         { .irq = -1 }
2177 };
2178
2179 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2180         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2181         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2182         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2183         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2184         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2185         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2186         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2187         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2188         { .dma_req = -1 }
2189 };
2190
2191 /* mcspi1 dev_attr */
2192 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2193         .num_chipselect = 4,
2194 };
2195
2196 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2197         .name           = "mcspi1",
2198         .class          = &omap44xx_mcspi_hwmod_class,
2199         .clkdm_name     = "l4_per_clkdm",
2200         .mpu_irqs       = omap44xx_mcspi1_irqs,
2201         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2202         .main_clk       = "mcspi1_fck",
2203         .prcm = {
2204                 .omap4 = {
2205                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2206                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2207                         .modulemode   = MODULEMODE_SWCTRL,
2208                 },
2209         },
2210         .dev_attr       = &mcspi1_dev_attr,
2211 };
2212
2213 /* mcspi2 */
2214 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2215         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2216         { .irq = -1 }
2217 };
2218
2219 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2220         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2221         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2222         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2223         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2224         { .dma_req = -1 }
2225 };
2226
2227 /* mcspi2 dev_attr */
2228 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2229         .num_chipselect = 2,
2230 };
2231
2232 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2233         .name           = "mcspi2",
2234         .class          = &omap44xx_mcspi_hwmod_class,
2235         .clkdm_name     = "l4_per_clkdm",
2236         .mpu_irqs       = omap44xx_mcspi2_irqs,
2237         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2238         .main_clk       = "mcspi2_fck",
2239         .prcm = {
2240                 .omap4 = {
2241                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2242                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2243                         .modulemode   = MODULEMODE_SWCTRL,
2244                 },
2245         },
2246         .dev_attr       = &mcspi2_dev_attr,
2247 };
2248
2249 /* mcspi3 */
2250 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2251         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2252         { .irq = -1 }
2253 };
2254
2255 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2256         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2257         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2258         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2259         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2260         { .dma_req = -1 }
2261 };
2262
2263 /* mcspi3 dev_attr */
2264 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2265         .num_chipselect = 2,
2266 };
2267
2268 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2269         .name           = "mcspi3",
2270         .class          = &omap44xx_mcspi_hwmod_class,
2271         .clkdm_name     = "l4_per_clkdm",
2272         .mpu_irqs       = omap44xx_mcspi3_irqs,
2273         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2274         .main_clk       = "mcspi3_fck",
2275         .prcm = {
2276                 .omap4 = {
2277                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2278                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2279                         .modulemode   = MODULEMODE_SWCTRL,
2280                 },
2281         },
2282         .dev_attr       = &mcspi3_dev_attr,
2283 };
2284
2285 /* mcspi4 */
2286 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2287         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2288         { .irq = -1 }
2289 };
2290
2291 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2292         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2293         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2294         { .dma_req = -1 }
2295 };
2296
2297 /* mcspi4 dev_attr */
2298 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2299         .num_chipselect = 1,
2300 };
2301
2302 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2303         .name           = "mcspi4",
2304         .class          = &omap44xx_mcspi_hwmod_class,
2305         .clkdm_name     = "l4_per_clkdm",
2306         .mpu_irqs       = omap44xx_mcspi4_irqs,
2307         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2308         .main_clk       = "mcspi4_fck",
2309         .prcm = {
2310                 .omap4 = {
2311                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2312                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2313                         .modulemode   = MODULEMODE_SWCTRL,
2314                 },
2315         },
2316         .dev_attr       = &mcspi4_dev_attr,
2317 };
2318
2319 /*
2320  * 'mmc' class
2321  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2322  */
2323
2324 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2325         .rev_offs       = 0x0000,
2326         .sysc_offs      = 0x0010,
2327         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2328                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2329                            SYSC_HAS_SOFTRESET),
2330         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2331                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2332                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2333         .sysc_fields    = &omap_hwmod_sysc_type2,
2334 };
2335
2336 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2337         .name   = "mmc",
2338         .sysc   = &omap44xx_mmc_sysc,
2339 };
2340
2341 /* mmc1 */
2342 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2343         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2344         { .irq = -1 }
2345 };
2346
2347 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2348         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2349         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2350         { .dma_req = -1 }
2351 };
2352
2353 /* mmc1 dev_attr */
2354 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2355         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2356 };
2357
2358 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2359         .name           = "mmc1",
2360         .class          = &omap44xx_mmc_hwmod_class,
2361         .clkdm_name     = "l3_init_clkdm",
2362         .mpu_irqs       = omap44xx_mmc1_irqs,
2363         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2364         .main_clk       = "mmc1_fck",
2365         .prcm = {
2366                 .omap4 = {
2367                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2368                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2369                         .modulemode   = MODULEMODE_SWCTRL,
2370                 },
2371         },
2372         .dev_attr       = &mmc1_dev_attr,
2373 };
2374
2375 /* mmc2 */
2376 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2377         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2378         { .irq = -1 }
2379 };
2380
2381 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2382         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2383         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2384         { .dma_req = -1 }
2385 };
2386
2387 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2388         .name           = "mmc2",
2389         .class          = &omap44xx_mmc_hwmod_class,
2390         .clkdm_name     = "l3_init_clkdm",
2391         .mpu_irqs       = omap44xx_mmc2_irqs,
2392         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2393         .main_clk       = "mmc2_fck",
2394         .prcm = {
2395                 .omap4 = {
2396                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2397                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2398                         .modulemode   = MODULEMODE_SWCTRL,
2399                 },
2400         },
2401 };
2402
2403 /* mmc3 */
2404 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2405         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2406         { .irq = -1 }
2407 };
2408
2409 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2410         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2411         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2412         { .dma_req = -1 }
2413 };
2414
2415 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2416         .name           = "mmc3",
2417         .class          = &omap44xx_mmc_hwmod_class,
2418         .clkdm_name     = "l4_per_clkdm",
2419         .mpu_irqs       = omap44xx_mmc3_irqs,
2420         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2421         .main_clk       = "mmc3_fck",
2422         .prcm = {
2423                 .omap4 = {
2424                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2425                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2426                         .modulemode   = MODULEMODE_SWCTRL,
2427                 },
2428         },
2429 };
2430
2431 /* mmc4 */
2432 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2433         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2434         { .irq = -1 }
2435 };
2436
2437 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2438         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2439         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2440         { .dma_req = -1 }
2441 };
2442
2443 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2444         .name           = "mmc4",
2445         .class          = &omap44xx_mmc_hwmod_class,
2446         .clkdm_name     = "l4_per_clkdm",
2447         .mpu_irqs       = omap44xx_mmc4_irqs,
2448         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2449         .main_clk       = "mmc4_fck",
2450         .prcm = {
2451                 .omap4 = {
2452                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2453                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2454                         .modulemode   = MODULEMODE_SWCTRL,
2455                 },
2456         },
2457 };
2458
2459 /* mmc5 */
2460 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2461         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2462         { .irq = -1 }
2463 };
2464
2465 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2466         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2467         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2468         { .dma_req = -1 }
2469 };
2470
2471 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2472         .name           = "mmc5",
2473         .class          = &omap44xx_mmc_hwmod_class,
2474         .clkdm_name     = "l4_per_clkdm",
2475         .mpu_irqs       = omap44xx_mmc5_irqs,
2476         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2477         .main_clk       = "mmc5_fck",
2478         .prcm = {
2479                 .omap4 = {
2480                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2481                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2482                         .modulemode   = MODULEMODE_SWCTRL,
2483                 },
2484         },
2485 };
2486
2487 /*
2488  * 'mmu' class
2489  * The memory management unit performs virtual to physical address translation
2490  * for its requestors.
2491  */
2492
2493 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2494         .rev_offs       = 0x000,
2495         .sysc_offs      = 0x010,
2496         .syss_offs      = 0x014,
2497         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2498                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2499         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2500         .sysc_fields    = &omap_hwmod_sysc_type1,
2501 };
2502
2503 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2504         .name = "mmu",
2505         .sysc = &mmu_sysc,
2506 };
2507
2508 /* mmu ipu */
2509
2510 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2511         .da_start       = 0x0,
2512         .da_end         = 0xfffff000,
2513         .nr_tlb_entries = 32,
2514 };
2515
2516 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2517 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2518         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2519         { .irq = -1 }
2520 };
2521
2522 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2523         { .name = "mmu_cache", .rst_shift = 2 },
2524 };
2525
2526 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2527         {
2528                 .pa_start       = 0x55082000,
2529                 .pa_end         = 0x550820ff,
2530                 .flags          = ADDR_TYPE_RT,
2531         },
2532         { }
2533 };
2534
2535 /* l3_main_2 -> mmu_ipu */
2536 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2537         .master         = &omap44xx_l3_main_2_hwmod,
2538         .slave          = &omap44xx_mmu_ipu_hwmod,
2539         .clk            = "l3_div_ck",
2540         .addr           = omap44xx_mmu_ipu_addrs,
2541         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2542 };
2543
2544 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2545         .name           = "mmu_ipu",
2546         .class          = &omap44xx_mmu_hwmod_class,
2547         .clkdm_name     = "ducati_clkdm",
2548         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2549         .rst_lines      = omap44xx_mmu_ipu_resets,
2550         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2551         .main_clk       = "ducati_clk_mux_ck",
2552         .prcm = {
2553                 .omap4 = {
2554                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2555                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2556                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2557                         .modulemode   = MODULEMODE_HWCTRL,
2558                 },
2559         },
2560         .dev_attr       = &mmu_ipu_dev_attr,
2561 };
2562
2563 /* mmu dsp */
2564
2565 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2566         .da_start       = 0x0,
2567         .da_end         = 0xfffff000,
2568         .nr_tlb_entries = 32,
2569 };
2570
2571 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2572 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2573         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2574         { .irq = -1 }
2575 };
2576
2577 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2578         { .name = "mmu_cache", .rst_shift = 1 },
2579 };
2580
2581 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2582         {
2583                 .pa_start       = 0x4a066000,
2584                 .pa_end         = 0x4a0660ff,
2585                 .flags          = ADDR_TYPE_RT,
2586         },
2587         { }
2588 };
2589
2590 /* l4_cfg -> dsp */
2591 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2592         .master         = &omap44xx_l4_cfg_hwmod,
2593         .slave          = &omap44xx_mmu_dsp_hwmod,
2594         .clk            = "l4_div_ck",
2595         .addr           = omap44xx_mmu_dsp_addrs,
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2600         .name           = "mmu_dsp",
2601         .class          = &omap44xx_mmu_hwmod_class,
2602         .clkdm_name     = "tesla_clkdm",
2603         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2604         .rst_lines      = omap44xx_mmu_dsp_resets,
2605         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2606         .main_clk       = "dpll_iva_m4x2_ck",
2607         .prcm = {
2608                 .omap4 = {
2609                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2610                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2611                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2612                         .modulemode   = MODULEMODE_HWCTRL,
2613                 },
2614         },
2615         .dev_attr       = &mmu_dsp_dev_attr,
2616 };
2617
2618 /*
2619  * 'mpu' class
2620  * mpu sub-system
2621  */
2622
2623 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2624         .name   = "mpu",
2625 };
2626
2627 /* mpu */
2628 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2629         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2630         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2634         { .irq = -1 }
2635 };
2636
2637 static struct omap_hwmod omap44xx_mpu_hwmod = {
2638         .name           = "mpu",
2639         .class          = &omap44xx_mpu_hwmod_class,
2640         .clkdm_name     = "mpuss_clkdm",
2641         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2642         .mpu_irqs       = omap44xx_mpu_irqs,
2643         .main_clk       = "dpll_mpu_m2_ck",
2644         .prcm = {
2645                 .omap4 = {
2646                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2647                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2648                 },
2649         },
2650 };
2651
2652 /*
2653  * 'ocmc_ram' class
2654  * top-level core on-chip ram
2655  */
2656
2657 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2658         .name   = "ocmc_ram",
2659 };
2660
2661 /* ocmc_ram */
2662 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2663         .name           = "ocmc_ram",
2664         .class          = &omap44xx_ocmc_ram_hwmod_class,
2665         .clkdm_name     = "l3_2_clkdm",
2666         .prcm = {
2667                 .omap4 = {
2668                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2669                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2670                 },
2671         },
2672 };
2673
2674 /*
2675  * 'ocp2scp' class
2676  * bridge to transform ocp interface protocol to scp (serial control port)
2677  * protocol
2678  */
2679
2680 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2681         .rev_offs       = 0x0000,
2682         .sysc_offs      = 0x0010,
2683         .syss_offs      = 0x0014,
2684         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2685                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2687         .sysc_fields    = &omap_hwmod_sysc_type1,
2688 };
2689
2690 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2691         .name   = "ocp2scp",
2692         .sysc   = &omap44xx_ocp2scp_sysc,
2693 };
2694
2695 /* ocp2scp dev_attr */
2696 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2697         {
2698                 .name           = "usb_phy",
2699                 .start          = 0x4a0ad080,
2700                 .end            = 0x4a0ae000,
2701                 .flags          = IORESOURCE_MEM,
2702         },
2703         {
2704                 /* XXX: Remove this once control module driver is in place */
2705                 .name           = "ctrl_dev",
2706                 .start          = 0x4a002300,
2707                 .end            = 0x4a002303,
2708                 .flags          = IORESOURCE_MEM,
2709         },
2710         { }
2711 };
2712
2713 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2714         {
2715                 .drv_name       = "omap-usb2",
2716                 .res            = omap44xx_usb_phy_and_pll_addrs,
2717         },
2718         { }
2719 };
2720
2721 /* ocp2scp_usb_phy */
2722 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2723         .name           = "ocp2scp_usb_phy",
2724         .class          = &omap44xx_ocp2scp_hwmod_class,
2725         .clkdm_name     = "l3_init_clkdm",
2726         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2727         .prcm = {
2728                 .omap4 = {
2729                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2730                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2731                         .modulemode   = MODULEMODE_HWCTRL,
2732                 },
2733         },
2734         .dev_attr       = ocp2scp_dev_attr,
2735 };
2736
2737 /*
2738  * 'prcm' class
2739  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2740  * + clock manager 1 (in always on power domain) + local prm in mpu
2741  */
2742
2743 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2744         .name   = "prcm",
2745 };
2746
2747 /* prcm_mpu */
2748 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2749         .name           = "prcm_mpu",
2750         .class          = &omap44xx_prcm_hwmod_class,
2751         .clkdm_name     = "l4_wkup_clkdm",
2752         .flags          = HWMOD_NO_IDLEST,
2753         .prcm = {
2754                 .omap4 = {
2755                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2756                 },
2757         },
2758 };
2759
2760 /* cm_core_aon */
2761 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2762         .name           = "cm_core_aon",
2763         .class          = &omap44xx_prcm_hwmod_class,
2764         .flags          = HWMOD_NO_IDLEST,
2765         .prcm = {
2766                 .omap4 = {
2767                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2768                 },
2769         },
2770 };
2771
2772 /* cm_core */
2773 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2774         .name           = "cm_core",
2775         .class          = &omap44xx_prcm_hwmod_class,
2776         .flags          = HWMOD_NO_IDLEST,
2777         .prcm = {
2778                 .omap4 = {
2779                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2780                 },
2781         },
2782 };
2783
2784 /* prm */
2785 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2786         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2787         { .irq = -1 }
2788 };
2789
2790 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2791         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2792         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2793 };
2794
2795 static struct omap_hwmod omap44xx_prm_hwmod = {
2796         .name           = "prm",
2797         .class          = &omap44xx_prcm_hwmod_class,
2798         .mpu_irqs       = omap44xx_prm_irqs,
2799         .rst_lines      = omap44xx_prm_resets,
2800         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2801 };
2802
2803 /*
2804  * 'scrm' class
2805  * system clock and reset manager
2806  */
2807
2808 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2809         .name   = "scrm",
2810 };
2811
2812 /* scrm */
2813 static struct omap_hwmod omap44xx_scrm_hwmod = {
2814         .name           = "scrm",
2815         .class          = &omap44xx_scrm_hwmod_class,
2816         .clkdm_name     = "l4_wkup_clkdm",
2817         .prcm = {
2818                 .omap4 = {
2819                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2820                 },
2821         },
2822 };
2823
2824 /*
2825  * 'sl2if' class
2826  * shared level 2 memory interface
2827  */
2828
2829 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2830         .name   = "sl2if",
2831 };
2832
2833 /* sl2if */
2834 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2835         .name           = "sl2if",
2836         .class          = &omap44xx_sl2if_hwmod_class,
2837         .clkdm_name     = "ivahd_clkdm",
2838         .prcm = {
2839                 .omap4 = {
2840                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2841                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2842                         .modulemode   = MODULEMODE_HWCTRL,
2843                 },
2844         },
2845 };
2846
2847 /*
2848  * 'slimbus' class
2849  * bidirectional, multi-drop, multi-channel two-line serial interface between
2850  * the device and external components
2851  */
2852
2853 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2854         .rev_offs       = 0x0000,
2855         .sysc_offs      = 0x0010,
2856         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2857                            SYSC_HAS_SOFTRESET),
2858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2859                            SIDLE_SMART_WKUP),
2860         .sysc_fields    = &omap_hwmod_sysc_type2,
2861 };
2862
2863 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2864         .name   = "slimbus",
2865         .sysc   = &omap44xx_slimbus_sysc,
2866 };
2867
2868 /* slimbus1 */
2869 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2870         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2871         { .irq = -1 }
2872 };
2873
2874 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2875         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2876         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2877         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2878         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2879         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2882         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2883         { .dma_req = -1 }
2884 };
2885
2886 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2887         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2888         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2889         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2890         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2891 };
2892
2893 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2894         .name           = "slimbus1",
2895         .class          = &omap44xx_slimbus_hwmod_class,
2896         .clkdm_name     = "abe_clkdm",
2897         .mpu_irqs       = omap44xx_slimbus1_irqs,
2898         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2899         .prcm = {
2900                 .omap4 = {
2901                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2902                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2903                         .modulemode   = MODULEMODE_SWCTRL,
2904                 },
2905         },
2906         .opt_clks       = slimbus1_opt_clks,
2907         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2908 };
2909
2910 /* slimbus2 */
2911 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2912         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2913         { .irq = -1 }
2914 };
2915
2916 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2917         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2918         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2919         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2920         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2921         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2924         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2925         { .dma_req = -1 }
2926 };
2927
2928 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2929         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2930         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2931         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2932 };
2933
2934 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2935         .name           = "slimbus2",
2936         .class          = &omap44xx_slimbus_hwmod_class,
2937         .clkdm_name     = "l4_per_clkdm",
2938         .mpu_irqs       = omap44xx_slimbus2_irqs,
2939         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2940         .prcm = {
2941                 .omap4 = {
2942                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2943                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2944                         .modulemode   = MODULEMODE_SWCTRL,
2945                 },
2946         },
2947         .opt_clks       = slimbus2_opt_clks,
2948         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2949 };
2950
2951 /*
2952  * 'smartreflex' class
2953  * smartreflex module (monitor silicon performance and outputs a measure of
2954  * performance error)
2955  */
2956
2957 /* The IP is not compliant to type1 / type2 scheme */
2958 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2959         .sidle_shift    = 24,
2960         .enwkup_shift   = 26,
2961 };
2962
2963 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2964         .sysc_offs      = 0x0038,
2965         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2966         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2967                            SIDLE_SMART_WKUP),
2968         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2969 };
2970
2971 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2972         .name   = "smartreflex",
2973         .sysc   = &omap44xx_smartreflex_sysc,
2974         .rev    = 2,
2975 };
2976
2977 /* smartreflex_core */
2978 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2979         .sensor_voltdm_name   = "core",
2980 };
2981
2982 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2983         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2984         { .irq = -1 }
2985 };
2986
2987 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2988         .name           = "smartreflex_core",
2989         .class          = &omap44xx_smartreflex_hwmod_class,
2990         .clkdm_name     = "l4_ao_clkdm",
2991         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2992
2993         .main_clk       = "smartreflex_core_fck",
2994         .prcm = {
2995                 .omap4 = {
2996                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2997                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2998                         .modulemode   = MODULEMODE_SWCTRL,
2999                 },
3000         },
3001         .dev_attr       = &smartreflex_core_dev_attr,
3002 };
3003
3004 /* smartreflex_iva */
3005 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3006         .sensor_voltdm_name     = "iva",
3007 };
3008
3009 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3010         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3011         { .irq = -1 }
3012 };
3013
3014 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3015         .name           = "smartreflex_iva",
3016         .class          = &omap44xx_smartreflex_hwmod_class,
3017         .clkdm_name     = "l4_ao_clkdm",
3018         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3019         .main_clk       = "smartreflex_iva_fck",
3020         .prcm = {
3021                 .omap4 = {
3022                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3023                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3024                         .modulemode   = MODULEMODE_SWCTRL,
3025                 },
3026         },
3027         .dev_attr       = &smartreflex_iva_dev_attr,
3028 };
3029
3030 /* smartreflex_mpu */
3031 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3032         .sensor_voltdm_name     = "mpu",
3033 };
3034
3035 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3036         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3037         { .irq = -1 }
3038 };
3039
3040 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3041         .name           = "smartreflex_mpu",
3042         .class          = &omap44xx_smartreflex_hwmod_class,
3043         .clkdm_name     = "l4_ao_clkdm",
3044         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3045         .main_clk       = "smartreflex_mpu_fck",
3046         .prcm = {
3047                 .omap4 = {
3048                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3049                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3050                         .modulemode   = MODULEMODE_SWCTRL,
3051                 },
3052         },
3053         .dev_attr       = &smartreflex_mpu_dev_attr,
3054 };
3055
3056 /*
3057  * 'spinlock' class
3058  * spinlock provides hardware assistance for synchronizing the processes
3059  * running on multiple processors
3060  */
3061
3062 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3063         .rev_offs       = 0x0000,
3064         .sysc_offs      = 0x0010,
3065         .syss_offs      = 0x0014,
3066         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3067                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3068                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3070                            SIDLE_SMART_WKUP),
3071         .sysc_fields    = &omap_hwmod_sysc_type1,
3072 };
3073
3074 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3075         .name   = "spinlock",
3076         .sysc   = &omap44xx_spinlock_sysc,
3077 };
3078
3079 /* spinlock */
3080 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3081         .name           = "spinlock",
3082         .class          = &omap44xx_spinlock_hwmod_class,
3083         .clkdm_name     = "l4_cfg_clkdm",
3084         .prcm = {
3085                 .omap4 = {
3086                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3087                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3088                 },
3089         },
3090 };
3091
3092 /*
3093  * 'timer' class
3094  * general purpose timer module with accurate 1ms tick
3095  * This class contains several variants: ['timer_1ms', 'timer']
3096  */
3097
3098 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3099         .rev_offs       = 0x0000,
3100         .sysc_offs      = 0x0010,
3101         .syss_offs      = 0x0014,
3102         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3103                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3104                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3105                            SYSS_HAS_RESET_STATUS),
3106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3107         .clockact       = CLOCKACT_TEST_ICLK,
3108         .sysc_fields    = &omap_hwmod_sysc_type1,
3109 };
3110
3111 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3112         .name   = "timer",
3113         .sysc   = &omap44xx_timer_1ms_sysc,
3114 };
3115
3116 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3117         .rev_offs       = 0x0000,
3118         .sysc_offs      = 0x0010,
3119         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3120                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3122                            SIDLE_SMART_WKUP),
3123         .sysc_fields    = &omap_hwmod_sysc_type2,
3124 };
3125
3126 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3127         .name   = "timer",
3128         .sysc   = &omap44xx_timer_sysc,
3129 };
3130
3131 /* always-on timers dev attribute */
3132 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3133         .timer_capability       = OMAP_TIMER_ALWON,
3134 };
3135
3136 /* pwm timers dev attribute */
3137 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3138         .timer_capability       = OMAP_TIMER_HAS_PWM,
3139 };
3140
3141 /* timers with DSP interrupt dev attribute */
3142 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3143         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3144 };
3145
3146 /* pwm timers with DSP interrupt dev attribute */
3147 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3148         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3149 };
3150
3151 /* timer1 */
3152 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3153         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3154         { .irq = -1 }
3155 };
3156
3157 static struct omap_hwmod omap44xx_timer1_hwmod = {
3158         .name           = "timer1",
3159         .class          = &omap44xx_timer_1ms_hwmod_class,
3160         .clkdm_name     = "l4_wkup_clkdm",
3161         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3162         .mpu_irqs       = omap44xx_timer1_irqs,
3163         .main_clk       = "timer1_fck",
3164         .prcm = {
3165                 .omap4 = {
3166                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3167                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3168                         .modulemode   = MODULEMODE_SWCTRL,
3169                 },
3170         },
3171         .dev_attr       = &capability_alwon_dev_attr,
3172 };
3173
3174 /* timer2 */
3175 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3176         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3177         { .irq = -1 }
3178 };
3179
3180 static struct omap_hwmod omap44xx_timer2_hwmod = {
3181         .name           = "timer2",
3182         .class          = &omap44xx_timer_1ms_hwmod_class,
3183         .clkdm_name     = "l4_per_clkdm",
3184         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3185         .mpu_irqs       = omap44xx_timer2_irqs,
3186         .main_clk       = "timer2_fck",
3187         .prcm = {
3188                 .omap4 = {
3189                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3190                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3191                         .modulemode   = MODULEMODE_SWCTRL,
3192                 },
3193         },
3194 };
3195
3196 /* timer3 */
3197 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3198         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3199         { .irq = -1 }
3200 };
3201
3202 static struct omap_hwmod omap44xx_timer3_hwmod = {
3203         .name           = "timer3",
3204         .class          = &omap44xx_timer_hwmod_class,
3205         .clkdm_name     = "l4_per_clkdm",
3206         .mpu_irqs       = omap44xx_timer3_irqs,
3207         .main_clk       = "timer3_fck",
3208         .prcm = {
3209                 .omap4 = {
3210                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3211                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3212                         .modulemode   = MODULEMODE_SWCTRL,
3213                 },
3214         },
3215 };
3216
3217 /* timer4 */
3218 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3219         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3220         { .irq = -1 }
3221 };
3222
3223 static struct omap_hwmod omap44xx_timer4_hwmod = {
3224         .name           = "timer4",
3225         .class          = &omap44xx_timer_hwmod_class,
3226         .clkdm_name     = "l4_per_clkdm",
3227         .mpu_irqs       = omap44xx_timer4_irqs,
3228         .main_clk       = "timer4_fck",
3229         .prcm = {
3230                 .omap4 = {
3231                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3232                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3233                         .modulemode   = MODULEMODE_SWCTRL,
3234                 },
3235         },
3236 };
3237
3238 /* timer5 */
3239 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3240         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3241         { .irq = -1 }
3242 };
3243
3244 static struct omap_hwmod omap44xx_timer5_hwmod = {
3245         .name           = "timer5",
3246         .class          = &omap44xx_timer_hwmod_class,
3247         .clkdm_name     = "abe_clkdm",
3248         .mpu_irqs       = omap44xx_timer5_irqs,
3249         .main_clk       = "timer5_fck",
3250         .prcm = {
3251                 .omap4 = {
3252                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3253                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3254                         .modulemode   = MODULEMODE_SWCTRL,
3255                 },
3256         },
3257         .dev_attr       = &capability_dsp_dev_attr,
3258 };
3259
3260 /* timer6 */
3261 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3262         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3263         { .irq = -1 }
3264 };
3265
3266 static struct omap_hwmod omap44xx_timer6_hwmod = {
3267         .name           = "timer6",
3268         .class          = &omap44xx_timer_hwmod_class,
3269         .clkdm_name     = "abe_clkdm",
3270         .mpu_irqs       = omap44xx_timer6_irqs,
3271
3272         .main_clk       = "timer6_fck",
3273         .prcm = {
3274                 .omap4 = {
3275                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3276                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3277                         .modulemode   = MODULEMODE_SWCTRL,
3278                 },
3279         },
3280         .dev_attr       = &capability_dsp_dev_attr,
3281 };
3282
3283 /* timer7 */
3284 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3285         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3286         { .irq = -1 }
3287 };
3288
3289 static struct omap_hwmod omap44xx_timer7_hwmod = {
3290         .name           = "timer7",
3291         .class          = &omap44xx_timer_hwmod_class,
3292         .clkdm_name     = "abe_clkdm",
3293         .mpu_irqs       = omap44xx_timer7_irqs,
3294         .main_clk       = "timer7_fck",
3295         .prcm = {
3296                 .omap4 = {
3297                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3298                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3299                         .modulemode   = MODULEMODE_SWCTRL,
3300                 },
3301         },
3302         .dev_attr       = &capability_dsp_dev_attr,
3303 };
3304
3305 /* timer8 */
3306 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3307         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3308         { .irq = -1 }
3309 };
3310
3311 static struct omap_hwmod omap44xx_timer8_hwmod = {
3312         .name           = "timer8",
3313         .class          = &omap44xx_timer_hwmod_class,
3314         .clkdm_name     = "abe_clkdm",
3315         .mpu_irqs       = omap44xx_timer8_irqs,
3316         .main_clk       = "timer8_fck",
3317         .prcm = {
3318                 .omap4 = {
3319                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3320                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3321                         .modulemode   = MODULEMODE_SWCTRL,
3322                 },
3323         },
3324         .dev_attr       = &capability_dsp_pwm_dev_attr,
3325 };
3326
3327 /* timer9 */
3328 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3329         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3330         { .irq = -1 }
3331 };
3332
3333 static struct omap_hwmod omap44xx_timer9_hwmod = {
3334         .name           = "timer9",
3335         .class          = &omap44xx_timer_hwmod_class,
3336         .clkdm_name     = "l4_per_clkdm",
3337         .mpu_irqs       = omap44xx_timer9_irqs,
3338         .main_clk       = "timer9_fck",
3339         .prcm = {
3340                 .omap4 = {
3341                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3342                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3343                         .modulemode   = MODULEMODE_SWCTRL,
3344                 },
3345         },
3346         .dev_attr       = &capability_pwm_dev_attr,
3347 };
3348
3349 /* timer10 */
3350 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3351         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3352         { .irq = -1 }
3353 };
3354
3355 static struct omap_hwmod omap44xx_timer10_hwmod = {
3356         .name           = "timer10",
3357         .class          = &omap44xx_timer_1ms_hwmod_class,
3358         .clkdm_name     = "l4_per_clkdm",
3359         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3360         .mpu_irqs       = omap44xx_timer10_irqs,
3361         .main_clk       = "timer10_fck",
3362         .prcm = {
3363                 .omap4 = {
3364                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3365                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3366                         .modulemode   = MODULEMODE_SWCTRL,
3367                 },
3368         },
3369         .dev_attr       = &capability_pwm_dev_attr,
3370 };
3371
3372 /* timer11 */
3373 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3374         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3375         { .irq = -1 }
3376 };
3377
3378 static struct omap_hwmod omap44xx_timer11_hwmod = {
3379         .name           = "timer11",
3380         .class          = &omap44xx_timer_hwmod_class,
3381         .clkdm_name     = "l4_per_clkdm",
3382         .mpu_irqs       = omap44xx_timer11_irqs,
3383         .main_clk       = "timer11_fck",
3384         .prcm = {
3385                 .omap4 = {
3386                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3387                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3388                         .modulemode   = MODULEMODE_SWCTRL,
3389                 },
3390         },
3391         .dev_attr       = &capability_pwm_dev_attr,
3392 };
3393
3394 /*
3395  * 'uart' class
3396  * universal asynchronous receiver/transmitter (uart)
3397  */
3398
3399 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3400         .rev_offs       = 0x0050,
3401         .sysc_offs      = 0x0054,
3402         .syss_offs      = 0x0058,
3403         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3404                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3405                            SYSS_HAS_RESET_STATUS),
3406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3407                            SIDLE_SMART_WKUP),
3408         .sysc_fields    = &omap_hwmod_sysc_type1,
3409 };
3410
3411 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3412         .name   = "uart",
3413         .sysc   = &omap44xx_uart_sysc,
3414 };
3415
3416 /* uart1 */
3417 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3418         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3419         { .irq = -1 }
3420 };
3421
3422 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3423         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3424         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3425         { .dma_req = -1 }
3426 };
3427
3428 static struct omap_hwmod omap44xx_uart1_hwmod = {
3429         .name           = "uart1",
3430         .class          = &omap44xx_uart_hwmod_class,
3431         .clkdm_name     = "l4_per_clkdm",
3432         .mpu_irqs       = omap44xx_uart1_irqs,
3433         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3434         .main_clk       = "uart1_fck",
3435         .prcm = {
3436                 .omap4 = {
3437                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3438                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3439                         .modulemode   = MODULEMODE_SWCTRL,
3440                 },
3441         },
3442 };
3443
3444 /* uart2 */
3445 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3446         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3447         { .irq = -1 }
3448 };
3449
3450 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3451         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3452         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3453         { .dma_req = -1 }
3454 };
3455
3456 static struct omap_hwmod omap44xx_uart2_hwmod = {
3457         .name           = "uart2",
3458         .class          = &omap44xx_uart_hwmod_class,
3459         .clkdm_name     = "l4_per_clkdm",
3460         .mpu_irqs       = omap44xx_uart2_irqs,
3461         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3462         .main_clk       = "uart2_fck",
3463         .prcm = {
3464                 .omap4 = {
3465                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3466                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3467                         .modulemode   = MODULEMODE_SWCTRL,
3468                 },
3469         },
3470 };
3471
3472 /* uart3 */
3473 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3474         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3475         { .irq = -1 }
3476 };
3477
3478 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3479         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3480         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3481         { .dma_req = -1 }
3482 };
3483
3484 static struct omap_hwmod omap44xx_uart3_hwmod = {
3485         .name           = "uart3",
3486         .class          = &omap44xx_uart_hwmod_class,
3487         .clkdm_name     = "l4_per_clkdm",
3488         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3489         .mpu_irqs       = omap44xx_uart3_irqs,
3490         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3491         .main_clk       = "uart3_fck",
3492         .prcm = {
3493                 .omap4 = {
3494                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3495                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3496                         .modulemode   = MODULEMODE_SWCTRL,
3497                 },
3498         },
3499 };
3500
3501 /* uart4 */
3502 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3503         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3504         { .irq = -1 }
3505 };
3506
3507 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3508         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3509         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3510         { .dma_req = -1 }
3511 };
3512
3513 static struct omap_hwmod omap44xx_uart4_hwmod = {
3514         .name           = "uart4",
3515         .class          = &omap44xx_uart_hwmod_class,
3516         .clkdm_name     = "l4_per_clkdm",
3517         .mpu_irqs       = omap44xx_uart4_irqs,
3518         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3519         .main_clk       = "uart4_fck",
3520         .prcm = {
3521                 .omap4 = {
3522                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3523                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3524                         .modulemode   = MODULEMODE_SWCTRL,
3525                 },
3526         },
3527 };
3528
3529 /*
3530  * 'usb_host_fs' class
3531  * full-speed usb host controller
3532  */
3533
3534 /* The IP is not compliant to type1 / type2 scheme */
3535 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3536         .midle_shift    = 4,
3537         .sidle_shift    = 2,
3538         .srst_shift     = 1,
3539 };
3540
3541 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3542         .rev_offs       = 0x0000,
3543         .sysc_offs      = 0x0210,
3544         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3545                            SYSC_HAS_SOFTRESET),
3546         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3547                            SIDLE_SMART_WKUP),
3548         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3549 };
3550
3551 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3552         .name   = "usb_host_fs",
3553         .sysc   = &omap44xx_usb_host_fs_sysc,
3554 };
3555
3556 /* usb_host_fs */
3557 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3558         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3559         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3560         { .irq = -1 }
3561 };
3562
3563 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3564         .name           = "usb_host_fs",
3565         .class          = &omap44xx_usb_host_fs_hwmod_class,
3566         .clkdm_name     = "l3_init_clkdm",
3567         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3568         .main_clk       = "usb_host_fs_fck",
3569         .prcm = {
3570                 .omap4 = {
3571                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3572                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3573                         .modulemode   = MODULEMODE_SWCTRL,
3574                 },
3575         },
3576 };
3577
3578 /*
3579  * 'usb_host_hs' class
3580  * high-speed multi-port usb host controller
3581  */
3582
3583 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3584         .rev_offs       = 0x0000,
3585         .sysc_offs      = 0x0010,
3586         .syss_offs      = 0x0014,
3587         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3588                            SYSC_HAS_SOFTRESET),
3589         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3590                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3591                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3592         .sysc_fields    = &omap_hwmod_sysc_type2,
3593 };
3594
3595 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3596         .name   = "usb_host_hs",
3597         .sysc   = &omap44xx_usb_host_hs_sysc,
3598 };
3599
3600 /* usb_host_hs */
3601 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3602         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3603         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3604         { .irq = -1 }
3605 };
3606
3607 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3608         .name           = "usb_host_hs",
3609         .class          = &omap44xx_usb_host_hs_hwmod_class,
3610         .clkdm_name     = "l3_init_clkdm",
3611         .main_clk       = "usb_host_hs_fck",
3612         .prcm = {
3613                 .omap4 = {
3614                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3615                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3616                         .modulemode   = MODULEMODE_SWCTRL,
3617                 },
3618         },
3619         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3620
3621         /*
3622          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3623          * id: i660
3624          *
3625          * Description:
3626          * In the following configuration :
3627          * - USBHOST module is set to smart-idle mode
3628          * - PRCM asserts idle_req to the USBHOST module ( This typically
3629          *   happens when the system is going to a low power mode : all ports
3630          *   have been suspended, the master part of the USBHOST module has
3631          *   entered the standby state, and SW has cut the functional clocks)
3632          * - an USBHOST interrupt occurs before the module is able to answer
3633          *   idle_ack, typically a remote wakeup IRQ.
3634          * Then the USB HOST module will enter a deadlock situation where it
3635          * is no more accessible nor functional.
3636          *
3637          * Workaround:
3638          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3639          */
3640
3641         /*
3642          * Errata: USB host EHCI may stall when entering smart-standby mode
3643          * Id: i571
3644          *
3645          * Description:
3646          * When the USBHOST module is set to smart-standby mode, and when it is
3647          * ready to enter the standby state (i.e. all ports are suspended and
3648          * all attached devices are in suspend mode), then it can wrongly assert
3649          * the Mstandby signal too early while there are still some residual OCP
3650          * transactions ongoing. If this condition occurs, the internal state
3651          * machine may go to an undefined state and the USB link may be stuck
3652          * upon the next resume.
3653          *
3654          * Workaround:
3655          * Don't use smart standby; use only force standby,
3656          * hence HWMOD_SWSUP_MSTANDBY
3657          */
3658
3659         /*
3660          * During system boot; If the hwmod framework resets the module
3661          * the module will have smart idle settings; which can lead to deadlock
3662          * (above Errata Id:i660); so, dont reset the module during boot;
3663          * Use HWMOD_INIT_NO_RESET.
3664          */
3665
3666         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3667                           HWMOD_INIT_NO_RESET,
3668 };
3669
3670 /*
3671  * 'usb_otg_hs' class
3672  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3673  */
3674
3675 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3676         .rev_offs       = 0x0400,
3677         .sysc_offs      = 0x0404,
3678         .syss_offs      = 0x0408,
3679         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3680                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3681                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3682         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3683                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3684                            MSTANDBY_SMART),
3685         .sysc_fields    = &omap_hwmod_sysc_type1,
3686 };
3687
3688 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3689         .name   = "usb_otg_hs",
3690         .sysc   = &omap44xx_usb_otg_hs_sysc,
3691 };
3692
3693 /* usb_otg_hs */
3694 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3695         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3696         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3697         { .irq = -1 }
3698 };
3699
3700 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3701         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3702 };
3703
3704 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3705         .name           = "usb_otg_hs",
3706         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3707         .clkdm_name     = "l3_init_clkdm",
3708         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3709         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3710         .main_clk       = "usb_otg_hs_ick",
3711         .prcm = {
3712                 .omap4 = {
3713                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3714                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3715                         .modulemode   = MODULEMODE_HWCTRL,
3716                 },
3717         },
3718         .opt_clks       = usb_otg_hs_opt_clks,
3719         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3720 };
3721
3722 /*
3723  * 'usb_tll_hs' class
3724  * usb_tll_hs module is the adapter on the usb_host_hs ports
3725  */
3726
3727 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3728         .rev_offs       = 0x0000,
3729         .sysc_offs      = 0x0010,
3730         .syss_offs      = 0x0014,
3731         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3732                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3733                            SYSC_HAS_AUTOIDLE),
3734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3735         .sysc_fields    = &omap_hwmod_sysc_type1,
3736 };
3737
3738 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3739         .name   = "usb_tll_hs",
3740         .sysc   = &omap44xx_usb_tll_hs_sysc,
3741 };
3742
3743 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3744         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3745         { .irq = -1 }
3746 };
3747
3748 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3749         .name           = "usb_tll_hs",
3750         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3751         .clkdm_name     = "l3_init_clkdm",
3752         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3753         .main_clk       = "usb_tll_hs_ick",
3754         .prcm = {
3755                 .omap4 = {
3756                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3757                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3758                         .modulemode   = MODULEMODE_HWCTRL,
3759                 },
3760         },
3761 };
3762
3763 /*
3764  * 'wd_timer' class
3765  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3766  * overflow condition
3767  */
3768
3769 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3770         .rev_offs       = 0x0000,
3771         .sysc_offs      = 0x0010,
3772         .syss_offs      = 0x0014,
3773         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3774                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3775         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3776                            SIDLE_SMART_WKUP),
3777         .sysc_fields    = &omap_hwmod_sysc_type1,
3778 };
3779
3780 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3781         .name           = "wd_timer",
3782         .sysc           = &omap44xx_wd_timer_sysc,
3783         .pre_shutdown   = &omap2_wd_timer_disable,
3784         .reset          = &omap2_wd_timer_reset,
3785 };
3786
3787 /* wd_timer2 */
3788 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3789         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3790         { .irq = -1 }
3791 };
3792
3793 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3794         .name           = "wd_timer2",
3795         .class          = &omap44xx_wd_timer_hwmod_class,
3796         .clkdm_name     = "l4_wkup_clkdm",
3797         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3798         .main_clk       = "wd_timer2_fck",
3799         .prcm = {
3800                 .omap4 = {
3801                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3802                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3803                         .modulemode   = MODULEMODE_SWCTRL,
3804                 },
3805         },
3806 };
3807
3808 /* wd_timer3 */
3809 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3810         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3811         { .irq = -1 }
3812 };
3813
3814 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3815         .name           = "wd_timer3",
3816         .class          = &omap44xx_wd_timer_hwmod_class,
3817         .clkdm_name     = "abe_clkdm",
3818         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3819         .main_clk       = "wd_timer3_fck",
3820         .prcm = {
3821                 .omap4 = {
3822                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3823                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3824                         .modulemode   = MODULEMODE_SWCTRL,
3825                 },
3826         },
3827 };
3828
3829
3830 /*
3831  * interfaces
3832  */
3833
3834 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3835         {
3836                 .pa_start       = 0x4a204000,
3837                 .pa_end         = 0x4a2040ff,
3838                 .flags          = ADDR_TYPE_RT
3839         },
3840         { }
3841 };
3842
3843 /* c2c -> c2c_target_fw */
3844 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3845         .master         = &omap44xx_c2c_hwmod,
3846         .slave          = &omap44xx_c2c_target_fw_hwmod,
3847         .clk            = "div_core_ck",
3848         .addr           = omap44xx_c2c_target_fw_addrs,
3849         .user           = OCP_USER_MPU,
3850 };
3851
3852 /* l4_cfg -> c2c_target_fw */
3853 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3854         .master         = &omap44xx_l4_cfg_hwmod,
3855         .slave          = &omap44xx_c2c_target_fw_hwmod,
3856         .clk            = "l4_div_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 /* l3_main_1 -> dmm */
3861 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3862         .master         = &omap44xx_l3_main_1_hwmod,
3863         .slave          = &omap44xx_dmm_hwmod,
3864         .clk            = "l3_div_ck",
3865         .user           = OCP_USER_SDMA,
3866 };
3867
3868 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3869         {
3870                 .pa_start       = 0x4e000000,
3871                 .pa_end         = 0x4e0007ff,
3872                 .flags          = ADDR_TYPE_RT
3873         },
3874         { }
3875 };
3876
3877 /* mpu -> dmm */
3878 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3879         .master         = &omap44xx_mpu_hwmod,
3880         .slave          = &omap44xx_dmm_hwmod,
3881         .clk            = "l3_div_ck",
3882         .addr           = omap44xx_dmm_addrs,
3883         .user           = OCP_USER_MPU,
3884 };
3885
3886 /* c2c -> emif_fw */
3887 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3888         .master         = &omap44xx_c2c_hwmod,
3889         .slave          = &omap44xx_emif_fw_hwmod,
3890         .clk            = "div_core_ck",
3891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3892 };
3893
3894 /* dmm -> emif_fw */
3895 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3896         .master         = &omap44xx_dmm_hwmod,
3897         .slave          = &omap44xx_emif_fw_hwmod,
3898         .clk            = "l3_div_ck",
3899         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3900 };
3901
3902 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3903         {
3904                 .pa_start       = 0x4a20c000,
3905                 .pa_end         = 0x4a20c0ff,
3906                 .flags          = ADDR_TYPE_RT
3907         },
3908         { }
3909 };
3910
3911 /* l4_cfg -> emif_fw */
3912 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3913         .master         = &omap44xx_l4_cfg_hwmod,
3914         .slave          = &omap44xx_emif_fw_hwmod,
3915         .clk            = "l4_div_ck",
3916         .addr           = omap44xx_emif_fw_addrs,
3917         .user           = OCP_USER_MPU,
3918 };
3919
3920 /* iva -> l3_instr */
3921 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3922         .master         = &omap44xx_iva_hwmod,
3923         .slave          = &omap44xx_l3_instr_hwmod,
3924         .clk            = "l3_div_ck",
3925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3926 };
3927
3928 /* l3_main_3 -> l3_instr */
3929 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3930         .master         = &omap44xx_l3_main_3_hwmod,
3931         .slave          = &omap44xx_l3_instr_hwmod,
3932         .clk            = "l3_div_ck",
3933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3934 };
3935
3936 /* ocp_wp_noc -> l3_instr */
3937 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3938         .master         = &omap44xx_ocp_wp_noc_hwmod,
3939         .slave          = &omap44xx_l3_instr_hwmod,
3940         .clk            = "l3_div_ck",
3941         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3942 };
3943
3944 /* dsp -> l3_main_1 */
3945 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3946         .master         = &omap44xx_dsp_hwmod,
3947         .slave          = &omap44xx_l3_main_1_hwmod,
3948         .clk            = "l3_div_ck",
3949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3950 };
3951
3952 /* dss -> l3_main_1 */
3953 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3954         .master         = &omap44xx_dss_hwmod,
3955         .slave          = &omap44xx_l3_main_1_hwmod,
3956         .clk            = "l3_div_ck",
3957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3958 };
3959
3960 /* l3_main_2 -> l3_main_1 */
3961 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3962         .master         = &omap44xx_l3_main_2_hwmod,
3963         .slave          = &omap44xx_l3_main_1_hwmod,
3964         .clk            = "l3_div_ck",
3965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3966 };
3967
3968 /* l4_cfg -> l3_main_1 */
3969 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3970         .master         = &omap44xx_l4_cfg_hwmod,
3971         .slave          = &omap44xx_l3_main_1_hwmod,
3972         .clk            = "l4_div_ck",
3973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3974 };
3975
3976 /* mmc1 -> l3_main_1 */
3977 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3978         .master         = &omap44xx_mmc1_hwmod,
3979         .slave          = &omap44xx_l3_main_1_hwmod,
3980         .clk            = "l3_div_ck",
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 /* mmc2 -> l3_main_1 */
3985 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3986         .master         = &omap44xx_mmc2_hwmod,
3987         .slave          = &omap44xx_l3_main_1_hwmod,
3988         .clk            = "l3_div_ck",
3989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3990 };
3991
3992 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3993         {
3994                 .pa_start       = 0x44000000,
3995                 .pa_end         = 0x44000fff,
3996                 .flags          = ADDR_TYPE_RT
3997         },
3998         { }
3999 };
4000
4001 /* mpu -> l3_main_1 */
4002 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4003         .master         = &omap44xx_mpu_hwmod,
4004         .slave          = &omap44xx_l3_main_1_hwmod,
4005         .clk            = "l3_div_ck",
4006         .addr           = omap44xx_l3_main_1_addrs,
4007         .user           = OCP_USER_MPU,
4008 };
4009
4010 /* c2c_target_fw -> l3_main_2 */
4011 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4012         .master         = &omap44xx_c2c_target_fw_hwmod,
4013         .slave          = &omap44xx_l3_main_2_hwmod,
4014         .clk            = "l3_div_ck",
4015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4017
4018 /* debugss -> l3_main_2 */
4019 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4020         .master         = &omap44xx_debugss_hwmod,
4021         .slave          = &omap44xx_l3_main_2_hwmod,
4022         .clk            = "dbgclk_mux_ck",
4023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4025
4026 /* dma_system -> l3_main_2 */
4027 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4028         .master         = &omap44xx_dma_system_hwmod,
4029         .slave          = &omap44xx_l3_main_2_hwmod,
4030         .clk            = "l3_div_ck",
4031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4032 };
4033
4034 /* fdif -> l3_main_2 */
4035 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4036         .master         = &omap44xx_fdif_hwmod,
4037         .slave          = &omap44xx_l3_main_2_hwmod,
4038         .clk            = "l3_div_ck",
4039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4040 };
4041
4042 /* gpu -> l3_main_2 */
4043 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4044         .master         = &omap44xx_gpu_hwmod,
4045         .slave          = &omap44xx_l3_main_2_hwmod,
4046         .clk            = "l3_div_ck",
4047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4048 };
4049
4050 /* hsi -> l3_main_2 */
4051 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4052         .master         = &omap44xx_hsi_hwmod,
4053         .slave          = &omap44xx_l3_main_2_hwmod,
4054         .clk            = "l3_div_ck",
4055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4056 };
4057
4058 /* ipu -> l3_main_2 */
4059 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4060         .master         = &omap44xx_ipu_hwmod,
4061         .slave          = &omap44xx_l3_main_2_hwmod,
4062         .clk            = "l3_div_ck",
4063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4064 };
4065
4066 /* iss -> l3_main_2 */
4067 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4068         .master         = &omap44xx_iss_hwmod,
4069         .slave          = &omap44xx_l3_main_2_hwmod,
4070         .clk            = "l3_div_ck",
4071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* iva -> l3_main_2 */
4075 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4076         .master         = &omap44xx_iva_hwmod,
4077         .slave          = &omap44xx_l3_main_2_hwmod,
4078         .clk            = "l3_div_ck",
4079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4083         {
4084                 .pa_start       = 0x44800000,
4085                 .pa_end         = 0x44801fff,
4086                 .flags          = ADDR_TYPE_RT
4087         },
4088         { }
4089 };
4090
4091 /* l3_main_1 -> l3_main_2 */
4092 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4093         .master         = &omap44xx_l3_main_1_hwmod,
4094         .slave          = &omap44xx_l3_main_2_hwmod,
4095         .clk            = "l3_div_ck",
4096         .addr           = omap44xx_l3_main_2_addrs,
4097         .user           = OCP_USER_MPU,
4098 };
4099
4100 /* l4_cfg -> l3_main_2 */
4101 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4102         .master         = &omap44xx_l4_cfg_hwmod,
4103         .slave          = &omap44xx_l3_main_2_hwmod,
4104         .clk            = "l4_div_ck",
4105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4106 };
4107
4108 /* usb_host_fs -> l3_main_2 */
4109 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4110         .master         = &omap44xx_usb_host_fs_hwmod,
4111         .slave          = &omap44xx_l3_main_2_hwmod,
4112         .clk            = "l3_div_ck",
4113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4115
4116 /* usb_host_hs -> l3_main_2 */
4117 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4118         .master         = &omap44xx_usb_host_hs_hwmod,
4119         .slave          = &omap44xx_l3_main_2_hwmod,
4120         .clk            = "l3_div_ck",
4121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 /* usb_otg_hs -> l3_main_2 */
4125 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4126         .master         = &omap44xx_usb_otg_hs_hwmod,
4127         .slave          = &omap44xx_l3_main_2_hwmod,
4128         .clk            = "l3_div_ck",
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4133         {
4134                 .pa_start       = 0x45000000,
4135                 .pa_end         = 0x45000fff,
4136                 .flags          = ADDR_TYPE_RT
4137         },
4138         { }
4139 };
4140
4141 /* l3_main_1 -> l3_main_3 */
4142 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4143         .master         = &omap44xx_l3_main_1_hwmod,
4144         .slave          = &omap44xx_l3_main_3_hwmod,
4145         .clk            = "l3_div_ck",
4146         .addr           = omap44xx_l3_main_3_addrs,
4147         .user           = OCP_USER_MPU,
4148 };
4149
4150 /* l3_main_2 -> l3_main_3 */
4151 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4152         .master         = &omap44xx_l3_main_2_hwmod,
4153         .slave          = &omap44xx_l3_main_3_hwmod,
4154         .clk            = "l3_div_ck",
4155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4156 };
4157
4158 /* l4_cfg -> l3_main_3 */
4159 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4160         .master         = &omap44xx_l4_cfg_hwmod,
4161         .slave          = &omap44xx_l3_main_3_hwmod,
4162         .clk            = "l4_div_ck",
4163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4164 };
4165
4166 /* aess -> l4_abe */
4167 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4168         .master         = &omap44xx_aess_hwmod,
4169         .slave          = &omap44xx_l4_abe_hwmod,
4170         .clk            = "ocp_abe_iclk",
4171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4172 };
4173
4174 /* dsp -> l4_abe */
4175 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4176         .master         = &omap44xx_dsp_hwmod,
4177         .slave          = &omap44xx_l4_abe_hwmod,
4178         .clk            = "ocp_abe_iclk",
4179         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4180 };
4181
4182 /* l3_main_1 -> l4_abe */
4183 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4184         .master         = &omap44xx_l3_main_1_hwmod,
4185         .slave          = &omap44xx_l4_abe_hwmod,
4186         .clk            = "l3_div_ck",
4187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4188 };
4189
4190 /* mpu -> l4_abe */
4191 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4192         .master         = &omap44xx_mpu_hwmod,
4193         .slave          = &omap44xx_l4_abe_hwmod,
4194         .clk            = "ocp_abe_iclk",
4195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4196 };
4197
4198 /* l3_main_1 -> l4_cfg */
4199 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4200         .master         = &omap44xx_l3_main_1_hwmod,
4201         .slave          = &omap44xx_l4_cfg_hwmod,
4202         .clk            = "l3_div_ck",
4203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4204 };
4205
4206 /* l3_main_2 -> l4_per */
4207 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4208         .master         = &omap44xx_l3_main_2_hwmod,
4209         .slave          = &omap44xx_l4_per_hwmod,
4210         .clk            = "l3_div_ck",
4211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4213
4214 /* l4_cfg -> l4_wkup */
4215 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4216         .master         = &omap44xx_l4_cfg_hwmod,
4217         .slave          = &omap44xx_l4_wkup_hwmod,
4218         .clk            = "l4_div_ck",
4219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4220 };
4221
4222 /* mpu -> mpu_private */
4223 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4224         .master         = &omap44xx_mpu_hwmod,
4225         .slave          = &omap44xx_mpu_private_hwmod,
4226         .clk            = "l3_div_ck",
4227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4228 };
4229
4230 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4231         {
4232                 .pa_start       = 0x4a102000,
4233                 .pa_end         = 0x4a10207f,
4234                 .flags          = ADDR_TYPE_RT
4235         },
4236         { }
4237 };
4238
4239 /* l4_cfg -> ocp_wp_noc */
4240 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4241         .master         = &omap44xx_l4_cfg_hwmod,
4242         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4243         .clk            = "l4_div_ck",
4244         .addr           = omap44xx_ocp_wp_noc_addrs,
4245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4246 };
4247
4248 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4249         {
4250                 .pa_start       = 0x401f1000,
4251                 .pa_end         = 0x401f13ff,
4252                 .flags          = ADDR_TYPE_RT
4253         },
4254         { }
4255 };
4256
4257 /* l4_abe -> aess */
4258 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4259         .master         = &omap44xx_l4_abe_hwmod,
4260         .slave          = &omap44xx_aess_hwmod,
4261         .clk            = "ocp_abe_iclk",
4262         .addr           = omap44xx_aess_addrs,
4263         .user           = OCP_USER_MPU,
4264 };
4265
4266 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4267         {
4268                 .pa_start       = 0x490f1000,
4269                 .pa_end         = 0x490f13ff,
4270                 .flags          = ADDR_TYPE_RT
4271         },
4272         { }
4273 };
4274
4275 /* l4_abe -> aess (dma) */
4276 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4277         .master         = &omap44xx_l4_abe_hwmod,
4278         .slave          = &omap44xx_aess_hwmod,
4279         .clk            = "ocp_abe_iclk",
4280         .addr           = omap44xx_aess_dma_addrs,
4281         .user           = OCP_USER_SDMA,
4282 };
4283
4284 /* l3_main_2 -> c2c */
4285 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4286         .master         = &omap44xx_l3_main_2_hwmod,
4287         .slave          = &omap44xx_c2c_hwmod,
4288         .clk            = "l3_div_ck",
4289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4290 };
4291
4292 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4293         {
4294                 .pa_start       = 0x4a304000,
4295                 .pa_end         = 0x4a30401f,
4296                 .flags          = ADDR_TYPE_RT
4297         },
4298         { }
4299 };
4300
4301 /* l4_wkup -> counter_32k */
4302 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4303         .master         = &omap44xx_l4_wkup_hwmod,
4304         .slave          = &omap44xx_counter_32k_hwmod,
4305         .clk            = "l4_wkup_clk_mux_ck",
4306         .addr           = omap44xx_counter_32k_addrs,
4307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4308 };
4309
4310 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4311         {
4312                 .pa_start       = 0x4a002000,
4313                 .pa_end         = 0x4a0027ff,
4314                 .flags          = ADDR_TYPE_RT
4315         },
4316         { }
4317 };
4318
4319 /* l4_cfg -> ctrl_module_core */
4320 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4321         .master         = &omap44xx_l4_cfg_hwmod,
4322         .slave          = &omap44xx_ctrl_module_core_hwmod,
4323         .clk            = "l4_div_ck",
4324         .addr           = omap44xx_ctrl_module_core_addrs,
4325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4326 };
4327
4328 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4329         {
4330                 .pa_start       = 0x4a100000,
4331                 .pa_end         = 0x4a1007ff,
4332                 .flags          = ADDR_TYPE_RT
4333         },
4334         { }
4335 };
4336
4337 /* l4_cfg -> ctrl_module_pad_core */
4338 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4339         .master         = &omap44xx_l4_cfg_hwmod,
4340         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4341         .clk            = "l4_div_ck",
4342         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4344 };
4345
4346 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4347         {
4348                 .pa_start       = 0x4a30c000,
4349                 .pa_end         = 0x4a30c7ff,
4350                 .flags          = ADDR_TYPE_RT
4351         },
4352         { }
4353 };
4354
4355 /* l4_wkup -> ctrl_module_wkup */
4356 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4357         .master         = &omap44xx_l4_wkup_hwmod,
4358         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4359         .clk            = "l4_wkup_clk_mux_ck",
4360         .addr           = omap44xx_ctrl_module_wkup_addrs,
4361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4362 };
4363
4364 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4365         {
4366                 .pa_start       = 0x4a31e000,
4367                 .pa_end         = 0x4a31e7ff,
4368                 .flags          = ADDR_TYPE_RT
4369         },
4370         { }
4371 };
4372
4373 /* l4_wkup -> ctrl_module_pad_wkup */
4374 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4375         .master         = &omap44xx_l4_wkup_hwmod,
4376         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4377         .clk            = "l4_wkup_clk_mux_ck",
4378         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4380 };
4381
4382 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4383         {
4384                 .pa_start       = 0x54160000,
4385                 .pa_end         = 0x54167fff,
4386                 .flags          = ADDR_TYPE_RT
4387         },
4388         { }
4389 };
4390
4391 /* l3_instr -> debugss */
4392 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4393         .master         = &omap44xx_l3_instr_hwmod,
4394         .slave          = &omap44xx_debugss_hwmod,
4395         .clk            = "l3_div_ck",
4396         .addr           = omap44xx_debugss_addrs,
4397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4398 };
4399
4400 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4401         {
4402                 .pa_start       = 0x4a056000,
4403                 .pa_end         = 0x4a056fff,
4404                 .flags          = ADDR_TYPE_RT
4405         },
4406         { }
4407 };
4408
4409 /* l4_cfg -> dma_system */
4410 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4411         .master         = &omap44xx_l4_cfg_hwmod,
4412         .slave          = &omap44xx_dma_system_hwmod,
4413         .clk            = "l4_div_ck",
4414         .addr           = omap44xx_dma_system_addrs,
4415         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4416 };
4417
4418 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4419         {
4420                 .name           = "mpu",
4421                 .pa_start       = 0x4012e000,
4422                 .pa_end         = 0x4012e07f,
4423                 .flags          = ADDR_TYPE_RT
4424         },
4425         { }
4426 };
4427
4428 /* l4_abe -> dmic */
4429 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4430         .master         = &omap44xx_l4_abe_hwmod,
4431         .slave          = &omap44xx_dmic_hwmod,
4432         .clk            = "ocp_abe_iclk",
4433         .addr           = omap44xx_dmic_addrs,
4434         .user           = OCP_USER_MPU,
4435 };
4436
4437 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4438         {
4439                 .name           = "dma",
4440                 .pa_start       = 0x4902e000,
4441                 .pa_end         = 0x4902e07f,
4442                 .flags          = ADDR_TYPE_RT
4443         },
4444         { }
4445 };
4446
4447 /* l4_abe -> dmic (dma) */
4448 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4449         .master         = &omap44xx_l4_abe_hwmod,
4450         .slave          = &omap44xx_dmic_hwmod,
4451         .clk            = "ocp_abe_iclk",
4452         .addr           = omap44xx_dmic_dma_addrs,
4453         .user           = OCP_USER_SDMA,
4454 };
4455
4456 /* dsp -> iva */
4457 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4458         .master         = &omap44xx_dsp_hwmod,
4459         .slave          = &omap44xx_iva_hwmod,
4460         .clk            = "dpll_iva_m5x2_ck",
4461         .user           = OCP_USER_DSP,
4462 };
4463
4464 /* dsp -> sl2if */
4465 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4466         .master         = &omap44xx_dsp_hwmod,
4467         .slave          = &omap44xx_sl2if_hwmod,
4468         .clk            = "dpll_iva_m5x2_ck",
4469         .user           = OCP_USER_DSP,
4470 };
4471
4472 /* l4_cfg -> dsp */
4473 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4474         .master         = &omap44xx_l4_cfg_hwmod,
4475         .slave          = &omap44xx_dsp_hwmod,
4476         .clk            = "l4_div_ck",
4477         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4478 };
4479
4480 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4481         {
4482                 .pa_start       = 0x58000000,
4483                 .pa_end         = 0x5800007f,
4484                 .flags          = ADDR_TYPE_RT
4485         },
4486         { }
4487 };
4488
4489 /* l3_main_2 -> dss */
4490 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4491         .master         = &omap44xx_l3_main_2_hwmod,
4492         .slave          = &omap44xx_dss_hwmod,
4493         .clk            = "dss_fck",
4494         .addr           = omap44xx_dss_dma_addrs,
4495         .user           = OCP_USER_SDMA,
4496 };
4497
4498 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4499         {
4500                 .pa_start       = 0x48040000,
4501                 .pa_end         = 0x4804007f,
4502                 .flags          = ADDR_TYPE_RT
4503         },
4504         { }
4505 };
4506
4507 /* l4_per -> dss */
4508 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4509         .master         = &omap44xx_l4_per_hwmod,
4510         .slave          = &omap44xx_dss_hwmod,
4511         .clk            = "l4_div_ck",
4512         .addr           = omap44xx_dss_addrs,
4513         .user           = OCP_USER_MPU,
4514 };
4515
4516 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4517         {
4518                 .pa_start       = 0x58001000,
4519                 .pa_end         = 0x58001fff,
4520                 .flags          = ADDR_TYPE_RT
4521         },
4522         { }
4523 };
4524
4525 /* l3_main_2 -> dss_dispc */
4526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4527         .master         = &omap44xx_l3_main_2_hwmod,
4528         .slave          = &omap44xx_dss_dispc_hwmod,
4529         .clk            = "dss_fck",
4530         .addr           = omap44xx_dss_dispc_dma_addrs,
4531         .user           = OCP_USER_SDMA,
4532 };
4533
4534 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4535         {
4536                 .pa_start       = 0x48041000,
4537                 .pa_end         = 0x48041fff,
4538                 .flags          = ADDR_TYPE_RT
4539         },
4540         { }
4541 };
4542
4543 /* l4_per -> dss_dispc */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4545         .master         = &omap44xx_l4_per_hwmod,
4546         .slave          = &omap44xx_dss_dispc_hwmod,
4547         .clk            = "l4_div_ck",
4548         .addr           = omap44xx_dss_dispc_addrs,
4549         .user           = OCP_USER_MPU,
4550 };
4551
4552 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4553         {
4554                 .pa_start       = 0x58004000,
4555                 .pa_end         = 0x580041ff,
4556                 .flags          = ADDR_TYPE_RT
4557         },
4558         { }
4559 };
4560
4561 /* l3_main_2 -> dss_dsi1 */
4562 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4563         .master         = &omap44xx_l3_main_2_hwmod,
4564         .slave          = &omap44xx_dss_dsi1_hwmod,
4565         .clk            = "dss_fck",
4566         .addr           = omap44xx_dss_dsi1_dma_addrs,
4567         .user           = OCP_USER_SDMA,
4568 };
4569
4570 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4571         {
4572                 .pa_start       = 0x48044000,
4573                 .pa_end         = 0x480441ff,
4574                 .flags          = ADDR_TYPE_RT
4575         },
4576         { }
4577 };
4578
4579 /* l4_per -> dss_dsi1 */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4581         .master         = &omap44xx_l4_per_hwmod,
4582         .slave          = &omap44xx_dss_dsi1_hwmod,
4583         .clk            = "l4_div_ck",
4584         .addr           = omap44xx_dss_dsi1_addrs,
4585         .user           = OCP_USER_MPU,
4586 };
4587
4588 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4589         {
4590                 .pa_start       = 0x58005000,
4591                 .pa_end         = 0x580051ff,
4592                 .flags          = ADDR_TYPE_RT
4593         },
4594         { }
4595 };
4596
4597 /* l3_main_2 -> dss_dsi2 */
4598 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4599         .master         = &omap44xx_l3_main_2_hwmod,
4600         .slave          = &omap44xx_dss_dsi2_hwmod,
4601         .clk            = "dss_fck",
4602         .addr           = omap44xx_dss_dsi2_dma_addrs,
4603         .user           = OCP_USER_SDMA,
4604 };
4605
4606 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4607         {
4608                 .pa_start       = 0x48045000,
4609                 .pa_end         = 0x480451ff,
4610                 .flags          = ADDR_TYPE_RT
4611         },
4612         { }
4613 };
4614
4615 /* l4_per -> dss_dsi2 */
4616 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4617         .master         = &omap44xx_l4_per_hwmod,
4618         .slave          = &omap44xx_dss_dsi2_hwmod,
4619         .clk            = "l4_div_ck",
4620         .addr           = omap44xx_dss_dsi2_addrs,
4621         .user           = OCP_USER_MPU,
4622 };
4623
4624 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4625         {
4626                 .pa_start       = 0x58006000,
4627                 .pa_end         = 0x58006fff,
4628                 .flags          = ADDR_TYPE_RT
4629         },
4630         { }
4631 };
4632
4633 /* l3_main_2 -> dss_hdmi */
4634 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4635         .master         = &omap44xx_l3_main_2_hwmod,
4636         .slave          = &omap44xx_dss_hdmi_hwmod,
4637         .clk            = "dss_fck",
4638         .addr           = omap44xx_dss_hdmi_dma_addrs,
4639         .user           = OCP_USER_SDMA,
4640 };
4641
4642 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4643         {
4644                 .pa_start       = 0x48046000,
4645                 .pa_end         = 0x48046fff,
4646                 .flags          = ADDR_TYPE_RT
4647         },
4648         { }
4649 };
4650
4651 /* l4_per -> dss_hdmi */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4653         .master         = &omap44xx_l4_per_hwmod,
4654         .slave          = &omap44xx_dss_hdmi_hwmod,
4655         .clk            = "l4_div_ck",
4656         .addr           = omap44xx_dss_hdmi_addrs,
4657         .user           = OCP_USER_MPU,
4658 };
4659
4660 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4661         {
4662                 .pa_start       = 0x58002000,
4663                 .pa_end         = 0x580020ff,
4664                 .flags          = ADDR_TYPE_RT
4665         },
4666         { }
4667 };
4668
4669 /* l3_main_2 -> dss_rfbi */
4670 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4671         .master         = &omap44xx_l3_main_2_hwmod,
4672         .slave          = &omap44xx_dss_rfbi_hwmod,
4673         .clk            = "dss_fck",
4674         .addr           = omap44xx_dss_rfbi_dma_addrs,
4675         .user           = OCP_USER_SDMA,
4676 };
4677
4678 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4679         {
4680                 .pa_start       = 0x48042000,
4681                 .pa_end         = 0x480420ff,
4682                 .flags          = ADDR_TYPE_RT
4683         },
4684         { }
4685 };
4686
4687 /* l4_per -> dss_rfbi */
4688 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4689         .master         = &omap44xx_l4_per_hwmod,
4690         .slave          = &omap44xx_dss_rfbi_hwmod,
4691         .clk            = "l4_div_ck",
4692         .addr           = omap44xx_dss_rfbi_addrs,
4693         .user           = OCP_USER_MPU,
4694 };
4695
4696 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4697         {
4698                 .pa_start       = 0x58003000,
4699                 .pa_end         = 0x580030ff,
4700                 .flags          = ADDR_TYPE_RT
4701         },
4702         { }
4703 };
4704
4705 /* l3_main_2 -> dss_venc */
4706 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4707         .master         = &omap44xx_l3_main_2_hwmod,
4708         .slave          = &omap44xx_dss_venc_hwmod,
4709         .clk            = "dss_fck",
4710         .addr           = omap44xx_dss_venc_dma_addrs,
4711         .user           = OCP_USER_SDMA,
4712 };
4713
4714 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4715         {
4716                 .pa_start       = 0x48043000,
4717                 .pa_end         = 0x480430ff,
4718                 .flags          = ADDR_TYPE_RT
4719         },
4720         { }
4721 };
4722
4723 /* l4_per -> dss_venc */
4724 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4725         .master         = &omap44xx_l4_per_hwmod,
4726         .slave          = &omap44xx_dss_venc_hwmod,
4727         .clk            = "l4_div_ck",
4728         .addr           = omap44xx_dss_venc_addrs,
4729         .user           = OCP_USER_MPU,
4730 };
4731
4732 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4733         {
4734                 .pa_start       = 0x48078000,
4735                 .pa_end         = 0x48078fff,
4736                 .flags          = ADDR_TYPE_RT
4737         },
4738         { }
4739 };
4740
4741 /* l4_per -> elm */
4742 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4743         .master         = &omap44xx_l4_per_hwmod,
4744         .slave          = &omap44xx_elm_hwmod,
4745         .clk            = "l4_div_ck",
4746         .addr           = omap44xx_elm_addrs,
4747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4748 };
4749
4750 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4751         {
4752                 .pa_start       = 0x4c000000,
4753                 .pa_end         = 0x4c0000ff,
4754                 .flags          = ADDR_TYPE_RT
4755         },
4756         { }
4757 };
4758
4759 /* emif_fw -> emif1 */
4760 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4761         .master         = &omap44xx_emif_fw_hwmod,
4762         .slave          = &omap44xx_emif1_hwmod,
4763         .clk            = "l3_div_ck",
4764         .addr           = omap44xx_emif1_addrs,
4765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4766 };
4767
4768 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4769         {
4770                 .pa_start       = 0x4d000000,
4771                 .pa_end         = 0x4d0000ff,
4772                 .flags          = ADDR_TYPE_RT
4773         },
4774         { }
4775 };
4776
4777 /* emif_fw -> emif2 */
4778 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4779         .master         = &omap44xx_emif_fw_hwmod,
4780         .slave          = &omap44xx_emif2_hwmod,
4781         .clk            = "l3_div_ck",
4782         .addr           = omap44xx_emif2_addrs,
4783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4784 };
4785
4786 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4787         {
4788                 .pa_start       = 0x4a10a000,
4789                 .pa_end         = 0x4a10a1ff,
4790                 .flags          = ADDR_TYPE_RT
4791         },
4792         { }
4793 };
4794
4795 /* l4_cfg -> fdif */
4796 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4797         .master         = &omap44xx_l4_cfg_hwmod,
4798         .slave          = &omap44xx_fdif_hwmod,
4799         .clk            = "l4_div_ck",
4800         .addr           = omap44xx_fdif_addrs,
4801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4802 };
4803
4804 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4805         {
4806                 .pa_start       = 0x4a310000,
4807                 .pa_end         = 0x4a3101ff,
4808                 .flags          = ADDR_TYPE_RT
4809         },
4810         { }
4811 };
4812
4813 /* l4_wkup -> gpio1 */
4814 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4815         .master         = &omap44xx_l4_wkup_hwmod,
4816         .slave          = &omap44xx_gpio1_hwmod,
4817         .clk            = "l4_wkup_clk_mux_ck",
4818         .addr           = omap44xx_gpio1_addrs,
4819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4820 };
4821
4822 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4823         {
4824                 .pa_start       = 0x48055000,
4825                 .pa_end         = 0x480551ff,
4826                 .flags          = ADDR_TYPE_RT
4827         },
4828         { }
4829 };
4830
4831 /* l4_per -> gpio2 */
4832 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4833         .master         = &omap44xx_l4_per_hwmod,
4834         .slave          = &omap44xx_gpio2_hwmod,
4835         .clk            = "l4_div_ck",
4836         .addr           = omap44xx_gpio2_addrs,
4837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4838 };
4839
4840 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4841         {
4842                 .pa_start       = 0x48057000,
4843                 .pa_end         = 0x480571ff,
4844                 .flags          = ADDR_TYPE_RT
4845         },
4846         { }
4847 };
4848
4849 /* l4_per -> gpio3 */
4850 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4851         .master         = &omap44xx_l4_per_hwmod,
4852         .slave          = &omap44xx_gpio3_hwmod,
4853         .clk            = "l4_div_ck",
4854         .addr           = omap44xx_gpio3_addrs,
4855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4856 };
4857
4858 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4859         {
4860                 .pa_start       = 0x48059000,
4861                 .pa_end         = 0x480591ff,
4862                 .flags          = ADDR_TYPE_RT
4863         },
4864         { }
4865 };
4866
4867 /* l4_per -> gpio4 */
4868 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4869         .master         = &omap44xx_l4_per_hwmod,
4870         .slave          = &omap44xx_gpio4_hwmod,
4871         .clk            = "l4_div_ck",
4872         .addr           = omap44xx_gpio4_addrs,
4873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4874 };
4875
4876 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4877         {
4878                 .pa_start       = 0x4805b000,
4879                 .pa_end         = 0x4805b1ff,
4880                 .flags          = ADDR_TYPE_RT
4881         },
4882         { }
4883 };
4884
4885 /* l4_per -> gpio5 */
4886 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4887         .master         = &omap44xx_l4_per_hwmod,
4888         .slave          = &omap44xx_gpio5_hwmod,
4889         .clk            = "l4_div_ck",
4890         .addr           = omap44xx_gpio5_addrs,
4891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4892 };
4893
4894 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4895         {
4896                 .pa_start       = 0x4805d000,
4897                 .pa_end         = 0x4805d1ff,
4898                 .flags          = ADDR_TYPE_RT
4899         },
4900         { }
4901 };
4902
4903 /* l4_per -> gpio6 */
4904 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4905         .master         = &omap44xx_l4_per_hwmod,
4906         .slave          = &omap44xx_gpio6_hwmod,
4907         .clk            = "l4_div_ck",
4908         .addr           = omap44xx_gpio6_addrs,
4909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4910 };
4911
4912 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4913         {
4914                 .pa_start       = 0x50000000,
4915                 .pa_end         = 0x500003ff,
4916                 .flags          = ADDR_TYPE_RT
4917         },
4918         { }
4919 };
4920
4921 /* l3_main_2 -> gpmc */
4922 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4923         .master         = &omap44xx_l3_main_2_hwmod,
4924         .slave          = &omap44xx_gpmc_hwmod,
4925         .clk            = "l3_div_ck",
4926         .addr           = omap44xx_gpmc_addrs,
4927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4928 };
4929
4930 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4931         {
4932                 .pa_start       = 0x56000000,
4933                 .pa_end         = 0x5600ffff,
4934                 .flags          = ADDR_TYPE_RT
4935         },
4936         { }
4937 };
4938
4939 /* l3_main_2 -> gpu */
4940 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4941         .master         = &omap44xx_l3_main_2_hwmod,
4942         .slave          = &omap44xx_gpu_hwmod,
4943         .clk            = "l3_div_ck",
4944         .addr           = omap44xx_gpu_addrs,
4945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4946 };
4947
4948 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4949         {
4950                 .pa_start       = 0x480b2000,
4951                 .pa_end         = 0x480b201f,
4952                 .flags          = ADDR_TYPE_RT
4953         },
4954         { }
4955 };
4956
4957 /* l4_per -> hdq1w */
4958 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4959         .master         = &omap44xx_l4_per_hwmod,
4960         .slave          = &omap44xx_hdq1w_hwmod,
4961         .clk            = "l4_div_ck",
4962         .addr           = omap44xx_hdq1w_addrs,
4963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4964 };
4965
4966 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4967         {
4968                 .pa_start       = 0x4a058000,
4969                 .pa_end         = 0x4a05bfff,
4970                 .flags          = ADDR_TYPE_RT
4971         },
4972         { }
4973 };
4974
4975 /* l4_cfg -> hsi */
4976 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4977         .master         = &omap44xx_l4_cfg_hwmod,
4978         .slave          = &omap44xx_hsi_hwmod,
4979         .clk            = "l4_div_ck",
4980         .addr           = omap44xx_hsi_addrs,
4981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4982 };
4983
4984 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4985         {
4986                 .pa_start       = 0x48070000,
4987                 .pa_end         = 0x480700ff,
4988                 .flags          = ADDR_TYPE_RT
4989         },
4990         { }
4991 };
4992
4993 /* l4_per -> i2c1 */
4994 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4995         .master         = &omap44xx_l4_per_hwmod,
4996         .slave          = &omap44xx_i2c1_hwmod,
4997         .clk            = "l4_div_ck",
4998         .addr           = omap44xx_i2c1_addrs,
4999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5000 };
5001
5002 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5003         {
5004                 .pa_start       = 0x48072000,
5005                 .pa_end         = 0x480720ff,
5006                 .flags          = ADDR_TYPE_RT
5007         },
5008         { }
5009 };
5010
5011 /* l4_per -> i2c2 */
5012 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5013         .master         = &omap44xx_l4_per_hwmod,
5014         .slave          = &omap44xx_i2c2_hwmod,
5015         .clk            = "l4_div_ck",
5016         .addr           = omap44xx_i2c2_addrs,
5017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5018 };
5019
5020 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5021         {
5022                 .pa_start       = 0x48060000,
5023                 .pa_end         = 0x480600ff,
5024                 .flags          = ADDR_TYPE_RT
5025         },
5026         { }
5027 };
5028
5029 /* l4_per -> i2c3 */
5030 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5031         .master         = &omap44xx_l4_per_hwmod,
5032         .slave          = &omap44xx_i2c3_hwmod,
5033         .clk            = "l4_div_ck",
5034         .addr           = omap44xx_i2c3_addrs,
5035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5036 };
5037
5038 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5039         {
5040                 .pa_start       = 0x48350000,
5041                 .pa_end         = 0x483500ff,
5042                 .flags          = ADDR_TYPE_RT
5043         },
5044         { }
5045 };
5046
5047 /* l4_per -> i2c4 */
5048 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5049         .master         = &omap44xx_l4_per_hwmod,
5050         .slave          = &omap44xx_i2c4_hwmod,
5051         .clk            = "l4_div_ck",
5052         .addr           = omap44xx_i2c4_addrs,
5053         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5054 };
5055
5056 /* l3_main_2 -> ipu */
5057 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5058         .master         = &omap44xx_l3_main_2_hwmod,
5059         .slave          = &omap44xx_ipu_hwmod,
5060         .clk            = "l3_div_ck",
5061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5062 };
5063
5064 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5065         {
5066                 .pa_start       = 0x52000000,
5067                 .pa_end         = 0x520000ff,
5068                 .flags          = ADDR_TYPE_RT
5069         },
5070         { }
5071 };
5072
5073 /* l3_main_2 -> iss */
5074 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5075         .master         = &omap44xx_l3_main_2_hwmod,
5076         .slave          = &omap44xx_iss_hwmod,
5077         .clk            = "l3_div_ck",
5078         .addr           = omap44xx_iss_addrs,
5079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5080 };
5081
5082 /* iva -> sl2if */
5083 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5084         .master         = &omap44xx_iva_hwmod,
5085         .slave          = &omap44xx_sl2if_hwmod,
5086         .clk            = "dpll_iva_m5x2_ck",
5087         .user           = OCP_USER_IVA,
5088 };
5089
5090 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5091         {
5092                 .pa_start       = 0x5a000000,
5093                 .pa_end         = 0x5a07ffff,
5094                 .flags          = ADDR_TYPE_RT
5095         },
5096         { }
5097 };
5098
5099 /* l3_main_2 -> iva */
5100 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5101         .master         = &omap44xx_l3_main_2_hwmod,
5102         .slave          = &omap44xx_iva_hwmod,
5103         .clk            = "l3_div_ck",
5104         .addr           = omap44xx_iva_addrs,
5105         .user           = OCP_USER_MPU,
5106 };
5107
5108 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5109         {
5110                 .pa_start       = 0x4a31c000,
5111                 .pa_end         = 0x4a31c07f,
5112                 .flags          = ADDR_TYPE_RT
5113         },
5114         { }
5115 };
5116
5117 /* l4_wkup -> kbd */
5118 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5119         .master         = &omap44xx_l4_wkup_hwmod,
5120         .slave          = &omap44xx_kbd_hwmod,
5121         .clk            = "l4_wkup_clk_mux_ck",
5122         .addr           = omap44xx_kbd_addrs,
5123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5124 };
5125
5126 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5127         {
5128                 .pa_start       = 0x4a0f4000,
5129                 .pa_end         = 0x4a0f41ff,
5130                 .flags          = ADDR_TYPE_RT
5131         },
5132         { }
5133 };
5134
5135 /* l4_cfg -> mailbox */
5136 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5137         .master         = &omap44xx_l4_cfg_hwmod,
5138         .slave          = &omap44xx_mailbox_hwmod,
5139         .clk            = "l4_div_ck",
5140         .addr           = omap44xx_mailbox_addrs,
5141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5142 };
5143
5144 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5145         {
5146                 .pa_start       = 0x40128000,
5147                 .pa_end         = 0x401283ff,
5148                 .flags          = ADDR_TYPE_RT
5149         },
5150         { }
5151 };
5152
5153 /* l4_abe -> mcasp */
5154 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5155         .master         = &omap44xx_l4_abe_hwmod,
5156         .slave          = &omap44xx_mcasp_hwmod,
5157         .clk            = "ocp_abe_iclk",
5158         .addr           = omap44xx_mcasp_addrs,
5159         .user           = OCP_USER_MPU,
5160 };
5161
5162 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5163         {
5164                 .pa_start       = 0x49028000,
5165                 .pa_end         = 0x490283ff,
5166                 .flags          = ADDR_TYPE_RT
5167         },
5168         { }
5169 };
5170
5171 /* l4_abe -> mcasp (dma) */
5172 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5173         .master         = &omap44xx_l4_abe_hwmod,
5174         .slave          = &omap44xx_mcasp_hwmod,
5175         .clk            = "ocp_abe_iclk",
5176         .addr           = omap44xx_mcasp_dma_addrs,
5177         .user           = OCP_USER_SDMA,
5178 };
5179
5180 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5181         {
5182                 .name           = "mpu",
5183                 .pa_start       = 0x40122000,
5184                 .pa_end         = 0x401220ff,
5185                 .flags          = ADDR_TYPE_RT
5186         },
5187         { }
5188 };
5189
5190 /* l4_abe -> mcbsp1 */
5191 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5192         .master         = &omap44xx_l4_abe_hwmod,
5193         .slave          = &omap44xx_mcbsp1_hwmod,
5194         .clk            = "ocp_abe_iclk",
5195         .addr           = omap44xx_mcbsp1_addrs,
5196         .user           = OCP_USER_MPU,
5197 };
5198
5199 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5200         {
5201                 .name           = "dma",
5202                 .pa_start       = 0x49022000,
5203                 .pa_end         = 0x490220ff,
5204                 .flags          = ADDR_TYPE_RT
5205         },
5206         { }
5207 };
5208
5209 /* l4_abe -> mcbsp1 (dma) */
5210 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5211         .master         = &omap44xx_l4_abe_hwmod,
5212         .slave          = &omap44xx_mcbsp1_hwmod,
5213         .clk            = "ocp_abe_iclk",
5214         .addr           = omap44xx_mcbsp1_dma_addrs,
5215         .user           = OCP_USER_SDMA,
5216 };
5217
5218 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5219         {
5220                 .name           = "mpu",
5221                 .pa_start       = 0x40124000,
5222                 .pa_end         = 0x401240ff,
5223                 .flags          = ADDR_TYPE_RT
5224         },
5225         { }
5226 };
5227
5228 /* l4_abe -> mcbsp2 */
5229 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5230         .master         = &omap44xx_l4_abe_hwmod,
5231         .slave          = &omap44xx_mcbsp2_hwmod,
5232         .clk            = "ocp_abe_iclk",
5233         .addr           = omap44xx_mcbsp2_addrs,
5234         .user           = OCP_USER_MPU,
5235 };
5236
5237 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5238         {
5239                 .name           = "dma",
5240                 .pa_start       = 0x49024000,
5241                 .pa_end         = 0x490240ff,
5242                 .flags          = ADDR_TYPE_RT
5243         },
5244         { }
5245 };
5246
5247 /* l4_abe -> mcbsp2 (dma) */
5248 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5249         .master         = &omap44xx_l4_abe_hwmod,
5250         .slave          = &omap44xx_mcbsp2_hwmod,
5251         .clk            = "ocp_abe_iclk",
5252         .addr           = omap44xx_mcbsp2_dma_addrs,
5253         .user           = OCP_USER_SDMA,
5254 };
5255
5256 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5257         {
5258                 .name           = "mpu",
5259                 .pa_start       = 0x40126000,
5260                 .pa_end         = 0x401260ff,
5261                 .flags          = ADDR_TYPE_RT
5262         },
5263         { }
5264 };
5265
5266 /* l4_abe -> mcbsp3 */
5267 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5268         .master         = &omap44xx_l4_abe_hwmod,
5269         .slave          = &omap44xx_mcbsp3_hwmod,
5270         .clk            = "ocp_abe_iclk",
5271         .addr           = omap44xx_mcbsp3_addrs,
5272         .user           = OCP_USER_MPU,
5273 };
5274
5275 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5276         {
5277                 .name           = "dma",
5278                 .pa_start       = 0x49026000,
5279                 .pa_end         = 0x490260ff,
5280                 .flags          = ADDR_TYPE_RT
5281         },
5282         { }
5283 };
5284
5285 /* l4_abe -> mcbsp3 (dma) */
5286 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5287         .master         = &omap44xx_l4_abe_hwmod,
5288         .slave          = &omap44xx_mcbsp3_hwmod,
5289         .clk            = "ocp_abe_iclk",
5290         .addr           = omap44xx_mcbsp3_dma_addrs,
5291         .user           = OCP_USER_SDMA,
5292 };
5293
5294 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5295         {
5296                 .pa_start       = 0x48096000,
5297                 .pa_end         = 0x480960ff,
5298                 .flags          = ADDR_TYPE_RT
5299         },
5300         { }
5301 };
5302
5303 /* l4_per -> mcbsp4 */
5304 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5305         .master         = &omap44xx_l4_per_hwmod,
5306         .slave          = &omap44xx_mcbsp4_hwmod,
5307         .clk            = "l4_div_ck",
5308         .addr           = omap44xx_mcbsp4_addrs,
5309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5310 };
5311
5312 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5313         {
5314                 .name           = "mpu",
5315                 .pa_start       = 0x40132000,
5316                 .pa_end         = 0x4013207f,
5317                 .flags          = ADDR_TYPE_RT
5318         },
5319         { }
5320 };
5321
5322 /* l4_abe -> mcpdm */
5323 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5324         .master         = &omap44xx_l4_abe_hwmod,
5325         .slave          = &omap44xx_mcpdm_hwmod,
5326         .clk            = "ocp_abe_iclk",
5327         .addr           = omap44xx_mcpdm_addrs,
5328         .user           = OCP_USER_MPU,
5329 };
5330
5331 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5332         {
5333                 .name           = "dma",
5334                 .pa_start       = 0x49032000,
5335                 .pa_end         = 0x4903207f,
5336                 .flags          = ADDR_TYPE_RT
5337         },
5338         { }
5339 };
5340
5341 /* l4_abe -> mcpdm (dma) */
5342 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5343         .master         = &omap44xx_l4_abe_hwmod,
5344         .slave          = &omap44xx_mcpdm_hwmod,
5345         .clk            = "ocp_abe_iclk",
5346         .addr           = omap44xx_mcpdm_dma_addrs,
5347         .user           = OCP_USER_SDMA,
5348 };
5349
5350 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5351         {
5352                 .pa_start       = 0x48098000,
5353                 .pa_end         = 0x480981ff,
5354                 .flags          = ADDR_TYPE_RT
5355         },
5356         { }
5357 };
5358
5359 /* l4_per -> mcspi1 */
5360 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5361         .master         = &omap44xx_l4_per_hwmod,
5362         .slave          = &omap44xx_mcspi1_hwmod,
5363         .clk            = "l4_div_ck",
5364         .addr           = omap44xx_mcspi1_addrs,
5365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5366 };
5367
5368 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5369         {
5370                 .pa_start       = 0x4809a000,
5371                 .pa_end         = 0x4809a1ff,
5372                 .flags          = ADDR_TYPE_RT
5373         },
5374         { }
5375 };
5376
5377 /* l4_per -> mcspi2 */
5378 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5379         .master         = &omap44xx_l4_per_hwmod,
5380         .slave          = &omap44xx_mcspi2_hwmod,
5381         .clk            = "l4_div_ck",
5382         .addr           = omap44xx_mcspi2_addrs,
5383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5384 };
5385
5386 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5387         {
5388                 .pa_start       = 0x480b8000,
5389                 .pa_end         = 0x480b81ff,
5390                 .flags          = ADDR_TYPE_RT
5391         },
5392         { }
5393 };
5394
5395 /* l4_per -> mcspi3 */
5396 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5397         .master         = &omap44xx_l4_per_hwmod,
5398         .slave          = &omap44xx_mcspi3_hwmod,
5399         .clk            = "l4_div_ck",
5400         .addr           = omap44xx_mcspi3_addrs,
5401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5402 };
5403
5404 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5405         {
5406                 .pa_start       = 0x480ba000,
5407                 .pa_end         = 0x480ba1ff,
5408                 .flags          = ADDR_TYPE_RT
5409         },
5410         { }
5411 };
5412
5413 /* l4_per -> mcspi4 */
5414 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5415         .master         = &omap44xx_l4_per_hwmod,
5416         .slave          = &omap44xx_mcspi4_hwmod,
5417         .clk            = "l4_div_ck",
5418         .addr           = omap44xx_mcspi4_addrs,
5419         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5420 };
5421
5422 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5423         {
5424                 .pa_start       = 0x4809c000,
5425                 .pa_end         = 0x4809c3ff,
5426                 .flags          = ADDR_TYPE_RT
5427         },
5428         { }
5429 };
5430
5431 /* l4_per -> mmc1 */
5432 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5433         .master         = &omap44xx_l4_per_hwmod,
5434         .slave          = &omap44xx_mmc1_hwmod,
5435         .clk            = "l4_div_ck",
5436         .addr           = omap44xx_mmc1_addrs,
5437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5438 };
5439
5440 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5441         {
5442                 .pa_start       = 0x480b4000,
5443                 .pa_end         = 0x480b43ff,
5444                 .flags          = ADDR_TYPE_RT
5445         },
5446         { }
5447 };
5448
5449 /* l4_per -> mmc2 */
5450 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5451         .master         = &omap44xx_l4_per_hwmod,
5452         .slave          = &omap44xx_mmc2_hwmod,
5453         .clk            = "l4_div_ck",
5454         .addr           = omap44xx_mmc2_addrs,
5455         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5456 };
5457
5458 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5459         {
5460                 .pa_start       = 0x480ad000,
5461                 .pa_end         = 0x480ad3ff,
5462                 .flags          = ADDR_TYPE_RT
5463         },
5464         { }
5465 };
5466
5467 /* l4_per -> mmc3 */
5468 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5469         .master         = &omap44xx_l4_per_hwmod,
5470         .slave          = &omap44xx_mmc3_hwmod,
5471         .clk            = "l4_div_ck",
5472         .addr           = omap44xx_mmc3_addrs,
5473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5474 };
5475
5476 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5477         {
5478                 .pa_start       = 0x480d1000,
5479                 .pa_end         = 0x480d13ff,
5480                 .flags          = ADDR_TYPE_RT
5481         },
5482         { }
5483 };
5484
5485 /* l4_per -> mmc4 */
5486 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5487         .master         = &omap44xx_l4_per_hwmod,
5488         .slave          = &omap44xx_mmc4_hwmod,
5489         .clk            = "l4_div_ck",
5490         .addr           = omap44xx_mmc4_addrs,
5491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5492 };
5493
5494 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5495         {
5496                 .pa_start       = 0x480d5000,
5497                 .pa_end         = 0x480d53ff,
5498                 .flags          = ADDR_TYPE_RT
5499         },
5500         { }
5501 };
5502
5503 /* l4_per -> mmc5 */
5504 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5505         .master         = &omap44xx_l4_per_hwmod,
5506         .slave          = &omap44xx_mmc5_hwmod,
5507         .clk            = "l4_div_ck",
5508         .addr           = omap44xx_mmc5_addrs,
5509         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5510 };
5511
5512 /* l3_main_2 -> ocmc_ram */
5513 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5514         .master         = &omap44xx_l3_main_2_hwmod,
5515         .slave          = &omap44xx_ocmc_ram_hwmod,
5516         .clk            = "l3_div_ck",
5517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5518 };
5519
5520 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5521         {
5522                 .pa_start       = 0x4a0ad000,
5523                 .pa_end         = 0x4a0ad01f,
5524                 .flags          = ADDR_TYPE_RT
5525         },
5526         { }
5527 };
5528
5529 /* l4_cfg -> ocp2scp_usb_phy */
5530 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5531         .master         = &omap44xx_l4_cfg_hwmod,
5532         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5533         .clk            = "l4_div_ck",
5534         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5536 };
5537
5538 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5539         {
5540                 .pa_start       = 0x48243000,
5541                 .pa_end         = 0x48243fff,
5542                 .flags          = ADDR_TYPE_RT
5543         },
5544         { }
5545 };
5546
5547 /* mpu_private -> prcm_mpu */
5548 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5549         .master         = &omap44xx_mpu_private_hwmod,
5550         .slave          = &omap44xx_prcm_mpu_hwmod,
5551         .clk            = "l3_div_ck",
5552         .addr           = omap44xx_prcm_mpu_addrs,
5553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5554 };
5555
5556 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5557         {
5558                 .pa_start       = 0x4a004000,
5559                 .pa_end         = 0x4a004fff,
5560                 .flags          = ADDR_TYPE_RT
5561         },
5562         { }
5563 };
5564
5565 /* l4_wkup -> cm_core_aon */
5566 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5567         .master         = &omap44xx_l4_wkup_hwmod,
5568         .slave          = &omap44xx_cm_core_aon_hwmod,
5569         .clk            = "l4_wkup_clk_mux_ck",
5570         .addr           = omap44xx_cm_core_aon_addrs,
5571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5572 };
5573
5574 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5575         {
5576                 .pa_start       = 0x4a008000,
5577                 .pa_end         = 0x4a009fff,
5578                 .flags          = ADDR_TYPE_RT
5579         },
5580         { }
5581 };
5582
5583 /* l4_cfg -> cm_core */
5584 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5585         .master         = &omap44xx_l4_cfg_hwmod,
5586         .slave          = &omap44xx_cm_core_hwmod,
5587         .clk            = "l4_div_ck",
5588         .addr           = omap44xx_cm_core_addrs,
5589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5590 };
5591
5592 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5593         {
5594                 .pa_start       = 0x4a306000,
5595                 .pa_end         = 0x4a307fff,
5596                 .flags          = ADDR_TYPE_RT
5597         },
5598         { }
5599 };
5600
5601 /* l4_wkup -> prm */
5602 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5603         .master         = &omap44xx_l4_wkup_hwmod,
5604         .slave          = &omap44xx_prm_hwmod,
5605         .clk            = "l4_wkup_clk_mux_ck",
5606         .addr           = omap44xx_prm_addrs,
5607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5608 };
5609
5610 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5611         {
5612                 .pa_start       = 0x4a30a000,
5613                 .pa_end         = 0x4a30a7ff,
5614                 .flags          = ADDR_TYPE_RT
5615         },
5616         { }
5617 };
5618
5619 /* l4_wkup -> scrm */
5620 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5621         .master         = &omap44xx_l4_wkup_hwmod,
5622         .slave          = &omap44xx_scrm_hwmod,
5623         .clk            = "l4_wkup_clk_mux_ck",
5624         .addr           = omap44xx_scrm_addrs,
5625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5626 };
5627
5628 /* l3_main_2 -> sl2if */
5629 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5630         .master         = &omap44xx_l3_main_2_hwmod,
5631         .slave          = &omap44xx_sl2if_hwmod,
5632         .clk            = "l3_div_ck",
5633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5634 };
5635
5636 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5637         {
5638                 .pa_start       = 0x4012c000,
5639                 .pa_end         = 0x4012c3ff,
5640                 .flags          = ADDR_TYPE_RT
5641         },
5642         { }
5643 };
5644
5645 /* l4_abe -> slimbus1 */
5646 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5647         .master         = &omap44xx_l4_abe_hwmod,
5648         .slave          = &omap44xx_slimbus1_hwmod,
5649         .clk            = "ocp_abe_iclk",
5650         .addr           = omap44xx_slimbus1_addrs,
5651         .user           = OCP_USER_MPU,
5652 };
5653
5654 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5655         {
5656                 .pa_start       = 0x4902c000,
5657                 .pa_end         = 0x4902c3ff,
5658                 .flags          = ADDR_TYPE_RT
5659         },
5660         { }
5661 };
5662
5663 /* l4_abe -> slimbus1 (dma) */
5664 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5665         .master         = &omap44xx_l4_abe_hwmod,
5666         .slave          = &omap44xx_slimbus1_hwmod,
5667         .clk            = "ocp_abe_iclk",
5668         .addr           = omap44xx_slimbus1_dma_addrs,
5669         .user           = OCP_USER_SDMA,
5670 };
5671
5672 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5673         {
5674                 .pa_start       = 0x48076000,
5675                 .pa_end         = 0x480763ff,
5676                 .flags          = ADDR_TYPE_RT
5677         },
5678         { }
5679 };
5680
5681 /* l4_per -> slimbus2 */
5682 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5683         .master         = &omap44xx_l4_per_hwmod,
5684         .slave          = &omap44xx_slimbus2_hwmod,
5685         .clk            = "l4_div_ck",
5686         .addr           = omap44xx_slimbus2_addrs,
5687         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5688 };
5689
5690 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5691         {
5692                 .pa_start       = 0x4a0dd000,
5693                 .pa_end         = 0x4a0dd03f,
5694                 .flags          = ADDR_TYPE_RT
5695         },
5696         { }
5697 };
5698
5699 /* l4_cfg -> smartreflex_core */
5700 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5701         .master         = &omap44xx_l4_cfg_hwmod,
5702         .slave          = &omap44xx_smartreflex_core_hwmod,
5703         .clk            = "l4_div_ck",
5704         .addr           = omap44xx_smartreflex_core_addrs,
5705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5706 };
5707
5708 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5709         {
5710                 .pa_start       = 0x4a0db000,
5711                 .pa_end         = 0x4a0db03f,
5712                 .flags          = ADDR_TYPE_RT
5713         },
5714         { }
5715 };
5716
5717 /* l4_cfg -> smartreflex_iva */
5718 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5719         .master         = &omap44xx_l4_cfg_hwmod,
5720         .slave          = &omap44xx_smartreflex_iva_hwmod,
5721         .clk            = "l4_div_ck",
5722         .addr           = omap44xx_smartreflex_iva_addrs,
5723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5724 };
5725
5726 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5727         {
5728                 .pa_start       = 0x4a0d9000,
5729                 .pa_end         = 0x4a0d903f,
5730                 .flags          = ADDR_TYPE_RT
5731         },
5732         { }
5733 };
5734
5735 /* l4_cfg -> smartreflex_mpu */
5736 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5737         .master         = &omap44xx_l4_cfg_hwmod,
5738         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5739         .clk            = "l4_div_ck",
5740         .addr           = omap44xx_smartreflex_mpu_addrs,
5741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5742 };
5743
5744 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5745         {
5746                 .pa_start       = 0x4a0f6000,
5747                 .pa_end         = 0x4a0f6fff,
5748                 .flags          = ADDR_TYPE_RT
5749         },
5750         { }
5751 };
5752
5753 /* l4_cfg -> spinlock */
5754 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5755         .master         = &omap44xx_l4_cfg_hwmod,
5756         .slave          = &omap44xx_spinlock_hwmod,
5757         .clk            = "l4_div_ck",
5758         .addr           = omap44xx_spinlock_addrs,
5759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5760 };
5761
5762 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5763         {
5764                 .pa_start       = 0x4a318000,
5765                 .pa_end         = 0x4a31807f,
5766                 .flags          = ADDR_TYPE_RT
5767         },
5768         { }
5769 };
5770
5771 /* l4_wkup -> timer1 */
5772 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5773         .master         = &omap44xx_l4_wkup_hwmod,
5774         .slave          = &omap44xx_timer1_hwmod,
5775         .clk            = "l4_wkup_clk_mux_ck",
5776         .addr           = omap44xx_timer1_addrs,
5777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5778 };
5779
5780 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5781         {
5782                 .pa_start       = 0x48032000,
5783                 .pa_end         = 0x4803207f,
5784                 .flags          = ADDR_TYPE_RT
5785         },
5786         { }
5787 };
5788
5789 /* l4_per -> timer2 */
5790 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5791         .master         = &omap44xx_l4_per_hwmod,
5792         .slave          = &omap44xx_timer2_hwmod,
5793         .clk            = "l4_div_ck",
5794         .addr           = omap44xx_timer2_addrs,
5795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5796 };
5797
5798 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5799         {
5800                 .pa_start       = 0x48034000,
5801                 .pa_end         = 0x4803407f,
5802                 .flags          = ADDR_TYPE_RT
5803         },
5804         { }
5805 };
5806
5807 /* l4_per -> timer3 */
5808 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5809         .master         = &omap44xx_l4_per_hwmod,
5810         .slave          = &omap44xx_timer3_hwmod,
5811         .clk            = "l4_div_ck",
5812         .addr           = omap44xx_timer3_addrs,
5813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5814 };
5815
5816 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5817         {
5818                 .pa_start       = 0x48036000,
5819                 .pa_end         = 0x4803607f,
5820                 .flags          = ADDR_TYPE_RT
5821         },
5822         { }
5823 };
5824
5825 /* l4_per -> timer4 */
5826 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5827         .master         = &omap44xx_l4_per_hwmod,
5828         .slave          = &omap44xx_timer4_hwmod,
5829         .clk            = "l4_div_ck",
5830         .addr           = omap44xx_timer4_addrs,
5831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5832 };
5833
5834 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5835         {
5836                 .pa_start       = 0x40138000,
5837                 .pa_end         = 0x4013807f,
5838                 .flags          = ADDR_TYPE_RT
5839         },
5840         { }
5841 };
5842
5843 /* l4_abe -> timer5 */
5844 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5845         .master         = &omap44xx_l4_abe_hwmod,
5846         .slave          = &omap44xx_timer5_hwmod,
5847         .clk            = "ocp_abe_iclk",
5848         .addr           = omap44xx_timer5_addrs,
5849         .user           = OCP_USER_MPU,
5850 };
5851
5852 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5853         {
5854                 .pa_start       = 0x49038000,
5855                 .pa_end         = 0x4903807f,
5856                 .flags          = ADDR_TYPE_RT
5857         },
5858         { }
5859 };
5860
5861 /* l4_abe -> timer5 (dma) */
5862 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5863         .master         = &omap44xx_l4_abe_hwmod,
5864         .slave          = &omap44xx_timer5_hwmod,
5865         .clk            = "ocp_abe_iclk",
5866         .addr           = omap44xx_timer5_dma_addrs,
5867         .user           = OCP_USER_SDMA,
5868 };
5869
5870 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5871         {
5872                 .pa_start       = 0x4013a000,
5873                 .pa_end         = 0x4013a07f,
5874                 .flags          = ADDR_TYPE_RT
5875         },
5876         { }
5877 };
5878
5879 /* l4_abe -> timer6 */
5880 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5881         .master         = &omap44xx_l4_abe_hwmod,
5882         .slave          = &omap44xx_timer6_hwmod,
5883         .clk            = "ocp_abe_iclk",
5884         .addr           = omap44xx_timer6_addrs,
5885         .user           = OCP_USER_MPU,
5886 };
5887
5888 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5889         {
5890                 .pa_start       = 0x4903a000,
5891                 .pa_end         = 0x4903a07f,
5892                 .flags          = ADDR_TYPE_RT
5893         },
5894         { }
5895 };
5896
5897 /* l4_abe -> timer6 (dma) */
5898 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5899         .master         = &omap44xx_l4_abe_hwmod,
5900         .slave          = &omap44xx_timer6_hwmod,
5901         .clk            = "ocp_abe_iclk",
5902         .addr           = omap44xx_timer6_dma_addrs,
5903         .user           = OCP_USER_SDMA,
5904 };
5905
5906 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5907         {
5908                 .pa_start       = 0x4013c000,
5909                 .pa_end         = 0x4013c07f,
5910                 .flags          = ADDR_TYPE_RT
5911         },
5912         { }
5913 };
5914
5915 /* l4_abe -> timer7 */
5916 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5917         .master         = &omap44xx_l4_abe_hwmod,
5918         .slave          = &omap44xx_timer7_hwmod,
5919         .clk            = "ocp_abe_iclk",
5920         .addr           = omap44xx_timer7_addrs,
5921         .user           = OCP_USER_MPU,
5922 };
5923
5924 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5925         {
5926                 .pa_start       = 0x4903c000,
5927                 .pa_end         = 0x4903c07f,
5928                 .flags          = ADDR_TYPE_RT
5929         },
5930         { }
5931 };
5932
5933 /* l4_abe -> timer7 (dma) */
5934 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5935         .master         = &omap44xx_l4_abe_hwmod,
5936         .slave          = &omap44xx_timer7_hwmod,
5937         .clk            = "ocp_abe_iclk",
5938         .addr           = omap44xx_timer7_dma_addrs,
5939         .user           = OCP_USER_SDMA,
5940 };
5941
5942 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5943         {
5944                 .pa_start       = 0x4013e000,
5945                 .pa_end         = 0x4013e07f,
5946                 .flags          = ADDR_TYPE_RT
5947         },
5948         { }
5949 };
5950
5951 /* l4_abe -> timer8 */
5952 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5953         .master         = &omap44xx_l4_abe_hwmod,
5954         .slave          = &omap44xx_timer8_hwmod,
5955         .clk            = "ocp_abe_iclk",
5956         .addr           = omap44xx_timer8_addrs,
5957         .user           = OCP_USER_MPU,
5958 };
5959
5960 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5961         {
5962                 .pa_start       = 0x4903e000,
5963                 .pa_end         = 0x4903e07f,
5964                 .flags          = ADDR_TYPE_RT
5965         },
5966         { }
5967 };
5968
5969 /* l4_abe -> timer8 (dma) */
5970 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5971         .master         = &omap44xx_l4_abe_hwmod,
5972         .slave          = &omap44xx_timer8_hwmod,
5973         .clk            = "ocp_abe_iclk",
5974         .addr           = omap44xx_timer8_dma_addrs,
5975         .user           = OCP_USER_SDMA,
5976 };
5977
5978 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5979         {
5980                 .pa_start       = 0x4803e000,
5981                 .pa_end         = 0x4803e07f,
5982                 .flags          = ADDR_TYPE_RT
5983         },
5984         { }
5985 };
5986
5987 /* l4_per -> timer9 */
5988 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5989         .master         = &omap44xx_l4_per_hwmod,
5990         .slave          = &omap44xx_timer9_hwmod,
5991         .clk            = "l4_div_ck",
5992         .addr           = omap44xx_timer9_addrs,
5993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5994 };
5995
5996 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5997         {
5998                 .pa_start       = 0x48086000,
5999                 .pa_end         = 0x4808607f,
6000                 .flags          = ADDR_TYPE_RT
6001         },
6002         { }
6003 };
6004
6005 /* l4_per -> timer10 */
6006 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6007         .master         = &omap44xx_l4_per_hwmod,
6008         .slave          = &omap44xx_timer10_hwmod,
6009         .clk            = "l4_div_ck",
6010         .addr           = omap44xx_timer10_addrs,
6011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6012 };
6013
6014 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6015         {
6016                 .pa_start       = 0x48088000,
6017                 .pa_end         = 0x4808807f,
6018                 .flags          = ADDR_TYPE_RT
6019         },
6020         { }
6021 };
6022
6023 /* l4_per -> timer11 */
6024 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6025         .master         = &omap44xx_l4_per_hwmod,
6026         .slave          = &omap44xx_timer11_hwmod,
6027         .clk            = "l4_div_ck",
6028         .addr           = omap44xx_timer11_addrs,
6029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6030 };
6031
6032 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6033         {
6034                 .pa_start       = 0x4806a000,
6035                 .pa_end         = 0x4806a0ff,
6036                 .flags          = ADDR_TYPE_RT
6037         },
6038         { }
6039 };
6040
6041 /* l4_per -> uart1 */
6042 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6043         .master         = &omap44xx_l4_per_hwmod,
6044         .slave          = &omap44xx_uart1_hwmod,
6045         .clk            = "l4_div_ck",
6046         .addr           = omap44xx_uart1_addrs,
6047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6048 };
6049
6050 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6051         {
6052                 .pa_start       = 0x4806c000,
6053                 .pa_end         = 0x4806c0ff,
6054                 .flags          = ADDR_TYPE_RT
6055         },
6056         { }
6057 };
6058
6059 /* l4_per -> uart2 */
6060 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6061         .master         = &omap44xx_l4_per_hwmod,
6062         .slave          = &omap44xx_uart2_hwmod,
6063         .clk            = "l4_div_ck",
6064         .addr           = omap44xx_uart2_addrs,
6065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6066 };
6067
6068 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6069         {
6070                 .pa_start       = 0x48020000,
6071                 .pa_end         = 0x480200ff,
6072                 .flags          = ADDR_TYPE_RT
6073         },
6074         { }
6075 };
6076
6077 /* l4_per -> uart3 */
6078 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6079         .master         = &omap44xx_l4_per_hwmod,
6080         .slave          = &omap44xx_uart3_hwmod,
6081         .clk            = "l4_div_ck",
6082         .addr           = omap44xx_uart3_addrs,
6083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6084 };
6085
6086 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6087         {
6088                 .pa_start       = 0x4806e000,
6089                 .pa_end         = 0x4806e0ff,
6090                 .flags          = ADDR_TYPE_RT
6091         },
6092         { }
6093 };
6094
6095 /* l4_per -> uart4 */
6096 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6097         .master         = &omap44xx_l4_per_hwmod,
6098         .slave          = &omap44xx_uart4_hwmod,
6099         .clk            = "l4_div_ck",
6100         .addr           = omap44xx_uart4_addrs,
6101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6102 };
6103
6104 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6105         {
6106                 .pa_start       = 0x4a0a9000,
6107                 .pa_end         = 0x4a0a93ff,
6108                 .flags          = ADDR_TYPE_RT
6109         },
6110         { }
6111 };
6112
6113 /* l4_cfg -> usb_host_fs */
6114 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6115         .master         = &omap44xx_l4_cfg_hwmod,
6116         .slave          = &omap44xx_usb_host_fs_hwmod,
6117         .clk            = "l4_div_ck",
6118         .addr           = omap44xx_usb_host_fs_addrs,
6119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6120 };
6121
6122 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6123         {
6124                 .name           = "uhh",
6125                 .pa_start       = 0x4a064000,
6126                 .pa_end         = 0x4a0647ff,
6127                 .flags          = ADDR_TYPE_RT
6128         },
6129         {
6130                 .name           = "ohci",
6131                 .pa_start       = 0x4a064800,
6132                 .pa_end         = 0x4a064bff,
6133         },
6134         {
6135                 .name           = "ehci",
6136                 .pa_start       = 0x4a064c00,
6137                 .pa_end         = 0x4a064fff,
6138         },
6139         {}
6140 };
6141
6142 /* l4_cfg -> usb_host_hs */
6143 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6144         .master         = &omap44xx_l4_cfg_hwmod,
6145         .slave          = &omap44xx_usb_host_hs_hwmod,
6146         .clk            = "l4_div_ck",
6147         .addr           = omap44xx_usb_host_hs_addrs,
6148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6149 };
6150
6151 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6152         {
6153                 .pa_start       = 0x4a0ab000,
6154                 .pa_end         = 0x4a0ab7ff,
6155                 .flags          = ADDR_TYPE_RT
6156         },
6157         {
6158                 /* XXX: Remove this once control module driver is in place */
6159                 .pa_start       = 0x4a00233c,
6160                 .pa_end         = 0x4a00233f,
6161                 .flags          = ADDR_TYPE_RT
6162         },
6163         { }
6164 };
6165
6166 /* l4_cfg -> usb_otg_hs */
6167 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6168         .master         = &omap44xx_l4_cfg_hwmod,
6169         .slave          = &omap44xx_usb_otg_hs_hwmod,
6170         .clk            = "l4_div_ck",
6171         .addr           = omap44xx_usb_otg_hs_addrs,
6172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6173 };
6174
6175 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6176         {
6177                 .name           = "tll",
6178                 .pa_start       = 0x4a062000,
6179                 .pa_end         = 0x4a063fff,
6180                 .flags          = ADDR_TYPE_RT
6181         },
6182         {}
6183 };
6184
6185 /* l4_cfg -> usb_tll_hs */
6186 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6187         .master         = &omap44xx_l4_cfg_hwmod,
6188         .slave          = &omap44xx_usb_tll_hs_hwmod,
6189         .clk            = "l4_div_ck",
6190         .addr           = omap44xx_usb_tll_hs_addrs,
6191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6192 };
6193
6194 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6195         {
6196                 .pa_start       = 0x4a314000,
6197                 .pa_end         = 0x4a31407f,
6198                 .flags          = ADDR_TYPE_RT
6199         },
6200         { }
6201 };
6202
6203 /* l4_wkup -> wd_timer2 */
6204 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6205         .master         = &omap44xx_l4_wkup_hwmod,
6206         .slave          = &omap44xx_wd_timer2_hwmod,
6207         .clk            = "l4_wkup_clk_mux_ck",
6208         .addr           = omap44xx_wd_timer2_addrs,
6209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6210 };
6211
6212 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6213         {
6214                 .pa_start       = 0x40130000,
6215                 .pa_end         = 0x4013007f,
6216                 .flags          = ADDR_TYPE_RT
6217         },
6218         { }
6219 };
6220
6221 /* l4_abe -> wd_timer3 */
6222 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6223         .master         = &omap44xx_l4_abe_hwmod,
6224         .slave          = &omap44xx_wd_timer3_hwmod,
6225         .clk            = "ocp_abe_iclk",
6226         .addr           = omap44xx_wd_timer3_addrs,
6227         .user           = OCP_USER_MPU,
6228 };
6229
6230 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6231         {
6232                 .pa_start       = 0x49030000,
6233                 .pa_end         = 0x4903007f,
6234                 .flags          = ADDR_TYPE_RT
6235         },
6236         { }
6237 };
6238
6239 /* l4_abe -> wd_timer3 (dma) */
6240 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6241         .master         = &omap44xx_l4_abe_hwmod,
6242         .slave          = &omap44xx_wd_timer3_hwmod,
6243         .clk            = "ocp_abe_iclk",
6244         .addr           = omap44xx_wd_timer3_dma_addrs,
6245         .user           = OCP_USER_SDMA,
6246 };
6247
6248 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6249         &omap44xx_c2c__c2c_target_fw,
6250         &omap44xx_l4_cfg__c2c_target_fw,
6251         &omap44xx_l3_main_1__dmm,
6252         &omap44xx_mpu__dmm,
6253         &omap44xx_c2c__emif_fw,
6254         &omap44xx_dmm__emif_fw,
6255         &omap44xx_l4_cfg__emif_fw,
6256         &omap44xx_iva__l3_instr,
6257         &omap44xx_l3_main_3__l3_instr,
6258         &omap44xx_ocp_wp_noc__l3_instr,
6259         &omap44xx_dsp__l3_main_1,
6260         &omap44xx_dss__l3_main_1,
6261         &omap44xx_l3_main_2__l3_main_1,
6262         &omap44xx_l4_cfg__l3_main_1,
6263         &omap44xx_mmc1__l3_main_1,
6264         &omap44xx_mmc2__l3_main_1,
6265         &omap44xx_mpu__l3_main_1,
6266         &omap44xx_c2c_target_fw__l3_main_2,
6267         &omap44xx_debugss__l3_main_2,
6268         &omap44xx_dma_system__l3_main_2,
6269         &omap44xx_fdif__l3_main_2,
6270         &omap44xx_gpu__l3_main_2,
6271         &omap44xx_hsi__l3_main_2,
6272         &omap44xx_ipu__l3_main_2,
6273         &omap44xx_iss__l3_main_2,
6274         &omap44xx_iva__l3_main_2,
6275         &omap44xx_l3_main_1__l3_main_2,
6276         &omap44xx_l4_cfg__l3_main_2,
6277         /* &omap44xx_usb_host_fs__l3_main_2, */
6278         &omap44xx_usb_host_hs__l3_main_2,
6279         &omap44xx_usb_otg_hs__l3_main_2,
6280         &omap44xx_l3_main_1__l3_main_3,
6281         &omap44xx_l3_main_2__l3_main_3,
6282         &omap44xx_l4_cfg__l3_main_3,
6283         /* &omap44xx_aess__l4_abe, */
6284         &omap44xx_dsp__l4_abe,
6285         &omap44xx_l3_main_1__l4_abe,
6286         &omap44xx_mpu__l4_abe,
6287         &omap44xx_l3_main_1__l4_cfg,
6288         &omap44xx_l3_main_2__l4_per,
6289         &omap44xx_l4_cfg__l4_wkup,
6290         &omap44xx_mpu__mpu_private,
6291         &omap44xx_l4_cfg__ocp_wp_noc,
6292         /* &omap44xx_l4_abe__aess, */
6293         /* &omap44xx_l4_abe__aess_dma, */
6294         &omap44xx_l3_main_2__c2c,
6295         &omap44xx_l4_wkup__counter_32k,
6296         &omap44xx_l4_cfg__ctrl_module_core,
6297         &omap44xx_l4_cfg__ctrl_module_pad_core,
6298         &omap44xx_l4_wkup__ctrl_module_wkup,
6299         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6300         &omap44xx_l3_instr__debugss,
6301         &omap44xx_l4_cfg__dma_system,
6302         &omap44xx_l4_abe__dmic,
6303         &omap44xx_l4_abe__dmic_dma,
6304         &omap44xx_dsp__iva,
6305         /* &omap44xx_dsp__sl2if, */
6306         &omap44xx_l4_cfg__dsp,
6307         &omap44xx_l3_main_2__dss,
6308         &omap44xx_l4_per__dss,
6309         &omap44xx_l3_main_2__dss_dispc,
6310         &omap44xx_l4_per__dss_dispc,
6311         &omap44xx_l3_main_2__dss_dsi1,
6312         &omap44xx_l4_per__dss_dsi1,
6313         &omap44xx_l3_main_2__dss_dsi2,
6314         &omap44xx_l4_per__dss_dsi2,
6315         &omap44xx_l3_main_2__dss_hdmi,
6316         &omap44xx_l4_per__dss_hdmi,
6317         &omap44xx_l3_main_2__dss_rfbi,
6318         &omap44xx_l4_per__dss_rfbi,
6319         &omap44xx_l3_main_2__dss_venc,
6320         &omap44xx_l4_per__dss_venc,
6321         &omap44xx_l4_per__elm,
6322         &omap44xx_emif_fw__emif1,
6323         &omap44xx_emif_fw__emif2,
6324         &omap44xx_l4_cfg__fdif,
6325         &omap44xx_l4_wkup__gpio1,
6326         &omap44xx_l4_per__gpio2,
6327         &omap44xx_l4_per__gpio3,
6328         &omap44xx_l4_per__gpio4,
6329         &omap44xx_l4_per__gpio5,
6330         &omap44xx_l4_per__gpio6,
6331         &omap44xx_l3_main_2__gpmc,
6332         &omap44xx_l3_main_2__gpu,
6333         &omap44xx_l4_per__hdq1w,
6334         &omap44xx_l4_cfg__hsi,
6335         &omap44xx_l4_per__i2c1,
6336         &omap44xx_l4_per__i2c2,
6337         &omap44xx_l4_per__i2c3,
6338         &omap44xx_l4_per__i2c4,
6339         &omap44xx_l3_main_2__ipu,
6340         &omap44xx_l3_main_2__iss,
6341         /* &omap44xx_iva__sl2if, */
6342         &omap44xx_l3_main_2__iva,
6343         &omap44xx_l4_wkup__kbd,
6344         &omap44xx_l4_cfg__mailbox,
6345         &omap44xx_l4_abe__mcasp,
6346         &omap44xx_l4_abe__mcasp_dma,
6347         &omap44xx_l4_abe__mcbsp1,
6348         &omap44xx_l4_abe__mcbsp1_dma,
6349         &omap44xx_l4_abe__mcbsp2,
6350         &omap44xx_l4_abe__mcbsp2_dma,
6351         &omap44xx_l4_abe__mcbsp3,
6352         &omap44xx_l4_abe__mcbsp3_dma,
6353         &omap44xx_l4_per__mcbsp4,
6354         &omap44xx_l4_abe__mcpdm,
6355         &omap44xx_l4_abe__mcpdm_dma,
6356         &omap44xx_l4_per__mcspi1,
6357         &omap44xx_l4_per__mcspi2,
6358         &omap44xx_l4_per__mcspi3,
6359         &omap44xx_l4_per__mcspi4,
6360         &omap44xx_l4_per__mmc1,
6361         &omap44xx_l4_per__mmc2,
6362         &omap44xx_l4_per__mmc3,
6363         &omap44xx_l4_per__mmc4,
6364         &omap44xx_l4_per__mmc5,
6365         &omap44xx_l3_main_2__mmu_ipu,
6366         &omap44xx_l4_cfg__mmu_dsp,
6367         &omap44xx_l3_main_2__ocmc_ram,
6368         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6369         &omap44xx_mpu_private__prcm_mpu,
6370         &omap44xx_l4_wkup__cm_core_aon,
6371         &omap44xx_l4_cfg__cm_core,
6372         &omap44xx_l4_wkup__prm,
6373         &omap44xx_l4_wkup__scrm,
6374         /* &omap44xx_l3_main_2__sl2if, */
6375         &omap44xx_l4_abe__slimbus1,
6376         &omap44xx_l4_abe__slimbus1_dma,
6377         &omap44xx_l4_per__slimbus2,
6378         &omap44xx_l4_cfg__smartreflex_core,
6379         &omap44xx_l4_cfg__smartreflex_iva,
6380         &omap44xx_l4_cfg__smartreflex_mpu,
6381         &omap44xx_l4_cfg__spinlock,
6382         &omap44xx_l4_wkup__timer1,
6383         &omap44xx_l4_per__timer2,
6384         &omap44xx_l4_per__timer3,
6385         &omap44xx_l4_per__timer4,
6386         &omap44xx_l4_abe__timer5,
6387         &omap44xx_l4_abe__timer5_dma,
6388         &omap44xx_l4_abe__timer6,
6389         &omap44xx_l4_abe__timer6_dma,
6390         &omap44xx_l4_abe__timer7,
6391         &omap44xx_l4_abe__timer7_dma,
6392         &omap44xx_l4_abe__timer8,
6393         &omap44xx_l4_abe__timer8_dma,
6394         &omap44xx_l4_per__timer9,
6395         &omap44xx_l4_per__timer10,
6396         &omap44xx_l4_per__timer11,
6397         &omap44xx_l4_per__uart1,
6398         &omap44xx_l4_per__uart2,
6399         &omap44xx_l4_per__uart3,
6400         &omap44xx_l4_per__uart4,
6401         /* &omap44xx_l4_cfg__usb_host_fs, */
6402         &omap44xx_l4_cfg__usb_host_hs,
6403         &omap44xx_l4_cfg__usb_otg_hs,
6404         &omap44xx_l4_cfg__usb_tll_hs,
6405         &omap44xx_l4_wkup__wd_timer2,
6406         &omap44xx_l4_abe__wd_timer3,
6407         &omap44xx_l4_abe__wd_timer3_dma,
6408         NULL,
6409 };
6410
6411 int __init omap44xx_hwmod_init(void)
6412 {
6413         omap_hwmod_init();
6414         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6415 }
6416