2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/rculist.h>
23 #include <asm/pci_x86.h>
26 #define PREFIX "PCI: "
28 /* Indicate if the mmcfg resources have been placed into the resource table. */
29 static int __initdata pci_mmcfg_resources_inserted;
30 static bool pci_mmcfg_running_state;
31 static bool pci_mmcfg_arch_init_failed;
32 static DEFINE_MUTEX(pci_mmcfg_lock);
34 LIST_HEAD(pci_mmcfg_list);
36 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
39 release_resource(&cfg->res);
44 static __init void free_all_mmcfg(void)
46 struct pci_mmcfg_region *cfg, *tmp;
48 pci_mmcfg_arch_free();
49 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
50 pci_mmconfig_remove(cfg);
53 static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
55 struct pci_mmcfg_region *cfg;
57 /* keep list sorted by segment and starting bus number */
58 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
59 if (cfg->segment > new->segment ||
60 (cfg->segment == new->segment &&
61 cfg->start_bus >= new->start_bus)) {
62 list_add_tail_rcu(&new->list, &cfg->list);
66 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
69 static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
73 struct pci_mmcfg_region *new;
79 new = kzalloc(sizeof(*new), GFP_KERNEL);
84 new->segment = segment;
85 new->start_bus = start;
89 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
90 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
91 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
92 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
93 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
94 res->name = new->name;
99 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
102 struct pci_mmcfg_region *new;
104 new = pci_mmconfig_alloc(segment, start, end, addr);
106 mutex_lock(&pci_mmcfg_lock);
107 list_add_sorted(new);
108 mutex_unlock(&pci_mmcfg_lock);
110 printk(KERN_INFO PREFIX
111 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
113 segment, start, end, &new->res, (unsigned long)addr);
119 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
121 struct pci_mmcfg_region *cfg;
123 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
124 if (cfg->segment == segment &&
125 cfg->start_bus <= bus && bus <= cfg->end_bus)
131 static const char __init *pci_mmcfg_e7520(void)
134 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
137 if (win == 0x0000 || win == 0xf000)
140 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
143 return "Intel Corporation E7520 Memory Controller Hub";
146 static const char __init *pci_mmcfg_intel_945(void)
148 u32 pciexbar, mask = 0, len = 0;
150 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
157 switch ((pciexbar >> 1) & 3) {
174 /* Errata #2, things break when not aligned on a 256Mb boundary */
175 /* Can only happen in 64M/128M mode */
177 if ((pciexbar & mask) & 0x0fffffffU)
180 /* Don't hit the APIC registers and their friends */
181 if ((pciexbar & mask) >= 0xf0000000U)
184 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
187 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
190 static const char __init *pci_mmcfg_amd_fam10h(void)
192 u32 low, high, address;
195 unsigned segnbits = 0, busnbits, end_bus;
197 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
200 address = MSR_FAM10H_MMIO_CONF_BASE;
201 if (rdmsr_safe(address, &low, &high))
208 /* mmconfig is not enable */
209 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
212 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
214 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
215 FAM10H_MMIO_CONF_BUSRANGE_MASK;
218 * only handle bus 0 ?
225 segnbits = busnbits - 8;
229 end_bus = (1 << busnbits) - 1;
230 for (i = 0; i < (1 << segnbits); i++)
231 if (pci_mmconfig_add(i, 0, end_bus,
232 base + (1<<28) * i) == NULL) {
237 return "AMD Family 10h NB";
240 static bool __initdata mcp55_checked;
241 static const char __init *pci_mmcfg_nvidia_mcp55(void)
244 int mcp55_mmconf_found = 0;
246 static const u32 extcfg_regnum = 0x90;
247 static const u32 extcfg_regsize = 4;
248 static const u32 extcfg_enable_mask = 1<<31;
249 static const u32 extcfg_start_mask = 0xff<<16;
250 static const int extcfg_start_shift = 16;
251 static const u32 extcfg_size_mask = 0x3<<28;
252 static const int extcfg_size_shift = 28;
253 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
254 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
255 static const int extcfg_base_lshift = 25;
258 * do check if amd fam10h already took over
260 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
263 mcp55_checked = true;
264 for (bus = 0; bus < 256; bus++) {
268 int start, size_index, end;
270 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
272 device = (l >> 16) & 0xffff;
274 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
277 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
278 extcfg_regsize, &extcfg);
280 if (!(extcfg & extcfg_enable_mask))
283 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
284 base = extcfg & extcfg_base_mask[size_index];
285 /* base could > 4G */
286 base <<= extcfg_base_lshift;
287 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
288 end = start + extcfg_sizebus[size_index] - 1;
289 if (pci_mmconfig_add(0, start, end, base) == NULL)
291 mcp55_mmconf_found++;
294 if (!mcp55_mmconf_found)
297 return "nVidia MCP55";
300 struct pci_mmcfg_hostbridge_probe {
305 const char *(*probe)(void);
308 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
309 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
310 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
311 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
312 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
313 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
314 0x1200, pci_mmcfg_amd_fam10h },
315 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
316 0x1200, pci_mmcfg_amd_fam10h },
317 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
318 0x0369, pci_mmcfg_nvidia_mcp55 },
321 static void __init pci_mmcfg_check_end_bus_number(void)
323 struct pci_mmcfg_region *cfg, *cfgx;
326 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
327 if (cfg->end_bus < cfg->start_bus)
330 /* Don't access the list head ! */
331 if (cfg->list.next == &pci_mmcfg_list)
334 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
335 if (cfg->end_bus >= cfgx->start_bus)
336 cfg->end_bus = cfgx->start_bus - 1;
340 static int __init pci_mmcfg_check_hostbridge(void)
353 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
354 bus = pci_mmcfg_probes[i].bus;
355 devfn = pci_mmcfg_probes[i].devfn;
356 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
358 device = (l >> 16) & 0xffff;
361 if (pci_mmcfg_probes[i].vendor == vendor &&
362 pci_mmcfg_probes[i].device == device)
363 name = pci_mmcfg_probes[i].probe();
366 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
370 /* some end_bus_number is crazy, fix it */
371 pci_mmcfg_check_end_bus_number();
373 return !list_empty(&pci_mmcfg_list);
376 static void __init pci_mmcfg_insert_resources(void)
378 struct pci_mmcfg_region *cfg;
380 list_for_each_entry(cfg, &pci_mmcfg_list, list)
381 if (!cfg->res.parent)
382 insert_resource(&iomem_resource, &cfg->res);
384 /* Mark that the resources have been inserted. */
385 pci_mmcfg_resources_inserted = 1;
388 static acpi_status __devinit check_mcfg_resource(struct acpi_resource *res,
391 struct resource *mcfg_res = data;
392 struct acpi_resource_address64 address;
395 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
396 struct acpi_resource_fixed_memory32 *fixmem32 =
397 &res->data.fixed_memory32;
400 if ((mcfg_res->start >= fixmem32->address) &&
401 (mcfg_res->end < (fixmem32->address +
402 fixmem32->address_length))) {
404 return AE_CTRL_TERMINATE;
407 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
408 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
411 status = acpi_resource_to_address64(res, &address);
412 if (ACPI_FAILURE(status) ||
413 (address.address_length <= 0) ||
414 (address.resource_type != ACPI_MEMORY_RANGE))
417 if ((mcfg_res->start >= address.minimum) &&
418 (mcfg_res->end < (address.minimum + address.address_length))) {
420 return AE_CTRL_TERMINATE;
425 static acpi_status __devinit find_mboard_resource(acpi_handle handle, u32 lvl,
426 void *context, void **rv)
428 struct resource *mcfg_res = context;
430 acpi_walk_resources(handle, METHOD_NAME__CRS,
431 check_mcfg_resource, context);
434 return AE_CTRL_TERMINATE;
439 static int __devinit is_acpi_reserved(u64 start, u64 end, unsigned not_used)
441 struct resource mcfg_res;
443 mcfg_res.start = start;
444 mcfg_res.end = end - 1;
447 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
450 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
453 return mcfg_res.flags;
456 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
458 static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
459 struct pci_mmcfg_region *cfg,
460 struct device *dev, int with_e820)
462 u64 addr = cfg->res.start;
463 u64 size = resource_size(&cfg->res);
466 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
468 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
470 if (size < (16UL<<20))
474 if (size < (16UL<<20) && size != old_size)
478 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
481 printk(KERN_INFO PREFIX
482 "MMCONFIG at %pR reserved in %s\n",
485 if (old_size != size) {
487 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
488 num_buses = cfg->end_bus - cfg->start_bus + 1;
489 cfg->res.end = cfg->res.start +
490 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
491 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
492 "PCI MMCONFIG %04x [bus %02x-%02x]",
493 cfg->segment, cfg->start_bus, cfg->end_bus);
498 "at %pR (base %#lx) (size reduced!)\n",
499 &cfg->res, (unsigned long) cfg->address);
501 printk(KERN_INFO PREFIX
502 "MMCONFIG for %04x [bus%02x-%02x] "
503 "at %pR (base %#lx) (size reduced!)\n",
504 cfg->segment, cfg->start_bus, cfg->end_bus,
505 &cfg->res, (unsigned long) cfg->address);
511 static int __ref pci_mmcfg_check_reserved(struct device *dev,
512 struct pci_mmcfg_region *cfg, int early)
514 if (!early && !acpi_disabled) {
515 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
519 dev_info(dev, FW_INFO
520 "MMCONFIG at %pR not reserved in "
521 "ACPI motherboard resources\n",
524 printk(KERN_INFO FW_INFO PREFIX
525 "MMCONFIG at %pR not reserved in "
526 "ACPI motherboard resources\n",
531 * e820_all_mapped() is marked as __init.
532 * All entries from ACPI MCFG table have been checked at boot time.
533 * For MCFG information constructed from hotpluggable host bridge's
534 * _CBA method, just assume it's reserved.
536 if (pci_mmcfg_running_state)
539 /* Don't try to do this check unless configuration
540 type 1 is available. how about type 2 ?*/
542 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
547 static void __init pci_mmcfg_reject_broken(int early)
549 struct pci_mmcfg_region *cfg;
551 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
552 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
553 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
560 static int __initdata known_bridge;
562 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
563 struct acpi_mcfg_allocation *cfg)
567 if (cfg->address < 0xFFFFFFFF)
570 if (!strcmp(mcfg->header.oem_id, "SGI") ||
571 !strcmp(mcfg->header.oem_id, "SGI2"))
574 if (mcfg->header.revision >= 1) {
575 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
580 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
581 "is above 4GB, ignored\n", cfg->pci_segment,
582 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
586 static int __init pci_parse_mcfg(struct acpi_table_header *header)
588 struct acpi_table_mcfg *mcfg;
589 struct acpi_mcfg_allocation *cfg_table, *cfg;
596 mcfg = (struct acpi_table_mcfg *)header;
598 /* how many config structures do we have */
601 i = header->length - sizeof(struct acpi_table_mcfg);
602 while (i >= sizeof(struct acpi_mcfg_allocation)) {
604 i -= sizeof(struct acpi_mcfg_allocation);
607 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
611 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
612 for (i = 0; i < entries; i++) {
614 if (acpi_mcfg_check_entry(mcfg, cfg)) {
619 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
620 cfg->end_bus_number, cfg->address) == NULL) {
621 printk(KERN_WARNING PREFIX
622 "no memory for MCFG entries\n");
631 static void __init __pci_mmcfg_init(int early)
633 /* MMCONFIG disabled */
634 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
637 /* MMCONFIG already enabled */
638 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
641 /* for late to exit */
646 if (pci_mmcfg_check_hostbridge())
651 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
653 pci_mmcfg_reject_broken(early);
655 if (list_empty(&pci_mmcfg_list))
658 if (pcibios_last_bus < 0) {
659 const struct pci_mmcfg_region *cfg;
661 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
664 pcibios_last_bus = cfg->end_bus;
668 if (pci_mmcfg_arch_init())
669 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
672 * Signal not to attempt to insert mmcfg resources because
673 * the architecture mmcfg setup could not initialize.
675 pci_mmcfg_resources_inserted = 1;
676 pci_mmcfg_arch_init_failed = true;
680 void __init pci_mmcfg_early_init(void)
685 void __init pci_mmcfg_late_init(void)
690 static int __init pci_mmcfg_late_insert_resources(void)
692 pci_mmcfg_running_state = true;
695 * If resources are already inserted or we are not using MMCONFIG,
696 * don't insert the resources.
698 if ((pci_mmcfg_resources_inserted == 1) ||
699 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
700 list_empty(&pci_mmcfg_list))
704 * Attempt to insert the mmcfg resources but not with the busy flag
705 * marked so it won't cause request errors when __request_region is
708 pci_mmcfg_insert_resources();
714 * Perform MMCONFIG resource insertion after PCI initialization to allow for
715 * misprogrammed MCFG tables that state larger sizes but actually conflict
716 * with other system resources.
718 late_initcall(pci_mmcfg_late_insert_resources);
720 /* Add MMCFG information for host bridges */
721 int __devinit pci_mmconfig_insert(struct device *dev,
722 u16 seg, u8 start, u8 end,
726 struct resource *tmp = NULL;
727 struct pci_mmcfg_region *cfg;
729 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
735 mutex_lock(&pci_mmcfg_lock);
736 cfg = pci_mmconfig_lookup(seg, start);
738 if (cfg->end_bus < end)
739 dev_info(dev, FW_INFO
741 "domain %04x [bus %02x-%02x] "
742 "only partially covers this bridge\n",
743 cfg->segment, cfg->start_bus, cfg->end_bus);
744 mutex_unlock(&pci_mmcfg_lock);
749 mutex_unlock(&pci_mmcfg_lock);
754 cfg = pci_mmconfig_alloc(seg, start, end, addr);
756 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
758 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
759 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
762 /* Insert resource if it's not in boot stage */
763 if (pci_mmcfg_running_state)
764 tmp = insert_resource_conflict(&iomem_resource,
769 "MMCONFIG %pR conflicts with "
771 &cfg->res, tmp->name, tmp);
772 } else if (pci_mmcfg_arch_map(cfg)) {
773 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
776 list_add_sorted(cfg);
777 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
778 &cfg->res, (unsigned long)addr);
786 release_resource(&cfg->res);
790 mutex_unlock(&pci_mmcfg_lock);
795 /* Delete MMCFG information for host bridges */
796 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
798 struct pci_mmcfg_region *cfg;
800 mutex_lock(&pci_mmcfg_lock);
801 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
802 if (cfg->segment == seg && cfg->start_bus == start &&
803 cfg->end_bus == end) {
804 list_del_rcu(&cfg->list);
806 pci_mmcfg_arch_unmap(cfg);
808 release_resource(&cfg->res);
809 mutex_unlock(&pci_mmcfg_lock);
813 mutex_unlock(&pci_mmcfg_lock);