1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/of_mdio.h>
82 #include <linux/of_platform.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
87 #include <linux/net_tstamp.h>
92 #include <asm/uaccess.h>
93 #include <linux/module.h>
94 #include <linux/dma-mapping.h>
95 #include <linux/crc32.h>
96 #include <linux/mii.h>
97 #include <linux/phy.h>
98 #include <linux/phy_fixed.h>
100 #include <linux/of_net.h>
104 #define TX_TIMEOUT (1*HZ)
106 const char gfar_driver_version[] = "1.3";
108 static int gfar_enet_open(struct net_device *dev);
109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
110 static void gfar_reset_task(struct work_struct *work);
111 static void gfar_timeout(struct net_device *dev);
112 static int gfar_close(struct net_device *dev);
113 struct sk_buff *gfar_new_skb(struct net_device *dev);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
115 struct sk_buff *skb);
116 static int gfar_set_mac_address(struct net_device *dev);
117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
118 static irqreturn_t gfar_error(int irq, void *dev_id);
119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
121 static void adjust_link(struct net_device *dev);
122 static void init_registers(struct net_device *dev);
123 static int init_phy(struct net_device *dev);
124 static int gfar_probe(struct platform_device *ofdev);
125 static int gfar_remove(struct platform_device *ofdev);
126 static void free_skb_resources(struct gfar_private *priv);
127 static void gfar_set_multi(struct net_device *dev);
128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
129 static void gfar_configure_serdes(struct net_device *dev);
130 static int gfar_poll(struct napi_struct *napi, int budget);
131 #ifdef CONFIG_NET_POLL_CONTROLLER
132 static void gfar_netpoll(struct net_device *dev);
134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 int amount_pull, struct napi_struct *napi);
138 void gfar_halt(struct net_device *dev);
139 static void gfar_halt_nodisable(struct net_device *dev);
140 void gfar_start(struct net_device *dev);
141 static void gfar_clear_exact_match(struct net_device *dev);
142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
157 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
158 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
159 lstatus |= BD_LFLAG(RXBD_WRAP);
163 bdp->lstatus = lstatus;
166 static int gfar_init_bds(struct net_device *ndev)
168 struct gfar_private *priv = netdev_priv(ndev);
169 struct gfar_priv_tx_q *tx_queue = NULL;
170 struct gfar_priv_rx_q *rx_queue = NULL;
175 for (i = 0; i < priv->num_tx_queues; i++) {
176 tx_queue = priv->tx_queue[i];
177 /* Initialize some variables in our dev structure */
178 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
179 tx_queue->dirty_tx = tx_queue->tx_bd_base;
180 tx_queue->cur_tx = tx_queue->tx_bd_base;
181 tx_queue->skb_curtx = 0;
182 tx_queue->skb_dirtytx = 0;
184 /* Initialize Transmit Descriptor Ring */
185 txbdp = tx_queue->tx_bd_base;
186 for (j = 0; j < tx_queue->tx_ring_size; j++) {
192 /* Set the last descriptor in the ring to indicate wrap */
194 txbdp->status |= TXBD_WRAP;
197 for (i = 0; i < priv->num_rx_queues; i++) {
198 rx_queue = priv->rx_queue[i];
199 rx_queue->cur_rx = rx_queue->rx_bd_base;
200 rx_queue->skb_currx = 0;
201 rxbdp = rx_queue->rx_bd_base;
203 for (j = 0; j < rx_queue->rx_ring_size; j++) {
204 struct sk_buff *skb = rx_queue->rx_skbuff[j];
207 gfar_init_rxbdp(rx_queue, rxbdp,
210 skb = gfar_new_skb(ndev);
212 netdev_err(ndev, "Can't allocate RX buffers\n");
213 goto err_rxalloc_fail;
215 rx_queue->rx_skbuff[j] = skb;
217 gfar_new_rxbdp(rx_queue, rxbdp, skb);
228 free_skb_resources(priv);
232 static int gfar_alloc_skb_resources(struct net_device *ndev)
237 struct gfar_private *priv = netdev_priv(ndev);
238 struct device *dev = &priv->ofdev->dev;
239 struct gfar_priv_tx_q *tx_queue = NULL;
240 struct gfar_priv_rx_q *rx_queue = NULL;
242 priv->total_tx_ring_size = 0;
243 for (i = 0; i < priv->num_tx_queues; i++)
244 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
246 priv->total_rx_ring_size = 0;
247 for (i = 0; i < priv->num_rx_queues; i++)
248 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
250 /* Allocate memory for the buffer descriptors */
251 vaddr = dma_alloc_coherent(dev,
252 sizeof(struct txbd8) * priv->total_tx_ring_size +
253 sizeof(struct rxbd8) * priv->total_rx_ring_size,
256 netif_err(priv, ifup, ndev,
257 "Could not allocate buffer descriptors!\n");
261 for (i = 0; i < priv->num_tx_queues; i++) {
262 tx_queue = priv->tx_queue[i];
263 tx_queue->tx_bd_base = vaddr;
264 tx_queue->tx_bd_dma_base = addr;
265 tx_queue->dev = ndev;
266 /* enet DMA only understands physical addresses */
267 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
268 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
271 /* Start the rx descriptor ring where the tx ring leaves off */
272 for (i = 0; i < priv->num_rx_queues; i++) {
273 rx_queue = priv->rx_queue[i];
274 rx_queue->rx_bd_base = vaddr;
275 rx_queue->rx_bd_dma_base = addr;
276 rx_queue->dev = ndev;
277 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
278 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
281 /* Setup the skbuff rings */
282 for (i = 0; i < priv->num_tx_queues; i++) {
283 tx_queue = priv->tx_queue[i];
284 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
285 tx_queue->tx_ring_size,
287 if (!tx_queue->tx_skbuff) {
288 netif_err(priv, ifup, ndev,
289 "Could not allocate tx_skbuff\n");
293 for (k = 0; k < tx_queue->tx_ring_size; k++)
294 tx_queue->tx_skbuff[k] = NULL;
297 for (i = 0; i < priv->num_rx_queues; i++) {
298 rx_queue = priv->rx_queue[i];
299 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
300 rx_queue->rx_ring_size,
303 if (!rx_queue->rx_skbuff) {
304 netif_err(priv, ifup, ndev,
305 "Could not allocate rx_skbuff\n");
309 for (j = 0; j < rx_queue->rx_ring_size; j++)
310 rx_queue->rx_skbuff[j] = NULL;
313 if (gfar_init_bds(ndev))
319 free_skb_resources(priv);
323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
325 struct gfar __iomem *regs = priv->gfargrp[0].regs;
329 baddr = ®s->tbase0;
330 for (i = 0; i < priv->num_tx_queues; i++) {
331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
335 baddr = ®s->rbase0;
336 for (i = 0; i < priv->num_rx_queues; i++) {
337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
342 static void gfar_init_mac(struct net_device *ndev)
344 struct gfar_private *priv = netdev_priv(ndev);
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
350 /* write the tx/rx base registers */
351 gfar_init_tx_rx_base(priv);
353 /* Configure the coalescing support */
354 gfar_configure_coalescing(priv, 0xFF, 0xFF);
356 if (priv->rx_filer_enable) {
357 rctrl |= RCTRL_FILREN;
358 /* Program the RIR0 reg with the required distribution */
359 gfar_write(®s->rir0, DEFAULT_RIR0);
362 if (ndev->features & NETIF_F_RXCSUM)
363 rctrl |= RCTRL_CHECKSUMMING;
365 if (priv->extended_hash) {
366 rctrl |= RCTRL_EXTHASH;
368 gfar_clear_exact_match(ndev);
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
377 /* Insert receive time stamps into padding alignment bytes */
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
379 rctrl &= ~RCTRL_PAL_MASK;
380 rctrl |= RCTRL_PADDING(8);
384 /* Enable HW time stamping if requested from user space */
385 if (priv->hwts_rx_en)
386 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
388 if (ndev->features & NETIF_F_HW_VLAN_RX)
389 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
391 /* Init rctrl based on our settings */
392 gfar_write(®s->rctrl, rctrl);
394 if (ndev->features & NETIF_F_IP_CSUM)
395 tctrl |= TCTRL_INIT_CSUM;
397 if (priv->prio_sched_en)
398 tctrl |= TCTRL_TXSCHED_PRIO;
400 tctrl |= TCTRL_TXSCHED_WRRS;
401 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
402 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
405 gfar_write(®s->tctrl, tctrl);
407 /* Set the extraction length and index */
408 attrs = ATTRELI_EL(priv->rx_stash_size) |
409 ATTRELI_EI(priv->rx_stash_index);
411 gfar_write(®s->attreli, attrs);
413 /* Start with defaults, and add stashing or locking
414 * depending on the approprate variables
416 attrs = ATTR_INIT_SETTINGS;
418 if (priv->bd_stash_en)
419 attrs |= ATTR_BDSTASH;
421 if (priv->rx_stash_size != 0)
422 attrs |= ATTR_BUFSTASH;
424 gfar_write(®s->attr, attrs);
426 gfar_write(®s->fifo_tx_thr, priv->fifo_threshold);
427 gfar_write(®s->fifo_tx_starve, priv->fifo_starve);
428 gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off);
431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
433 struct gfar_private *priv = netdev_priv(dev);
434 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
435 unsigned long tx_packets = 0, tx_bytes = 0;
438 for (i = 0; i < priv->num_rx_queues; i++) {
439 rx_packets += priv->rx_queue[i]->stats.rx_packets;
440 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
441 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
444 dev->stats.rx_packets = rx_packets;
445 dev->stats.rx_bytes = rx_bytes;
446 dev->stats.rx_dropped = rx_dropped;
448 for (i = 0; i < priv->num_tx_queues; i++) {
449 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
450 tx_packets += priv->tx_queue[i]->stats.tx_packets;
453 dev->stats.tx_bytes = tx_bytes;
454 dev->stats.tx_packets = tx_packets;
459 static const struct net_device_ops gfar_netdev_ops = {
460 .ndo_open = gfar_enet_open,
461 .ndo_start_xmit = gfar_start_xmit,
462 .ndo_stop = gfar_close,
463 .ndo_change_mtu = gfar_change_mtu,
464 .ndo_set_features = gfar_set_features,
465 .ndo_set_rx_mode = gfar_set_multi,
466 .ndo_tx_timeout = gfar_timeout,
467 .ndo_do_ioctl = gfar_ioctl,
468 .ndo_get_stats = gfar_get_stats,
469 .ndo_set_mac_address = eth_mac_addr,
470 .ndo_validate_addr = eth_validate_addr,
471 #ifdef CONFIG_NET_POLL_CONTROLLER
472 .ndo_poll_controller = gfar_netpoll,
476 void lock_rx_qs(struct gfar_private *priv)
480 for (i = 0; i < priv->num_rx_queues; i++)
481 spin_lock(&priv->rx_queue[i]->rxlock);
484 void lock_tx_qs(struct gfar_private *priv)
488 for (i = 0; i < priv->num_tx_queues; i++)
489 spin_lock(&priv->tx_queue[i]->txlock);
492 void unlock_rx_qs(struct gfar_private *priv)
496 for (i = 0; i < priv->num_rx_queues; i++)
497 spin_unlock(&priv->rx_queue[i]->rxlock);
500 void unlock_tx_qs(struct gfar_private *priv)
504 for (i = 0; i < priv->num_tx_queues; i++)
505 spin_unlock(&priv->tx_queue[i]->txlock);
508 static bool gfar_is_vlan_on(struct gfar_private *priv)
510 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
511 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
514 /* Returns 1 if incoming frames use an FCB */
515 static inline int gfar_uses_fcb(struct gfar_private *priv)
517 return gfar_is_vlan_on(priv) ||
518 (priv->ndev->features & NETIF_F_RXCSUM) ||
519 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
522 static void free_tx_pointers(struct gfar_private *priv)
526 for (i = 0; i < priv->num_tx_queues; i++)
527 kfree(priv->tx_queue[i]);
530 static void free_rx_pointers(struct gfar_private *priv)
534 for (i = 0; i < priv->num_rx_queues; i++)
535 kfree(priv->rx_queue[i]);
538 static void unmap_group_regs(struct gfar_private *priv)
542 for (i = 0; i < MAXGROUPS; i++)
543 if (priv->gfargrp[i].regs)
544 iounmap(priv->gfargrp[i].regs);
547 static void disable_napi(struct gfar_private *priv)
551 for (i = 0; i < priv->num_grps; i++)
552 napi_disable(&priv->gfargrp[i].napi);
555 static void enable_napi(struct gfar_private *priv)
559 for (i = 0; i < priv->num_grps; i++)
560 napi_enable(&priv->gfargrp[i].napi);
563 static int gfar_parse_group(struct device_node *np,
564 struct gfar_private *priv, const char *model)
568 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
569 if (!priv->gfargrp[priv->num_grps].regs)
572 priv->gfargrp[priv->num_grps].interruptTransmit =
573 irq_of_parse_and_map(np, 0);
575 /* If we aren't the FEC we have multiple interrupts */
576 if (model && strcasecmp(model, "FEC")) {
577 priv->gfargrp[priv->num_grps].interruptReceive =
578 irq_of_parse_and_map(np, 1);
579 priv->gfargrp[priv->num_grps].interruptError =
580 irq_of_parse_and_map(np,2);
581 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
582 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
583 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
587 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
588 priv->gfargrp[priv->num_grps].priv = priv;
589 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
590 if (priv->mode == MQ_MG_MODE) {
591 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
592 priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
593 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
594 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
595 priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
596 *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
598 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
599 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
610 const void *mac_addr;
612 struct net_device *dev = NULL;
613 struct gfar_private *priv = NULL;
614 struct device_node *np = ofdev->dev.of_node;
615 struct device_node *child = NULL;
617 const u32 *stash_len;
618 const u32 *stash_idx;
619 unsigned int num_tx_qs, num_rx_qs;
620 u32 *tx_queues, *rx_queues;
622 if (!np || !of_device_is_available(np))
625 /* parse the num of tx and rx queues */
626 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
627 num_tx_qs = tx_queues ? *tx_queues : 1;
629 if (num_tx_qs > MAX_TX_QS) {
630 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
631 num_tx_qs, MAX_TX_QS);
632 pr_err("Cannot do alloc_etherdev, aborting\n");
636 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
637 num_rx_qs = rx_queues ? *rx_queues : 1;
639 if (num_rx_qs > MAX_RX_QS) {
640 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
641 num_rx_qs, MAX_RX_QS);
642 pr_err("Cannot do alloc_etherdev, aborting\n");
646 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
651 priv = netdev_priv(dev);
652 priv->node = ofdev->dev.of_node;
655 priv->num_tx_queues = num_tx_qs;
656 netif_set_real_num_rx_queues(dev, num_rx_qs);
657 priv->num_rx_queues = num_rx_qs;
658 priv->num_grps = 0x0;
660 /* Init Rx queue filer rule set linked list */
661 INIT_LIST_HEAD(&priv->rx_list.list);
662 priv->rx_list.count = 0;
663 mutex_init(&priv->rx_queue_access);
665 model = of_get_property(np, "model", NULL);
667 for (i = 0; i < MAXGROUPS; i++)
668 priv->gfargrp[i].regs = NULL;
670 /* Parse and initialize group specific information */
671 if (of_device_is_compatible(np, "fsl,etsec2")) {
672 priv->mode = MQ_MG_MODE;
673 for_each_child_of_node(np, child) {
674 err = gfar_parse_group(child, priv, model);
679 priv->mode = SQ_SG_MODE;
680 err = gfar_parse_group(np, priv, model);
685 for (i = 0; i < priv->num_tx_queues; i++)
686 priv->tx_queue[i] = NULL;
687 for (i = 0; i < priv->num_rx_queues; i++)
688 priv->rx_queue[i] = NULL;
690 for (i = 0; i < priv->num_tx_queues; i++) {
691 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
693 if (!priv->tx_queue[i]) {
695 goto tx_alloc_failed;
697 priv->tx_queue[i]->tx_skbuff = NULL;
698 priv->tx_queue[i]->qindex = i;
699 priv->tx_queue[i]->dev = dev;
700 spin_lock_init(&(priv->tx_queue[i]->txlock));
703 for (i = 0; i < priv->num_rx_queues; i++) {
704 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
706 if (!priv->rx_queue[i]) {
708 goto rx_alloc_failed;
710 priv->rx_queue[i]->rx_skbuff = NULL;
711 priv->rx_queue[i]->qindex = i;
712 priv->rx_queue[i]->dev = dev;
713 spin_lock_init(&(priv->rx_queue[i]->rxlock));
717 stash = of_get_property(np, "bd-stash", NULL);
720 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
721 priv->bd_stash_en = 1;
724 stash_len = of_get_property(np, "rx-stash-len", NULL);
727 priv->rx_stash_size = *stash_len;
729 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
732 priv->rx_stash_index = *stash_idx;
734 if (stash_len || stash_idx)
735 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
737 mac_addr = of_get_mac_address(np);
740 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
742 if (model && !strcasecmp(model, "TSEC"))
743 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
744 FSL_GIANFAR_DEV_HAS_COALESCE |
745 FSL_GIANFAR_DEV_HAS_RMON |
746 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
748 if (model && !strcasecmp(model, "eTSEC"))
749 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
750 FSL_GIANFAR_DEV_HAS_COALESCE |
751 FSL_GIANFAR_DEV_HAS_RMON |
752 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
753 FSL_GIANFAR_DEV_HAS_PADDING |
754 FSL_GIANFAR_DEV_HAS_CSUM |
755 FSL_GIANFAR_DEV_HAS_VLAN |
756 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
757 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
758 FSL_GIANFAR_DEV_HAS_TIMER;
760 ctype = of_get_property(np, "phy-connection-type", NULL);
762 /* We only care about rgmii-id. The rest are autodetected */
763 if (ctype && !strcmp(ctype, "rgmii-id"))
764 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
766 priv->interface = PHY_INTERFACE_MODE_MII;
768 if (of_get_property(np, "fsl,magic-packet", NULL))
769 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
771 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
773 /* Find the TBI PHY. If it's not there, we don't support SGMII */
774 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
779 free_rx_pointers(priv);
781 free_tx_pointers(priv);
783 unmap_group_regs(priv);
788 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
789 struct ifreq *ifr, int cmd)
791 struct hwtstamp_config config;
792 struct gfar_private *priv = netdev_priv(netdev);
794 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
797 /* reserved for future extensions */
801 switch (config.tx_type) {
802 case HWTSTAMP_TX_OFF:
803 priv->hwts_tx_en = 0;
806 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
808 priv->hwts_tx_en = 1;
814 switch (config.rx_filter) {
815 case HWTSTAMP_FILTER_NONE:
816 if (priv->hwts_rx_en) {
818 priv->hwts_rx_en = 0;
819 startup_gfar(netdev);
823 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
825 if (!priv->hwts_rx_en) {
827 priv->hwts_rx_en = 1;
828 startup_gfar(netdev);
830 config.rx_filter = HWTSTAMP_FILTER_ALL;
834 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
838 /* Ioctl MII Interface */
839 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
841 struct gfar_private *priv = netdev_priv(dev);
843 if (!netif_running(dev))
846 if (cmd == SIOCSHWTSTAMP)
847 return gfar_hwtstamp_ioctl(dev, rq, cmd);
852 return phy_mii_ioctl(priv->phydev, rq, cmd);
855 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
857 unsigned int new_bit_map = 0x0;
858 int mask = 0x1 << (max_qs - 1), i;
860 for (i = 0; i < max_qs; i++) {
862 new_bit_map = new_bit_map + (1 << i);
868 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
871 u32 rqfpr = FPR_FILER_MASK;
875 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
876 priv->ftp_rqfpr[rqfar] = rqfpr;
877 priv->ftp_rqfcr[rqfar] = rqfcr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
881 rqfcr = RQFCR_CMP_NOMATCH;
882 priv->ftp_rqfpr[rqfar] = rqfpr;
883 priv->ftp_rqfcr[rqfar] = rqfcr;
884 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
887 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
889 priv->ftp_rqfcr[rqfar] = rqfcr;
890 priv->ftp_rqfpr[rqfar] = rqfpr;
891 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
894 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
896 priv->ftp_rqfcr[rqfar] = rqfcr;
897 priv->ftp_rqfpr[rqfar] = rqfpr;
898 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
903 static void gfar_init_filer_table(struct gfar_private *priv)
906 u32 rqfar = MAX_FILER_IDX;
908 u32 rqfpr = FPR_FILER_MASK;
911 rqfcr = RQFCR_CMP_MATCH;
912 priv->ftp_rqfcr[rqfar] = rqfcr;
913 priv->ftp_rqfpr[rqfar] = rqfpr;
914 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
916 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
917 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
918 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
919 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
920 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
921 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
923 /* cur_filer_idx indicated the first non-masked rule */
924 priv->cur_filer_idx = rqfar;
926 /* Rest are masked rules */
927 rqfcr = RQFCR_CMP_NOMATCH;
928 for (i = 0; i < rqfar; i++) {
929 priv->ftp_rqfcr[i] = rqfcr;
930 priv->ftp_rqfpr[i] = rqfpr;
931 gfar_write_filer(priv, i, rqfcr, rqfpr);
935 static void gfar_detect_errata(struct gfar_private *priv)
937 struct device *dev = &priv->ofdev->dev;
938 unsigned int pvr = mfspr(SPRN_PVR);
939 unsigned int svr = mfspr(SPRN_SVR);
940 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
941 unsigned int rev = svr & 0xffff;
943 /* MPC8313 Rev 2.0 and higher; All MPC837x */
944 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
945 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
946 priv->errata |= GFAR_ERRATA_74;
948 /* MPC8313 and MPC837x all rev */
949 if ((pvr == 0x80850010 && mod == 0x80b0) ||
950 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
951 priv->errata |= GFAR_ERRATA_76;
953 /* MPC8313 and MPC837x all rev */
954 if ((pvr == 0x80850010 && mod == 0x80b0) ||
955 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
956 priv->errata |= GFAR_ERRATA_A002;
958 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
959 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
960 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
961 priv->errata |= GFAR_ERRATA_12;
964 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
968 /* Set up the ethernet device structure, private data,
969 * and anything else we need before we start
971 static int gfar_probe(struct platform_device *ofdev)
974 struct net_device *dev = NULL;
975 struct gfar_private *priv = NULL;
976 struct gfar __iomem *regs = NULL;
977 int err = 0, i, grp_idx = 0;
978 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
982 err = gfar_of_init(ofdev, &dev);
987 priv = netdev_priv(dev);
990 priv->node = ofdev->dev.of_node;
991 SET_NETDEV_DEV(dev, &ofdev->dev);
993 spin_lock_init(&priv->bflock);
994 INIT_WORK(&priv->reset_task, gfar_reset_task);
996 dev_set_drvdata(&ofdev->dev, priv);
997 regs = priv->gfargrp[0].regs;
999 gfar_detect_errata(priv);
1001 /* Stop the DMA engine now, in case it was running before
1002 * (The firmware could have used it, and left it running).
1006 /* Reset MAC layer */
1007 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1009 /* We need to delay at least 3 TX clocks */
1012 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1013 gfar_write(®s->maccfg1, tempval);
1015 /* Initialize MACCFG2. */
1016 tempval = MACCFG2_INIT_SETTINGS;
1017 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1018 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1019 gfar_write(®s->maccfg2, tempval);
1021 /* Initialize ECNTRL */
1022 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1024 /* Set the dev->base_addr to the gfar reg region */
1025 dev->base_addr = (unsigned long) regs;
1027 SET_NETDEV_DEV(dev, &ofdev->dev);
1029 /* Fill in the dev structure */
1030 dev->watchdog_timeo = TX_TIMEOUT;
1032 dev->netdev_ops = &gfar_netdev_ops;
1033 dev->ethtool_ops = &gfar_ethtool_ops;
1035 /* Register for napi ...We are registering NAPI for each grp */
1036 for (i = 0; i < priv->num_grps; i++)
1037 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1040 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1041 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1043 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1044 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1047 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1048 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1049 dev->features |= NETIF_F_HW_VLAN_RX;
1052 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1053 priv->extended_hash = 1;
1054 priv->hash_width = 9;
1056 priv->hash_regs[0] = ®s->igaddr0;
1057 priv->hash_regs[1] = ®s->igaddr1;
1058 priv->hash_regs[2] = ®s->igaddr2;
1059 priv->hash_regs[3] = ®s->igaddr3;
1060 priv->hash_regs[4] = ®s->igaddr4;
1061 priv->hash_regs[5] = ®s->igaddr5;
1062 priv->hash_regs[6] = ®s->igaddr6;
1063 priv->hash_regs[7] = ®s->igaddr7;
1064 priv->hash_regs[8] = ®s->gaddr0;
1065 priv->hash_regs[9] = ®s->gaddr1;
1066 priv->hash_regs[10] = ®s->gaddr2;
1067 priv->hash_regs[11] = ®s->gaddr3;
1068 priv->hash_regs[12] = ®s->gaddr4;
1069 priv->hash_regs[13] = ®s->gaddr5;
1070 priv->hash_regs[14] = ®s->gaddr6;
1071 priv->hash_regs[15] = ®s->gaddr7;
1074 priv->extended_hash = 0;
1075 priv->hash_width = 8;
1077 priv->hash_regs[0] = ®s->gaddr0;
1078 priv->hash_regs[1] = ®s->gaddr1;
1079 priv->hash_regs[2] = ®s->gaddr2;
1080 priv->hash_regs[3] = ®s->gaddr3;
1081 priv->hash_regs[4] = ®s->gaddr4;
1082 priv->hash_regs[5] = ®s->gaddr5;
1083 priv->hash_regs[6] = ®s->gaddr6;
1084 priv->hash_regs[7] = ®s->gaddr7;
1087 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1088 priv->padding = DEFAULT_PADDING;
1092 if (dev->features & NETIF_F_IP_CSUM ||
1093 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1094 dev->needed_headroom = GMAC_FCB_LEN;
1096 /* Program the isrg regs only if number of grps > 1 */
1097 if (priv->num_grps > 1) {
1098 baddr = ®s->isrg0;
1099 for (i = 0; i < priv->num_grps; i++) {
1100 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1101 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1102 gfar_write(baddr, isrg);
1108 /* Need to reverse the bit maps as bit_map's MSB is q0
1109 * but, for_each_set_bit parses from right to left, which
1110 * basically reverses the queue numbers
1112 for (i = 0; i< priv->num_grps; i++) {
1113 priv->gfargrp[i].tx_bit_map =
1114 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1115 priv->gfargrp[i].rx_bit_map =
1116 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1119 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1120 * also assign queues to groups
1122 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1123 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1125 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1126 priv->num_rx_queues) {
1127 priv->gfargrp[grp_idx].num_rx_queues++;
1128 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1129 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1130 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1132 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1134 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1135 priv->num_tx_queues) {
1136 priv->gfargrp[grp_idx].num_tx_queues++;
1137 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1138 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1139 tqueue = tqueue | (TQUEUE_EN0 >> i);
1141 priv->gfargrp[grp_idx].rstat = rstat;
1142 priv->gfargrp[grp_idx].tstat = tstat;
1146 gfar_write(®s->rqueue, rqueue);
1147 gfar_write(®s->tqueue, tqueue);
1149 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1151 /* Initializing some of the rx/tx queue level parameters */
1152 for (i = 0; i < priv->num_tx_queues; i++) {
1153 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1154 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1155 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1156 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1159 for (i = 0; i < priv->num_rx_queues; i++) {
1160 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1161 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1162 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1165 /* always enable rx filer */
1166 priv->rx_filer_enable = 1;
1167 /* Enable most messages by default */
1168 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1169 /* use pritority h/w tx queue scheduling for single queue devices */
1170 if (priv->num_tx_queues == 1)
1171 priv->prio_sched_en = 1;
1173 /* Carrier starts down, phylib will bring it up */
1174 netif_carrier_off(dev);
1176 err = register_netdev(dev);
1179 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1183 device_init_wakeup(&dev->dev,
1184 priv->device_flags &
1185 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1187 /* fill out IRQ number and name fields */
1188 for (i = 0; i < priv->num_grps; i++) {
1189 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1190 sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1191 dev->name, "_g", '0' + i, "_tx");
1192 sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1193 dev->name, "_g", '0' + i, "_rx");
1194 sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1195 dev->name, "_g", '0' + i, "_er");
1197 strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1200 /* Initialize the filer table */
1201 gfar_init_filer_table(priv);
1203 /* Create all the sysfs files */
1204 gfar_init_sysfs(dev);
1206 /* Print out the device info */
1207 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1209 /* Even more device info helps when determining which kernel
1210 * provided which set of benchmarks.
1212 netdev_info(dev, "Running with NAPI enabled\n");
1213 for (i = 0; i < priv->num_rx_queues; i++)
1214 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1215 i, priv->rx_queue[i]->rx_ring_size);
1216 for (i = 0; i < priv->num_tx_queues; i++)
1217 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1218 i, priv->tx_queue[i]->tx_ring_size);
1223 unmap_group_regs(priv);
1224 free_tx_pointers(priv);
1225 free_rx_pointers(priv);
1227 of_node_put(priv->phy_node);
1229 of_node_put(priv->tbi_node);
1234 static int gfar_remove(struct platform_device *ofdev)
1236 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1239 of_node_put(priv->phy_node);
1241 of_node_put(priv->tbi_node);
1243 dev_set_drvdata(&ofdev->dev, NULL);
1245 unregister_netdev(priv->ndev);
1246 unmap_group_regs(priv);
1247 free_netdev(priv->ndev);
1254 static int gfar_suspend(struct device *dev)
1256 struct gfar_private *priv = dev_get_drvdata(dev);
1257 struct net_device *ndev = priv->ndev;
1258 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1259 unsigned long flags;
1262 int magic_packet = priv->wol_en &&
1263 (priv->device_flags &
1264 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1266 netif_device_detach(ndev);
1268 if (netif_running(ndev)) {
1270 local_irq_save(flags);
1274 gfar_halt_nodisable(ndev);
1276 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1277 tempval = gfar_read(®s->maccfg1);
1279 tempval &= ~MACCFG1_TX_EN;
1282 tempval &= ~MACCFG1_RX_EN;
1284 gfar_write(®s->maccfg1, tempval);
1288 local_irq_restore(flags);
1293 /* Enable interrupt on Magic Packet */
1294 gfar_write(®s->imask, IMASK_MAG);
1296 /* Enable Magic Packet mode */
1297 tempval = gfar_read(®s->maccfg2);
1298 tempval |= MACCFG2_MPEN;
1299 gfar_write(®s->maccfg2, tempval);
1301 phy_stop(priv->phydev);
1308 static int gfar_resume(struct device *dev)
1310 struct gfar_private *priv = dev_get_drvdata(dev);
1311 struct net_device *ndev = priv->ndev;
1312 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1313 unsigned long flags;
1315 int magic_packet = priv->wol_en &&
1316 (priv->device_flags &
1317 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1319 if (!netif_running(ndev)) {
1320 netif_device_attach(ndev);
1324 if (!magic_packet && priv->phydev)
1325 phy_start(priv->phydev);
1327 /* Disable Magic Packet mode, in case something
1330 local_irq_save(flags);
1334 tempval = gfar_read(®s->maccfg2);
1335 tempval &= ~MACCFG2_MPEN;
1336 gfar_write(®s->maccfg2, tempval);
1342 local_irq_restore(flags);
1344 netif_device_attach(ndev);
1351 static int gfar_restore(struct device *dev)
1353 struct gfar_private *priv = dev_get_drvdata(dev);
1354 struct net_device *ndev = priv->ndev;
1356 if (!netif_running(ndev))
1359 gfar_init_bds(ndev);
1360 init_registers(ndev);
1361 gfar_set_mac_address(ndev);
1362 gfar_init_mac(ndev);
1367 priv->oldduplex = -1;
1370 phy_start(priv->phydev);
1372 netif_device_attach(ndev);
1378 static struct dev_pm_ops gfar_pm_ops = {
1379 .suspend = gfar_suspend,
1380 .resume = gfar_resume,
1381 .freeze = gfar_suspend,
1382 .thaw = gfar_resume,
1383 .restore = gfar_restore,
1386 #define GFAR_PM_OPS (&gfar_pm_ops)
1390 #define GFAR_PM_OPS NULL
1394 /* Reads the controller's registers to determine what interface
1395 * connects it to the PHY.
1397 static phy_interface_t gfar_get_interface(struct net_device *dev)
1399 struct gfar_private *priv = netdev_priv(dev);
1400 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1403 ecntrl = gfar_read(®s->ecntrl);
1405 if (ecntrl & ECNTRL_SGMII_MODE)
1406 return PHY_INTERFACE_MODE_SGMII;
1408 if (ecntrl & ECNTRL_TBI_MODE) {
1409 if (ecntrl & ECNTRL_REDUCED_MODE)
1410 return PHY_INTERFACE_MODE_RTBI;
1412 return PHY_INTERFACE_MODE_TBI;
1415 if (ecntrl & ECNTRL_REDUCED_MODE) {
1416 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1417 return PHY_INTERFACE_MODE_RMII;
1420 phy_interface_t interface = priv->interface;
1422 /* This isn't autodetected right now, so it must
1423 * be set by the device tree or platform code.
1425 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1426 return PHY_INTERFACE_MODE_RGMII_ID;
1428 return PHY_INTERFACE_MODE_RGMII;
1432 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1433 return PHY_INTERFACE_MODE_GMII;
1435 return PHY_INTERFACE_MODE_MII;
1439 /* Initializes driver's PHY state, and attaches to the PHY.
1440 * Returns 0 on success.
1442 static int init_phy(struct net_device *dev)
1444 struct gfar_private *priv = netdev_priv(dev);
1445 uint gigabit_support =
1446 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1447 SUPPORTED_1000baseT_Full : 0;
1448 phy_interface_t interface;
1452 priv->oldduplex = -1;
1454 interface = gfar_get_interface(dev);
1456 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1459 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1461 if (!priv->phydev) {
1462 dev_err(&dev->dev, "could not attach to PHY\n");
1466 if (interface == PHY_INTERFACE_MODE_SGMII)
1467 gfar_configure_serdes(dev);
1469 /* Remove any features not supported by the controller */
1470 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1471 priv->phydev->advertising = priv->phydev->supported;
1476 /* Initialize TBI PHY interface for communicating with the
1477 * SERDES lynx PHY on the chip. We communicate with this PHY
1478 * through the MDIO bus on each controller, treating it as a
1479 * "normal" PHY at the address found in the TBIPA register. We assume
1480 * that the TBIPA register is valid. Either the MDIO bus code will set
1481 * it to a value that doesn't conflict with other PHYs on the bus, or the
1482 * value doesn't matter, as there are no other PHYs on the bus.
1484 static void gfar_configure_serdes(struct net_device *dev)
1486 struct gfar_private *priv = netdev_priv(dev);
1487 struct phy_device *tbiphy;
1489 if (!priv->tbi_node) {
1490 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1491 "device tree specify a tbi-handle\n");
1495 tbiphy = of_phy_find_device(priv->tbi_node);
1497 dev_err(&dev->dev, "error: Could not get TBI device\n");
1501 /* If the link is already up, we must already be ok, and don't need to
1502 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1503 * everything for us? Resetting it takes the link down and requires
1504 * several seconds for it to come back.
1506 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1509 /* Single clk mode, mii mode off(for serdes communication) */
1510 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1512 phy_write(tbiphy, MII_ADVERTISE,
1513 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1514 ADVERTISE_1000XPSE_ASYM);
1516 phy_write(tbiphy, MII_BMCR,
1517 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1521 static void init_registers(struct net_device *dev)
1523 struct gfar_private *priv = netdev_priv(dev);
1524 struct gfar __iomem *regs = NULL;
1527 for (i = 0; i < priv->num_grps; i++) {
1528 regs = priv->gfargrp[i].regs;
1530 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1532 /* Initialize IMASK */
1533 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1536 regs = priv->gfargrp[0].regs;
1537 /* Init hash registers to zero */
1538 gfar_write(®s->igaddr0, 0);
1539 gfar_write(®s->igaddr1, 0);
1540 gfar_write(®s->igaddr2, 0);
1541 gfar_write(®s->igaddr3, 0);
1542 gfar_write(®s->igaddr4, 0);
1543 gfar_write(®s->igaddr5, 0);
1544 gfar_write(®s->igaddr6, 0);
1545 gfar_write(®s->igaddr7, 0);
1547 gfar_write(®s->gaddr0, 0);
1548 gfar_write(®s->gaddr1, 0);
1549 gfar_write(®s->gaddr2, 0);
1550 gfar_write(®s->gaddr3, 0);
1551 gfar_write(®s->gaddr4, 0);
1552 gfar_write(®s->gaddr5, 0);
1553 gfar_write(®s->gaddr6, 0);
1554 gfar_write(®s->gaddr7, 0);
1556 /* Zero out the rmon mib registers if it has them */
1557 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1558 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1560 /* Mask off the CAM interrupts */
1561 gfar_write(®s->rmon.cam1, 0xffffffff);
1562 gfar_write(®s->rmon.cam2, 0xffffffff);
1565 /* Initialize the max receive buffer length */
1566 gfar_write(®s->mrblr, priv->rx_buffer_size);
1568 /* Initialize the Minimum Frame Length Register */
1569 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1572 static int __gfar_is_rx_idle(struct gfar_private *priv)
1576 /* Normaly TSEC should not hang on GRS commands, so we should
1577 * actually wait for IEVENT_GRSC flag.
1579 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1582 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1583 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1584 * and the Rx can be safely reset.
1586 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1588 if ((res & 0xffff) == (res >> 16))
1594 /* Halt the receive and transmit queues */
1595 static void gfar_halt_nodisable(struct net_device *dev)
1597 struct gfar_private *priv = netdev_priv(dev);
1598 struct gfar __iomem *regs = NULL;
1602 for (i = 0; i < priv->num_grps; i++) {
1603 regs = priv->gfargrp[i].regs;
1604 /* Mask all interrupts */
1605 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1607 /* Clear all interrupts */
1608 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
1611 regs = priv->gfargrp[0].regs;
1612 /* Stop the DMA, and wait for it to stop */
1613 tempval = gfar_read(®s->dmactrl);
1614 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1615 (DMACTRL_GRS | DMACTRL_GTS)) {
1618 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1619 gfar_write(®s->dmactrl, tempval);
1622 ret = spin_event_timeout(((gfar_read(®s->ievent) &
1623 (IEVENT_GRSC | IEVENT_GTSC)) ==
1624 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1625 if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC))
1626 ret = __gfar_is_rx_idle(priv);
1631 /* Halt the receive and transmit queues */
1632 void gfar_halt(struct net_device *dev)
1634 struct gfar_private *priv = netdev_priv(dev);
1635 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1638 gfar_halt_nodisable(dev);
1640 /* Disable Rx and Tx */
1641 tempval = gfar_read(®s->maccfg1);
1642 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1643 gfar_write(®s->maccfg1, tempval);
1646 static void free_grp_irqs(struct gfar_priv_grp *grp)
1648 free_irq(grp->interruptError, grp);
1649 free_irq(grp->interruptTransmit, grp);
1650 free_irq(grp->interruptReceive, grp);
1653 void stop_gfar(struct net_device *dev)
1655 struct gfar_private *priv = netdev_priv(dev);
1656 unsigned long flags;
1659 phy_stop(priv->phydev);
1663 local_irq_save(flags);
1671 local_irq_restore(flags);
1674 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1675 for (i = 0; i < priv->num_grps; i++)
1676 free_grp_irqs(&priv->gfargrp[i]);
1678 for (i = 0; i < priv->num_grps; i++)
1679 free_irq(priv->gfargrp[i].interruptTransmit,
1683 free_skb_resources(priv);
1686 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1688 struct txbd8 *txbdp;
1689 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1692 txbdp = tx_queue->tx_bd_base;
1694 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1695 if (!tx_queue->tx_skbuff[i])
1698 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1699 txbdp->length, DMA_TO_DEVICE);
1701 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1704 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1705 txbdp->length, DMA_TO_DEVICE);
1708 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1709 tx_queue->tx_skbuff[i] = NULL;
1711 kfree(tx_queue->tx_skbuff);
1714 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1716 struct rxbd8 *rxbdp;
1717 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1720 rxbdp = rx_queue->rx_bd_base;
1722 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1723 if (rx_queue->rx_skbuff[i]) {
1724 dma_unmap_single(&priv->ofdev->dev,
1725 rxbdp->bufPtr, priv->rx_buffer_size,
1727 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1728 rx_queue->rx_skbuff[i] = NULL;
1734 kfree(rx_queue->rx_skbuff);
1737 /* If there are any tx skbs or rx skbs still around, free them.
1738 * Then free tx_skbuff and rx_skbuff
1740 static void free_skb_resources(struct gfar_private *priv)
1742 struct gfar_priv_tx_q *tx_queue = NULL;
1743 struct gfar_priv_rx_q *rx_queue = NULL;
1746 /* Go through all the buffer descriptors and free their data buffers */
1747 for (i = 0; i < priv->num_tx_queues; i++) {
1748 struct netdev_queue *txq;
1750 tx_queue = priv->tx_queue[i];
1751 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1752 if (tx_queue->tx_skbuff)
1753 free_skb_tx_queue(tx_queue);
1754 netdev_tx_reset_queue(txq);
1757 for (i = 0; i < priv->num_rx_queues; i++) {
1758 rx_queue = priv->rx_queue[i];
1759 if (rx_queue->rx_skbuff)
1760 free_skb_rx_queue(rx_queue);
1763 dma_free_coherent(&priv->ofdev->dev,
1764 sizeof(struct txbd8) * priv->total_tx_ring_size +
1765 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1766 priv->tx_queue[0]->tx_bd_base,
1767 priv->tx_queue[0]->tx_bd_dma_base);
1768 skb_queue_purge(&priv->rx_recycle);
1771 void gfar_start(struct net_device *dev)
1773 struct gfar_private *priv = netdev_priv(dev);
1774 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1778 /* Enable Rx and Tx in MACCFG1 */
1779 tempval = gfar_read(®s->maccfg1);
1780 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1781 gfar_write(®s->maccfg1, tempval);
1783 /* Initialize DMACTRL to have WWR and WOP */
1784 tempval = gfar_read(®s->dmactrl);
1785 tempval |= DMACTRL_INIT_SETTINGS;
1786 gfar_write(®s->dmactrl, tempval);
1788 /* Make sure we aren't stopped */
1789 tempval = gfar_read(®s->dmactrl);
1790 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1791 gfar_write(®s->dmactrl, tempval);
1793 for (i = 0; i < priv->num_grps; i++) {
1794 regs = priv->gfargrp[i].regs;
1795 /* Clear THLT/RHLT, so that the DMA starts polling now */
1796 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
1797 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1798 /* Unmask the interrupts we look for */
1799 gfar_write(®s->imask, IMASK_DEFAULT);
1802 dev->trans_start = jiffies; /* prevent tx timeout */
1805 void gfar_configure_coalescing(struct gfar_private *priv,
1806 unsigned long tx_mask, unsigned long rx_mask)
1808 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1812 /* Backward compatible case ---- even if we enable
1813 * multiple queues, there's only single reg to program
1815 gfar_write(®s->txic, 0);
1816 if (likely(priv->tx_queue[0]->txcoalescing))
1817 gfar_write(®s->txic, priv->tx_queue[0]->txic);
1819 gfar_write(®s->rxic, 0);
1820 if (unlikely(priv->rx_queue[0]->rxcoalescing))
1821 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
1823 if (priv->mode == MQ_MG_MODE) {
1824 baddr = ®s->txic0;
1825 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1826 gfar_write(baddr + i, 0);
1827 if (likely(priv->tx_queue[i]->txcoalescing))
1828 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1831 baddr = ®s->rxic0;
1832 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1833 gfar_write(baddr + i, 0);
1834 if (likely(priv->rx_queue[i]->rxcoalescing))
1835 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1840 static int register_grp_irqs(struct gfar_priv_grp *grp)
1842 struct gfar_private *priv = grp->priv;
1843 struct net_device *dev = priv->ndev;
1846 /* If the device has multiple interrupts, register for
1847 * them. Otherwise, only register for the one
1849 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1850 /* Install our interrupt handlers for Error,
1851 * Transmit, and Receive
1853 if ((err = request_irq(grp->interruptError, gfar_error,
1854 0, grp->int_name_er, grp)) < 0) {
1855 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1856 grp->interruptError);
1861 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1862 0, grp->int_name_tx, grp)) < 0) {
1863 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1864 grp->interruptTransmit);
1868 if ((err = request_irq(grp->interruptReceive, gfar_receive,
1869 0, grp->int_name_rx, grp)) < 0) {
1870 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1871 grp->interruptReceive);
1875 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
1876 0, grp->int_name_tx, grp)) < 0) {
1877 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1878 grp->interruptTransmit);
1886 free_irq(grp->interruptTransmit, grp);
1888 free_irq(grp->interruptError, grp);
1894 /* Bring the controller up and running */
1895 int startup_gfar(struct net_device *ndev)
1897 struct gfar_private *priv = netdev_priv(ndev);
1898 struct gfar __iomem *regs = NULL;
1901 for (i = 0; i < priv->num_grps; i++) {
1902 regs= priv->gfargrp[i].regs;
1903 gfar_write(®s->imask, IMASK_INIT_CLEAR);
1906 regs= priv->gfargrp[0].regs;
1907 err = gfar_alloc_skb_resources(ndev);
1911 gfar_init_mac(ndev);
1913 for (i = 0; i < priv->num_grps; i++) {
1914 err = register_grp_irqs(&priv->gfargrp[i]);
1916 for (j = 0; j < i; j++)
1917 free_grp_irqs(&priv->gfargrp[j]);
1922 /* Start the controller */
1925 phy_start(priv->phydev);
1927 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1932 free_skb_resources(priv);
1936 /* Called when something needs to use the ethernet device
1937 * Returns 0 for success.
1939 static int gfar_enet_open(struct net_device *dev)
1941 struct gfar_private *priv = netdev_priv(dev);
1946 skb_queue_head_init(&priv->rx_recycle);
1948 /* Initialize a bunch of registers */
1949 init_registers(dev);
1951 gfar_set_mac_address(dev);
1953 err = init_phy(dev);
1960 err = startup_gfar(dev);
1966 netif_tx_start_all_queues(dev);
1968 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1973 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1975 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1977 memset(fcb, 0, GMAC_FCB_LEN);
1982 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1985 /* If we're here, it's a IP packet with a TCP or UDP
1986 * payload. We set it to checksum, using a pseudo-header
1989 u8 flags = TXFCB_DEFAULT;
1991 /* Tell the controller what the protocol is
1992 * And provide the already calculated phcs
1994 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1996 fcb->phcs = udp_hdr(skb)->check;
1998 fcb->phcs = tcp_hdr(skb)->check;
2000 /* l3os is the distance between the start of the
2001 * frame (skb->data) and the start of the IP hdr.
2002 * l4os is the distance between the start of the
2003 * l3 hdr and the l4 hdr
2005 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2006 fcb->l4os = skb_network_header_len(skb);
2011 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2013 fcb->flags |= TXFCB_VLN;
2014 fcb->vlctl = vlan_tx_tag_get(skb);
2017 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2018 struct txbd8 *base, int ring_size)
2020 struct txbd8 *new_bd = bdp + stride;
2022 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2025 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2028 return skip_txbd(bdp, 1, base, ring_size);
2031 /* This is called by the kernel when a frame is ready for transmission.
2032 * It is pointed to by the dev->hard_start_xmit function pointer
2034 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2036 struct gfar_private *priv = netdev_priv(dev);
2037 struct gfar_priv_tx_q *tx_queue = NULL;
2038 struct netdev_queue *txq;
2039 struct gfar __iomem *regs = NULL;
2040 struct txfcb *fcb = NULL;
2041 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2043 int i, rq = 0, do_tstamp = 0;
2045 unsigned long flags;
2046 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2048 /* TOE=1 frames larger than 2500 bytes may see excess delays
2049 * before start of transmission.
2051 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2052 skb->ip_summed == CHECKSUM_PARTIAL &&
2056 ret = skb_checksum_help(skb);
2061 rq = skb->queue_mapping;
2062 tx_queue = priv->tx_queue[rq];
2063 txq = netdev_get_tx_queue(dev, rq);
2064 base = tx_queue->tx_bd_base;
2065 regs = tx_queue->grp->regs;
2067 /* check if time stamp should be generated */
2068 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2069 priv->hwts_tx_en)) {
2071 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2074 /* make space for additional header when fcb is needed */
2075 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2076 vlan_tx_tag_present(skb) ||
2077 unlikely(do_tstamp)) &&
2078 (skb_headroom(skb) < fcb_length)) {
2079 struct sk_buff *skb_new;
2081 skb_new = skb_realloc_headroom(skb, fcb_length);
2083 dev->stats.tx_errors++;
2085 return NETDEV_TX_OK;
2089 skb_set_owner_w(skb_new, skb->sk);
2094 /* total number of fragments in the SKB */
2095 nr_frags = skb_shinfo(skb)->nr_frags;
2097 /* calculate the required number of TxBDs for this skb */
2098 if (unlikely(do_tstamp))
2099 nr_txbds = nr_frags + 2;
2101 nr_txbds = nr_frags + 1;
2103 /* check if there is space to queue this packet */
2104 if (nr_txbds > tx_queue->num_txbdfree) {
2105 /* no space, stop the queue */
2106 netif_tx_stop_queue(txq);
2107 dev->stats.tx_fifo_errors++;
2108 return NETDEV_TX_BUSY;
2111 /* Update transmit stats */
2112 tx_queue->stats.tx_bytes += skb->len;
2113 tx_queue->stats.tx_packets++;
2115 txbdp = txbdp_start = tx_queue->cur_tx;
2116 lstatus = txbdp->lstatus;
2118 /* Time stamp insertion requires one additional TxBD */
2119 if (unlikely(do_tstamp))
2120 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2121 tx_queue->tx_ring_size);
2123 if (nr_frags == 0) {
2124 if (unlikely(do_tstamp))
2125 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2128 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2130 /* Place the fragment addresses and lengths into the TxBDs */
2131 for (i = 0; i < nr_frags; i++) {
2132 /* Point at the next BD, wrapping as needed */
2133 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2135 length = skb_shinfo(skb)->frags[i].size;
2137 lstatus = txbdp->lstatus | length |
2138 BD_LFLAG(TXBD_READY);
2140 /* Handle the last BD specially */
2141 if (i == nr_frags - 1)
2142 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2144 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2145 &skb_shinfo(skb)->frags[i],
2150 /* set the TxBD length and buffer pointer */
2151 txbdp->bufPtr = bufaddr;
2152 txbdp->lstatus = lstatus;
2155 lstatus = txbdp_start->lstatus;
2158 /* Add TxPAL between FCB and frame if required */
2159 if (unlikely(do_tstamp)) {
2160 skb_push(skb, GMAC_TXPAL_LEN);
2161 memset(skb->data, 0, GMAC_TXPAL_LEN);
2164 /* Set up checksumming */
2165 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2166 fcb = gfar_add_fcb(skb);
2167 /* as specified by errata */
2168 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2169 ((unsigned long)fcb % 0x20) > 0x18)) {
2170 __skb_pull(skb, GMAC_FCB_LEN);
2171 skb_checksum_help(skb);
2173 lstatus |= BD_LFLAG(TXBD_TOE);
2174 gfar_tx_checksum(skb, fcb, fcb_length);
2178 if (vlan_tx_tag_present(skb)) {
2179 if (unlikely(NULL == fcb)) {
2180 fcb = gfar_add_fcb(skb);
2181 lstatus |= BD_LFLAG(TXBD_TOE);
2184 gfar_tx_vlan(skb, fcb);
2187 /* Setup tx hardware time stamping if requested */
2188 if (unlikely(do_tstamp)) {
2189 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2191 fcb = gfar_add_fcb(skb);
2193 lstatus |= BD_LFLAG(TXBD_TOE);
2196 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2197 skb_headlen(skb), DMA_TO_DEVICE);
2199 /* If time stamping is requested one additional TxBD must be set up. The
2200 * first TxBD points to the FCB and must have a data length of
2201 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2202 * the full frame length.
2204 if (unlikely(do_tstamp)) {
2205 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2206 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2207 (skb_headlen(skb) - fcb_length);
2208 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2210 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2213 netdev_tx_sent_queue(txq, skb->len);
2215 /* We can work in parallel with gfar_clean_tx_ring(), except
2216 * when modifying num_txbdfree. Note that we didn't grab the lock
2217 * when we were reading the num_txbdfree and checking for available
2218 * space, that's because outside of this function it can only grow,
2219 * and once we've got needed space, it cannot suddenly disappear.
2221 * The lock also protects us from gfar_error(), which can modify
2222 * regs->tstat and thus retrigger the transfers, which is why we
2223 * also must grab the lock before setting ready bit for the first
2224 * to be transmitted BD.
2226 spin_lock_irqsave(&tx_queue->txlock, flags);
2228 /* The powerpc-specific eieio() is used, as wmb() has too strong
2229 * semantics (it requires synchronization between cacheable and
2230 * uncacheable mappings, which eieio doesn't provide and which we
2231 * don't need), thus requiring a more expensive sync instruction. At
2232 * some point, the set of architecture-independent barrier functions
2233 * should be expanded to include weaker barriers.
2237 txbdp_start->lstatus = lstatus;
2239 eieio(); /* force lstatus write before tx_skbuff */
2241 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2243 /* Update the current skb pointer to the next entry we will use
2244 * (wrapping if necessary)
2246 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2247 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2249 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2251 /* reduce TxBD free count */
2252 tx_queue->num_txbdfree -= (nr_txbds);
2254 /* If the next BD still needs to be cleaned up, then the bds
2255 * are full. We need to tell the kernel to stop sending us stuff.
2257 if (!tx_queue->num_txbdfree) {
2258 netif_tx_stop_queue(txq);
2260 dev->stats.tx_fifo_errors++;
2263 /* Tell the DMA to go go go */
2264 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2267 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2269 return NETDEV_TX_OK;
2272 /* Stops the kernel queue, and halts the controller */
2273 static int gfar_close(struct net_device *dev)
2275 struct gfar_private *priv = netdev_priv(dev);
2279 cancel_work_sync(&priv->reset_task);
2282 /* Disconnect from the PHY */
2283 phy_disconnect(priv->phydev);
2284 priv->phydev = NULL;
2286 netif_tx_stop_all_queues(dev);
2291 /* Changes the mac address if the controller is not running. */
2292 static int gfar_set_mac_address(struct net_device *dev)
2294 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2299 /* Check if rx parser should be activated */
2300 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2302 struct gfar __iomem *regs;
2305 regs = priv->gfargrp[0].regs;
2307 tempval = gfar_read(®s->rctrl);
2308 /* If parse is no longer required, then disable parser */
2309 if (tempval & RCTRL_REQ_PARSER)
2310 tempval |= RCTRL_PRSDEP_INIT;
2312 tempval &= ~RCTRL_PRSDEP_INIT;
2313 gfar_write(®s->rctrl, tempval);
2316 /* Enables and disables VLAN insertion/extraction */
2317 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2319 struct gfar_private *priv = netdev_priv(dev);
2320 struct gfar __iomem *regs = NULL;
2321 unsigned long flags;
2324 regs = priv->gfargrp[0].regs;
2325 local_irq_save(flags);
2328 if (features & NETIF_F_HW_VLAN_TX) {
2329 /* Enable VLAN tag insertion */
2330 tempval = gfar_read(®s->tctrl);
2331 tempval |= TCTRL_VLINS;
2332 gfar_write(®s->tctrl, tempval);
2334 /* Disable VLAN tag insertion */
2335 tempval = gfar_read(®s->tctrl);
2336 tempval &= ~TCTRL_VLINS;
2337 gfar_write(®s->tctrl, tempval);
2340 if (features & NETIF_F_HW_VLAN_RX) {
2341 /* Enable VLAN tag extraction */
2342 tempval = gfar_read(®s->rctrl);
2343 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2344 gfar_write(®s->rctrl, tempval);
2346 /* Disable VLAN tag extraction */
2347 tempval = gfar_read(®s->rctrl);
2348 tempval &= ~RCTRL_VLEX;
2349 gfar_write(®s->rctrl, tempval);
2351 gfar_check_rx_parser_mode(priv);
2354 gfar_change_mtu(dev, dev->mtu);
2357 local_irq_restore(flags);
2360 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2362 int tempsize, tempval;
2363 struct gfar_private *priv = netdev_priv(dev);
2364 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2365 int oldsize = priv->rx_buffer_size;
2366 int frame_size = new_mtu + ETH_HLEN;
2368 if (gfar_is_vlan_on(priv))
2369 frame_size += VLAN_HLEN;
2371 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2372 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2376 if (gfar_uses_fcb(priv))
2377 frame_size += GMAC_FCB_LEN;
2379 frame_size += priv->padding;
2381 tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2382 INCREMENTAL_BUFFER_SIZE;
2384 /* Only stop and start the controller if it isn't already
2385 * stopped, and we changed something
2387 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2390 priv->rx_buffer_size = tempsize;
2394 gfar_write(®s->mrblr, priv->rx_buffer_size);
2395 gfar_write(®s->maxfrm, priv->rx_buffer_size);
2397 /* If the mtu is larger than the max size for standard
2398 * ethernet frames (ie, a jumbo frame), then set maccfg2
2399 * to allow huge frames, and to check the length
2401 tempval = gfar_read(®s->maccfg2);
2403 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2404 gfar_has_errata(priv, GFAR_ERRATA_74))
2405 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2407 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2409 gfar_write(®s->maccfg2, tempval);
2411 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2417 /* gfar_reset_task gets scheduled when a packet has not been
2418 * transmitted after a set amount of time.
2419 * For now, assume that clearing out all the structures, and
2420 * starting over will fix the problem.
2422 static void gfar_reset_task(struct work_struct *work)
2424 struct gfar_private *priv = container_of(work, struct gfar_private,
2426 struct net_device *dev = priv->ndev;
2428 if (dev->flags & IFF_UP) {
2429 netif_tx_stop_all_queues(dev);
2432 netif_tx_start_all_queues(dev);
2435 netif_tx_schedule_all(dev);
2438 static void gfar_timeout(struct net_device *dev)
2440 struct gfar_private *priv = netdev_priv(dev);
2442 dev->stats.tx_errors++;
2443 schedule_work(&priv->reset_task);
2446 static void gfar_align_skb(struct sk_buff *skb)
2448 /* We need the data buffer to be aligned properly. We will reserve
2449 * as many bytes as needed to align the data properly
2451 skb_reserve(skb, RXBUF_ALIGNMENT -
2452 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2455 /* Interrupt Handler for Transmit complete */
2456 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2458 struct net_device *dev = tx_queue->dev;
2459 struct netdev_queue *txq;
2460 struct gfar_private *priv = netdev_priv(dev);
2461 struct gfar_priv_rx_q *rx_queue = NULL;
2462 struct txbd8 *bdp, *next = NULL;
2463 struct txbd8 *lbdp = NULL;
2464 struct txbd8 *base = tx_queue->tx_bd_base;
2465 struct sk_buff *skb;
2467 int tx_ring_size = tx_queue->tx_ring_size;
2468 int frags = 0, nr_txbds = 0;
2471 int tqi = tx_queue->qindex;
2472 unsigned int bytes_sent = 0;
2476 rx_queue = priv->rx_queue[tqi];
2477 txq = netdev_get_tx_queue(dev, tqi);
2478 bdp = tx_queue->dirty_tx;
2479 skb_dirtytx = tx_queue->skb_dirtytx;
2481 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2482 unsigned long flags;
2484 frags = skb_shinfo(skb)->nr_frags;
2486 /* When time stamping, one additional TxBD must be freed.
2487 * Also, we need to dma_unmap_single() the TxPAL.
2489 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2490 nr_txbds = frags + 2;
2492 nr_txbds = frags + 1;
2494 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2496 lstatus = lbdp->lstatus;
2498 /* Only clean completed frames */
2499 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2500 (lstatus & BD_LENGTH_MASK))
2503 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2504 next = next_txbd(bdp, base, tx_ring_size);
2505 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2507 buflen = bdp->length;
2509 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2510 buflen, DMA_TO_DEVICE);
2512 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2513 struct skb_shared_hwtstamps shhwtstamps;
2514 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2516 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2517 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2518 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2519 skb_tstamp_tx(skb, &shhwtstamps);
2520 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2524 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2525 bdp = next_txbd(bdp, base, tx_ring_size);
2527 for (i = 0; i < frags; i++) {
2528 dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2529 bdp->length, DMA_TO_DEVICE);
2530 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2531 bdp = next_txbd(bdp, base, tx_ring_size);
2534 bytes_sent += skb->len;
2536 /* If there's room in the queue (limit it to rx_buffer_size)
2537 * we add this skb back into the pool, if it's the right size
2539 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2540 skb_recycle_check(skb, priv->rx_buffer_size +
2542 gfar_align_skb(skb);
2543 skb_queue_head(&priv->rx_recycle, skb);
2545 dev_kfree_skb_any(skb);
2547 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2549 skb_dirtytx = (skb_dirtytx + 1) &
2550 TX_RING_MOD_MASK(tx_ring_size);
2553 spin_lock_irqsave(&tx_queue->txlock, flags);
2554 tx_queue->num_txbdfree += nr_txbds;
2555 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2558 /* If we freed a buffer, we can restart transmission, if necessary */
2559 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2560 netif_wake_subqueue(dev, tqi);
2562 /* Update dirty indicators */
2563 tx_queue->skb_dirtytx = skb_dirtytx;
2564 tx_queue->dirty_tx = bdp;
2566 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2571 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2573 unsigned long flags;
2575 spin_lock_irqsave(&gfargrp->grplock, flags);
2576 if (napi_schedule_prep(&gfargrp->napi)) {
2577 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2578 __napi_schedule(&gfargrp->napi);
2580 /* Clear IEVENT, so interrupts aren't called again
2581 * because of the packets that have already arrived.
2583 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2585 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2589 /* Interrupt Handler for Transmit complete */
2590 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2592 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2596 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2597 struct sk_buff *skb)
2599 struct net_device *dev = rx_queue->dev;
2600 struct gfar_private *priv = netdev_priv(dev);
2603 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2604 priv->rx_buffer_size, DMA_FROM_DEVICE);
2605 gfar_init_rxbdp(rx_queue, bdp, buf);
2608 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2610 struct gfar_private *priv = netdev_priv(dev);
2611 struct sk_buff *skb = NULL;
2613 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2617 gfar_align_skb(skb);
2622 struct sk_buff *gfar_new_skb(struct net_device *dev)
2624 struct gfar_private *priv = netdev_priv(dev);
2625 struct sk_buff *skb = NULL;
2627 skb = skb_dequeue(&priv->rx_recycle);
2629 skb = gfar_alloc_skb(dev);
2634 static inline void count_errors(unsigned short status, struct net_device *dev)
2636 struct gfar_private *priv = netdev_priv(dev);
2637 struct net_device_stats *stats = &dev->stats;
2638 struct gfar_extra_stats *estats = &priv->extra_stats;
2640 /* If the packet was truncated, none of the other errors matter */
2641 if (status & RXBD_TRUNCATED) {
2642 stats->rx_length_errors++;
2648 /* Count the errors, if there were any */
2649 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2650 stats->rx_length_errors++;
2652 if (status & RXBD_LARGE)
2657 if (status & RXBD_NONOCTET) {
2658 stats->rx_frame_errors++;
2659 estats->rx_nonoctet++;
2661 if (status & RXBD_CRCERR) {
2662 estats->rx_crcerr++;
2663 stats->rx_crc_errors++;
2665 if (status & RXBD_OVERRUN) {
2666 estats->rx_overrun++;
2667 stats->rx_crc_errors++;
2671 irqreturn_t gfar_receive(int irq, void *grp_id)
2673 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2677 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2679 /* If valid headers were found, and valid sums
2680 * were verified, then we tell the kernel that no
2681 * checksumming is necessary. Otherwise, it is [FIXME]
2683 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2684 skb->ip_summed = CHECKSUM_UNNECESSARY;
2686 skb_checksum_none_assert(skb);
2690 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2691 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2692 int amount_pull, struct napi_struct *napi)
2694 struct gfar_private *priv = netdev_priv(dev);
2695 struct rxfcb *fcb = NULL;
2699 /* fcb is at the beginning if exists */
2700 fcb = (struct rxfcb *)skb->data;
2702 /* Remove the FCB from the skb
2703 * Remove the padded bytes, if there are any
2706 skb_record_rx_queue(skb, fcb->rq);
2707 skb_pull(skb, amount_pull);
2710 /* Get receive timestamp from the skb */
2711 if (priv->hwts_rx_en) {
2712 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2713 u64 *ns = (u64 *) skb->data;
2715 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2716 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2720 skb_pull(skb, priv->padding);
2722 if (dev->features & NETIF_F_RXCSUM)
2723 gfar_rx_checksum(skb, fcb);
2725 /* Tell the skb what kind of packet this is */
2726 skb->protocol = eth_type_trans(skb, dev);
2728 /* There's need to check for NETIF_F_HW_VLAN_RX here.
2729 * Even if vlan rx accel is disabled, on some chips
2730 * RXFCB_VLN is pseudo randomly set.
2732 if (dev->features & NETIF_F_HW_VLAN_RX &&
2733 fcb->flags & RXFCB_VLN)
2734 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2736 /* Send the packet up the stack */
2737 ret = napi_gro_receive(napi, skb);
2739 if (GRO_DROP == ret)
2740 priv->extra_stats.kernel_dropped++;
2745 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2746 * until the budget/quota has been reached. Returns the number
2749 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2751 struct net_device *dev = rx_queue->dev;
2752 struct rxbd8 *bdp, *base;
2753 struct sk_buff *skb;
2757 struct gfar_private *priv = netdev_priv(dev);
2759 /* Get the first full descriptor */
2760 bdp = rx_queue->cur_rx;
2761 base = rx_queue->rx_bd_base;
2763 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2765 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2766 struct sk_buff *newskb;
2770 /* Add another skb for the future */
2771 newskb = gfar_new_skb(dev);
2773 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2775 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2776 priv->rx_buffer_size, DMA_FROM_DEVICE);
2778 if (unlikely(!(bdp->status & RXBD_ERR) &&
2779 bdp->length > priv->rx_buffer_size))
2780 bdp->status = RXBD_LARGE;
2782 /* We drop the frame if we failed to allocate a new buffer */
2783 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2784 bdp->status & RXBD_ERR)) {
2785 count_errors(bdp->status, dev);
2787 if (unlikely(!newskb))
2790 skb_queue_head(&priv->rx_recycle, skb);
2792 /* Increment the number of packets */
2793 rx_queue->stats.rx_packets++;
2797 pkt_len = bdp->length - ETH_FCS_LEN;
2798 /* Remove the FCS from the packet length */
2799 skb_put(skb, pkt_len);
2800 rx_queue->stats.rx_bytes += pkt_len;
2801 skb_record_rx_queue(skb, rx_queue->qindex);
2802 gfar_process_frame(dev, skb, amount_pull,
2803 &rx_queue->grp->napi);
2806 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2807 rx_queue->stats.rx_dropped++;
2808 priv->extra_stats.rx_skbmissing++;
2813 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2815 /* Setup the new bdp */
2816 gfar_new_rxbdp(rx_queue, bdp, newskb);
2818 /* Update to the next pointer */
2819 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2821 /* update to point at the next skb */
2822 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2823 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2826 /* Update the current rxbd pointer to be the next one */
2827 rx_queue->cur_rx = bdp;
2832 static int gfar_poll(struct napi_struct *napi, int budget)
2834 struct gfar_priv_grp *gfargrp =
2835 container_of(napi, struct gfar_priv_grp, napi);
2836 struct gfar_private *priv = gfargrp->priv;
2837 struct gfar __iomem *regs = gfargrp->regs;
2838 struct gfar_priv_tx_q *tx_queue = NULL;
2839 struct gfar_priv_rx_q *rx_queue = NULL;
2840 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2841 int tx_cleaned = 0, i, left_over_budget = budget;
2842 unsigned long serviced_queues = 0;
2845 num_queues = gfargrp->num_rx_queues;
2846 budget_per_queue = budget/num_queues;
2848 /* Clear IEVENT, so interrupts aren't called again
2849 * because of the packets that have already arrived
2851 gfar_write(®s->ievent, IEVENT_RTX_MASK);
2853 while (num_queues && left_over_budget) {
2854 budget_per_queue = left_over_budget/num_queues;
2855 left_over_budget = 0;
2857 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2858 if (test_bit(i, &serviced_queues))
2860 rx_queue = priv->rx_queue[i];
2861 tx_queue = priv->tx_queue[rx_queue->qindex];
2863 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2864 rx_cleaned_per_queue =
2865 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2866 rx_cleaned += rx_cleaned_per_queue;
2867 if (rx_cleaned_per_queue < budget_per_queue) {
2868 left_over_budget = left_over_budget +
2870 rx_cleaned_per_queue);
2871 set_bit(i, &serviced_queues);
2880 if (rx_cleaned < budget) {
2881 napi_complete(napi);
2883 /* Clear the halt bit in RSTAT */
2884 gfar_write(®s->rstat, gfargrp->rstat);
2886 gfar_write(®s->imask, IMASK_DEFAULT);
2888 /* If we are coalescing interrupts, update the timer
2889 * Otherwise, clear it
2891 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2892 gfargrp->tx_bit_map);
2898 #ifdef CONFIG_NET_POLL_CONTROLLER
2899 /* Polling 'interrupt' - used by things like netconsole to send skbs
2900 * without having to re-enable interrupts. It's not called while
2901 * the interrupt routine is executing.
2903 static void gfar_netpoll(struct net_device *dev)
2905 struct gfar_private *priv = netdev_priv(dev);
2908 /* If the device has multiple interrupts, run tx/rx */
2909 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2910 for (i = 0; i < priv->num_grps; i++) {
2911 disable_irq(priv->gfargrp[i].interruptTransmit);
2912 disable_irq(priv->gfargrp[i].interruptReceive);
2913 disable_irq(priv->gfargrp[i].interruptError);
2914 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2916 enable_irq(priv->gfargrp[i].interruptError);
2917 enable_irq(priv->gfargrp[i].interruptReceive);
2918 enable_irq(priv->gfargrp[i].interruptTransmit);
2921 for (i = 0; i < priv->num_grps; i++) {
2922 disable_irq(priv->gfargrp[i].interruptTransmit);
2923 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2925 enable_irq(priv->gfargrp[i].interruptTransmit);
2931 /* The interrupt handler for devices with one interrupt */
2932 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2934 struct gfar_priv_grp *gfargrp = grp_id;
2936 /* Save ievent for future reference */
2937 u32 events = gfar_read(&gfargrp->regs->ievent);
2939 /* Check for reception */
2940 if (events & IEVENT_RX_MASK)
2941 gfar_receive(irq, grp_id);
2943 /* Check for transmit completion */
2944 if (events & IEVENT_TX_MASK)
2945 gfar_transmit(irq, grp_id);
2947 /* Check for errors */
2948 if (events & IEVENT_ERR_MASK)
2949 gfar_error(irq, grp_id);
2954 /* Called every time the controller might need to be made
2955 * aware of new link state. The PHY code conveys this
2956 * information through variables in the phydev structure, and this
2957 * function converts those variables into the appropriate
2958 * register values, and can bring down the device if needed.
2960 static void adjust_link(struct net_device *dev)
2962 struct gfar_private *priv = netdev_priv(dev);
2963 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2964 unsigned long flags;
2965 struct phy_device *phydev = priv->phydev;
2968 local_irq_save(flags);
2972 u32 tempval = gfar_read(®s->maccfg2);
2973 u32 ecntrl = gfar_read(®s->ecntrl);
2975 /* Now we make sure that we can be in full duplex mode.
2976 * If not, we operate in half-duplex mode.
2978 if (phydev->duplex != priv->oldduplex) {
2980 if (!(phydev->duplex))
2981 tempval &= ~(MACCFG2_FULL_DUPLEX);
2983 tempval |= MACCFG2_FULL_DUPLEX;
2985 priv->oldduplex = phydev->duplex;
2988 if (phydev->speed != priv->oldspeed) {
2990 switch (phydev->speed) {
2993 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2995 ecntrl &= ~(ECNTRL_R100);
3000 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3002 /* Reduced mode distinguishes
3003 * between 10 and 100
3005 if (phydev->speed == SPEED_100)
3006 ecntrl |= ECNTRL_R100;
3008 ecntrl &= ~(ECNTRL_R100);
3011 netif_warn(priv, link, dev,
3012 "Ack! Speed (%d) is not 10/100/1000!\n",
3017 priv->oldspeed = phydev->speed;
3020 gfar_write(®s->maccfg2, tempval);
3021 gfar_write(®s->ecntrl, ecntrl);
3023 if (!priv->oldlink) {
3027 } else if (priv->oldlink) {
3031 priv->oldduplex = -1;
3034 if (new_state && netif_msg_link(priv))
3035 phy_print_status(phydev);
3037 local_irq_restore(flags);
3040 /* Update the hash table based on the current list of multicast
3041 * addresses we subscribe to. Also, change the promiscuity of
3042 * the device based on the flags (this function is called
3043 * whenever dev->flags is changed
3045 static void gfar_set_multi(struct net_device *dev)
3047 struct netdev_hw_addr *ha;
3048 struct gfar_private *priv = netdev_priv(dev);
3049 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3052 if (dev->flags & IFF_PROMISC) {
3053 /* Set RCTRL to PROM */
3054 tempval = gfar_read(®s->rctrl);
3055 tempval |= RCTRL_PROM;
3056 gfar_write(®s->rctrl, tempval);
3058 /* Set RCTRL to not PROM */
3059 tempval = gfar_read(®s->rctrl);
3060 tempval &= ~(RCTRL_PROM);
3061 gfar_write(®s->rctrl, tempval);
3064 if (dev->flags & IFF_ALLMULTI) {
3065 /* Set the hash to rx all multicast frames */
3066 gfar_write(®s->igaddr0, 0xffffffff);
3067 gfar_write(®s->igaddr1, 0xffffffff);
3068 gfar_write(®s->igaddr2, 0xffffffff);
3069 gfar_write(®s->igaddr3, 0xffffffff);
3070 gfar_write(®s->igaddr4, 0xffffffff);
3071 gfar_write(®s->igaddr5, 0xffffffff);
3072 gfar_write(®s->igaddr6, 0xffffffff);
3073 gfar_write(®s->igaddr7, 0xffffffff);
3074 gfar_write(®s->gaddr0, 0xffffffff);
3075 gfar_write(®s->gaddr1, 0xffffffff);
3076 gfar_write(®s->gaddr2, 0xffffffff);
3077 gfar_write(®s->gaddr3, 0xffffffff);
3078 gfar_write(®s->gaddr4, 0xffffffff);
3079 gfar_write(®s->gaddr5, 0xffffffff);
3080 gfar_write(®s->gaddr6, 0xffffffff);
3081 gfar_write(®s->gaddr7, 0xffffffff);
3086 /* zero out the hash */
3087 gfar_write(®s->igaddr0, 0x0);
3088 gfar_write(®s->igaddr1, 0x0);
3089 gfar_write(®s->igaddr2, 0x0);
3090 gfar_write(®s->igaddr3, 0x0);
3091 gfar_write(®s->igaddr4, 0x0);
3092 gfar_write(®s->igaddr5, 0x0);
3093 gfar_write(®s->igaddr6, 0x0);
3094 gfar_write(®s->igaddr7, 0x0);
3095 gfar_write(®s->gaddr0, 0x0);
3096 gfar_write(®s->gaddr1, 0x0);
3097 gfar_write(®s->gaddr2, 0x0);
3098 gfar_write(®s->gaddr3, 0x0);
3099 gfar_write(®s->gaddr4, 0x0);
3100 gfar_write(®s->gaddr5, 0x0);
3101 gfar_write(®s->gaddr6, 0x0);
3102 gfar_write(®s->gaddr7, 0x0);
3104 /* If we have extended hash tables, we need to
3105 * clear the exact match registers to prepare for
3108 if (priv->extended_hash) {
3109 em_num = GFAR_EM_NUM + 1;
3110 gfar_clear_exact_match(dev);
3117 if (netdev_mc_empty(dev))
3120 /* Parse the list, and set the appropriate bits */
3121 netdev_for_each_mc_addr(ha, dev) {
3123 gfar_set_mac_for_addr(dev, idx, ha->addr);
3126 gfar_set_hash_for_addr(dev, ha->addr);
3132 /* Clears each of the exact match registers to zero, so they
3133 * don't interfere with normal reception
3135 static void gfar_clear_exact_match(struct net_device *dev)
3138 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3140 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3141 gfar_set_mac_for_addr(dev, idx, zero_arr);
3144 /* Set the appropriate hash bit for the given addr */
3145 /* The algorithm works like so:
3146 * 1) Take the Destination Address (ie the multicast address), and
3147 * do a CRC on it (little endian), and reverse the bits of the
3149 * 2) Use the 8 most significant bits as a hash into a 256-entry
3150 * table. The table is controlled through 8 32-bit registers:
3151 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3152 * gaddr7. This means that the 3 most significant bits in the
3153 * hash index which gaddr register to use, and the 5 other bits
3154 * indicate which bit (assuming an IBM numbering scheme, which
3155 * for PowerPC (tm) is usually the case) in the register holds
3158 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3161 struct gfar_private *priv = netdev_priv(dev);
3162 u32 result = ether_crc(ETH_ALEN, addr);
3163 int width = priv->hash_width;
3164 u8 whichbit = (result >> (32 - width)) & 0x1f;
3165 u8 whichreg = result >> (32 - width + 5);
3166 u32 value = (1 << (31-whichbit));
3168 tempval = gfar_read(priv->hash_regs[whichreg]);
3170 gfar_write(priv->hash_regs[whichreg], tempval);
3174 /* There are multiple MAC Address register pairs on some controllers
3175 * This function sets the numth pair to a given address
3177 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3180 struct gfar_private *priv = netdev_priv(dev);
3181 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3183 char tmpbuf[ETH_ALEN];
3185 u32 __iomem *macptr = ®s->macstnaddr1;
3189 /* Now copy it into the mac registers backwards, cuz
3190 * little endian is silly
3192 for (idx = 0; idx < ETH_ALEN; idx++)
3193 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3195 gfar_write(macptr, *((u32 *) (tmpbuf)));
3197 tempval = *((u32 *) (tmpbuf + 4));
3199 gfar_write(macptr+1, tempval);
3202 /* GFAR error interrupt handler */
3203 static irqreturn_t gfar_error(int irq, void *grp_id)
3205 struct gfar_priv_grp *gfargrp = grp_id;
3206 struct gfar __iomem *regs = gfargrp->regs;
3207 struct gfar_private *priv= gfargrp->priv;
3208 struct net_device *dev = priv->ndev;
3210 /* Save ievent for future reference */
3211 u32 events = gfar_read(®s->ievent);
3214 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3216 /* Magic Packet is not an error. */
3217 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3218 (events & IEVENT_MAG))
3219 events &= ~IEVENT_MAG;
3222 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3224 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3225 events, gfar_read(®s->imask));
3227 /* Update the error counters */
3228 if (events & IEVENT_TXE) {
3229 dev->stats.tx_errors++;
3231 if (events & IEVENT_LC)
3232 dev->stats.tx_window_errors++;
3233 if (events & IEVENT_CRL)
3234 dev->stats.tx_aborted_errors++;
3235 if (events & IEVENT_XFUN) {
3236 unsigned long flags;
3238 netif_dbg(priv, tx_err, dev,
3239 "TX FIFO underrun, packet dropped\n");
3240 dev->stats.tx_dropped++;
3241 priv->extra_stats.tx_underrun++;
3243 local_irq_save(flags);
3246 /* Reactivate the Tx Queues */
3247 gfar_write(®s->tstat, gfargrp->tstat);
3250 local_irq_restore(flags);
3252 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3254 if (events & IEVENT_BSY) {
3255 dev->stats.rx_errors++;
3256 priv->extra_stats.rx_bsy++;
3258 gfar_receive(irq, grp_id);
3260 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3261 gfar_read(®s->rstat));
3263 if (events & IEVENT_BABR) {
3264 dev->stats.rx_errors++;
3265 priv->extra_stats.rx_babr++;
3267 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3269 if (events & IEVENT_EBERR) {
3270 priv->extra_stats.eberr++;
3271 netif_dbg(priv, rx_err, dev, "bus error\n");
3273 if (events & IEVENT_RXC)
3274 netif_dbg(priv, rx_status, dev, "control frame\n");
3276 if (events & IEVENT_BABT) {
3277 priv->extra_stats.tx_babt++;
3278 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3283 static struct of_device_id gfar_match[] =
3287 .compatible = "gianfar",
3290 .compatible = "fsl,etsec2",
3294 MODULE_DEVICE_TABLE(of, gfar_match);
3296 /* Structure for a device driver */
3297 static struct platform_driver gfar_driver = {
3299 .name = "fsl-gianfar",
3300 .owner = THIS_MODULE,
3302 .of_match_table = gfar_match,
3304 .probe = gfar_probe,
3305 .remove = gfar_remove,
3308 module_platform_driver(gfar_driver);