2 * clkt_clksel.c - OMAP2/3/4 clksel clock functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 * clksel clocks are clocks that do not have a fixed parent, or that
17 * can divide their parent's rate, or possibly both at the same time, based
18 * on the contents of a hardware register bitfield.
20 * All of the various mux and divider settings can be encoded into
21 * struct clksel* data structures, and then these can be autogenerated
22 * from some hardware database for each new chip generation. This
23 * should avoid the need to write, review, and validate a lot of new
24 * clock code for each new chip, since it can be exported from the SoC
25 * design flow. This is now done on OMAP4.
27 * The fusion of mux and divider clocks is a software creation. In
28 * hardware reality, the multiplexer (parent selection) and the
29 * divider exist separately. XXX At some point these clksel clocks
30 * should be split into "divider" clocks and "mux" clocks to better
33 * (The name "clksel" comes from the name of the corresponding
34 * register field in the OMAP2/3 family of SoCs.)
36 * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
37 * many of the OMAP1 clocks should be convertible to use this
42 #include <linux/kernel.h>
43 #include <linux/errno.h>
44 #include <linux/clk.h>
46 #include <linux/bug.h>
50 /* Private functions */
53 * _get_clksel_by_parent() - return clksel struct for a given clk & parent
54 * @clk: OMAP struct clk ptr to inspect
55 * @src_clk: OMAP struct clk ptr of the parent clk to search for
57 * Scan the struct clksel array associated with the clock to find
58 * the element associated with the supplied parent clock address.
59 * Returns a pointer to the struct clksel on success or NULL on error.
61 static const struct clksel *_get_clksel_by_parent(struct clk *clk,
64 const struct clksel *clks;
66 for (clks = clk->clksel; clks->parent; clks++)
67 if (clks->parent == src_clk)
68 break; /* Found the requested parent */
71 /* This indicates a data problem */
72 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
73 __clk_get_name(clk), __clk_get_name(src_clk));
81 * _get_div_and_fieldval() - find the new clksel divisor and field value to use
82 * @src_clk: planned new parent struct clk *
83 * @clk: struct clk * that is being reparented
84 * @field_val: pointer to a u32 to contain the register data for the divisor
86 * Given an intended new parent struct clk * @src_clk, and the struct
87 * clk * @clk to the clock that is being reparented, find the
88 * appropriate rate divisor for the new clock (returned as the return
89 * value), and the corresponding register bitfield data to program to
90 * reach that divisor (returned in the u32 pointed to by @field_val).
91 * Returns 0 on error, or returns the newly-selected divisor upon
92 * success (in this latter case, the corresponding register bitfield
93 * value is passed back in the variable pointed to by @field_val)
95 static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
98 const struct clksel *clks;
99 const struct clksel_rate *clkr, *max_clkr = NULL;
102 clks = _get_clksel_by_parent(clk, src_clk);
107 * Find the highest divisor (e.g., the one resulting in the
108 * lowest rate) to use as the default. This should avoid
109 * clock rates that are too high for the device. XXX A better
110 * solution here would be to try to determine if there is a
111 * divisor matching the original clock rate before the parent
112 * switch, and if it cannot be found, to fall back to the
115 for (clkr = clks->rates; clkr->div; clkr++) {
116 if (!(clkr->flags & cpu_mask))
119 if (clkr->div > max_div) {
126 /* This indicates an error in the clksel data */
127 WARN(1, "clock: %s: could not find divisor for parent %s\n",
129 __clk_get_name(__clk_get_parent(src_clk)));
133 *field_val = max_clkr->val;
139 * _write_clksel_reg() - program a clock's clksel register in hardware
140 * @clk: struct clk * to program
141 * @v: clksel bitfield value to program (with LSB at bit 0)
143 * Shift the clksel register bitfield value @v to its appropriate
144 * location in the clksel register and write it in. This function
145 * will ensure that the write to the clksel_reg reaches its
146 * destination before returning -- important since PRM and CM register
147 * accesses can be quite slow compared to ARM cycles -- but does not
148 * take into account any time the hardware might take to switch the
151 static void _write_clksel_reg(struct clk *clk, u32 field_val)
155 v = __raw_readl(clk->clksel_reg);
156 v &= ~clk->clksel_mask;
157 v |= field_val << __ffs(clk->clksel_mask);
158 __raw_writel(v, clk->clksel_reg);
160 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
164 * _clksel_to_divisor() - turn clksel field value into integer divider
165 * @clk: OMAP struct clk to use
166 * @field_val: register field value to find
168 * Given a struct clk of a rate-selectable clksel clock, and a register field
169 * value to search for, find the corresponding clock divisor. The register
170 * field value should be pre-masked and shifted down so the LSB is at bit 0
171 * before calling. Returns 0 on error or returns the actual integer divisor
174 static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
176 const struct clksel *clks;
177 const struct clksel_rate *clkr;
180 parent = __clk_get_parent(clk);
181 clks = _get_clksel_by_parent(clk, parent);
185 for (clkr = clks->rates; clkr->div; clkr++) {
186 if (!(clkr->flags & cpu_mask))
189 if (clkr->val == field_val)
194 /* This indicates a data error */
195 WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
196 __clk_get_name(clk), field_val, __clk_get_name(parent));
204 * _divisor_to_clksel() - turn clksel integer divisor into a field value
205 * @clk: OMAP struct clk to use
206 * @div: integer divisor to search for
208 * Given a struct clk of a rate-selectable clksel clock, and a clock
209 * divisor, find the corresponding register field value. Returns the
210 * register field value _before_ left-shifting (i.e., LSB is at bit
211 * 0); or returns 0xFFFFFFFF (~0) upon error.
213 static u32 _divisor_to_clksel(struct clk *clk, u32 div)
215 const struct clksel *clks;
216 const struct clksel_rate *clkr;
219 /* should never happen */
222 parent = __clk_get_parent(clk);
223 clks = _get_clksel_by_parent(clk, parent);
227 for (clkr = clks->rates; clkr->div; clkr++) {
228 if (!(clkr->flags & cpu_mask))
231 if (clkr->div == div)
236 pr_err("clock: %s: could not find divisor %d for parent %s\n",
237 __clk_get_name(clk), div, __clk_get_name(parent));
245 * _read_divisor() - get current divisor applied to parent clock (from hdwr)
246 * @clk: OMAP struct clk to use.
248 * Read the current divisor register value for @clk that is programmed
249 * into the hardware, convert it into the actual divisor value, and
250 * return it; or return 0 on error.
252 static u32 _read_divisor(struct clk *clk)
256 if (!clk->clksel || !clk->clksel_mask)
259 v = __raw_readl(clk->clksel_reg);
260 v &= clk->clksel_mask;
261 v >>= __ffs(clk->clksel_mask);
263 return _clksel_to_divisor(clk, v);
266 /* Public functions */
269 * omap2_clksel_round_rate_div() - find divisor for the given clock and rate
270 * @clk: OMAP struct clk to use
271 * @target_rate: desired clock rate
272 * @new_div: ptr to where we should store the divisor
274 * Finds 'best' divider value in an array based on the source and target
275 * rates. The divider array must be sorted with smallest divider first.
276 * This function is also used by the DPLL3 M2 divider code.
278 * Returns the rounded clock rate or returns 0xffffffff on error.
280 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
283 unsigned long test_rate;
284 const struct clksel *clks;
285 const struct clksel_rate *clkr;
288 unsigned long parent_rate;
289 const char *clk_name;
291 parent = __clk_get_parent(clk);
292 parent_rate = __clk_get_rate(parent);
293 clk_name = __clk_get_name(clk);
295 if (!clk->clksel || !clk->clksel_mask)
298 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
299 clk_name, target_rate);
303 clks = _get_clksel_by_parent(clk, parent);
307 for (clkr = clks->rates; clkr->div; clkr++) {
308 if (!(clkr->flags & cpu_mask))
312 if (clkr->div <= last_div)
313 pr_err("clock: %s: clksel_rate table not sorted\n",
316 last_div = clkr->div;
318 test_rate = parent_rate / clkr->div;
320 if (test_rate <= target_rate)
321 break; /* found it */
325 pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
326 clk_name, target_rate, __clk_get_name(parent));
330 *new_div = clkr->div;
332 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
333 (parent_rate / clkr->div));
335 return parent_rate / clkr->div;
339 * Clocktype interface functions to the OMAP clock code
340 * (i.e., those used in struct clk field function pointers, etc.)
344 * omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
345 * @clk: OMAP clock struct ptr to use
347 * Given a pointer @clk to a source-selectable struct clk, read the
348 * hardware register and determine what its parent is currently set
349 * to. Update @clk's .parent field with the appropriate clk ptr. No
352 void omap2_init_clksel_parent(struct clk *clk)
354 const struct clksel *clks;
355 const struct clksel_rate *clkr;
358 const char *clk_name;
360 if (!clk->clksel || !clk->clksel_mask)
363 parent = __clk_get_parent(clk);
364 clk_name = __clk_get_name(clk);
366 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
367 r >>= __ffs(clk->clksel_mask);
369 for (clks = clk->clksel; clks->parent && !found; clks++) {
370 for (clkr = clks->rates; clkr->div && !found; clkr++) {
371 if (!(clkr->flags & cpu_mask))
374 if (clkr->val == r) {
375 if (parent != clks->parent) {
376 pr_debug("clock: %s: inited parent to %s (was %s)\n",
378 __clk_get_name(clks->parent),
380 __clk_get_name(parent) :
382 clk_reparent(clk, clks->parent);
389 /* This indicates a data error */
390 WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
397 * omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
400 * This function is intended to be called only by the clock framework.
401 * Each clksel clock should have its struct clk .recalc field set to this
402 * function. Returns the clock's current rate, based on its parent's rate
403 * and its current divisor setting in the hardware.
405 unsigned long omap2_clksel_recalc(struct clk *clk)
411 div = _read_divisor(clk);
413 return __clk_get_rate(clk);
415 parent = __clk_get_parent(clk);
416 rate = __clk_get_rate(parent) / div;
418 pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
419 __clk_get_name(clk), rate, div);
425 * omap2_clksel_round_rate() - find rounded rate for the given clock and rate
426 * @clk: OMAP struct clk to use
427 * @target_rate: desired clock rate
429 * This function is intended to be called only by the clock framework.
430 * Finds best target rate based on the source clock and possible dividers.
431 * rates. The divider array must be sorted with smallest divider first.
433 * Returns the rounded clock rate or returns 0xffffffff on error.
435 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
439 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
443 * omap2_clksel_set_rate() - program clock rate in hardware
444 * @clk: struct clk * to program rate
445 * @rate: target rate to program
447 * This function is intended to be called only by the clock framework.
448 * Program @clk's rate to @rate in the hardware. The clock can be
449 * either enabled or disabled when this happens, although if the clock
450 * is enabled, some downstream devices may glitch or behave
451 * unpredictably when the clock rate is changed - this depends on the
452 * hardware. This function does not currently check the usecount of
453 * the clock, so if multiple drivers are using the clock, and the rate
454 * is changed, they will all be affected without any notification.
455 * Returns -EINVAL upon error, or 0 upon success.
457 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
459 u32 field_val, validrate, new_div = 0;
461 if (!clk->clksel || !clk->clksel_mask)
464 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
465 if (validrate != rate)
468 field_val = _divisor_to_clksel(clk, new_div);
472 _write_clksel_reg(clk, field_val);
474 clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
476 pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
477 __clk_get_rate(clk));
483 * Clksel parent setting function - not passed in struct clk function
484 * pointer - instead, the OMAP clock code currently assumes that any
485 * parent-setting clock is a clksel clock, and calls
486 * omap2_clksel_set_parent() by default
490 * omap2_clksel_set_parent() - change a clock's parent clock
491 * @clk: struct clk * of the child clock
492 * @new_parent: struct clk * of the new parent clock
494 * This function is intended to be called only by the clock framework.
495 * Change the parent clock of clock @clk to @new_parent. This is
496 * intended to be used while @clk is disabled. This function does not
497 * currently check the usecount of the clock, so if multiple drivers
498 * are using the clock, and the parent is changed, they will all be
499 * affected without any notification. Returns -EINVAL upon error, or
502 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
507 if (!clk->clksel || !clk->clksel_mask)
510 parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
514 _write_clksel_reg(clk, field_val);
516 clk_reparent(clk, new_parent);
518 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
519 clk->rate = __clk_get_rate(new_parent);
522 __clk_get_rate(clk) /= parent_div;
524 pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
526 __clk_get_name(__clk_get_parent(clk)),
527 __clk_get_rate(clk));