2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/pinctrl/machine.h>
24 #include <asm/pgtable.h>
25 #include <asm/system_misc.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/mach/map.h>
29 #include <mach/common.h>
30 #include <mach/devices-common.h>
31 #include <mach/hardware.h>
32 #include <mach/iomux-v3.h>
34 #include "crmregs-imx3.h"
36 void __iomem *mx3_ccm_base;
38 static void imx3_idle(void)
40 unsigned long reg = 0;
42 mx3_cpu_lp_set(MX3_WAIT);
45 /* disable I and D cache */
46 "mrc p15, 0, %0, c1, c0, 0\n"
47 "bic %0, %0, #0x00001000\n"
48 "bic %0, %0, #0x00000004\n"
49 "mcr p15, 0, %0, c1, c0, 0\n"
50 /* invalidate I cache */
52 "mcr p15, 0, %0, c7, c5, 0\n"
53 /* clear and invalidate D cache */
55 "mcr p15, 0, %0, c7, c14, 0\n"
58 "mcr p15, 0, %0, c7, c0, 4\n"
59 "nop\n" "nop\n" "nop\n" "nop\n"
60 "nop\n" "nop\n" "nop\n"
61 /* enable I and D cache */
62 "mrc p15, 0, %0, c1, c0, 0\n"
63 "orr %0, %0, #0x00001000\n"
64 "orr %0, %0, #0x00000004\n"
65 "mcr p15, 0, %0, c1, c0, 0\n"
69 static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
70 unsigned int mtype, void *caller)
72 if (mtype == MT_DEVICE) {
74 * Access all peripherals below 0x80000000 as nonshared device
75 * on mx3, but leave l2cc alone. Otherwise cache corruptions
78 if (phys_addr < 0x80000000 &&
79 !addr_in_module(phys_addr, MX3x_L2CC))
80 mtype = MT_DEVICE_NONSHARED;
83 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
86 void __init imx3_init_l2x0(void)
88 #ifdef CONFIG_CACHE_L2X0
89 void __iomem *l2x0_base;
90 void __iomem *clkctl_base;
93 * First of all, we must repair broken chip settings. There are some
94 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
95 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
96 * Workaraound is to setup the correct register setting prior enabling the
97 * L2 cache. This should not hurt already working CPUs, as they are using the
100 #define L2_MEM_VAL 0x10
102 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
103 if (clkctl_base != NULL) {
104 writel(0x00000515, clkctl_base + L2_MEM_VAL);
105 iounmap(clkctl_base);
107 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
110 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
112 printk(KERN_ERR "remapping L2 cache area failed\n");
116 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
120 #ifdef CONFIG_SOC_IMX31
121 static struct map_desc mx31_io_desc[] __initdata = {
122 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
123 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
124 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
125 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
126 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
130 * This function initializes the memory map. It is called during the
131 * system startup to create static physical to virtual memory mappings
132 * for the IO modules.
134 void __init mx31_map_io(void)
136 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
139 void __init imx31_init_early(void)
141 mxc_set_cpu_type(MXC_CPU_MX31);
142 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
143 arch_ioremap_caller = imx3_ioremap_caller;
144 arm_pm_idle = imx3_idle;
145 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
148 void __init mx31_init_irq(void)
150 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
153 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
154 .per_2_per_addr = 1677,
157 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
160 .bp_2_ap_addr = 1029,
163 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
164 .fw_name = "sdma-imx31-to2.bin",
165 .script_addrs = &imx31_to2_sdma_script,
168 static const struct resource imx31_audmux_res[] __initconst = {
169 DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
172 void __init imx31_soc_init(void)
174 int to_version = mx31_revision() >> 4;
178 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
179 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
180 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
182 pinctrl_provide_dummies();
184 if (to_version == 1) {
185 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
186 strlen(imx31_sdma_pdata.fw_name));
187 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
190 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
192 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
193 imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
195 platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
196 ARRAY_SIZE(imx31_audmux_res));
198 #endif /* ifdef CONFIG_SOC_IMX31 */
200 #ifdef CONFIG_SOC_IMX35
201 static struct map_desc mx35_io_desc[] __initdata = {
202 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
203 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
204 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
205 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
206 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
209 void __init mx35_map_io(void)
211 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
214 void __init imx35_init_early(void)
216 mxc_set_cpu_type(MXC_CPU_MX35);
217 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
218 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
219 arm_pm_idle = imx3_idle;
220 arch_ioremap_caller = imx3_ioremap_caller;
221 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
224 void __init mx35_init_irq(void)
226 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
229 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
231 .uart_2_mcu_addr = 817,
232 .mcu_2_app_addr = 747,
233 .uartsh_2_mcu_addr = 1183,
234 .per_2_shp_addr = 1033,
235 .mcu_2_shp_addr = 961,
236 .ata_2_mcu_addr = 1333,
237 .mcu_2_ata_addr = 1252,
238 .app_2_mcu_addr = 683,
239 .shp_2_per_addr = 1111,
240 .shp_2_mcu_addr = 892,
243 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
245 .uart_2_mcu_addr = 904,
246 .per_2_app_addr = 1597,
247 .mcu_2_app_addr = 834,
248 .uartsh_2_mcu_addr = 1270,
249 .per_2_shp_addr = 1120,
250 .mcu_2_shp_addr = 1048,
251 .ata_2_mcu_addr = 1429,
252 .mcu_2_ata_addr = 1339,
253 .app_2_per_addr = 1531,
254 .app_2_mcu_addr = 770,
255 .shp_2_per_addr = 1198,
256 .shp_2_mcu_addr = 979,
259 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
260 .fw_name = "sdma-imx35-to2.bin",
261 .script_addrs = &imx35_to2_sdma_script,
264 static const struct resource imx35_audmux_res[] __initconst = {
265 DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
268 void __init imx35_soc_init(void)
270 int to_version = mx35_revision() >> 4;
274 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
275 mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
276 mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
278 pinctrl_provide_dummies();
279 if (to_version == 1) {
280 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
281 strlen(imx35_sdma_pdata.fw_name));
282 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
285 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
287 /* Setup AIPS registers */
288 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
289 imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
291 /* i.mx35 has the i.mx31 type audmux */
292 platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
293 ARRAY_SIZE(imx35_audmux_res));
295 #endif /* ifdef CONFIG_SOC_IMX35 */