2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
70 aips@50000000 { /* AIPS1 */
71 compatible = "fsl,aips-bus", "simple-bus";
74 reg = <0x50000000 0x10000000>;
78 compatible = "fsl,spba-bus", "simple-bus";
81 reg = <0x50000000 0x40000>;
84 esdhc@50004000 { /* ESDHC1 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50004000 0x4000>;
92 esdhc@50008000 { /* ESDHC2 */
93 compatible = "fsl,imx53-esdhc";
94 reg = <0x50008000 0x4000>;
100 uart3: serial@5000c000 {
101 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
102 reg = <0x5000c000 0x4000>;
107 ecspi@50010000 { /* ECSPI1 */
108 #address-cells = <1>;
110 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
111 reg = <0x50010000 0x4000>;
117 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
118 reg = <0x50014000 0x4000>;
120 fsl,fifo-depth = <15>;
121 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
125 esdhc@50020000 { /* ESDHC3 */
126 compatible = "fsl,imx53-esdhc";
127 reg = <0x50020000 0x4000>;
133 esdhc@50024000 { /* ESDHC4 */
134 compatible = "fsl,imx53-esdhc";
135 reg = <0x50024000 0x4000>;
143 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
144 reg = <0x53f80000 0x0200>;
150 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
151 reg = <0x53f80200 0x0200>;
157 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
158 reg = <0x53f80400 0x0200>;
164 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
165 reg = <0x53f80600 0x0200>;
170 gpio1: gpio@53f84000 {
171 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
172 reg = <0x53f84000 0x4000>;
173 interrupts = <50 51>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
180 gpio2: gpio@53f88000 {
181 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
182 reg = <0x53f88000 0x4000>;
183 interrupts = <52 53>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
190 gpio3: gpio@53f8c000 {
191 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
192 reg = <0x53f8c000 0x4000>;
193 interrupts = <54 55>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
200 gpio4: gpio@53f90000 {
201 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
202 reg = <0x53f90000 0x4000>;
203 interrupts = <56 57>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
210 wdog@53f98000 { /* WDOG1 */
211 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
212 reg = <0x53f98000 0x4000>;
216 wdog@53f9c000 { /* WDOG2 */
217 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
218 reg = <0x53f9c000 0x4000>;
224 compatible = "fsl,imx53-iomuxc";
225 reg = <0x53fa8000 0x4000>;
228 pinctrl_audmux_1: audmuxgrp-1 {
230 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
231 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
232 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
233 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
239 pinctrl_fec_1: fecgrp-1 {
241 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
242 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
243 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
244 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
245 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
246 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
247 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
248 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
249 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
250 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
256 pinctrl_ecspi1_1: ecspi1grp-1 {
258 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
259 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
260 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
266 pinctrl_esdhc1_1: esdhc1grp-1 {
268 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
269 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
270 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
271 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
272 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
273 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
277 pinctrl_esdhc1_2: esdhc1grp-2 {
279 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
280 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
281 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
282 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
283 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
284 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
285 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
286 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
287 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
288 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
294 pinctrl_esdhc2_1: esdhc2grp-1 {
296 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
297 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
298 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
299 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
300 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
301 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
307 pinctrl_esdhc3_1: esdhc3grp-1 {
309 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
310 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
311 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
312 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
313 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
314 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
315 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
316 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
317 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
318 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
324 pinctrl_can1_1: can1grp-1 {
326 847 0x80000000 /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
327 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
333 pinctrl_can2_1: can2grp-1 {
335 67 0x80000000 /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
336 74 0x80000000 /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
342 pinctrl_i2c1_1: i2c1grp-1 {
344 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
345 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
351 pinctrl_i2c2_1: i2c2grp-1 {
353 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
354 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
360 pinctrl_i2c3_1: i2c3grp-1 {
362 1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
363 1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
369 pinctrl_uart1_1: uart1grp-1 {
371 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
372 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
376 pinctrl_uart1_2: uart1grp-2 {
378 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
379 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
385 pinctrl_uart2_1: uart2grp-1 {
387 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
388 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
394 pinctrl_uart3_1: uart3grp-1 {
396 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
397 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
398 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
399 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
405 pinctrl_uart4_1: uart4grp-1 {
407 11 0x1c5 /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
408 18 0x1c5 /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
414 pinctrl_uart5_1: uart5grp-1 {
416 24 0x1c5 /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
417 31 0x1c5 /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
424 uart1: serial@53fbc000 {
425 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
426 reg = <0x53fbc000 0x4000>;
431 uart2: serial@53fc0000 {
432 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
433 reg = <0x53fc0000 0x4000>;
439 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
440 reg = <0x53fc8000 0x4000>;
446 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
447 reg = <0x53fcc000 0x4000>;
452 gpio5: gpio@53fdc000 {
453 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
454 reg = <0x53fdc000 0x4000>;
455 interrupts = <103 104>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
462 gpio6: gpio@53fe0000 {
463 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
464 reg = <0x53fe0000 0x4000>;
465 interrupts = <105 106>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
472 gpio7: gpio@53fe4000 {
473 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
474 reg = <0x53fe4000 0x4000>;
475 interrupts = <107 108>;
478 interrupt-controller;
479 #interrupt-cells = <2>;
482 i2c@53fec000 { /* I2C3 */
483 #address-cells = <1>;
485 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
486 reg = <0x53fec000 0x4000>;
491 uart4: serial@53ff0000 {
492 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
493 reg = <0x53ff0000 0x4000>;
499 aips@60000000 { /* AIPS2 */
500 compatible = "fsl,aips-bus", "simple-bus";
501 #address-cells = <1>;
503 reg = <0x60000000 0x10000000>;
506 uart5: serial@63f90000 {
507 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
508 reg = <0x63f90000 0x4000>;
513 ecspi@63fac000 { /* ECSPI2 */
514 #address-cells = <1>;
516 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
517 reg = <0x63fac000 0x4000>;
523 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
524 reg = <0x63fb0000 0x4000>;
526 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
530 #address-cells = <1>;
532 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
533 reg = <0x63fc0000 0x4000>;
538 i2c@63fc4000 { /* I2C2 */
539 #address-cells = <1>;
541 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
542 reg = <0x63fc4000 0x4000>;
547 i2c@63fc8000 { /* I2C1 */
548 #address-cells = <1>;
550 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
551 reg = <0x63fc8000 0x4000>;
557 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
558 reg = <0x63fcc000 0x4000>;
560 fsl,fifo-depth = <15>;
561 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
566 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
567 reg = <0x63fd0000 0x4000>;
572 compatible = "fsl,imx53-nand";
573 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
579 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
580 reg = <0x63fe8000 0x4000>;
582 fsl,fifo-depth = <15>;
583 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
588 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
589 reg = <0x63fec000 0x4000>;