4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_KERNEL_THREAD
16 select GENERIC_KERNEL_EXECVE
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
61 The ARM series is a line of low-power-consumption RISC chip designs
62 licensed by ARM Ltd and targeted at embedded applications and
63 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
64 manufactured, but legacy ARM-based PC hardware remains popular in
65 Europe. There is an ARM Linux project with a web page at
66 <http://www.arm.linux.org.uk/>.
68 config ARM_HAS_SG_CHAIN
71 config NEED_SG_DMA_LENGTH
74 config ARM_DMA_USE_IOMMU
76 select ARM_HAS_SG_CHAIN
77 select NEED_SG_DMA_LENGTH
85 config SYS_SUPPORTS_APM_EMULATION
93 select GENERIC_ALLOCATOR
104 The Extended Industry Standard Architecture (EISA) bus was
105 developed as an open alternative to the IBM MicroChannel bus.
107 The EISA bus provided some of the features of the IBM MicroChannel
108 bus while maintaining backward compatibility with cards made for
109 the older ISA bus. The EISA bus saw limited use between 1988 and
110 1995 when it was made obsolete by the PCI bus.
112 Say Y here if you are building a kernel for an EISA-based machine.
119 config STACKTRACE_SUPPORT
123 config HAVE_LATENCYTOP_SUPPORT
128 config LOCKDEP_SUPPORT
132 config TRACE_IRQFLAGS_SUPPORT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config GENERIC_HWEIGHT
160 config GENERIC_CALIBRATE_DELAY
164 config ARCH_MAY_HAVE_PC_FDC
170 config NEED_DMA_MAP_STATE
173 config ARCH_HAS_DMA_SET_COHERENT_MASK
176 config GENERIC_ISA_DMA
182 config NEED_RET_TO_USER
190 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
191 default DRAM_BASE if REMAP_VECTORS_TO_RAM
194 The base address of exception vectors.
196 config ARM_PATCH_PHYS_VIRT
197 bool "Patch physical to virtual translations at runtime" if EMBEDDED
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary.
209 Only disable this option if you know that you do not require
210 this feature (eg, building a kernel for a single machine) and
211 you need to shrink the kernel to the minimal size.
213 config NEED_MACH_GPIO_H
216 Select this when mach/gpio.h is required to provide special
217 definitions for this platform. The need for mach/gpio.h should
218 be avoided when possible.
220 config NEED_MACH_IO_H
223 Select this when mach/io.h is required to provide special
224 definitions for this platform. The need for mach/io.h should
225 be avoided when possible.
227 config NEED_MACH_MEMORY_H
230 Select this when mach/memory.h is required to provide special
231 definitions for this platform. The need for mach/memory.h should
232 be avoided when possible.
235 hex "Physical address of main memory" if MMU
236 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
237 default DRAM_BASE if !MMU
239 Please provide the physical address corresponding to the
240 location of main memory in your system.
246 source "init/Kconfig"
248 source "kernel/Kconfig.freezer"
253 bool "MMU-based Paged Memory Management Support"
256 Select if you want MMU-based virtualised addressing space
257 support by paged memory management. If unsure, say 'Y'.
260 # The "ARM system type" choice list is ordered alphabetically by option
261 # text. Please add new entries in the option alphabetic order.
264 prompt "ARM system type"
265 default ARCH_MULTIPLATFORM
267 config ARCH_MULTIPLATFORM
268 bool "Allow multiple platforms to be selected"
270 select ARM_PATCH_PHYS_VIRT
273 select MULTI_IRQ_HANDLER
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
279 select ARCH_HAS_CPUFREQ
282 select COMMON_CLK_VERSATILE
283 select GENERIC_CLOCKEVENTS
286 select MULTI_IRQ_HANDLER
287 select NEED_MACH_MEMORY_H
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_FPGA_IRQ
292 Support for ARM's Integrator platform.
295 bool "ARM Ltd. RealView family"
296 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select ARM_TIMER_SP804
300 select COMMON_CLK_VERSATILE
301 select GENERIC_CLOCKEVENTS
302 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
308 This enables support for ARM Ltd RealView boards.
310 config ARCH_VERSATILE
311 bool "ARM Ltd. Versatile family"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select ARM_TIMER_SP804
317 select GENERIC_CLOCKEVENTS
318 select HAVE_MACH_CLKDEV
320 select PLAT_VERSATILE
321 select PLAT_VERSATILE_CLCD
322 select PLAT_VERSATILE_CLOCK
323 select PLAT_VERSATILE_FPGA_IRQ
325 This enables support for ARM Ltd Versatile board.
329 select ARCH_REQUIRE_GPIOLIB
333 select NEED_MACH_GPIO_H
334 select NEED_MACH_IO_H if PCCARD
336 select PINCTRL_AT91 if USE_OF
338 This enables support for systems based on Atmel
339 AT91RM9200 and AT91SAM9* processors.
342 bool "Broadcom BCM2835 family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_ERRATA_411920
346 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select MULTI_IRQ_HANDLER
355 This enables support for the Broadcom BCM2835 SoC. This SoC is
356 use in the Raspberry Pi, and Roku 2 devices.
359 bool "Cavium Networks CNS3XXX family"
362 select GENERIC_CLOCKEVENTS
363 select MIGHT_HAVE_CACHE_L2X0
364 select MIGHT_HAVE_PCI
365 select PCI_DOMAINS if PCI
367 Support for Cavium Networks CNS3XXX platform.
370 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
371 select ARCH_REQUIRE_GPIOLIB
372 select ARCH_USES_GETTIMEOFFSET
376 select NEED_MACH_MEMORY_H
378 Support for Cirrus Logic 711x/721x/731x based boards.
381 bool "Cortina Systems Gemini"
382 select ARCH_REQUIRE_GPIOLIB
383 select ARCH_USES_GETTIMEOFFSET
386 Support for the Cortina Systems Gemini family SoCs
390 select ARCH_REQUIRE_GPIOLIB
392 select GENERIC_CLOCKEVENTS
393 select GENERIC_IRQ_CHIP
394 select MIGHT_HAVE_CACHE_L2X0
400 Support for CSR SiRFprimaII/Marco/Polo platforms
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 select ARCH_HAS_HOLES_MEMORYMODEL
419 select ARCH_REQUIRE_GPIOLIB
420 select ARCH_USES_GETTIMEOFFSET
425 select NEED_MACH_MEMORY_H
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_IO_H if !MMU
436 select NEED_MACH_MEMORY_H
438 Support for systems based on the DC21285 companion chip
439 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 bool "Freescale MXC/iMX-based"
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_CLOCKEVENTS
447 select GENERIC_IRQ_CHIP
448 select MULTI_IRQ_HANDLER
452 Support for Freescale MXC/iMX-based family of processors
455 bool "Freescale MXS-based"
456 select ARCH_REQUIRE_GPIOLIB
460 select GENERIC_CLOCKEVENTS
461 select HAVE_CLK_PREPARE
462 select MULTI_IRQ_HANDLER
467 Support for Freescale MXS-based family of processors
470 bool "Hilscher NetX based"
474 select GENERIC_CLOCKEVENTS
476 This enables support for systems based on the Hilscher NetX Soc
479 bool "Hynix HMS720x-based"
480 select ARCH_USES_GETTIMEOFFSET
484 This enables support for systems based on the Hynix HMS720x
489 select ARCH_SUPPORTS_MSI
491 select NEED_MACH_MEMORY_H
492 select NEED_RET_TO_USER
497 Support for Intel's IOP13XX (XScale) family of processors.
502 select ARCH_REQUIRE_GPIOLIB
504 select NEED_MACH_GPIO_H
505 select NEED_RET_TO_USER
509 Support for Intel's 80219 and IOP32X (XScale) family of
515 select ARCH_REQUIRE_GPIOLIB
517 select NEED_MACH_GPIO_H
518 select NEED_RET_TO_USER
522 Support for Intel's IOP33X (XScale) family of processors.
527 select ARCH_HAS_DMA_SET_COHERENT_MASK
528 select ARCH_REQUIRE_GPIOLIB
531 select DMABOUNCE if PCI
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
534 select NEED_MACH_IO_H
536 Support for Intel's IXP4XX (XScale) family of processors.
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
543 select MIGHT_HAVE_PCI
544 select PLAT_ORION_LEGACY
545 select USB_ARCH_HAS_EHCI
547 Support for the Marvell Dove SoC 88AP510
550 bool "Marvell Kirkwood"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
556 select PLAT_ORION_LEGACY
558 Support for the following Marvell Kirkwood series SoCs:
559 88F6180, 88F6192 and 88F6281.
562 bool "Marvell MV78xx0"
563 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
567 select PLAT_ORION_LEGACY
569 Support for the following Marvell MV78xx0 series SoCs:
575 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Orion 5x series SoCs:
582 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
583 Orion-2 (5281), Orion-1-90 (6183).
586 bool "Marvell PXA168/910/MMP2"
588 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_ALLOCATOR
591 select GENERIC_CLOCKEVENTS
594 select NEED_MACH_GPIO_H
599 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
602 bool "Micrel/Kendin KS8695"
603 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
607 select NEED_MACH_MEMORY_H
609 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
610 System-on-Chip devices.
613 bool "Nuvoton W90X900 CPU"
614 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
620 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
621 At present, the w90x900 has been renamed nuc900, regarding
622 the ARM series product line, you can login the following
623 link address to know more.
625 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
626 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
630 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
638 select USB_ARCH_HAS_OHCI
641 Support for the NXP LPC32XX family of processors
645 select ARCH_HAS_CPUFREQ
649 select GENERIC_CLOCKEVENTS
653 select MIGHT_HAVE_CACHE_L2X0
656 This enables support for NVIDIA Tegra based systems (Tegra APX,
657 Tegra 6xx and Tegra 2 series).
660 bool "PXA2xx/PXA3xx-based"
662 select ARCH_HAS_CPUFREQ
664 select ARCH_REQUIRE_GPIOLIB
665 select ARM_CPU_SUSPEND if PM
669 select GENERIC_CLOCKEVENTS
672 select MULTI_IRQ_HANDLER
673 select NEED_MACH_GPIO_H
677 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
681 select ARCH_REQUIRE_GPIOLIB
683 select GENERIC_CLOCKEVENTS
686 Support for Qualcomm MSM/QSD based systems. This runs on the
687 apps processor of the MSM/QSD and depends on a shared memory
688 interface to the modem processor which runs the baseband
689 stack and controls some vital subsystems
690 (clock and power control, etc).
693 bool "Renesas SH-Mobile / R-Mobile"
695 select GENERIC_CLOCKEVENTS
697 select HAVE_MACH_CLKDEV
699 select MIGHT_HAVE_CACHE_L2X0
700 select MULTI_IRQ_HANDLER
701 select NEED_MACH_MEMORY_H
703 select PM_GENERIC_DOMAINS if PM
706 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
711 select ARCH_MAY_HAVE_PC_FDC
712 select ARCH_SPARSEMEM_ENABLE
713 select ARCH_USES_GETTIMEOFFSET
716 select HAVE_PATA_PLATFORM
718 select NEED_MACH_IO_H
719 select NEED_MACH_MEMORY_H
722 On the Acorn Risc-PC, Linux can support the internal IDE disk and
723 CD-ROM interface, serial and parallel port, and the floppy drive.
727 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
730 select ARCH_SPARSEMEM_ENABLE
735 select GENERIC_CLOCKEVENTS
738 select NEED_MACH_GPIO_H
739 select NEED_MACH_MEMORY_H
742 Support for StrongARM 11x0 based boards.
745 bool "Samsung S3C24XX SoCs"
746 select ARCH_HAS_CPUFREQ
747 select ARCH_USES_GETTIMEOFFSET
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select HAVE_S3C_RTC if RTC_CLASS
754 select NEED_MACH_GPIO_H
755 select NEED_MACH_IO_H
757 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
758 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
759 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
760 Samsung SMDK2410 development board (and derivatives).
763 bool "Samsung S3C64XX"
764 select ARCH_HAS_CPUFREQ
765 select ARCH_REQUIRE_GPIOLIB
766 select ARCH_USES_GETTIMEOFFSET
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 select NEED_MACH_GPIO_H
778 select S3C_GPIO_TRACK
779 select SAMSUNG_CLKSRC
780 select SAMSUNG_GPIOLIB_4BIT
781 select SAMSUNG_IRQ_VIC_TIMER
782 select USB_ARCH_HAS_OHCI
784 Samsung S3C64XX series based systems
787 bool "Samsung S5P6440 S5P6450"
791 select GENERIC_CLOCKEVENTS
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
799 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
803 bool "Samsung S5PC100"
804 select ARCH_USES_GETTIMEOFFSET
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select HAVE_S3C_RTC if RTC_CLASS
812 select NEED_MACH_GPIO_H
814 Samsung S5PC100 series based systems
817 bool "Samsung S5PV210/S5PC110"
818 select ARCH_HAS_CPUFREQ
819 select ARCH_HAS_HOLES_MEMORYMODEL
820 select ARCH_SPARSEMEM_ENABLE
824 select GENERIC_CLOCKEVENTS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select HAVE_S3C_RTC if RTC_CLASS
830 select NEED_MACH_GPIO_H
831 select NEED_MACH_MEMORY_H
833 Samsung S5PV210/S5PC110 series based systems
836 bool "Samsung EXYNOS"
837 select ARCH_HAS_CPUFREQ
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_SPARSEMEM_ENABLE
842 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C2410_WATCHDOG if WATCHDOG
847 select HAVE_S3C_RTC if RTC_CLASS
848 select NEED_MACH_GPIO_H
849 select NEED_MACH_MEMORY_H
851 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
855 select ARCH_USES_GETTIMEOFFSET
859 select NEED_MACH_MEMORY_H
863 Support for the StrongARM based Digital DNARD machine, also known
864 as "Shark" (<http://www.shark-linux.de/shark.html>).
867 bool "ST-Ericsson U300 Series"
869 select ARCH_REQUIRE_GPIOLIB
871 select ARM_PATCH_PHYS_VIRT
877 select GENERIC_CLOCKEVENTS
882 Support for ST-Ericsson U300 series mobile platforms.
885 bool "ST-Ericsson U8500 Series"
887 select ARCH_HAS_CPUFREQ
888 select ARCH_REQUIRE_GPIOLIB
892 select GENERIC_CLOCKEVENTS
894 select MIGHT_HAVE_CACHE_L2X0
896 Support for ST-Ericsson's Ux500 architecture
899 bool "STMicroelectronics Nomadik"
900 select ARCH_REQUIRE_GPIOLIB
905 select GENERIC_CLOCKEVENTS
906 select MIGHT_HAVE_CACHE_L2X0
908 select PINCTRL_STN8815
910 Support for the Nomadik platform by ST-Ericsson
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
920 select GENERIC_CLOCKEVENTS
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
934 select NEED_MACH_GPIO_H
937 Support for TI's DaVinci platform.
942 select ARCH_HAS_CPUFREQ
943 select ARCH_HAS_HOLES_MEMORYMODEL
944 select ARCH_REQUIRE_GPIOLIB
946 select GENERIC_CLOCKEVENTS
949 Support for TI's OMAP platform (OMAP1/2/3/4).
952 bool "VIA/WonderMedia 85xx"
953 select ARCH_HAS_CPUFREQ
954 select ARCH_REQUIRE_GPIOLIB
958 select GENERIC_CLOCKEVENTS
963 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
966 bool "Xilinx Zynq ARM Cortex A9 Platform"
971 select GENERIC_CLOCKEVENTS
973 select MIGHT_HAVE_CACHE_L2X0
976 Support for Xilinx Zynq ARM Cortex A9 Platform
979 menu "Multiple platform selection"
980 depends on ARCH_MULTIPLATFORM
982 comment "CPU Core family selection"
985 bool "ARMv4 based platforms (FA526, StrongARM)"
986 depends on !ARCH_MULTI_V6_V7
987 select ARCH_MULTI_V4_V5
989 config ARCH_MULTI_V4T
990 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
991 depends on !ARCH_MULTI_V6_V7
992 select ARCH_MULTI_V4_V5
995 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
996 depends on !ARCH_MULTI_V6_V7
997 select ARCH_MULTI_V4_V5
999 config ARCH_MULTI_V4_V5
1002 config ARCH_MULTI_V6
1003 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
1004 select ARCH_MULTI_V6_V7
1007 config ARCH_MULTI_V7
1008 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1010 select ARCH_MULTI_V6_V7
1011 select ARCH_VEXPRESS
1014 config ARCH_MULTI_V6_V7
1017 config ARCH_MULTI_CPU_AUTO
1018 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1019 select ARCH_MULTI_V5
1024 # This is sorted alphabetically by mach-* pathname. However, plat-*
1025 # Kconfigs may be included either alphabetically (according to the
1026 # plat- suffix) or along side the corresponding mach-* source.
1028 source "arch/arm/mach-mvebu/Kconfig"
1030 source "arch/arm/mach-at91/Kconfig"
1032 source "arch/arm/mach-clps711x/Kconfig"
1034 source "arch/arm/mach-cns3xxx/Kconfig"
1036 source "arch/arm/mach-davinci/Kconfig"
1038 source "arch/arm/mach-dove/Kconfig"
1040 source "arch/arm/mach-ep93xx/Kconfig"
1042 source "arch/arm/mach-footbridge/Kconfig"
1044 source "arch/arm/mach-gemini/Kconfig"
1046 source "arch/arm/mach-h720x/Kconfig"
1048 source "arch/arm/mach-highbank/Kconfig"
1050 source "arch/arm/mach-integrator/Kconfig"
1052 source "arch/arm/mach-iop32x/Kconfig"
1054 source "arch/arm/mach-iop33x/Kconfig"
1056 source "arch/arm/mach-iop13xx/Kconfig"
1058 source "arch/arm/mach-ixp4xx/Kconfig"
1060 source "arch/arm/mach-kirkwood/Kconfig"
1062 source "arch/arm/mach-ks8695/Kconfig"
1064 source "arch/arm/mach-msm/Kconfig"
1066 source "arch/arm/mach-mv78xx0/Kconfig"
1068 source "arch/arm/plat-mxc/Kconfig"
1070 source "arch/arm/mach-mxs/Kconfig"
1072 source "arch/arm/mach-netx/Kconfig"
1074 source "arch/arm/mach-nomadik/Kconfig"
1075 source "arch/arm/plat-nomadik/Kconfig"
1077 source "arch/arm/plat-omap/Kconfig"
1079 source "arch/arm/mach-omap1/Kconfig"
1081 source "arch/arm/mach-omap2/Kconfig"
1083 source "arch/arm/mach-orion5x/Kconfig"
1085 source "arch/arm/mach-picoxcell/Kconfig"
1087 source "arch/arm/mach-pxa/Kconfig"
1088 source "arch/arm/plat-pxa/Kconfig"
1090 source "arch/arm/mach-mmp/Kconfig"
1092 source "arch/arm/mach-realview/Kconfig"
1094 source "arch/arm/mach-sa1100/Kconfig"
1096 source "arch/arm/plat-samsung/Kconfig"
1097 source "arch/arm/plat-s3c24xx/Kconfig"
1099 source "arch/arm/mach-socfpga/Kconfig"
1101 source "arch/arm/plat-spear/Kconfig"
1103 source "arch/arm/mach-s3c24xx/Kconfig"
1105 source "arch/arm/mach-s3c2412/Kconfig"
1106 source "arch/arm/mach-s3c2440/Kconfig"
1110 source "arch/arm/mach-s3c64xx/Kconfig"
1113 source "arch/arm/mach-s5p64x0/Kconfig"
1115 source "arch/arm/mach-s5pc100/Kconfig"
1117 source "arch/arm/mach-s5pv210/Kconfig"
1119 source "arch/arm/mach-exynos/Kconfig"
1121 source "arch/arm/mach-shmobile/Kconfig"
1123 source "arch/arm/mach-prima2/Kconfig"
1125 source "arch/arm/mach-tegra/Kconfig"
1127 source "arch/arm/mach-u300/Kconfig"
1129 source "arch/arm/mach-ux500/Kconfig"
1131 source "arch/arm/mach-versatile/Kconfig"
1133 source "arch/arm/mach-vexpress/Kconfig"
1134 source "arch/arm/plat-versatile/Kconfig"
1136 source "arch/arm/mach-w90x900/Kconfig"
1138 # Definitions to make life easier
1144 select GENERIC_CLOCKEVENTS
1150 select GENERIC_IRQ_CHIP
1153 config PLAT_ORION_LEGACY
1160 config PLAT_VERSATILE
1163 config ARM_TIMER_SP804
1166 select HAVE_SCHED_CLOCK
1168 source arch/arm/mm/Kconfig
1172 default 16 if ARCH_EP93XX
1176 bool "Enable iWMMXt support"
1177 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1178 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1180 Enable support for iWMMXt context switching at run time if
1181 running on a CPU that supports it.
1185 depends on CPU_XSCALE
1188 config MULTI_IRQ_HANDLER
1191 Allow each machine to specify it's own IRQ handler at run time.
1194 source "arch/arm/Kconfig-nommu"
1197 config ARM_ERRATA_326103
1198 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1201 Executing a SWP instruction to read-only memory does not set bit 11
1202 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1203 treat the access as a read, preventing a COW from occurring and
1204 causing the faulting task to livelock.
1206 config ARM_ERRATA_411920
1207 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1208 depends on CPU_V6 || CPU_V6K
1210 Invalidation of the Instruction Cache operation can
1211 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1212 It does not affect the MPCore. This option enables the ARM Ltd.
1213 recommended workaround.
1215 config ARM_ERRATA_430973
1216 bool "ARM errata: Stale prediction on replaced interworking branch"
1219 This option enables the workaround for the 430973 Cortex-A8
1220 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1221 interworking branch is replaced with another code sequence at the
1222 same virtual address, whether due to self-modifying code or virtual
1223 to physical address re-mapping, Cortex-A8 does not recover from the
1224 stale interworking branch prediction. This results in Cortex-A8
1225 executing the new code sequence in the incorrect ARM or Thumb state.
1226 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1227 and also flushes the branch target cache at every context switch.
1228 Note that setting specific bits in the ACTLR register may not be
1229 available in non-secure mode.
1231 config ARM_ERRATA_458693
1232 bool "ARM errata: Processor deadlock when a false hazard is created"
1235 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1236 erratum. For very specific sequences of memory operations, it is
1237 possible for a hazard condition intended for a cache line to instead
1238 be incorrectly associated with a different cache line. This false
1239 hazard might then cause a processor deadlock. The workaround enables
1240 the L1 caching of the NEON accesses and disables the PLD instruction
1241 in the ACTLR register. Note that setting specific bits in the ACTLR
1242 register may not be available in non-secure mode.
1244 config ARM_ERRATA_460075
1245 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1248 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1249 erratum. Any asynchronous access to the L2 cache may encounter a
1250 situation in which recent store transactions to the L2 cache are lost
1251 and overwritten with stale memory contents from external memory. The
1252 workaround disables the write-allocate mode for the L2 cache via the
1253 ACTLR register. Note that setting specific bits in the ACTLR register
1254 may not be available in non-secure mode.
1256 config ARM_ERRATA_742230
1257 bool "ARM errata: DMB operation may be faulty"
1258 depends on CPU_V7 && SMP
1260 This option enables the workaround for the 742230 Cortex-A9
1261 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1262 between two write operations may not ensure the correct visibility
1263 ordering of the two writes. This workaround sets a specific bit in
1264 the diagnostic register of the Cortex-A9 which causes the DMB
1265 instruction to behave as a DSB, ensuring the correct behaviour of
1268 config ARM_ERRATA_742231
1269 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1270 depends on CPU_V7 && SMP
1272 This option enables the workaround for the 742231 Cortex-A9
1273 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1274 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1275 accessing some data located in the same cache line, may get corrupted
1276 data due to bad handling of the address hazard when the line gets
1277 replaced from one of the CPUs at the same time as another CPU is
1278 accessing it. This workaround sets specific bits in the diagnostic
1279 register of the Cortex-A9 which reduces the linefill issuing
1280 capabilities of the processor.
1282 config PL310_ERRATA_588369
1283 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1284 depends on CACHE_L2X0
1286 The PL310 L2 cache controller implements three types of Clean &
1287 Invalidate maintenance operations: by Physical Address
1288 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1289 They are architecturally defined to behave as the execution of a
1290 clean operation followed immediately by an invalidate operation,
1291 both performing to the same memory location. This functionality
1292 is not correctly implemented in PL310 as clean lines are not
1293 invalidated as a result of these operations.
1295 config ARM_ERRATA_720789
1296 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1299 This option enables the workaround for the 720789 Cortex-A9 (prior to
1300 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1301 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1302 As a consequence of this erratum, some TLB entries which should be
1303 invalidated are not, resulting in an incoherency in the system page
1304 tables. The workaround changes the TLB flushing routines to invalidate
1305 entries regardless of the ASID.
1307 config PL310_ERRATA_727915
1308 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1309 depends on CACHE_L2X0
1311 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1312 operation (offset 0x7FC). This operation runs in background so that
1313 PL310 can handle normal accesses while it is in progress. Under very
1314 rare circumstances, due to this erratum, write data can be lost when
1315 PL310 treats a cacheable write transaction during a Clean &
1316 Invalidate by Way operation.
1318 config ARM_ERRATA_743622
1319 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1322 This option enables the workaround for the 743622 Cortex-A9
1323 (r2p*) erratum. Under very rare conditions, a faulty
1324 optimisation in the Cortex-A9 Store Buffer may lead to data
1325 corruption. This workaround sets a specific bit in the diagnostic
1326 register of the Cortex-A9 which disables the Store Buffer
1327 optimisation, preventing the defect from occurring. This has no
1328 visible impact on the overall performance or power consumption of the
1331 config ARM_ERRATA_751472
1332 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1335 This option enables the workaround for the 751472 Cortex-A9 (prior
1336 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1337 completion of a following broadcasted operation if the second
1338 operation is received by a CPU before the ICIALLUIS has completed,
1339 potentially leading to corrupted entries in the cache or TLB.
1341 config PL310_ERRATA_753970
1342 bool "PL310 errata: cache sync operation may be faulty"
1343 depends on CACHE_PL310
1345 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1347 Under some condition the effect of cache sync operation on
1348 the store buffer still remains when the operation completes.
1349 This means that the store buffer is always asked to drain and
1350 this prevents it from merging any further writes. The workaround
1351 is to replace the normal offset of cache sync operation (0x730)
1352 by another offset targeting an unmapped PL310 register 0x740.
1353 This has the same effect as the cache sync operation: store buffer
1354 drain and waiting for all buffers empty.
1356 config ARM_ERRATA_754322
1357 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1360 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1361 r3p*) erratum. A speculative memory access may cause a page table walk
1362 which starts prior to an ASID switch but completes afterwards. This
1363 can populate the micro-TLB with a stale entry which may be hit with
1364 the new ASID. This workaround places two dsb instructions in the mm
1365 switching code so that no page table walks can cross the ASID switch.
1367 config ARM_ERRATA_754327
1368 bool "ARM errata: no automatic Store Buffer drain"
1369 depends on CPU_V7 && SMP
1371 This option enables the workaround for the 754327 Cortex-A9 (prior to
1372 r2p0) erratum. The Store Buffer does not have any automatic draining
1373 mechanism and therefore a livelock may occur if an external agent
1374 continuously polls a memory location waiting to observe an update.
1375 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1376 written polling loops from denying visibility of updates to memory.
1378 config ARM_ERRATA_364296
1379 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1380 depends on CPU_V6 && !SMP
1382 This options enables the workaround for the 364296 ARM1136
1383 r0p2 erratum (possible cache data corruption with
1384 hit-under-miss enabled). It sets the undocumented bit 31 in
1385 the auxiliary control register and the FI bit in the control
1386 register, thus disabling hit-under-miss without putting the
1387 processor into full low interrupt latency mode. ARM11MPCore
1390 config ARM_ERRATA_764369
1391 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1392 depends on CPU_V7 && SMP
1394 This option enables the workaround for erratum 764369
1395 affecting Cortex-A9 MPCore with two or more processors (all
1396 current revisions). Under certain timing circumstances, a data
1397 cache line maintenance operation by MVA targeting an Inner
1398 Shareable memory region may fail to proceed up to either the
1399 Point of Coherency or to the Point of Unification of the
1400 system. This workaround adds a DSB instruction before the
1401 relevant cache maintenance functions and sets a specific bit
1402 in the diagnostic control register of the SCU.
1404 config PL310_ERRATA_769419
1405 bool "PL310 errata: no automatic Store Buffer drain"
1406 depends on CACHE_L2X0
1408 On revisions of the PL310 prior to r3p2, the Store Buffer does
1409 not automatically drain. This can cause normal, non-cacheable
1410 writes to be retained when the memory system is idle, leading
1411 to suboptimal I/O performance for drivers using coherent DMA.
1412 This option adds a write barrier to the cpu_idle loop so that,
1413 on systems with an outer cache, the store buffer is drained
1416 config ARM_ERRATA_775420
1417 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1420 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1421 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1422 operation aborts with MMU exception, it might cause the processor
1423 to deadlock. This workaround puts DSB before executing ISB if
1424 an abort may occur on cache maintenance.
1428 source "arch/arm/common/Kconfig"
1438 Find out whether you have ISA slots on your motherboard. ISA is the
1439 name of a bus system, i.e. the way the CPU talks to the other stuff
1440 inside your box. Other bus systems are PCI, EISA, MicroChannel
1441 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1442 newer boards don't support it. If you have ISA, say Y, otherwise N.
1444 # Select ISA DMA controller support
1449 # Select ISA DMA interface
1454 bool "PCI support" if MIGHT_HAVE_PCI
1456 Find out whether you have a PCI motherboard. PCI is the name of a
1457 bus system, i.e. the way the CPU talks to the other stuff inside
1458 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1459 VESA. If you have PCI, say Y, otherwise N.
1465 config PCI_NANOENGINE
1466 bool "BSE nanoEngine PCI support"
1467 depends on SA1100_NANOENGINE
1469 Enable PCI on the BSE nanoEngine board.
1474 # Select the host bridge type
1475 config PCI_HOST_VIA82C505
1477 depends on PCI && ARCH_SHARK
1480 config PCI_HOST_ITE8152
1482 depends on PCI && MACH_ARMCORE
1486 source "drivers/pci/Kconfig"
1488 source "drivers/pcmcia/Kconfig"
1492 menu "Kernel Features"
1497 This option should be selected by machines which have an SMP-
1500 The only effect of this option is to make the SMP-related
1501 options available to the user for configuration.
1504 bool "Symmetric Multi-Processing"
1505 depends on CPU_V6K || CPU_V7
1506 depends on GENERIC_CLOCKEVENTS
1509 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1510 select USE_GENERIC_SMP_HELPERS
1512 This enables support for systems with more than one CPU. If you have
1513 a system with only one CPU, like most personal computers, say N. If
1514 you have a system with more than one CPU, say Y.
1516 If you say N here, the kernel will run on single and multiprocessor
1517 machines, but will use only one CPU of a multiprocessor machine. If
1518 you say Y here, the kernel will run on many, but not all, single
1519 processor machines. On a single processor machine, the kernel will
1520 run faster if you say N here.
1522 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1523 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1524 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1526 If you don't know what to do here, say N.
1529 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1530 depends on EXPERIMENTAL
1531 depends on SMP && !XIP_KERNEL
1534 SMP kernels contain instructions which fail on non-SMP processors.
1535 Enabling this option allows the kernel to modify itself to make
1536 these instructions safe. Disabling it allows about 1K of space
1539 If you don't know what to do here, say Y.
1541 config ARM_CPU_TOPOLOGY
1542 bool "Support cpu topology definition"
1543 depends on SMP && CPU_V7
1546 Support ARM cpu topology definition. The MPIDR register defines
1547 affinity between processors which is then used to describe the cpu
1548 topology of an ARM System.
1551 bool "Multi-core scheduler support"
1552 depends on ARM_CPU_TOPOLOGY
1554 Multi-core scheduler support improves the CPU scheduler's decision
1555 making when dealing with multi-core CPU chips at a cost of slightly
1556 increased overhead in some places. If unsure say N here.
1559 bool "SMT scheduler support"
1560 depends on ARM_CPU_TOPOLOGY
1562 Improves the CPU scheduler's decision making when dealing with
1563 MultiThreading at a cost of slightly increased overhead in some
1564 places. If unsure say N here.
1569 This option enables support for the ARM system coherency unit
1571 config ARM_ARCH_TIMER
1572 bool "Architected timer support"
1575 This option enables support for the ARM architected timer
1581 This options enables support for the ARM timer and watchdog unit
1584 prompt "Memory split"
1587 Select the desired split between kernel and user memory.
1589 If you are not absolutely sure what you are doing, leave this
1593 bool "3G/1G user/kernel split"
1595 bool "2G/2G user/kernel split"
1597 bool "1G/3G user/kernel split"
1602 default 0x40000000 if VMSPLIT_1G
1603 default 0x80000000 if VMSPLIT_2G
1607 int "Maximum number of CPUs (2-32)"
1613 bool "Support for hot-pluggable CPUs"
1614 depends on SMP && HOTPLUG
1616 Say Y here to experiment with turning CPUs off and on. CPUs
1617 can be controlled through /sys/devices/system/cpu.
1620 bool "Use local timer interrupts"
1623 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1625 Enable support for local timers on SMP platforms, rather then the
1626 legacy IPI broadcast method. Local timers allows the system
1627 accounting to be spread across the timer interval, preventing a
1628 "thundering herd" at every timer tick.
1632 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1633 default 355 if ARCH_U8500
1634 default 264 if MACH_H4700
1635 default 512 if SOC_OMAP5
1636 default 288 if ARCH_VT8500
1639 Maximum number of GPIOs in the system.
1641 If unsure, leave the default value.
1643 source kernel/Kconfig.preempt
1647 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1648 ARCH_S5PV210 || ARCH_EXYNOS4
1649 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1650 default AT91_TIMER_HZ if ARCH_AT91
1651 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1654 config THUMB2_KERNEL
1655 bool "Compile the kernel in Thumb-2 mode"
1656 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1658 select ARM_ASM_UNIFIED
1661 By enabling this option, the kernel will be compiled in
1662 Thumb-2 mode. A compiler/assembler that understand the unified
1663 ARM-Thumb syntax is needed.
1667 config THUMB2_AVOID_R_ARM_THM_JUMP11
1668 bool "Work around buggy Thumb-2 short branch relocations in gas"
1669 depends on THUMB2_KERNEL && MODULES
1672 Various binutils versions can resolve Thumb-2 branches to
1673 locally-defined, preemptible global symbols as short-range "b.n"
1674 branch instructions.
1676 This is a problem, because there's no guarantee the final
1677 destination of the symbol, or any candidate locations for a
1678 trampoline, are within range of the branch. For this reason, the
1679 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1680 relocation in modules at all, and it makes little sense to add
1683 The symptom is that the kernel fails with an "unsupported
1684 relocation" error when loading some modules.
1686 Until fixed tools are available, passing
1687 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1688 code which hits this problem, at the cost of a bit of extra runtime
1689 stack usage in some cases.
1691 The problem is described in more detail at:
1692 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1694 Only Thumb-2 kernels are affected.
1696 Unless you are sure your tools don't have this problem, say Y.
1698 config ARM_ASM_UNIFIED
1702 bool "Use the ARM EABI to compile the kernel"
1704 This option allows for the kernel to be compiled using the latest
1705 ARM ABI (aka EABI). This is only useful if you are using a user
1706 space environment that is also compiled with EABI.
1708 Since there are major incompatibilities between the legacy ABI and
1709 EABI, especially with regard to structure member alignment, this
1710 option also changes the kernel syscall calling convention to
1711 disambiguate both ABIs and allow for backward compatibility support
1712 (selected with CONFIG_OABI_COMPAT).
1714 To use this you need GCC version 4.0.0 or later.
1717 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1718 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1721 This option preserves the old syscall interface along with the
1722 new (ARM EABI) one. It also provides a compatibility layer to
1723 intercept syscalls that have structure arguments which layout
1724 in memory differs between the legacy ABI and the new ARM EABI
1725 (only for non "thumb" binaries). This option adds a tiny
1726 overhead to all syscalls and produces a slightly larger kernel.
1727 If you know you'll be using only pure EABI user space then you
1728 can say N here. If this option is not selected and you attempt
1729 to execute a legacy ABI binary then the result will be
1730 UNPREDICTABLE (in fact it can be predicted that it won't work
1731 at all). If in doubt say Y.
1733 config ARCH_HAS_HOLES_MEMORYMODEL
1736 config ARCH_SPARSEMEM_ENABLE
1739 config ARCH_SPARSEMEM_DEFAULT
1740 def_bool ARCH_SPARSEMEM_ENABLE
1742 config ARCH_SELECT_MEMORY_MODEL
1743 def_bool ARCH_SPARSEMEM_ENABLE
1745 config HAVE_ARCH_PFN_VALID
1746 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1749 bool "High Memory Support"
1752 The address space of ARM processors is only 4 Gigabytes large
1753 and it has to accommodate user address space, kernel address
1754 space as well as some memory mapped IO. That means that, if you
1755 have a large amount of physical memory and/or IO, not all of the
1756 memory can be "permanently mapped" by the kernel. The physical
1757 memory that is not permanently mapped is called "high memory".
1759 Depending on the selected kernel/user memory split, minimum
1760 vmalloc space and actual amount of RAM, you may not need this
1761 option which should result in a slightly faster kernel.
1766 bool "Allocate 2nd-level pagetables from highmem"
1769 config HW_PERF_EVENTS
1770 bool "Enable hardware performance counter support for perf events"
1771 depends on PERF_EVENTS
1774 Enable hardware performance counter support for perf events. If
1775 disabled, perf events will use software events only.
1779 config FORCE_MAX_ZONEORDER
1780 int "Maximum zone order" if ARCH_SHMOBILE
1781 range 11 64 if ARCH_SHMOBILE
1782 default "12" if SOC_AM33XX
1783 default "9" if SA1111
1786 The kernel memory allocator divides physically contiguous memory
1787 blocks into "zones", where each zone is a power of two number of
1788 pages. This option selects the largest power of two that the kernel
1789 keeps in the memory allocator. If you need to allocate very large
1790 blocks of physically contiguous memory, then you may need to
1791 increase this value.
1793 This config option is actually maximum order plus one. For example,
1794 a value of 11 means that the largest free memory block is 2^10 pages.
1796 config ALIGNMENT_TRAP
1798 depends on CPU_CP15_MMU
1799 default y if !ARCH_EBSA110
1800 select HAVE_PROC_CPU if PROC_FS
1802 ARM processors cannot fetch/store information which is not
1803 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1804 address divisible by 4. On 32-bit ARM processors, these non-aligned
1805 fetch/store instructions will be emulated in software if you say
1806 here, which has a severe performance impact. This is necessary for
1807 correct operation of some network protocols. With an IP-only
1808 configuration it is safe to say N, otherwise say Y.
1810 config UACCESS_WITH_MEMCPY
1811 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1813 default y if CPU_FEROCEON
1815 Implement faster copy_to_user and clear_user methods for CPU
1816 cores where a 8-word STM instruction give significantly higher
1817 memory write throughput than a sequence of individual 32bit stores.
1819 A possible side effect is a slight increase in scheduling latency
1820 between threads sharing the same address space if they invoke
1821 such copy operations with large buffers.
1823 However, if the CPU data cache is using a write-allocate mode,
1824 this option is unlikely to provide any performance gain.
1828 prompt "Enable seccomp to safely compute untrusted bytecode"
1830 This kernel feature is useful for number crunching applications
1831 that may need to compute untrusted bytecode during their
1832 execution. By using pipes or other transports made available to
1833 the process as file descriptors supporting the read/write
1834 syscalls, it's possible to isolate those applications in
1835 their own address space using seccomp. Once seccomp is
1836 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1837 and the task is only allowed to execute a few safe syscalls
1838 defined by each seccomp mode.
1840 config CC_STACKPROTECTOR
1841 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1842 depends on EXPERIMENTAL
1844 This option turns on the -fstack-protector GCC feature. This
1845 feature puts, at the beginning of functions, a canary value on
1846 the stack just before the return address, and validates
1847 the value just before actually returning. Stack based buffer
1848 overflows (that need to overwrite this return address) now also
1849 overwrite the canary, which gets detected and the attack is then
1850 neutralized via a kernel panic.
1851 This feature requires gcc version 4.2 or above.
1858 bool "Xen guest support on ARM (EXPERIMENTAL)"
1859 depends on EXPERIMENTAL && ARM && OF
1860 depends on CPU_V7 && !CPU_V6
1862 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1869 bool "Flattened Device Tree support"
1872 select OF_EARLY_FLATTREE
1874 Include support for flattened device tree machine descriptions.
1877 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1880 This is the traditional way of passing data to the kernel at boot
1881 time. If you are solely relying on the flattened device tree (or
1882 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1883 to remove ATAGS support from your kernel binary. If unsure,
1886 config DEPRECATED_PARAM_STRUCT
1887 bool "Provide old way to pass kernel parameters"
1890 This was deprecated in 2001 and announced to live on for 5 years.
1891 Some old boot loaders still use this way.
1893 # Compressed boot loader in ROM. Yes, we really want to ask about
1894 # TEXT and BSS so we preserve their values in the config files.
1895 config ZBOOT_ROM_TEXT
1896 hex "Compressed ROM boot loader base address"
1899 The physical address at which the ROM-able zImage is to be
1900 placed in the target. Platforms which normally make use of
1901 ROM-able zImage formats normally set this to a suitable
1902 value in their defconfig file.
1904 If ZBOOT_ROM is not enabled, this has no effect.
1906 config ZBOOT_ROM_BSS
1907 hex "Compressed ROM boot loader BSS address"
1910 The base address of an area of read/write memory in the target
1911 for the ROM-able zImage which must be available while the
1912 decompressor is running. It must be large enough to hold the
1913 entire decompressed kernel plus an additional 128 KiB.
1914 Platforms which normally make use of ROM-able zImage formats
1915 normally set this to a suitable value in their defconfig file.
1917 If ZBOOT_ROM is not enabled, this has no effect.
1920 bool "Compressed boot loader in ROM/flash"
1921 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1923 Say Y here if you intend to execute your compressed kernel image
1924 (zImage) directly from ROM or flash. If unsure, say N.
1927 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1928 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1929 default ZBOOT_ROM_NONE
1931 Include experimental SD/MMC loading code in the ROM-able zImage.
1932 With this enabled it is possible to write the ROM-able zImage
1933 kernel image to an MMC or SD card and boot the kernel straight
1934 from the reset vector. At reset the processor Mask ROM will load
1935 the first part of the ROM-able zImage which in turn loads the
1936 rest the kernel image to RAM.
1938 config ZBOOT_ROM_NONE
1939 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1941 Do not load image from SD or MMC
1943 config ZBOOT_ROM_MMCIF
1944 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1946 Load image from MMCIF hardware block.
1948 config ZBOOT_ROM_SH_MOBILE_SDHI
1949 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1951 Load image from SDHI hardware block
1955 config ARM_APPENDED_DTB
1956 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1957 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1959 With this option, the boot code will look for a device tree binary
1960 (DTB) appended to zImage
1961 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1963 This is meant as a backward compatibility convenience for those
1964 systems with a bootloader that can't be upgraded to accommodate
1965 the documented boot protocol using a device tree.
1967 Beware that there is very little in terms of protection against
1968 this option being confused by leftover garbage in memory that might
1969 look like a DTB header after a reboot if no actual DTB is appended
1970 to zImage. Do not leave this option active in a production kernel
1971 if you don't intend to always append a DTB. Proper passing of the
1972 location into r2 of a bootloader provided DTB is always preferable
1975 config ARM_ATAG_DTB_COMPAT
1976 bool "Supplement the appended DTB with traditional ATAG information"
1977 depends on ARM_APPENDED_DTB
1979 Some old bootloaders can't be updated to a DTB capable one, yet
1980 they provide ATAGs with memory configuration, the ramdisk address,
1981 the kernel cmdline string, etc. Such information is dynamically
1982 provided by the bootloader and can't always be stored in a static
1983 DTB. To allow a device tree enabled kernel to be used with such
1984 bootloaders, this option allows zImage to extract the information
1985 from the ATAG list and store it at run time into the appended DTB.
1988 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1989 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1991 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1992 bool "Use bootloader kernel arguments if available"
1994 Uses the command-line options passed by the boot loader instead of
1995 the device tree bootargs property. If the boot loader doesn't provide
1996 any, the device tree bootargs property will be used.
1998 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1999 bool "Extend with bootloader kernel arguments"
2001 The command-line arguments provided by the boot loader will be
2002 appended to the the device tree bootargs property.
2007 string "Default kernel command string"
2010 On some architectures (EBSA110 and CATS), there is currently no way
2011 for the boot loader to pass arguments to the kernel. For these
2012 architectures, you should supply some command-line options at build
2013 time by entering them here. As a minimum, you should specify the
2014 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2017 prompt "Kernel command line type" if CMDLINE != ""
2018 default CMDLINE_FROM_BOOTLOADER
2021 config CMDLINE_FROM_BOOTLOADER
2022 bool "Use bootloader kernel arguments if available"
2024 Uses the command-line options passed by the boot loader. If
2025 the boot loader doesn't provide any, the default kernel command
2026 string provided in CMDLINE will be used.
2028 config CMDLINE_EXTEND
2029 bool "Extend bootloader kernel arguments"
2031 The command-line arguments provided by the boot loader will be
2032 appended to the default kernel command string.
2034 config CMDLINE_FORCE
2035 bool "Always use the default kernel command string"
2037 Always use the default kernel command string, even if the boot
2038 loader passes other arguments to the kernel.
2039 This is useful if you cannot or don't want to change the
2040 command-line options your boot loader passes to the kernel.
2044 bool "Kernel Execute-In-Place from ROM"
2045 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2047 Execute-In-Place allows the kernel to run from non-volatile storage
2048 directly addressable by the CPU, such as NOR flash. This saves RAM
2049 space since the text section of the kernel is not loaded from flash
2050 to RAM. Read-write sections, such as the data section and stack,
2051 are still copied to RAM. The XIP kernel is not compressed since
2052 it has to run directly from flash, so it will take more space to
2053 store it. The flash address used to link the kernel object files,
2054 and for storing it, is configuration dependent. Therefore, if you
2055 say Y here, you must know the proper physical address where to
2056 store the kernel image depending on your own flash memory usage.
2058 Also note that the make target becomes "make xipImage" rather than
2059 "make zImage" or "make Image". The final kernel binary to put in
2060 ROM memory will be arch/arm/boot/xipImage.
2064 config XIP_PHYS_ADDR
2065 hex "XIP Kernel Physical Location"
2066 depends on XIP_KERNEL
2067 default "0x00080000"
2069 This is the physical address in your flash memory the kernel will
2070 be linked for and stored to. This address is dependent on your
2074 bool "Kexec system call (EXPERIMENTAL)"
2075 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2077 kexec is a system call that implements the ability to shutdown your
2078 current kernel, and to start another kernel. It is like a reboot
2079 but it is independent of the system firmware. And like a reboot
2080 you can start any kernel with it, not just Linux.
2082 It is an ongoing process to be certain the hardware in a machine
2083 is properly shutdown, so do not be surprised if this code does not
2084 initially work for you. It may help to enable device hotplugging
2088 bool "Export atags in procfs"
2089 depends on ATAGS && KEXEC
2092 Should the atags used to boot the kernel be exported in an "atags"
2093 file in procfs. Useful with kexec.
2096 bool "Build kdump crash kernel (EXPERIMENTAL)"
2097 depends on EXPERIMENTAL
2099 Generate crash dump after being started by kexec. This should
2100 be normally only set in special crash dump kernels which are
2101 loaded in the main kernel with kexec-tools into a specially
2102 reserved region and then later executed after a crash by
2103 kdump/kexec. The crash dump kernel must be compiled to a
2104 memory address not used by the main kernel
2106 For more details see Documentation/kdump/kdump.txt
2108 config AUTO_ZRELADDR
2109 bool "Auto calculation of the decompressed kernel image address"
2110 depends on !ZBOOT_ROM && !ARCH_U300
2112 ZRELADDR is the physical address where the decompressed kernel
2113 image will be placed. If AUTO_ZRELADDR is selected, the address
2114 will be determined at run-time by masking the current IP with
2115 0xf8000000. This assumes the zImage being placed in the first 128MB
2116 from start of memory.
2120 menu "CPU Power Management"
2124 source "drivers/cpufreq/Kconfig"
2127 tristate "CPUfreq driver for i.MX CPUs"
2128 depends on ARCH_MXC && CPU_FREQ
2129 select CPU_FREQ_TABLE
2131 This enables the CPUfreq driver for i.MX CPUs.
2133 config CPU_FREQ_SA1100
2136 config CPU_FREQ_SA1110
2139 config CPU_FREQ_INTEGRATOR
2140 tristate "CPUfreq driver for ARM Integrator CPUs"
2141 depends on ARCH_INTEGRATOR && CPU_FREQ
2144 This enables the CPUfreq driver for ARM Integrator CPUs.
2146 For details, take a look at <file:Documentation/cpu-freq>.
2152 depends on CPU_FREQ && ARCH_PXA && PXA25x
2154 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2155 select CPU_FREQ_TABLE
2160 Internal configuration node for common cpufreq on Samsung SoC
2162 config CPU_FREQ_S3C24XX
2163 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2164 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2167 This enables the CPUfreq driver for the Samsung S3C24XX family
2170 For details, take a look at <file:Documentation/cpu-freq>.
2174 config CPU_FREQ_S3C24XX_PLL
2175 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2176 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2178 Compile in support for changing the PLL frequency from the
2179 S3C24XX series CPUfreq driver. The PLL takes time to settle
2180 after a frequency change, so by default it is not enabled.
2182 This also means that the PLL tables for the selected CPU(s) will
2183 be built which may increase the size of the kernel image.
2185 config CPU_FREQ_S3C24XX_DEBUG
2186 bool "Debug CPUfreq Samsung driver core"
2187 depends on CPU_FREQ_S3C24XX
2189 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2191 config CPU_FREQ_S3C24XX_IODEBUG
2192 bool "Debug CPUfreq Samsung driver IO timing"
2193 depends on CPU_FREQ_S3C24XX
2195 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2197 config CPU_FREQ_S3C24XX_DEBUGFS
2198 bool "Export debugfs for CPUFreq"
2199 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2201 Export status information via debugfs.
2205 source "drivers/cpuidle/Kconfig"
2209 menu "Floating point emulation"
2211 comment "At least one emulation must be selected"
2214 bool "NWFPE math emulation"
2215 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2217 Say Y to include the NWFPE floating point emulator in the kernel.
2218 This is necessary to run most binaries. Linux does not currently
2219 support floating point hardware so you need to say Y here even if
2220 your machine has an FPA or floating point co-processor podule.
2222 You may say N here if you are going to load the Acorn FPEmulator
2223 early in the bootup.
2226 bool "Support extended precision"
2227 depends on FPE_NWFPE
2229 Say Y to include 80-bit support in the kernel floating-point
2230 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2231 Note that gcc does not generate 80-bit operations by default,
2232 so in most cases this option only enlarges the size of the
2233 floating point emulator without any good reason.
2235 You almost surely want to say N here.
2238 bool "FastFPE math emulation (EXPERIMENTAL)"
2239 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2241 Say Y here to include the FAST floating point emulator in the kernel.
2242 This is an experimental much faster emulator which now also has full
2243 precision for the mantissa. It does not support any exceptions.
2244 It is very simple, and approximately 3-6 times faster than NWFPE.
2246 It should be sufficient for most programs. It may be not suitable
2247 for scientific calculations, but you have to check this for yourself.
2248 If you do not feel you need a faster FP emulation you should better
2252 bool "VFP-format floating point maths"
2253 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2255 Say Y to include VFP support code in the kernel. This is needed
2256 if your hardware includes a VFP unit.
2258 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2259 release notes and additional status information.
2261 Say N if your target does not have VFP hardware.
2269 bool "Advanced SIMD (NEON) Extension support"
2270 depends on VFPv3 && CPU_V7
2272 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2277 menu "Userspace binary formats"
2279 source "fs/Kconfig.binfmt"
2282 tristate "RISC OS personality"
2285 Say Y here to include the kernel code necessary if you want to run
2286 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2287 experimental; if this sounds frightening, say N and sleep in peace.
2288 You can also say M here to compile this support as a module (which
2289 will be called arthur).
2293 menu "Power management options"
2295 source "kernel/power/Kconfig"
2297 config ARCH_SUSPEND_POSSIBLE
2298 depends on !ARCH_S5PC100
2299 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2300 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2303 config ARM_CPU_SUSPEND
2308 source "net/Kconfig"
2310 source "drivers/Kconfig"
2314 source "arch/arm/Kconfig.debug"
2316 source "security/Kconfig"
2318 source "crypto/Kconfig"
2320 source "lib/Kconfig"