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[can-eth-gw-linux.git] / sound / pci / rme9652 / hdspm.c
1 /*
2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3  *
4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
5  *      code based on hdsp.c   Paul Davis
6  *                             Marcus Andersson
7  *                             Thomas Charbonnel
8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
9  *                                               <remy.bruno@trinnov.com>
10  *
11  *      Modified 2009-04-13 for proper metering by Florian Faber
12  *                                               <faber@faberman.de>
13  *
14  *      Modified 2009-04-14 for native float support by Florian Faber
15  *                                               <faber@faberman.de>
16  *
17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18  *                                               <faber@faberman.de>
19  *
20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
21  *
22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23  *
24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25  *
26  *   This program is free software; you can redistribute it and/or modify
27  *   it under the terms of the GNU General Public License as published by
28  *   the Free Software Foundation; either version 2 of the License, or
29  *   (at your option) any later version.
30  *
31  *   This program is distributed in the hope that it will be useful,
32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
34  *   GNU General Public License for more details.
35  *
36  *   You should have received a copy of the GNU General Public License
37  *   along with this program; if not, write to the Free Software
38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
39  *
40  */
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
48 #include <asm/io.h>
49
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
59
60 #include <sound/hdspm.h>
61
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
65
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
68
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
71
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
74
75
76 MODULE_AUTHOR
77 (
78         "Winfried Ritsch <ritsch_AT_iem.at>, "
79         "Paul Davis <paul@linuxaudiosystems.com>, "
80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81         "Remy Bruno <remy.bruno@trinnov.com>, "
82         "Florian Faber <faberman@linuxproaudio.org>, "
83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
84 );
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
88
89 /* --- Write registers. ---
90   These are defined as byte-offsets from the iobase value.  */
91
92 #define HDSPM_WR_SETTINGS             0
93 #define HDSPM_outputBufferAddress    32
94 #define HDSPM_inputBufferAddress     36
95 #define HDSPM_controlRegister        64
96 #define HDSPM_interruptConfirmation  96
97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
98 #define HDSPM_freqReg                256  /* for AES32 */
99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
100 #define HDSPM_midiDataOut1           356
101 #define HDSPM_eeprom_wr              384  /* for AES32 */
102
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
106
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut       8192
110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
111
112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
113
114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
115
116 /* --- Read registers. ---
117    These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister    0
119 /*#define HDSPM_statusRegister2  96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121  * offset 192, for AES32 *and* MADI
122  * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2  192
124 #define HDSPM_timecodeRegister 128
125
126 /* AIO, RayDAT */
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
131
132 #define HDSPM_RD_TCO           256
133 #define HDSPM_RD_PLL_FREQ      512
134 #define HDSPM_WR_TCO           128
135
136 #define HDSPM_TCO1_TCO_lock                     0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
143
144 #define HDSPM_TCO1_set_TC                       0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
148
149 #define HDSPM_TCO2_TC_run                       0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
155 #define HDSPM_TCO2_set_flywheel                 0x00400000
156
157 #define HDSPM_TCO2_set_01_4                     0x01000000
158 #define HDSPM_TCO2_set_pull_down                0x02000000
159 #define HDSPM_TCO2_set_pull_up                  0x04000000
160 #define HDSPM_TCO2_set_freq                     0x08000000
161 #define HDSPM_TCO2_set_term_75R                 0x10000000
162 #define HDSPM_TCO2_set_input_LSB                0x20000000
163 #define HDSPM_TCO2_set_input_MSB                0x40000000
164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
165
166
167 #define HDSPM_midiDataOut0    352
168 #define HDSPM_midiDataOut1    356
169 #define HDSPM_midiDataOut2    368
170
171 #define HDSPM_midiDataIn0     360
172 #define HDSPM_midiDataIn1     364
173 #define HDSPM_midiDataIn2     372
174 #define HDSPM_midiDataIn3     376
175
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0  384
178 #define HDSPM_midiStatusOut1  388
179 #define HDSPM_midiStatusOut2  400
180
181 #define HDSPM_midiStatusIn0   392
182 #define HDSPM_midiStatusIn1   396
183 #define HDSPM_midiStatusIn2   404
184 #define HDSPM_midiStatusIn3   408
185
186
187 /* the meters are regular i/o-mapped registers, but offset
188    considerably from the rest. the peak registers are reset
189    when read; the least-significant 4 bits are full-scale counters;
190    the actual peak value is in the most-significant 24 bits.
191 */
192
193 #define HDSPM_MADI_INPUT_PEAK           4096
194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
195 #define HDSPM_MADI_OUTPUT_PEAK          4608
196
197 #define HDSPM_MADI_INPUT_RMS_L          6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
200
201 #define HDSPM_MADI_INPUT_RMS_H          7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
204
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start                (1<<0) /* start engine */
207
208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
211
212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
214                                           register [RayDAT, AIO] */
215
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
217
218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
222
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
225                                      56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
227
228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
229                                      0=off, 1=on  */ /* MADI ONLY */
230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
231
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
233                                     * -- MADI ONLY
234                                     */
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
236
237 #define HDSPM_SyncRef2     (1<<13)
238 #define HDSPM_SyncRef3     (1<<25)
239
240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
242                                       AES additional bits in
243                                       lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
246
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
251
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT         0x2000000
254
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
258
259 #define HDSPM_wclk_sel (1<<30)
260
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
264                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical   0
267 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269                               HDSPM_SyncRef2|HDSPM_SyncRef3)
270
271 #define HDSPM_c0_SyncRef0      0x2
272 #define HDSPM_c0_SyncRef1      0x4
273 #define HDSPM_c0_SyncRef2      0x8
274 #define HDSPM_c0_SyncRef3      0x10
275 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
277
278 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO     2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
282
283 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
289                                 HDSPM_Frequency0)
290 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
293                                  HDSPM_Frequency0)
294
295
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK    1
299 #define HDSPM_SYNC_CHECK_SYNC    2
300
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD      0
303 #define HDSPM_AUTOSYNC_FROM_MADI      1
304 #define HDSPM_AUTOSYNC_FROM_TCO       2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
306 #define HDSPM_AUTOSYNC_FROM_NONE      4
307
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0         /* optical   */
310 #define HDSPM_COAXIAL 1         /* BNC */
311
312 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
314
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
317
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS             (1<<0)
320 #define HDSPM_TCK             (1<<1)
321 #define HDSPM_TDI             (1<<2)
322 #define HDSPM_JTAG            (1<<3)
323 #define HDSPM_PWDN            (1<<4)
324 #define HDSPM_PROGRAM         (1<<5)
325 #define HDSPM_CONFIG_MODE_0   (1<<6)
326 #define HDSPM_CONFIG_MODE_1   (1<<7)
327 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE  (1<<9)
329 #define HDSPM_RD_MULTIPLE     (1<<10)
330
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332      that do not conflict with specific bits for AES32 seem to be valid also
333      for the AES32
334  */
335 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
338                                          * (like inp0)
339                                          */
340
341 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
343
344 #define HDSPM_tcoLock    0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status */
346
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
349
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351                         /* since 64byte accurate, last 6 bits are not used */
352
353
354
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
356
357 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
361
362 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
363                                          * Interrupt
364                                          */
365 #define HDSPM_tco_detect         0x08000000
366 #define HDSPM_tco_lock           0x20000000
367
368 #define HDSPM_s2_tco_detect      0x00000040
369 #define HDSPM_s2_AEBO_D          0x00000080
370 #define HDSPM_s2_AEBI_D          0x00000100
371
372
373 #define HDSPM_midi0IRQPending    0x40000000
374 #define HDSPM_midi1IRQPending    0x80000000
375 #define HDSPM_midi2IRQPending    0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending    0x00200000
378
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381                              HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
391
392 /* Status2 Register bits */ /* MADI ONLY */
393
394 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
397
398 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
400
401 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
402 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit   for               111=128, 1000=176.4, 1001=192 */
405
406 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
408
409 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
412
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
414
415 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
422
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
428
429
430 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
431                                     HDSPM_SelSyncRef2)
432 #define HDSPM_SelSyncRef_WORD      0
433 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
437                                     HDSPM_SelSyncRef2)
438
439 /*
440    For AES32, bits for status, status2 and timecode are different
441 */
442 /* status */
443 #define HDSPM_AES32_wcLock      0x0200000
444 #define HDSPM_AES32_wcFreq_bit  22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
446   HDSPM_bit2freq */
447 #define HDSPM_AES32_syncref_bit  16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
449
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
460
461 /*  status2 */
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES   0x80
464 #define HDSPM_LockAES1  0x80
465 #define HDSPM_LockAES2  0x40
466 #define HDSPM_LockAES3  0x20
467 #define HDSPM_LockAES4  0x10
468 #define HDSPM_LockAES5  0x8
469 #define HDSPM_LockAES6  0x4
470 #define HDSPM_LockAES7  0x2
471 #define HDSPM_LockAES8  0x1
472 /*
473    Timecode
474    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
475    AES i+1
476  bits 3210
477       0001  32kHz
478       0010  44.1kHz
479       0011  48kHz
480       0100  64kHz
481       0101  88.2kHz
482       0110  96kHz
483       0111  128kHz
484       1000  176.4kHz
485       1001  192kHz
486   NB: Timecode register doesn't seem to work on AES32 card revision 230
487 */
488
489 /* Mixer Values */
490 #define UNITY_GAIN          32768       /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
492
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS       64
495 #define MADI_DS_CHANNELS       32
496 #define MADI_QS_CHANNELS       16
497
498 #define RAYDAT_SS_CHANNELS     36
499 #define RAYDAT_DS_CHANNELS     20
500 #define RAYDAT_QS_CHANNELS     12
501
502 #define AIO_IN_SS_CHANNELS        14
503 #define AIO_IN_DS_CHANNELS        10
504 #define AIO_IN_QS_CHANNELS        8
505 #define AIO_OUT_SS_CHANNELS        16
506 #define AIO_OUT_DS_CHANNELS        12
507 #define AIO_OUT_QS_CHANNELS        10
508
509 #define AES32_CHANNELS          16
510
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
514
515 /* the size of the area we need to allocate for DMA transfers. the
516    size is the same regardless of the number of channels, and
517    also the latency to use.
518    for one direction !!!
519 */
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
522
523 #define HDSPM_RAYDAT_REV        211
524 #define HDSPM_AIO_REV           212
525 #define HDSPM_MADIFACE_REV      213
526
527 /* speed factor modes */
528 #define HDSPM_SPEED_SINGLE 0
529 #define HDSPM_SPEED_DOUBLE 1
530 #define HDSPM_SPEED_QUAD   2
531
532 /* names for speed modes */
533 static char *hdspm_speed_names[] = { "single", "double", "quad" };
534
535 static char *texts_autosync_aes_tco[] = { "Word Clock",
536                                           "AES1", "AES2", "AES3", "AES4",
537                                           "AES5", "AES6", "AES7", "AES8",
538                                           "TCO" };
539 static char *texts_autosync_aes[] = { "Word Clock",
540                                       "AES1", "AES2", "AES3", "AES4",
541                                       "AES5", "AES6", "AES7", "AES8" };
542 static char *texts_autosync_madi_tco[] = { "Word Clock",
543                                            "MADI", "TCO", "Sync In" };
544 static char *texts_autosync_madi[] = { "Word Clock",
545                                        "MADI", "Sync In" };
546
547 static char *texts_autosync_raydat_tco[] = {
548         "Word Clock",
549         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550         "AES", "SPDIF", "TCO", "Sync In"
551 };
552 static char *texts_autosync_raydat[] = {
553         "Word Clock",
554         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555         "AES", "SPDIF", "Sync In"
556 };
557 static char *texts_autosync_aio_tco[] = {
558         "Word Clock",
559         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
560 };
561 static char *texts_autosync_aio[] = { "Word Clock",
562                                       "ADAT", "AES", "SPDIF", "Sync In" };
563
564 static char *texts_freq[] = {
565         "No Lock",
566         "32 kHz",
567         "44.1 kHz",
568         "48 kHz",
569         "64 kHz",
570         "88.2 kHz",
571         "96 kHz",
572         "128 kHz",
573         "176.4 kHz",
574         "192 kHz"
575 };
576
577 static char *texts_ports_madi[] = {
578         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
589 };
590
591
592 static char *texts_ports_raydat_ss[] = {
593         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598         "ADAT4.7", "ADAT4.8",
599         "AES.L", "AES.R",
600         "SPDIF.L", "SPDIF.R"
601 };
602
603 static char *texts_ports_raydat_ds[] = {
604         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
608         "AES.L", "AES.R",
609         "SPDIF.L", "SPDIF.R"
610 };
611
612 static char *texts_ports_raydat_qs[] = {
613         "ADAT1.1", "ADAT1.2",
614         "ADAT2.1", "ADAT2.2",
615         "ADAT3.1", "ADAT3.2",
616         "ADAT4.1", "ADAT4.2",
617         "AES.L", "AES.R",
618         "SPDIF.L", "SPDIF.R"
619 };
620
621
622 static char *texts_ports_aio_in_ss[] = {
623         "Analogue.L", "Analogue.R",
624         "AES.L", "AES.R",
625         "SPDIF.L", "SPDIF.R",
626         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
627         "ADAT.7", "ADAT.8"
628 };
629
630 static char *texts_ports_aio_out_ss[] = {
631         "Analogue.L", "Analogue.R",
632         "AES.L", "AES.R",
633         "SPDIF.L", "SPDIF.R",
634         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
635         "ADAT.7", "ADAT.8",
636         "Phone.L", "Phone.R"
637 };
638
639 static char *texts_ports_aio_in_ds[] = {
640         "Analogue.L", "Analogue.R",
641         "AES.L", "AES.R",
642         "SPDIF.L", "SPDIF.R",
643         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
644 };
645
646 static char *texts_ports_aio_out_ds[] = {
647         "Analogue.L", "Analogue.R",
648         "AES.L", "AES.R",
649         "SPDIF.L", "SPDIF.R",
650         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
651         "Phone.L", "Phone.R"
652 };
653
654 static char *texts_ports_aio_in_qs[] = {
655         "Analogue.L", "Analogue.R",
656         "AES.L", "AES.R",
657         "SPDIF.L", "SPDIF.R",
658         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
659 };
660
661 static char *texts_ports_aio_out_qs[] = {
662         "Analogue.L", "Analogue.R",
663         "AES.L", "AES.R",
664         "SPDIF.L", "SPDIF.R",
665         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
666         "Phone.L", "Phone.R"
667 };
668
669 static char *texts_ports_aes32[] = {
670         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
672         "AES.15", "AES.16"
673 };
674
675 /* These tables map the ALSA channels 1..N to the channels that we
676    need to use in order to find the relevant channel buffer. RME
677    refers to this kind of mapping as between "the ADAT channel and
678    the DMA channel." We index it using the logical audio channel,
679    and the value is the DMA channel (i.e. channel buffer number)
680    where the data for that channel can be read/written from/to.
681 */
682
683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684         0, 1, 2, 3, 4, 5, 6, 7,
685         8, 9, 10, 11, 12, 13, 14, 15,
686         16, 17, 18, 19, 20, 21, 22, 23,
687         24, 25, 26, 27, 28, 29, 30, 31,
688         32, 33, 34, 35, 36, 37, 38, 39,
689         40, 41, 42, 43, 44, 45, 46, 47,
690         48, 49, 50, 51, 52, 53, 54, 55,
691         56, 57, 58, 59, 60, 61, 62, 63
692 };
693
694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
696         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
699         0, 1,                   /* AES */
700         2, 3,                   /* SPDIF */
701         -1, -1, -1, -1,
702         -1, -1, -1, -1, -1, -1, -1, -1,
703         -1, -1, -1, -1, -1, -1, -1, -1,
704         -1, -1, -1, -1, -1, -1, -1, -1,
705 };
706
707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708         4, 5, 6, 7,             /* ADAT 1 */
709         8, 9, 10, 11,           /* ADAT 2 */
710         12, 13, 14, 15,         /* ADAT 3 */
711         16, 17, 18, 19,         /* ADAT 4 */
712         0, 1,                   /* AES */
713         2, 3,                   /* SPDIF */
714         -1, -1, -1, -1,
715         -1, -1, -1, -1, -1, -1, -1, -1,
716         -1, -1, -1, -1, -1, -1, -1, -1,
717         -1, -1, -1, -1, -1, -1, -1, -1,
718         -1, -1, -1, -1, -1, -1, -1, -1,
719         -1, -1, -1, -1, -1, -1, -1, -1,
720 };
721
722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
723         4, 5,                   /* ADAT 1 */
724         6, 7,                   /* ADAT 2 */
725         8, 9,                   /* ADAT 3 */
726         10, 11,                 /* ADAT 4 */
727         0, 1,                   /* AES */
728         2, 3,                   /* SPDIF */
729         -1, -1, -1, -1,
730         -1, -1, -1, -1, -1, -1, -1, -1,
731         -1, -1, -1, -1, -1, -1, -1, -1,
732         -1, -1, -1, -1, -1, -1, -1, -1,
733         -1, -1, -1, -1, -1, -1, -1, -1,
734         -1, -1, -1, -1, -1, -1, -1, -1,
735         -1, -1, -1, -1, -1, -1, -1, -1,
736 };
737
738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
739         0, 1,                   /* line in */
740         8, 9,                   /* aes in, */
741         10, 11,                 /* spdif in */
742         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
743         -1, -1,
744         -1, -1, -1, -1, -1, -1, -1, -1,
745         -1, -1, -1, -1, -1, -1, -1, -1,
746         -1, -1, -1, -1, -1, -1, -1, -1,
747         -1, -1, -1, -1, -1, -1, -1, -1,
748         -1, -1, -1, -1, -1, -1, -1, -1,
749         -1, -1, -1, -1, -1, -1, -1, -1,
750 };
751
752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
753         0, 1,                   /* line out */
754         8, 9,                   /* aes out */
755         10, 11,                 /* spdif out */
756         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757         6, 7,                   /* phone out */
758         -1, -1, -1, -1, -1, -1, -1, -1,
759         -1, -1, -1, -1, -1, -1, -1, -1,
760         -1, -1, -1, -1, -1, -1, -1, -1,
761         -1, -1, -1, -1, -1, -1, -1, -1,
762         -1, -1, -1, -1, -1, -1, -1, -1,
763         -1, -1, -1, -1, -1, -1, -1, -1,
764 };
765
766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
767         0, 1,                   /* line in */
768         8, 9,                   /* aes in */
769         10, 11,                 /* spdif in */
770         12, 14, 16, 18,         /* adat in */
771         -1, -1, -1, -1, -1, -1,
772         -1, -1, -1, -1, -1, -1, -1, -1,
773         -1, -1, -1, -1, -1, -1, -1, -1,
774         -1, -1, -1, -1, -1, -1, -1, -1,
775         -1, -1, -1, -1, -1, -1, -1, -1,
776         -1, -1, -1, -1, -1, -1, -1, -1,
777         -1, -1, -1, -1, -1, -1, -1, -1
778 };
779
780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
781         0, 1,                   /* line out */
782         8, 9,                   /* aes out */
783         10, 11,                 /* spdif out */
784         12, 14, 16, 18,         /* adat out */
785         6, 7,                   /* phone out */
786         -1, -1, -1, -1,
787         -1, -1, -1, -1, -1, -1, -1, -1,
788         -1, -1, -1, -1, -1, -1, -1, -1,
789         -1, -1, -1, -1, -1, -1, -1, -1,
790         -1, -1, -1, -1, -1, -1, -1, -1,
791         -1, -1, -1, -1, -1, -1, -1, -1,
792         -1, -1, -1, -1, -1, -1, -1, -1
793 };
794
795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
796         0, 1,                   /* line in */
797         8, 9,                   /* aes in */
798         10, 11,                 /* spdif in */
799         12, 16,                 /* adat in */
800         -1, -1, -1, -1, -1, -1, -1, -1,
801         -1, -1, -1, -1, -1, -1, -1, -1,
802         -1, -1, -1, -1, -1, -1, -1, -1,
803         -1, -1, -1, -1, -1, -1, -1, -1,
804         -1, -1, -1, -1, -1, -1, -1, -1,
805         -1, -1, -1, -1, -1, -1, -1, -1,
806         -1, -1, -1, -1, -1, -1, -1, -1
807 };
808
809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
810         0, 1,                   /* line out */
811         8, 9,                   /* aes out */
812         10, 11,                 /* spdif out */
813         12, 16,                 /* adat out */
814         6, 7,                   /* phone out */
815         -1, -1, -1, -1, -1, -1,
816         -1, -1, -1, -1, -1, -1, -1, -1,
817         -1, -1, -1, -1, -1, -1, -1, -1,
818         -1, -1, -1, -1, -1, -1, -1, -1,
819         -1, -1, -1, -1, -1, -1, -1, -1,
820         -1, -1, -1, -1, -1, -1, -1, -1,
821         -1, -1, -1, -1, -1, -1, -1, -1
822 };
823
824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825         0, 1, 2, 3, 4, 5, 6, 7,
826         8, 9, 10, 11, 12, 13, 14, 15,
827         -1, -1, -1, -1, -1, -1, -1, -1,
828         -1, -1, -1, -1, -1, -1, -1, -1,
829         -1, -1, -1, -1, -1, -1, -1, -1,
830         -1, -1, -1, -1, -1, -1, -1, -1,
831         -1, -1, -1, -1, -1, -1, -1, -1,
832         -1, -1, -1, -1, -1, -1, -1, -1
833 };
834
835 struct hdspm_midi {
836         struct hdspm *hdspm;
837         int id;
838         struct snd_rawmidi *rmidi;
839         struct snd_rawmidi_substream *input;
840         struct snd_rawmidi_substream *output;
841         char istimer;           /* timer in use */
842         struct timer_list timer;
843         spinlock_t lock;
844         int pending;
845         int dataIn;
846         int statusIn;
847         int dataOut;
848         int statusOut;
849         int ie;
850         int irq;
851 };
852
853 struct hdspm_tco {
854         int input;
855         int framerate;
856         int wordclock;
857         int samplerate;
858         int pull;
859         int term; /* 0 = off, 1 = on */
860 };
861
862 struct hdspm {
863         spinlock_t lock;
864         /* only one playback and/or capture stream */
865         struct snd_pcm_substream *capture_substream;
866         struct snd_pcm_substream *playback_substream;
867
868         char *card_name;             /* for procinfo */
869         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
870
871         uint8_t io_type;
872
873         int monitor_outs;       /* set up monitoring outs init flag */
874
875         u32 control_register;   /* cached value */
876         u32 control2_register;  /* cached value */
877         u32 settings_register;
878
879         struct hdspm_midi midi[4];
880         struct tasklet_struct midi_tasklet;
881
882         size_t period_bytes;
883         unsigned char ss_in_channels;
884         unsigned char ds_in_channels;
885         unsigned char qs_in_channels;
886         unsigned char ss_out_channels;
887         unsigned char ds_out_channels;
888         unsigned char qs_out_channels;
889
890         unsigned char max_channels_in;
891         unsigned char max_channels_out;
892
893         signed char *channel_map_in;
894         signed char *channel_map_out;
895
896         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
898
899         char **port_names_in;
900         char **port_names_out;
901
902         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
904
905         unsigned char *playback_buffer; /* suitably aligned address */
906         unsigned char *capture_buffer;  /* suitably aligned address */
907
908         pid_t capture_pid;      /* process id which uses capture */
909         pid_t playback_pid;     /* process id which uses capture */
910         int running;            /* running status */
911
912         int last_external_sample_rate;  /* samplerate mystic ... */
913         int last_internal_sample_rate;
914         int system_sample_rate;
915
916         int dev;                /* Hardware vars... */
917         int irq;
918         unsigned long port;
919         void __iomem *iobase;
920
921         int irq_count;          /* for debug */
922         int midiPorts;
923
924         struct snd_card *card;  /* one card */
925         struct snd_pcm *pcm;            /* has one pcm */
926         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
927         struct pci_dev *pci;    /* and an pci info */
928
929         /* Mixer vars */
930         /* fast alsa mixer */
931         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932         /* but input to much, so not used */
933         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934         /* full mixer accessible over mixer ioctl or hwdep-device */
935         struct hdspm_mixer *mixer;
936
937         struct hdspm_tco *tco;  /* NULL if no TCO detected */
938
939         char **texts_autosync;
940         int texts_autosync_items;
941
942         cycles_t last_interrupt;
943
944         unsigned int serial;
945
946         struct hdspm_peak_rms peak_rms;
947 };
948
949
950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
951         {
952          .vendor = PCI_VENDOR_ID_XILINX,
953          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954          .subvendor = PCI_ANY_ID,
955          .subdevice = PCI_ANY_ID,
956          .class = 0,
957          .class_mask = 0,
958          .driver_data = 0},
959         {0,}
960 };
961
962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
963
964 /* prototypes */
965 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966                                                    struct hdspm * hdspm);
967 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968                                           struct hdspm * hdspm);
969
970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972 static int hdspm_autosync_ref(struct hdspm *hdspm);
973 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974 static int hdspm_system_clock_mode(struct hdspm *hdspm);
975 static void hdspm_set_sgbuf(struct hdspm *hdspm,
976                             struct snd_pcm_substream *substream,
977                              unsigned int reg, int channels);
978
979 static inline int HDSPM_bit2freq(int n)
980 {
981         static const int bit2freq_tab[] = {
982                 0, 32000, 44100, 48000, 64000, 88200,
983                 96000, 128000, 176400, 192000 };
984         if (n < 1 || n > 9)
985                 return 0;
986         return bit2freq_tab[n];
987 }
988
989 /* Write/read to/from HDSPM with Adresses in Bytes
990    not words but only 32Bit writes are allowed */
991
992 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
993                                unsigned int val)
994 {
995         writel(val, hdspm->iobase + reg);
996 }
997
998 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
999 {
1000         return readl(hdspm->iobase + reg);
1001 }
1002
1003 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1004    mixer is write only on hardware so we have to cache him for read
1005    each fader is a u32, but uses only the first 16 bit */
1006
1007 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1008                                      unsigned int in)
1009 {
1010         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1011                 return 0;
1012
1013         return hdspm->mixer->ch[chan].in[in];
1014 }
1015
1016 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1017                                      unsigned int pb)
1018 {
1019         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1020                 return 0;
1021         return hdspm->mixer->ch[chan].pb[pb];
1022 }
1023
1024 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1025                                       unsigned int in, unsigned short data)
1026 {
1027         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1028                 return -1;
1029
1030         hdspm_write(hdspm,
1031                     HDSPM_MADI_mixerBase +
1032                     ((in + 128 * chan) * sizeof(u32)),
1033                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1034         return 0;
1035 }
1036
1037 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1038                                       unsigned int pb, unsigned short data)
1039 {
1040         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1041                 return -1;
1042
1043         hdspm_write(hdspm,
1044                     HDSPM_MADI_mixerBase +
1045                     ((64 + pb + 128 * chan) * sizeof(u32)),
1046                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1047         return 0;
1048 }
1049
1050
1051 /* enable DMA for specific channels, now available for DSP-MADI */
1052 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1053 {
1054         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1055 }
1056
1057 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1058 {
1059         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1060 }
1061
1062 /* check if same process is writing and reading */
1063 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1064 {
1065         unsigned long flags;
1066         int ret = 1;
1067
1068         spin_lock_irqsave(&hdspm->lock, flags);
1069         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1070             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1071                 ret = 0;
1072         }
1073         spin_unlock_irqrestore(&hdspm->lock, flags);
1074         return ret;
1075 }
1076
1077 /* check for external sample rate */
1078 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1079 {
1080         unsigned int status, status2, timecode;
1081         int syncref, rate = 0, rate_bits;
1082
1083         switch (hdspm->io_type) {
1084         case AES32:
1085                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1086                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1087                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1088
1089                 syncref = hdspm_autosync_ref(hdspm);
1090
1091                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1092                                 status & HDSPM_AES32_wcLock)
1093                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1094
1095                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1096                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1097                                 status2 & (HDSPM_LockAES >>
1098                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1099                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1100                 return 0;
1101                 break;
1102
1103         case MADIface:
1104                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1105
1106                 if (!(status & HDSPM_madiLock)) {
1107                         rate = 0;  /* no lock */
1108                 } else {
1109                         switch (status & (HDSPM_status1_freqMask)) {
1110                         case HDSPM_status1_F_0*1:
1111                                 rate = 32000; break;
1112                         case HDSPM_status1_F_0*2:
1113                                 rate = 44100; break;
1114                         case HDSPM_status1_F_0*3:
1115                                 rate = 48000; break;
1116                         case HDSPM_status1_F_0*4:
1117                                 rate = 64000; break;
1118                         case HDSPM_status1_F_0*5:
1119                                 rate = 88200; break;
1120                         case HDSPM_status1_F_0*6:
1121                                 rate = 96000; break;
1122                         case HDSPM_status1_F_0*7:
1123                                 rate = 128000; break;
1124                         case HDSPM_status1_F_0*8:
1125                                 rate = 176400; break;
1126                         case HDSPM_status1_F_0*9:
1127                                 rate = 192000; break;
1128                         default:
1129                                 rate = 0; break;
1130                         }
1131                 }
1132
1133                 break;
1134
1135         case MADI:
1136         case AIO:
1137         case RayDAT:
1138                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1139                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1140                 rate = 0;
1141
1142                 /* if wordclock has synced freq and wordclock is valid */
1143                 if ((status2 & HDSPM_wcLock) != 0 &&
1144                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1145
1146                         rate_bits = status2 & HDSPM_wcFreqMask;
1147
1148
1149                         switch (rate_bits) {
1150                         case HDSPM_wcFreq32:
1151                                 rate = 32000;
1152                                 break;
1153                         case HDSPM_wcFreq44_1:
1154                                 rate = 44100;
1155                                 break;
1156                         case HDSPM_wcFreq48:
1157                                 rate = 48000;
1158                                 break;
1159                         case HDSPM_wcFreq64:
1160                                 rate = 64000;
1161                                 break;
1162                         case HDSPM_wcFreq88_2:
1163                                 rate = 88200;
1164                                 break;
1165                         case HDSPM_wcFreq96:
1166                                 rate = 96000;
1167                                 break;
1168                         default:
1169                                 rate = 0;
1170                                 break;
1171                         }
1172                 }
1173
1174                 /* if rate detected and Syncref is Word than have it,
1175                  * word has priority to MADI
1176                  */
1177                 if (rate != 0 &&
1178                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1179                         return rate;
1180
1181                 /* maybe a madi input (which is taken if sel sync is madi) */
1182                 if (status & HDSPM_madiLock) {
1183                         rate_bits = status & HDSPM_madiFreqMask;
1184
1185                         switch (rate_bits) {
1186                         case HDSPM_madiFreq32:
1187                                 rate = 32000;
1188                                 break;
1189                         case HDSPM_madiFreq44_1:
1190                                 rate = 44100;
1191                                 break;
1192                         case HDSPM_madiFreq48:
1193                                 rate = 48000;
1194                                 break;
1195                         case HDSPM_madiFreq64:
1196                                 rate = 64000;
1197                                 break;
1198                         case HDSPM_madiFreq88_2:
1199                                 rate = 88200;
1200                                 break;
1201                         case HDSPM_madiFreq96:
1202                                 rate = 96000;
1203                                 break;
1204                         case HDSPM_madiFreq128:
1205                                 rate = 128000;
1206                                 break;
1207                         case HDSPM_madiFreq176_4:
1208                                 rate = 176400;
1209                                 break;
1210                         case HDSPM_madiFreq192:
1211                                 rate = 192000;
1212                                 break;
1213                         default:
1214                                 rate = 0;
1215                                 break;
1216                         }
1217
1218                         /* QS and DS rates normally can not be detected
1219                          * automatically by the card. Only exception is MADI
1220                          * in 96k frame mode.
1221                          *
1222                          * So if we read SS values (32 .. 48k), check for
1223                          * user-provided DS/QS bits in the control register
1224                          * and multiply the base frequency accordingly.
1225                          */
1226                         if (rate <= 48000) {
1227                                 if (hdspm->control_register & HDSPM_QuadSpeed)
1228                                         rate *= 4;
1229                                 else if (hdspm->control_register &
1230                                                 HDSPM_DoubleSpeed)
1231                                         rate *= 2;
1232                         }
1233                 }
1234                 break;
1235         }
1236
1237         return rate;
1238 }
1239
1240 /* return latency in samples per period */
1241 static int hdspm_get_latency(struct hdspm *hdspm)
1242 {
1243         int n;
1244
1245         n = hdspm_decode_latency(hdspm->control_register);
1246
1247         /* Special case for new RME cards with 32 samples period size.
1248          * The three latency bits in the control register
1249          * (HDSP_LatencyMask) encode latency values of 64 samples as
1250          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1251          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1252          * it corresponds to 32 samples.
1253          */
1254         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1255                 n = -1;
1256
1257         return 1 << (n + 6);
1258 }
1259
1260 /* Latency function */
1261 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1262 {
1263         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1264 }
1265
1266
1267 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1268 {
1269         int position;
1270
1271         position = hdspm_read(hdspm, HDSPM_statusRegister);
1272
1273         switch (hdspm->io_type) {
1274         case RayDAT:
1275         case AIO:
1276                 position &= HDSPM_BufferPositionMask;
1277                 position /= 4; /* Bytes per sample */
1278                 break;
1279         default:
1280                 position = (position & HDSPM_BufferID) ?
1281                         (hdspm->period_bytes / 4) : 0;
1282         }
1283
1284         return position;
1285 }
1286
1287
1288 static inline void hdspm_start_audio(struct hdspm * s)
1289 {
1290         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1291         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1292 }
1293
1294 static inline void hdspm_stop_audio(struct hdspm * s)
1295 {
1296         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1297         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1298 }
1299
1300 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1301 static void hdspm_silence_playback(struct hdspm *hdspm)
1302 {
1303         int i;
1304         int n = hdspm->period_bytes;
1305         void *buf = hdspm->playback_buffer;
1306
1307         if (buf == NULL)
1308                 return;
1309
1310         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1311                 memset(buf, 0, n);
1312                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1313         }
1314 }
1315
1316 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1317 {
1318         int n;
1319
1320         spin_lock_irq(&s->lock);
1321
1322         if (32 == frames) {
1323                 /* Special case for new RME cards like RayDAT/AIO which
1324                  * support period sizes of 32 samples. Since latency is
1325                  * encoded in the three bits of HDSP_LatencyMask, we can only
1326                  * have values from 0 .. 7. While 0 still means 64 samples and
1327                  * 6 represents 4096 samples on all cards, 7 represents 8192
1328                  * on older cards and 32 samples on new cards.
1329                  *
1330                  * In other words, period size in samples is calculated by
1331                  * 2^(n+6) with n ranging from 0 .. 7.
1332                  */
1333                 n = 7;
1334         } else {
1335                 frames >>= 7;
1336                 n = 0;
1337                 while (frames) {
1338                         n++;
1339                         frames >>= 1;
1340                 }
1341         }
1342
1343         s->control_register &= ~HDSPM_LatencyMask;
1344         s->control_register |= hdspm_encode_latency(n);
1345
1346         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1347
1348         hdspm_compute_period_size(s);
1349
1350         spin_unlock_irq(&s->lock);
1351
1352         return 0;
1353 }
1354
1355 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1356 {
1357         u64 freq_const;
1358
1359         if (period == 0)
1360                 return 0;
1361
1362         switch (hdspm->io_type) {
1363         case MADI:
1364         case AES32:
1365                 freq_const = 110069313433624ULL;
1366                 break;
1367         case RayDAT:
1368         case AIO:
1369                 freq_const = 104857600000000ULL;
1370                 break;
1371         case MADIface:
1372                 freq_const = 131072000000000ULL;
1373                 break;
1374         default:
1375                 snd_BUG();
1376                 return 0;
1377         }
1378
1379         return div_u64(freq_const, period);
1380 }
1381
1382
1383 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1384 {
1385         u64 n;
1386
1387         if (rate >= 112000)
1388                 rate /= 4;
1389         else if (rate >= 56000)
1390                 rate /= 2;
1391
1392         switch (hdspm->io_type) {
1393         case MADIface:
1394                 n = 131072000000000ULL;  /* 125 MHz */
1395                 break;
1396         case MADI:
1397         case AES32:
1398                 n = 110069313433624ULL;  /* 105 MHz */
1399                 break;
1400         case RayDAT:
1401         case AIO:
1402                 n = 104857600000000ULL;  /* 100 MHz */
1403                 break;
1404         default:
1405                 snd_BUG();
1406                 return;
1407         }
1408
1409         n = div_u64(n, rate);
1410         /* n should be less than 2^32 for being written to FREQ register */
1411         snd_BUG_ON(n >> 32);
1412         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1413 }
1414
1415 /* dummy set rate lets see what happens */
1416 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1417 {
1418         int current_rate;
1419         int rate_bits;
1420         int not_set = 0;
1421         int current_speed, target_speed;
1422
1423         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1424            it (e.g. during module initialization).
1425          */
1426
1427         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1428
1429                 /* SLAVE --- */
1430                 if (called_internally) {
1431
1432                         /* request from ctl or card initialization
1433                            just make a warning an remember setting
1434                            for future master mode switching */
1435
1436                         snd_printk(KERN_WARNING "HDSPM: "
1437                                    "Warning: device is not running "
1438                                    "as a clock master.\n");
1439                         not_set = 1;
1440                 } else {
1441
1442                         /* hw_param request while in AutoSync mode */
1443                         int external_freq =
1444                             hdspm_external_sample_rate(hdspm);
1445
1446                         if (hdspm_autosync_ref(hdspm) ==
1447                             HDSPM_AUTOSYNC_FROM_NONE) {
1448
1449                                 snd_printk(KERN_WARNING "HDSPM: "
1450                                            "Detected no Externel Sync \n");
1451                                 not_set = 1;
1452
1453                         } else if (rate != external_freq) {
1454
1455                                 snd_printk(KERN_WARNING "HDSPM: "
1456                                            "Warning: No AutoSync source for "
1457                                            "requested rate\n");
1458                                 not_set = 1;
1459                         }
1460                 }
1461         }
1462
1463         current_rate = hdspm->system_sample_rate;
1464
1465         /* Changing between Singe, Double and Quad speed is not
1466            allowed if any substreams are open. This is because such a change
1467            causes a shift in the location of the DMA buffers and a reduction
1468            in the number of available buffers.
1469
1470            Note that a similar but essentially insoluble problem exists for
1471            externally-driven rate changes. All we can do is to flag rate
1472            changes in the read/write routines.
1473          */
1474
1475         if (current_rate <= 48000)
1476                 current_speed = HDSPM_SPEED_SINGLE;
1477         else if (current_rate <= 96000)
1478                 current_speed = HDSPM_SPEED_DOUBLE;
1479         else
1480                 current_speed = HDSPM_SPEED_QUAD;
1481
1482         if (rate <= 48000)
1483                 target_speed = HDSPM_SPEED_SINGLE;
1484         else if (rate <= 96000)
1485                 target_speed = HDSPM_SPEED_DOUBLE;
1486         else
1487                 target_speed = HDSPM_SPEED_QUAD;
1488
1489         switch (rate) {
1490         case 32000:
1491                 rate_bits = HDSPM_Frequency32KHz;
1492                 break;
1493         case 44100:
1494                 rate_bits = HDSPM_Frequency44_1KHz;
1495                 break;
1496         case 48000:
1497                 rate_bits = HDSPM_Frequency48KHz;
1498                 break;
1499         case 64000:
1500                 rate_bits = HDSPM_Frequency64KHz;
1501                 break;
1502         case 88200:
1503                 rate_bits = HDSPM_Frequency88_2KHz;
1504                 break;
1505         case 96000:
1506                 rate_bits = HDSPM_Frequency96KHz;
1507                 break;
1508         case 128000:
1509                 rate_bits = HDSPM_Frequency128KHz;
1510                 break;
1511         case 176400:
1512                 rate_bits = HDSPM_Frequency176_4KHz;
1513                 break;
1514         case 192000:
1515                 rate_bits = HDSPM_Frequency192KHz;
1516                 break;
1517         default:
1518                 return -EINVAL;
1519         }
1520
1521         if (current_speed != target_speed
1522             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1523                 snd_printk
1524                     (KERN_ERR "HDSPM: "
1525                      "cannot change from %s speed to %s speed mode "
1526                      "(capture PID = %d, playback PID = %d)\n",
1527                      hdspm_speed_names[current_speed],
1528                      hdspm_speed_names[target_speed],
1529                      hdspm->capture_pid, hdspm->playback_pid);
1530                 return -EBUSY;
1531         }
1532
1533         hdspm->control_register &= ~HDSPM_FrequencyMask;
1534         hdspm->control_register |= rate_bits;
1535         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1536
1537         /* For AES32, need to set DDS value in FREQ register
1538            For MADI, also apparently */
1539         hdspm_set_dds_value(hdspm, rate);
1540
1541         if (AES32 == hdspm->io_type && rate != current_rate)
1542                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1543
1544         hdspm->system_sample_rate = rate;
1545
1546         if (rate <= 48000) {
1547                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1548                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1549                 hdspm->max_channels_in = hdspm->ss_in_channels;
1550                 hdspm->max_channels_out = hdspm->ss_out_channels;
1551                 hdspm->port_names_in = hdspm->port_names_in_ss;
1552                 hdspm->port_names_out = hdspm->port_names_out_ss;
1553         } else if (rate <= 96000) {
1554                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1555                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1556                 hdspm->max_channels_in = hdspm->ds_in_channels;
1557                 hdspm->max_channels_out = hdspm->ds_out_channels;
1558                 hdspm->port_names_in = hdspm->port_names_in_ds;
1559                 hdspm->port_names_out = hdspm->port_names_out_ds;
1560         } else {
1561                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1562                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1563                 hdspm->max_channels_in = hdspm->qs_in_channels;
1564                 hdspm->max_channels_out = hdspm->qs_out_channels;
1565                 hdspm->port_names_in = hdspm->port_names_in_qs;
1566                 hdspm->port_names_out = hdspm->port_names_out_qs;
1567         }
1568
1569         if (not_set != 0)
1570                 return -1;
1571
1572         return 0;
1573 }
1574
1575 /* mainly for init to 0 on load */
1576 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1577 {
1578         int i, j;
1579         unsigned int gain;
1580
1581         if (sgain > UNITY_GAIN)
1582                 gain = UNITY_GAIN;
1583         else if (sgain < 0)
1584                 gain = 0;
1585         else
1586                 gain = sgain;
1587
1588         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1589                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1590                         hdspm_write_in_gain(hdspm, i, j, gain);
1591                         hdspm_write_pb_gain(hdspm, i, j, gain);
1592                 }
1593 }
1594
1595 /*----------------------------------------------------------------------------
1596    MIDI
1597   ----------------------------------------------------------------------------*/
1598
1599 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1600                                                       int id)
1601 {
1602         /* the hardware already does the relevant bit-mask with 0xff */
1603         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1604 }
1605
1606 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1607                                               int val)
1608 {
1609         /* the hardware already does the relevant bit-mask with 0xff */
1610         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1611 }
1612
1613 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1614 {
1615         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1616 }
1617
1618 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1619 {
1620         int fifo_bytes_used;
1621
1622         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1623
1624         if (fifo_bytes_used < 128)
1625                 return  128 - fifo_bytes_used;
1626         else
1627                 return 0;
1628 }
1629
1630 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1631 {
1632         while (snd_hdspm_midi_input_available (hdspm, id))
1633                 snd_hdspm_midi_read_byte (hdspm, id);
1634 }
1635
1636 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1637 {
1638         unsigned long flags;
1639         int n_pending;
1640         int to_write;
1641         int i;
1642         unsigned char buf[128];
1643
1644         /* Output is not interrupt driven */
1645
1646         spin_lock_irqsave (&hmidi->lock, flags);
1647         if (hmidi->output &&
1648             !snd_rawmidi_transmit_empty (hmidi->output)) {
1649                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1650                                                             hmidi->id);
1651                 if (n_pending > 0) {
1652                         if (n_pending > (int)sizeof (buf))
1653                                 n_pending = sizeof (buf);
1654
1655                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1656                                                          n_pending);
1657                         if (to_write > 0) {
1658                                 for (i = 0; i < to_write; ++i)
1659                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1660                                                                    hmidi->id,
1661                                                                    buf[i]);
1662                         }
1663                 }
1664         }
1665         spin_unlock_irqrestore (&hmidi->lock, flags);
1666         return 0;
1667 }
1668
1669 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1670 {
1671         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1672                                  * input FIFO size
1673                                  */
1674         unsigned long flags;
1675         int n_pending;
1676         int i;
1677
1678         spin_lock_irqsave (&hmidi->lock, flags);
1679         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1680         if (n_pending > 0) {
1681                 if (hmidi->input) {
1682                         if (n_pending > (int)sizeof (buf))
1683                                 n_pending = sizeof (buf);
1684                         for (i = 0; i < n_pending; ++i)
1685                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1686                                                                    hmidi->id);
1687                         if (n_pending)
1688                                 snd_rawmidi_receive (hmidi->input, buf,
1689                                                      n_pending);
1690                 } else {
1691                         /* flush the MIDI input FIFO */
1692                         while (n_pending--)
1693                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1694                                                           hmidi->id);
1695                 }
1696         }
1697         hmidi->pending = 0;
1698         spin_unlock_irqrestore(&hmidi->lock, flags);
1699
1700         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1701         hmidi->hdspm->control_register |= hmidi->ie;
1702         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1703                     hmidi->hdspm->control_register);
1704         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1705
1706         return snd_hdspm_midi_output_write (hmidi);
1707 }
1708
1709 static void
1710 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1711 {
1712         struct hdspm *hdspm;
1713         struct hdspm_midi *hmidi;
1714         unsigned long flags;
1715
1716         hmidi = substream->rmidi->private_data;
1717         hdspm = hmidi->hdspm;
1718
1719         spin_lock_irqsave (&hdspm->lock, flags);
1720         if (up) {
1721                 if (!(hdspm->control_register & hmidi->ie)) {
1722                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1723                         hdspm->control_register |= hmidi->ie;
1724                 }
1725         } else {
1726                 hdspm->control_register &= ~hmidi->ie;
1727         }
1728
1729         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1730         spin_unlock_irqrestore (&hdspm->lock, flags);
1731 }
1732
1733 static void snd_hdspm_midi_output_timer(unsigned long data)
1734 {
1735         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1736         unsigned long flags;
1737
1738         snd_hdspm_midi_output_write(hmidi);
1739         spin_lock_irqsave (&hmidi->lock, flags);
1740
1741         /* this does not bump hmidi->istimer, because the
1742            kernel automatically removed the timer when it
1743            expired, and we are now adding it back, thus
1744            leaving istimer wherever it was set before.
1745         */
1746
1747         if (hmidi->istimer) {
1748                 hmidi->timer.expires = 1 + jiffies;
1749                 add_timer(&hmidi->timer);
1750         }
1751
1752         spin_unlock_irqrestore (&hmidi->lock, flags);
1753 }
1754
1755 static void
1756 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1757 {
1758         struct hdspm_midi *hmidi;
1759         unsigned long flags;
1760
1761         hmidi = substream->rmidi->private_data;
1762         spin_lock_irqsave (&hmidi->lock, flags);
1763         if (up) {
1764                 if (!hmidi->istimer) {
1765                         init_timer(&hmidi->timer);
1766                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1767                         hmidi->timer.data = (unsigned long) hmidi;
1768                         hmidi->timer.expires = 1 + jiffies;
1769                         add_timer(&hmidi->timer);
1770                         hmidi->istimer++;
1771                 }
1772         } else {
1773                 if (hmidi->istimer && --hmidi->istimer <= 0)
1774                         del_timer (&hmidi->timer);
1775         }
1776         spin_unlock_irqrestore (&hmidi->lock, flags);
1777         if (up)
1778                 snd_hdspm_midi_output_write(hmidi);
1779 }
1780
1781 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1782 {
1783         struct hdspm_midi *hmidi;
1784
1785         hmidi = substream->rmidi->private_data;
1786         spin_lock_irq (&hmidi->lock);
1787         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1788         hmidi->input = substream;
1789         spin_unlock_irq (&hmidi->lock);
1790
1791         return 0;
1792 }
1793
1794 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1795 {
1796         struct hdspm_midi *hmidi;
1797
1798         hmidi = substream->rmidi->private_data;
1799         spin_lock_irq (&hmidi->lock);
1800         hmidi->output = substream;
1801         spin_unlock_irq (&hmidi->lock);
1802
1803         return 0;
1804 }
1805
1806 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1807 {
1808         struct hdspm_midi *hmidi;
1809
1810         snd_hdspm_midi_input_trigger (substream, 0);
1811
1812         hmidi = substream->rmidi->private_data;
1813         spin_lock_irq (&hmidi->lock);
1814         hmidi->input = NULL;
1815         spin_unlock_irq (&hmidi->lock);
1816
1817         return 0;
1818 }
1819
1820 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1821 {
1822         struct hdspm_midi *hmidi;
1823
1824         snd_hdspm_midi_output_trigger (substream, 0);
1825
1826         hmidi = substream->rmidi->private_data;
1827         spin_lock_irq (&hmidi->lock);
1828         hmidi->output = NULL;
1829         spin_unlock_irq (&hmidi->lock);
1830
1831         return 0;
1832 }
1833
1834 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1835 {
1836         .open =         snd_hdspm_midi_output_open,
1837         .close =        snd_hdspm_midi_output_close,
1838         .trigger =      snd_hdspm_midi_output_trigger,
1839 };
1840
1841 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1842 {
1843         .open =         snd_hdspm_midi_input_open,
1844         .close =        snd_hdspm_midi_input_close,
1845         .trigger =      snd_hdspm_midi_input_trigger,
1846 };
1847
1848 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1849                                             struct hdspm *hdspm, int id)
1850 {
1851         int err;
1852         char buf[32];
1853
1854         hdspm->midi[id].id = id;
1855         hdspm->midi[id].hdspm = hdspm;
1856         spin_lock_init (&hdspm->midi[id].lock);
1857
1858         if (0 == id) {
1859                 if (MADIface == hdspm->io_type) {
1860                         /* MIDI-over-MADI on HDSPe MADIface */
1861                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1862                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1863                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1864                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1865                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1866                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1867                 } else {
1868                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1869                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1870                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1871                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1872                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1873                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1874                 }
1875         } else if (1 == id) {
1876                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1877                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1878                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1879                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1880                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1881                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1882         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1883                 /* MIDI-over-MADI on HDSPe MADI */
1884                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1885                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1886                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1887                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1888                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1889                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1890         } else if (2 == id) {
1891                 /* TCO MTC, read only */
1892                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1893                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1894                 hdspm->midi[2].dataOut = -1;
1895                 hdspm->midi[2].statusOut = -1;
1896                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1897                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1898         } else if (3 == id) {
1899                 /* TCO MTC on HDSPe MADI */
1900                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1901                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1902                 hdspm->midi[3].dataOut = -1;
1903                 hdspm->midi[3].statusOut = -1;
1904                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1905                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1906         }
1907
1908         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1909                                         (MADIface == hdspm->io_type)))) {
1910                 if ((id == 0) && (MADIface == hdspm->io_type)) {
1911                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1912                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1913                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
1914                 } else {
1915                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1916                 }
1917                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1918                                 &hdspm->midi[id].rmidi);
1919                 if (err < 0)
1920                         return err;
1921
1922                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1923                                 card->id, id+1);
1924                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1925
1926                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1927                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
1928                                 &snd_hdspm_midi_output);
1929                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1930                                 SNDRV_RAWMIDI_STREAM_INPUT,
1931                                 &snd_hdspm_midi_input);
1932
1933                 hdspm->midi[id].rmidi->info_flags |=
1934                         SNDRV_RAWMIDI_INFO_OUTPUT |
1935                         SNDRV_RAWMIDI_INFO_INPUT |
1936                         SNDRV_RAWMIDI_INFO_DUPLEX;
1937         } else {
1938                 /* TCO MTC, read only */
1939                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1940                 err = snd_rawmidi_new(card, buf, id, 1, 1,
1941                                 &hdspm->midi[id].rmidi);
1942                 if (err < 0)
1943                         return err;
1944
1945                 sprintf(hdspm->midi[id].rmidi->name,
1946                                 "%s MTC %d", card->id, id+1);
1947                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1948
1949                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1950                                 SNDRV_RAWMIDI_STREAM_INPUT,
1951                                 &snd_hdspm_midi_input);
1952
1953                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1954         }
1955
1956         return 0;
1957 }
1958
1959
1960 static void hdspm_midi_tasklet(unsigned long arg)
1961 {
1962         struct hdspm *hdspm = (struct hdspm *)arg;
1963         int i = 0;
1964
1965         while (i < hdspm->midiPorts) {
1966                 if (hdspm->midi[i].pending)
1967                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
1968
1969                 i++;
1970         }
1971 }
1972
1973
1974 /*-----------------------------------------------------------------------------
1975   Status Interface
1976   ----------------------------------------------------------------------------*/
1977
1978 /* get the system sample rate which is set */
1979
1980
1981 /**
1982  * Calculate the real sample rate from the
1983  * current DDS value.
1984  **/
1985 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1986 {
1987         unsigned int period, rate;
1988
1989         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1990         rate = hdspm_calc_dds_value(hdspm, period);
1991
1992         if (rate > 207000) {
1993                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
1994                 if (0 == hdspm_system_clock_mode(hdspm)) {
1995                         /* master mode, return internal sample rate */
1996                         rate = hdspm->system_sample_rate;
1997                 } else {
1998                         /* slave mode, return external sample rate */
1999                         rate = hdspm_external_sample_rate(hdspm);
2000                 }
2001         }
2002
2003         return rate;
2004 }
2005
2006
2007 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2008 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2009         .name = xname, \
2010         .index = xindex, \
2011         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2012                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2013         .info = snd_hdspm_info_system_sample_rate, \
2014         .put = snd_hdspm_put_system_sample_rate, \
2015         .get = snd_hdspm_get_system_sample_rate \
2016 }
2017
2018 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2019                                              struct snd_ctl_elem_info *uinfo)
2020 {
2021         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2022         uinfo->count = 1;
2023         uinfo->value.integer.min = 27000;
2024         uinfo->value.integer.max = 207000;
2025         uinfo->value.integer.step = 1;
2026         return 0;
2027 }
2028
2029
2030 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2031                                             struct snd_ctl_elem_value *
2032                                             ucontrol)
2033 {
2034         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2035
2036         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2037         return 0;
2038 }
2039
2040 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2041                                             struct snd_ctl_elem_value *
2042                                             ucontrol)
2043 {
2044         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2045
2046         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2047         return 0;
2048 }
2049
2050
2051 /**
2052  * Returns the WordClock sample rate class for the given card.
2053  **/
2054 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2055 {
2056         int status;
2057
2058         switch (hdspm->io_type) {
2059         case RayDAT:
2060         case AIO:
2061                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2062                 return (status >> 16) & 0xF;
2063                 break;
2064         default:
2065                 break;
2066         }
2067
2068
2069         return 0;
2070 }
2071
2072
2073 /**
2074  * Returns the TCO sample rate class for the given card.
2075  **/
2076 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2077 {
2078         int status;
2079
2080         if (hdspm->tco) {
2081                 switch (hdspm->io_type) {
2082                 case RayDAT:
2083                 case AIO:
2084                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2085                         return (status >> 20) & 0xF;
2086                         break;
2087                 default:
2088                         break;
2089                 }
2090         }
2091
2092         return 0;
2093 }
2094
2095
2096 /**
2097  * Returns the SYNC_IN sample rate class for the given card.
2098  **/
2099 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2100 {
2101         int status;
2102
2103         if (hdspm->tco) {
2104                 switch (hdspm->io_type) {
2105                 case RayDAT:
2106                 case AIO:
2107                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2108                         return (status >> 12) & 0xF;
2109                         break;
2110                 default:
2111                         break;
2112                 }
2113         }
2114
2115         return 0;
2116 }
2117
2118
2119 /**
2120  * Returns the sample rate class for input source <idx> for
2121  * 'new style' cards like the AIO and RayDAT.
2122  **/
2123 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2124 {
2125         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2126
2127         return (status >> (idx*4)) & 0xF;
2128 }
2129
2130
2131
2132 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2133 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2134         .name = xname, \
2135         .private_value = xindex, \
2136         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2137         .info = snd_hdspm_info_autosync_sample_rate, \
2138         .get = snd_hdspm_get_autosync_sample_rate \
2139 }
2140
2141
2142 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2143                                                struct snd_ctl_elem_info *uinfo)
2144 {
2145         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2146         uinfo->count = 1;
2147         uinfo->value.enumerated.items = 10;
2148
2149         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2150                 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2151         strcpy(uinfo->value.enumerated.name,
2152                         texts_freq[uinfo->value.enumerated.item]);
2153         return 0;
2154 }
2155
2156
2157 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2158                                               struct snd_ctl_elem_value *
2159                                               ucontrol)
2160 {
2161         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2162
2163         switch (hdspm->io_type) {
2164         case RayDAT:
2165                 switch (kcontrol->private_value) {
2166                 case 0:
2167                         ucontrol->value.enumerated.item[0] =
2168                                 hdspm_get_wc_sample_rate(hdspm);
2169                         break;
2170                 case 7:
2171                         ucontrol->value.enumerated.item[0] =
2172                                 hdspm_get_tco_sample_rate(hdspm);
2173                         break;
2174                 case 8:
2175                         ucontrol->value.enumerated.item[0] =
2176                                 hdspm_get_sync_in_sample_rate(hdspm);
2177                         break;
2178                 default:
2179                         ucontrol->value.enumerated.item[0] =
2180                                 hdspm_get_s1_sample_rate(hdspm,
2181                                                 kcontrol->private_value-1);
2182                 }
2183                 break;
2184
2185         case AIO:
2186                 switch (kcontrol->private_value) {
2187                 case 0: /* WC */
2188                         ucontrol->value.enumerated.item[0] =
2189                                 hdspm_get_wc_sample_rate(hdspm);
2190                         break;
2191                 case 4: /* TCO */
2192                         ucontrol->value.enumerated.item[0] =
2193                                 hdspm_get_tco_sample_rate(hdspm);
2194                         break;
2195                 case 5: /* SYNC_IN */
2196                         ucontrol->value.enumerated.item[0] =
2197                                 hdspm_get_sync_in_sample_rate(hdspm);
2198                         break;
2199                 default:
2200                         ucontrol->value.enumerated.item[0] =
2201                                 hdspm_get_s1_sample_rate(hdspm,
2202                                                 ucontrol->id.index-1);
2203                 }
2204                 break;
2205
2206         case AES32:
2207
2208                 switch (kcontrol->private_value) {
2209                 case 0: /* WC */
2210                         ucontrol->value.enumerated.item[0] =
2211                                 hdspm_get_wc_sample_rate(hdspm);
2212                         break;
2213                 case 9: /* TCO */
2214                         ucontrol->value.enumerated.item[0] =
2215                                 hdspm_get_tco_sample_rate(hdspm);
2216                         break;
2217                 case 10: /* SYNC_IN */
2218                         ucontrol->value.enumerated.item[0] =
2219                                 hdspm_get_sync_in_sample_rate(hdspm);
2220                         break;
2221                 default: /* AES1 to AES8 */
2222                         ucontrol->value.enumerated.item[0] =
2223                                 hdspm_get_s1_sample_rate(hdspm,
2224                                                 kcontrol->private_value-1);
2225                         break;
2226                 }
2227                 break;
2228
2229         case MADI:
2230         case MADIface:
2231                 {
2232                         int rate = hdspm_external_sample_rate(hdspm);
2233                         int i, selected_rate = 0;
2234                         for (i = 1; i < 10; i++)
2235                                 if (HDSPM_bit2freq(i) == rate) {
2236                                         selected_rate = i;
2237                                         break;
2238                                 }
2239                         ucontrol->value.enumerated.item[0] = selected_rate;
2240                 }
2241                 break;
2242
2243         default:
2244                 break;
2245         }
2246
2247         return 0;
2248 }
2249
2250
2251 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2252 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2253         .name = xname, \
2254         .index = xindex, \
2255         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2256                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2257         .info = snd_hdspm_info_system_clock_mode, \
2258         .get = snd_hdspm_get_system_clock_mode, \
2259         .put = snd_hdspm_put_system_clock_mode, \
2260 }
2261
2262
2263 /**
2264  * Returns the system clock mode for the given card.
2265  * @returns 0 - master, 1 - slave
2266  **/
2267 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2268 {
2269         switch (hdspm->io_type) {
2270         case AIO:
2271         case RayDAT:
2272                 if (hdspm->settings_register & HDSPM_c0Master)
2273                         return 0;
2274                 break;
2275
2276         default:
2277                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2278                         return 0;
2279         }
2280
2281         return 1;
2282 }
2283
2284
2285 /**
2286  * Sets the system clock mode.
2287  * @param mode 0 - master, 1 - slave
2288  **/
2289 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2290 {
2291         switch (hdspm->io_type) {
2292         case AIO:
2293         case RayDAT:
2294                 if (0 == mode)
2295                         hdspm->settings_register |= HDSPM_c0Master;
2296                 else
2297                         hdspm->settings_register &= ~HDSPM_c0Master;
2298
2299                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2300                 break;
2301
2302         default:
2303                 if (0 == mode)
2304                         hdspm->control_register |= HDSPM_ClockModeMaster;
2305                 else
2306                         hdspm->control_register &= ~HDSPM_ClockModeMaster;
2307
2308                 hdspm_write(hdspm, HDSPM_controlRegister,
2309                                 hdspm->control_register);
2310         }
2311 }
2312
2313
2314 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2315                                             struct snd_ctl_elem_info *uinfo)
2316 {
2317         static char *texts[] = { "Master", "AutoSync" };
2318
2319         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2320         uinfo->count = 1;
2321         uinfo->value.enumerated.items = 2;
2322         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2323                 uinfo->value.enumerated.item =
2324                     uinfo->value.enumerated.items - 1;
2325         strcpy(uinfo->value.enumerated.name,
2326                texts[uinfo->value.enumerated.item]);
2327         return 0;
2328 }
2329
2330 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2331                                            struct snd_ctl_elem_value *ucontrol)
2332 {
2333         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2334
2335         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2336         return 0;
2337 }
2338
2339 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2340                                            struct snd_ctl_elem_value *ucontrol)
2341 {
2342         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2343         int val;
2344
2345         if (!snd_hdspm_use_is_exclusive(hdspm))
2346                 return -EBUSY;
2347
2348         val = ucontrol->value.enumerated.item[0];
2349         if (val < 0)
2350                 val = 0;
2351         else if (val > 1)
2352                 val = 1;
2353
2354         hdspm_set_system_clock_mode(hdspm, val);
2355
2356         return 0;
2357 }
2358
2359
2360 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2361 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2362         .name = xname, \
2363         .index = xindex, \
2364         .info = snd_hdspm_info_clock_source, \
2365         .get = snd_hdspm_get_clock_source, \
2366         .put = snd_hdspm_put_clock_source \
2367 }
2368
2369
2370 static int hdspm_clock_source(struct hdspm * hdspm)
2371 {
2372         switch (hdspm->system_sample_rate) {
2373         case 32000: return 0;
2374         case 44100: return 1;
2375         case 48000: return 2;
2376         case 64000: return 3;
2377         case 88200: return 4;
2378         case 96000: return 5;
2379         case 128000: return 6;
2380         case 176400: return 7;
2381         case 192000: return 8;
2382         }
2383
2384         return -1;
2385 }
2386
2387 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2388 {
2389         int rate;
2390         switch (mode) {
2391         case 0:
2392                 rate = 32000; break;
2393         case 1:
2394                 rate = 44100; break;
2395         case 2:
2396                 rate = 48000; break;
2397         case 3:
2398                 rate = 64000; break;
2399         case 4:
2400                 rate = 88200; break;
2401         case 5:
2402                 rate = 96000; break;
2403         case 6:
2404                 rate = 128000; break;
2405         case 7:
2406                 rate = 176400; break;
2407         case 8:
2408                 rate = 192000; break;
2409         default:
2410                 rate = 48000;
2411         }
2412         hdspm_set_rate(hdspm, rate, 1);
2413         return 0;
2414 }
2415
2416 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2417                                        struct snd_ctl_elem_info *uinfo)
2418 {
2419         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2420         uinfo->count = 1;
2421         uinfo->value.enumerated.items = 9;
2422
2423         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2424                 uinfo->value.enumerated.item =
2425                     uinfo->value.enumerated.items - 1;
2426
2427         strcpy(uinfo->value.enumerated.name,
2428                texts_freq[uinfo->value.enumerated.item+1]);
2429
2430         return 0;
2431 }
2432
2433 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2434                                       struct snd_ctl_elem_value *ucontrol)
2435 {
2436         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2437
2438         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2439         return 0;
2440 }
2441
2442 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2443                                       struct snd_ctl_elem_value *ucontrol)
2444 {
2445         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2446         int change;
2447         int val;
2448
2449         if (!snd_hdspm_use_is_exclusive(hdspm))
2450                 return -EBUSY;
2451         val = ucontrol->value.enumerated.item[0];
2452         if (val < 0)
2453                 val = 0;
2454         if (val > 9)
2455                 val = 9;
2456         spin_lock_irq(&hdspm->lock);
2457         if (val != hdspm_clock_source(hdspm))
2458                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2459         else
2460                 change = 0;
2461         spin_unlock_irq(&hdspm->lock);
2462         return change;
2463 }
2464
2465
2466 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2467 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2468         .name = xname, \
2469         .index = xindex, \
2470         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2471                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2472         .info = snd_hdspm_info_pref_sync_ref, \
2473         .get = snd_hdspm_get_pref_sync_ref, \
2474         .put = snd_hdspm_put_pref_sync_ref \
2475 }
2476
2477
2478 /**
2479  * Returns the current preferred sync reference setting.
2480  * The semantics of the return value are depending on the
2481  * card, please see the comments for clarification.
2482  **/
2483 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2484 {
2485         switch (hdspm->io_type) {
2486         case AES32:
2487                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2488                 case 0: return 0;  /* WC */
2489                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2490                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2491                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2492                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2493                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2494                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2495                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2496                                                     return 7; /* AES 7 */
2497                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2498                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2499                 }
2500                 break;
2501
2502         case MADI:
2503         case MADIface:
2504                 if (hdspm->tco) {
2505                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2506                         case 0: return 0;  /* WC */
2507                         case HDSPM_SyncRef0: return 1;  /* MADI */
2508                         case HDSPM_SyncRef1: return 2;  /* TCO */
2509                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2510                                              return 3;  /* SYNC_IN */
2511                         }
2512                 } else {
2513                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2514                         case 0: return 0;  /* WC */
2515                         case HDSPM_SyncRef0: return 1;  /* MADI */
2516                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2517                                              return 2;  /* SYNC_IN */
2518                         }
2519                 }
2520                 break;
2521
2522         case RayDAT:
2523                 if (hdspm->tco) {
2524                         switch ((hdspm->settings_register &
2525                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2526                         case 0: return 0;  /* WC */
2527                         case 3: return 1;  /* ADAT 1 */
2528                         case 4: return 2;  /* ADAT 2 */
2529                         case 5: return 3;  /* ADAT 3 */
2530                         case 6: return 4;  /* ADAT 4 */
2531                         case 1: return 5;  /* AES */
2532                         case 2: return 6;  /* SPDIF */
2533                         case 9: return 7;  /* TCO */
2534                         case 10: return 8; /* SYNC_IN */
2535                         }
2536                 } else {
2537                         switch ((hdspm->settings_register &
2538                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2539                         case 0: return 0;  /* WC */
2540                         case 3: return 1;  /* ADAT 1 */
2541                         case 4: return 2;  /* ADAT 2 */
2542                         case 5: return 3;  /* ADAT 3 */
2543                         case 6: return 4;  /* ADAT 4 */
2544                         case 1: return 5;  /* AES */
2545                         case 2: return 6;  /* SPDIF */
2546                         case 10: return 7; /* SYNC_IN */
2547                         }
2548                 }
2549
2550                 break;
2551
2552         case AIO:
2553                 if (hdspm->tco) {
2554                         switch ((hdspm->settings_register &
2555                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2556                         case 0: return 0;  /* WC */
2557                         case 3: return 1;  /* ADAT */
2558                         case 1: return 2;  /* AES */
2559                         case 2: return 3;  /* SPDIF */
2560                         case 9: return 4;  /* TCO */
2561                         case 10: return 5; /* SYNC_IN */
2562                         }
2563                 } else {
2564                         switch ((hdspm->settings_register &
2565                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2566                         case 0: return 0;  /* WC */
2567                         case 3: return 1;  /* ADAT */
2568                         case 1: return 2;  /* AES */
2569                         case 2: return 3;  /* SPDIF */
2570                         case 10: return 4; /* SYNC_IN */
2571                         }
2572                 }
2573
2574                 break;
2575         }
2576
2577         return -1;
2578 }
2579
2580
2581 /**
2582  * Set the preferred sync reference to <pref>. The semantics
2583  * of <pref> are depending on the card type, see the comments
2584  * for clarification.
2585  **/
2586 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2587 {
2588         int p = 0;
2589
2590         switch (hdspm->io_type) {
2591         case AES32:
2592                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2593                 switch (pref) {
2594                 case 0: /* WC  */
2595                         break;
2596                 case 1: /* AES 1 */
2597                         hdspm->control_register |= HDSPM_SyncRef0;
2598                         break;
2599                 case 2: /* AES 2 */
2600                         hdspm->control_register |= HDSPM_SyncRef1;
2601                         break;
2602                 case 3: /* AES 3 */
2603                         hdspm->control_register |=
2604                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2605                         break;
2606                 case 4: /* AES 4 */
2607                         hdspm->control_register |= HDSPM_SyncRef2;
2608                         break;
2609                 case 5: /* AES 5 */
2610                         hdspm->control_register |=
2611                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2612                         break;
2613                 case 6: /* AES 6 */
2614                         hdspm->control_register |=
2615                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2616                         break;
2617                 case 7: /* AES 7 */
2618                         hdspm->control_register |=
2619                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2620                         break;
2621                 case 8: /* AES 8 */
2622                         hdspm->control_register |= HDSPM_SyncRef3;
2623                         break;
2624                 case 9: /* TCO */
2625                         hdspm->control_register |=
2626                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2627                         break;
2628                 default:
2629                         return -1;
2630                 }
2631
2632                 break;
2633
2634         case MADI:
2635         case MADIface:
2636                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2637                 if (hdspm->tco) {
2638                         switch (pref) {
2639                         case 0: /* WC */
2640                                 break;
2641                         case 1: /* MADI */
2642                                 hdspm->control_register |= HDSPM_SyncRef0;
2643                                 break;
2644                         case 2: /* TCO */
2645                                 hdspm->control_register |= HDSPM_SyncRef1;
2646                                 break;
2647                         case 3: /* SYNC_IN */
2648                                 hdspm->control_register |=
2649                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2650                                 break;
2651                         default:
2652                                 return -1;
2653                         }
2654                 } else {
2655                         switch (pref) {
2656                         case 0: /* WC */
2657                                 break;
2658                         case 1: /* MADI */
2659                                 hdspm->control_register |= HDSPM_SyncRef0;
2660                                 break;
2661                         case 2: /* SYNC_IN */
2662                                 hdspm->control_register |=
2663                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2664                                 break;
2665                         default:
2666                                 return -1;
2667                         }
2668                 }
2669
2670                 break;
2671
2672         case RayDAT:
2673                 if (hdspm->tco) {
2674                         switch (pref) {
2675                         case 0: p = 0; break;  /* WC */
2676                         case 1: p = 3; break;  /* ADAT 1 */
2677                         case 2: p = 4; break;  /* ADAT 2 */
2678                         case 3: p = 5; break;  /* ADAT 3 */
2679                         case 4: p = 6; break;  /* ADAT 4 */
2680                         case 5: p = 1; break;  /* AES */
2681                         case 6: p = 2; break;  /* SPDIF */
2682                         case 7: p = 9; break;  /* TCO */
2683                         case 8: p = 10; break; /* SYNC_IN */
2684                         default: return -1;
2685                         }
2686                 } else {
2687                         switch (pref) {
2688                         case 0: p = 0; break;  /* WC */
2689                         case 1: p = 3; break;  /* ADAT 1 */
2690                         case 2: p = 4; break;  /* ADAT 2 */
2691                         case 3: p = 5; break;  /* ADAT 3 */
2692                         case 4: p = 6; break;  /* ADAT 4 */
2693                         case 5: p = 1; break;  /* AES */
2694                         case 6: p = 2; break;  /* SPDIF */
2695                         case 7: p = 10; break; /* SYNC_IN */
2696                         default: return -1;
2697                         }
2698                 }
2699                 break;
2700
2701         case AIO:
2702                 if (hdspm->tco) {
2703                         switch (pref) {
2704                         case 0: p = 0; break;  /* WC */
2705                         case 1: p = 3; break;  /* ADAT */
2706                         case 2: p = 1; break;  /* AES */
2707                         case 3: p = 2; break;  /* SPDIF */
2708                         case 4: p = 9; break;  /* TCO */
2709                         case 5: p = 10; break; /* SYNC_IN */
2710                         default: return -1;
2711                         }
2712                 } else {
2713                         switch (pref) {
2714                         case 0: p = 0; break;  /* WC */
2715                         case 1: p = 3; break;  /* ADAT */
2716                         case 2: p = 1; break;  /* AES */
2717                         case 3: p = 2; break;  /* SPDIF */
2718                         case 4: p = 10; break; /* SYNC_IN */
2719                         default: return -1;
2720                         }
2721                 }
2722                 break;
2723         }
2724
2725         switch (hdspm->io_type) {
2726         case RayDAT:
2727         case AIO:
2728                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2729                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2730                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2731                 break;
2732
2733         case MADI:
2734         case MADIface:
2735         case AES32:
2736                 hdspm_write(hdspm, HDSPM_controlRegister,
2737                                 hdspm->control_register);
2738         }
2739
2740         return 0;
2741 }
2742
2743
2744 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2745                                         struct snd_ctl_elem_info *uinfo)
2746 {
2747         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2748
2749         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2750         uinfo->count = 1;
2751         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2752
2753         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2754                 uinfo->value.enumerated.item =
2755                         uinfo->value.enumerated.items - 1;
2756
2757         strcpy(uinfo->value.enumerated.name,
2758                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2759
2760         return 0;
2761 }
2762
2763 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2764                                        struct snd_ctl_elem_value *ucontrol)
2765 {
2766         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2767         int psf = hdspm_pref_sync_ref(hdspm);
2768
2769         if (psf >= 0) {
2770                 ucontrol->value.enumerated.item[0] = psf;
2771                 return 0;
2772         }
2773
2774         return -1;
2775 }
2776
2777 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2778                                        struct snd_ctl_elem_value *ucontrol)
2779 {
2780         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2781         int val, change = 0;
2782
2783         if (!snd_hdspm_use_is_exclusive(hdspm))
2784                 return -EBUSY;
2785
2786         val = ucontrol->value.enumerated.item[0];
2787
2788         if (val < 0)
2789                 val = 0;
2790         else if (val >= hdspm->texts_autosync_items)
2791                 val = hdspm->texts_autosync_items-1;
2792
2793         spin_lock_irq(&hdspm->lock);
2794         if (val != hdspm_pref_sync_ref(hdspm))
2795                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2796
2797         spin_unlock_irq(&hdspm->lock);
2798         return change;
2799 }
2800
2801
2802 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2803 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2804         .name = xname, \
2805         .index = xindex, \
2806         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2807         .info = snd_hdspm_info_autosync_ref, \
2808         .get = snd_hdspm_get_autosync_ref, \
2809 }
2810
2811 static int hdspm_autosync_ref(struct hdspm *hdspm)
2812 {
2813         if (AES32 == hdspm->io_type) {
2814                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2815                 unsigned int syncref =
2816                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2817                 if (syncref == 0)
2818                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2819                 if (syncref <= 8)
2820                         return syncref;
2821                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2822         } else if (MADI == hdspm->io_type) {
2823                 /* This looks at the autosync selected sync reference */
2824                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2825
2826                 switch (status2 & HDSPM_SelSyncRefMask) {
2827                 case HDSPM_SelSyncRef_WORD:
2828                         return HDSPM_AUTOSYNC_FROM_WORD;
2829                 case HDSPM_SelSyncRef_MADI:
2830                         return HDSPM_AUTOSYNC_FROM_MADI;
2831                 case HDSPM_SelSyncRef_TCO:
2832                         return HDSPM_AUTOSYNC_FROM_TCO;
2833                 case HDSPM_SelSyncRef_SyncIn:
2834                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2835                 case HDSPM_SelSyncRef_NVALID:
2836                         return HDSPM_AUTOSYNC_FROM_NONE;
2837                 default:
2838                         return 0;
2839                 }
2840
2841         }
2842         return 0;
2843 }
2844
2845
2846 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2847                                        struct snd_ctl_elem_info *uinfo)
2848 {
2849         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2850
2851         if (AES32 == hdspm->io_type) {
2852                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2853                         "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2854
2855                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2856                 uinfo->count = 1;
2857                 uinfo->value.enumerated.items = 10;
2858                 if (uinfo->value.enumerated.item >=
2859                     uinfo->value.enumerated.items)
2860                         uinfo->value.enumerated.item =
2861                                 uinfo->value.enumerated.items - 1;
2862                 strcpy(uinfo->value.enumerated.name,
2863                                 texts[uinfo->value.enumerated.item]);
2864         } else if (MADI == hdspm->io_type) {
2865                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2866                         "Sync In", "None" };
2867
2868                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2869                 uinfo->count = 1;
2870                 uinfo->value.enumerated.items = 5;
2871                 if (uinfo->value.enumerated.item >=
2872                                 uinfo->value.enumerated.items)
2873                         uinfo->value.enumerated.item =
2874                                 uinfo->value.enumerated.items - 1;
2875                 strcpy(uinfo->value.enumerated.name,
2876                                 texts[uinfo->value.enumerated.item]);
2877         }
2878         return 0;
2879 }
2880
2881 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2882                                       struct snd_ctl_elem_value *ucontrol)
2883 {
2884         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2885
2886         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2887         return 0;
2888 }
2889
2890
2891 #define HDSPM_LINE_OUT(xname, xindex) \
2892 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2893         .name = xname, \
2894         .index = xindex, \
2895         .info = snd_hdspm_info_line_out, \
2896         .get = snd_hdspm_get_line_out, \
2897         .put = snd_hdspm_put_line_out \
2898 }
2899
2900 static int hdspm_line_out(struct hdspm * hdspm)
2901 {
2902         return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2903 }
2904
2905
2906 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2907 {
2908         if (out)
2909                 hdspm->control_register |= HDSPM_LineOut;
2910         else
2911                 hdspm->control_register &= ~HDSPM_LineOut;
2912         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2913
2914         return 0;
2915 }
2916
2917 #define snd_hdspm_info_line_out         snd_ctl_boolean_mono_info
2918
2919 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2920                                   struct snd_ctl_elem_value *ucontrol)
2921 {
2922         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2923
2924         spin_lock_irq(&hdspm->lock);
2925         ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2926         spin_unlock_irq(&hdspm->lock);
2927         return 0;
2928 }
2929
2930 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2931                                   struct snd_ctl_elem_value *ucontrol)
2932 {
2933         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2934         int change;
2935         unsigned int val;
2936
2937         if (!snd_hdspm_use_is_exclusive(hdspm))
2938                 return -EBUSY;
2939         val = ucontrol->value.integer.value[0] & 1;
2940         spin_lock_irq(&hdspm->lock);
2941         change = (int) val != hdspm_line_out(hdspm);
2942         hdspm_set_line_output(hdspm, val);
2943         spin_unlock_irq(&hdspm->lock);
2944         return change;
2945 }
2946
2947
2948 #define HDSPM_TX_64(xname, xindex) \
2949 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2950         .name = xname, \
2951         .index = xindex, \
2952         .info = snd_hdspm_info_tx_64, \
2953         .get = snd_hdspm_get_tx_64, \
2954         .put = snd_hdspm_put_tx_64 \
2955 }
2956
2957 static int hdspm_tx_64(struct hdspm * hdspm)
2958 {
2959         return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2960 }
2961
2962 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2963 {
2964         if (out)
2965                 hdspm->control_register |= HDSPM_TX_64ch;
2966         else
2967                 hdspm->control_register &= ~HDSPM_TX_64ch;
2968         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2969
2970         return 0;
2971 }
2972
2973 #define snd_hdspm_info_tx_64            snd_ctl_boolean_mono_info
2974
2975 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2976                                struct snd_ctl_elem_value *ucontrol)
2977 {
2978         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2979
2980         spin_lock_irq(&hdspm->lock);
2981         ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2982         spin_unlock_irq(&hdspm->lock);
2983         return 0;
2984 }
2985
2986 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2987                                struct snd_ctl_elem_value *ucontrol)
2988 {
2989         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2990         int change;
2991         unsigned int val;
2992
2993         if (!snd_hdspm_use_is_exclusive(hdspm))
2994                 return -EBUSY;
2995         val = ucontrol->value.integer.value[0] & 1;
2996         spin_lock_irq(&hdspm->lock);
2997         change = (int) val != hdspm_tx_64(hdspm);
2998         hdspm_set_tx_64(hdspm, val);
2999         spin_unlock_irq(&hdspm->lock);
3000         return change;
3001 }
3002
3003
3004 #define HDSPM_C_TMS(xname, xindex) \
3005 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3006         .name = xname, \
3007         .index = xindex, \
3008         .info = snd_hdspm_info_c_tms, \
3009         .get = snd_hdspm_get_c_tms, \
3010         .put = snd_hdspm_put_c_tms \
3011 }
3012
3013 static int hdspm_c_tms(struct hdspm * hdspm)
3014 {
3015         return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
3016 }
3017
3018 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
3019 {
3020         if (out)
3021                 hdspm->control_register |= HDSPM_clr_tms;
3022         else
3023                 hdspm->control_register &= ~HDSPM_clr_tms;
3024         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3025
3026         return 0;
3027 }
3028
3029 #define snd_hdspm_info_c_tms            snd_ctl_boolean_mono_info
3030
3031 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
3032                                struct snd_ctl_elem_value *ucontrol)
3033 {
3034         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3035
3036         spin_lock_irq(&hdspm->lock);
3037         ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
3038         spin_unlock_irq(&hdspm->lock);
3039         return 0;
3040 }
3041
3042 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3043                                struct snd_ctl_elem_value *ucontrol)
3044 {
3045         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3046         int change;
3047         unsigned int val;
3048
3049         if (!snd_hdspm_use_is_exclusive(hdspm))
3050                 return -EBUSY;
3051         val = ucontrol->value.integer.value[0] & 1;
3052         spin_lock_irq(&hdspm->lock);
3053         change = (int) val != hdspm_c_tms(hdspm);
3054         hdspm_set_c_tms(hdspm, val);
3055         spin_unlock_irq(&hdspm->lock);
3056         return change;
3057 }
3058
3059
3060 #define HDSPM_SAFE_MODE(xname, xindex) \
3061 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3062         .name = xname, \
3063         .index = xindex, \
3064         .info = snd_hdspm_info_safe_mode, \
3065         .get = snd_hdspm_get_safe_mode, \
3066         .put = snd_hdspm_put_safe_mode \
3067 }
3068
3069 static int hdspm_safe_mode(struct hdspm * hdspm)
3070 {
3071         return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3072 }
3073
3074 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3075 {
3076         if (out)
3077                 hdspm->control_register |= HDSPM_AutoInp;
3078         else
3079                 hdspm->control_register &= ~HDSPM_AutoInp;
3080         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3081
3082         return 0;
3083 }
3084
3085 #define snd_hdspm_info_safe_mode        snd_ctl_boolean_mono_info
3086
3087 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3088                                    struct snd_ctl_elem_value *ucontrol)
3089 {
3090         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3091
3092         spin_lock_irq(&hdspm->lock);
3093         ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3094         spin_unlock_irq(&hdspm->lock);
3095         return 0;
3096 }
3097
3098 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3099                                    struct snd_ctl_elem_value *ucontrol)
3100 {
3101         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3102         int change;
3103         unsigned int val;
3104
3105         if (!snd_hdspm_use_is_exclusive(hdspm))
3106                 return -EBUSY;
3107         val = ucontrol->value.integer.value[0] & 1;
3108         spin_lock_irq(&hdspm->lock);
3109         change = (int) val != hdspm_safe_mode(hdspm);
3110         hdspm_set_safe_mode(hdspm, val);
3111         spin_unlock_irq(&hdspm->lock);
3112         return change;
3113 }
3114
3115
3116 #define HDSPM_EMPHASIS(xname, xindex) \
3117 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3118         .name = xname, \
3119         .index = xindex, \
3120         .info = snd_hdspm_info_emphasis, \
3121         .get = snd_hdspm_get_emphasis, \
3122         .put = snd_hdspm_put_emphasis \
3123 }
3124
3125 static int hdspm_emphasis(struct hdspm * hdspm)
3126 {
3127         return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3128 }
3129
3130 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3131 {
3132         if (emp)
3133                 hdspm->control_register |= HDSPM_Emphasis;
3134         else
3135                 hdspm->control_register &= ~HDSPM_Emphasis;
3136         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3137
3138         return 0;
3139 }
3140
3141 #define snd_hdspm_info_emphasis         snd_ctl_boolean_mono_info
3142
3143 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3144                                   struct snd_ctl_elem_value *ucontrol)
3145 {
3146         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3147
3148         spin_lock_irq(&hdspm->lock);
3149         ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3150         spin_unlock_irq(&hdspm->lock);
3151         return 0;
3152 }
3153
3154 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3155                                   struct snd_ctl_elem_value *ucontrol)
3156 {
3157         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3158         int change;
3159         unsigned int val;
3160
3161         if (!snd_hdspm_use_is_exclusive(hdspm))
3162                 return -EBUSY;
3163         val = ucontrol->value.integer.value[0] & 1;
3164         spin_lock_irq(&hdspm->lock);
3165         change = (int) val != hdspm_emphasis(hdspm);
3166         hdspm_set_emphasis(hdspm, val);
3167         spin_unlock_irq(&hdspm->lock);
3168         return change;
3169 }
3170
3171
3172 #define HDSPM_DOLBY(xname, xindex) \
3173 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3174         .name = xname, \
3175         .index = xindex, \
3176         .info = snd_hdspm_info_dolby, \
3177         .get = snd_hdspm_get_dolby, \
3178         .put = snd_hdspm_put_dolby \
3179 }
3180
3181 static int hdspm_dolby(struct hdspm * hdspm)
3182 {
3183         return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3184 }
3185
3186 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3187 {
3188         if (dol)
3189                 hdspm->control_register |= HDSPM_Dolby;
3190         else
3191                 hdspm->control_register &= ~HDSPM_Dolby;
3192         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3193
3194         return 0;
3195 }
3196
3197 #define snd_hdspm_info_dolby            snd_ctl_boolean_mono_info
3198
3199 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3200                                struct snd_ctl_elem_value *ucontrol)
3201 {
3202         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3203
3204         spin_lock_irq(&hdspm->lock);
3205         ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3206         spin_unlock_irq(&hdspm->lock);
3207         return 0;
3208 }
3209
3210 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3211                                struct snd_ctl_elem_value *ucontrol)
3212 {
3213         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3214         int change;
3215         unsigned int val;
3216
3217         if (!snd_hdspm_use_is_exclusive(hdspm))
3218                 return -EBUSY;
3219         val = ucontrol->value.integer.value[0] & 1;
3220         spin_lock_irq(&hdspm->lock);
3221         change = (int) val != hdspm_dolby(hdspm);
3222         hdspm_set_dolby(hdspm, val);
3223         spin_unlock_irq(&hdspm->lock);
3224         return change;
3225 }
3226
3227
3228 #define HDSPM_PROFESSIONAL(xname, xindex) \
3229 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3230         .name = xname, \
3231         .index = xindex, \
3232         .info = snd_hdspm_info_professional, \
3233         .get = snd_hdspm_get_professional, \
3234         .put = snd_hdspm_put_professional \
3235 }
3236
3237 static int hdspm_professional(struct hdspm * hdspm)
3238 {
3239         return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3240 }
3241
3242 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3243 {
3244         if (dol)
3245                 hdspm->control_register |= HDSPM_Professional;
3246         else
3247                 hdspm->control_register &= ~HDSPM_Professional;
3248         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3249
3250         return 0;
3251 }
3252
3253 #define snd_hdspm_info_professional     snd_ctl_boolean_mono_info
3254
3255 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3256                                       struct snd_ctl_elem_value *ucontrol)
3257 {
3258         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3259
3260         spin_lock_irq(&hdspm->lock);
3261         ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3262         spin_unlock_irq(&hdspm->lock);
3263         return 0;
3264 }
3265
3266 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3267                                       struct snd_ctl_elem_value *ucontrol)
3268 {
3269         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3270         int change;
3271         unsigned int val;
3272
3273         if (!snd_hdspm_use_is_exclusive(hdspm))
3274                 return -EBUSY;
3275         val = ucontrol->value.integer.value[0] & 1;
3276         spin_lock_irq(&hdspm->lock);
3277         change = (int) val != hdspm_professional(hdspm);
3278         hdspm_set_professional(hdspm, val);
3279         spin_unlock_irq(&hdspm->lock);
3280         return change;
3281 }
3282
3283 #define HDSPM_INPUT_SELECT(xname, xindex) \
3284 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3285         .name = xname, \
3286         .index = xindex, \
3287         .info = snd_hdspm_info_input_select, \
3288         .get = snd_hdspm_get_input_select, \
3289         .put = snd_hdspm_put_input_select \
3290 }
3291
3292 static int hdspm_input_select(struct hdspm * hdspm)
3293 {
3294         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3295 }
3296
3297 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3298 {
3299         if (out)
3300                 hdspm->control_register |= HDSPM_InputSelect0;
3301         else
3302                 hdspm->control_register &= ~HDSPM_InputSelect0;
3303         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3304
3305         return 0;
3306 }
3307
3308 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3309                                        struct snd_ctl_elem_info *uinfo)
3310 {
3311         static char *texts[] = { "optical", "coaxial" };
3312
3313         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3314         uinfo->count = 1;
3315         uinfo->value.enumerated.items = 2;
3316
3317         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3318                 uinfo->value.enumerated.item =
3319                     uinfo->value.enumerated.items - 1;
3320         strcpy(uinfo->value.enumerated.name,
3321                texts[uinfo->value.enumerated.item]);
3322
3323         return 0;
3324 }
3325
3326 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3327                                       struct snd_ctl_elem_value *ucontrol)
3328 {
3329         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3330
3331         spin_lock_irq(&hdspm->lock);
3332         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3333         spin_unlock_irq(&hdspm->lock);
3334         return 0;
3335 }
3336
3337 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3338                                       struct snd_ctl_elem_value *ucontrol)
3339 {
3340         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3341         int change;
3342         unsigned int val;
3343
3344         if (!snd_hdspm_use_is_exclusive(hdspm))
3345                 return -EBUSY;
3346         val = ucontrol->value.integer.value[0] & 1;
3347         spin_lock_irq(&hdspm->lock);
3348         change = (int) val != hdspm_input_select(hdspm);
3349         hdspm_set_input_select(hdspm, val);
3350         spin_unlock_irq(&hdspm->lock);
3351         return change;
3352 }
3353
3354
3355 #define HDSPM_DS_WIRE(xname, xindex) \
3356 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3357         .name = xname, \
3358         .index = xindex, \
3359         .info = snd_hdspm_info_ds_wire, \
3360         .get = snd_hdspm_get_ds_wire, \
3361         .put = snd_hdspm_put_ds_wire \
3362 }
3363
3364 static int hdspm_ds_wire(struct hdspm * hdspm)
3365 {
3366         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3367 }
3368
3369 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3370 {
3371         if (ds)
3372                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3373         else
3374                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3375         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3376
3377         return 0;
3378 }
3379
3380 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3381                                   struct snd_ctl_elem_info *uinfo)
3382 {
3383         static char *texts[] = { "Single", "Double" };
3384
3385         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3386         uinfo->count = 1;
3387         uinfo->value.enumerated.items = 2;
3388
3389         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3390                 uinfo->value.enumerated.item =
3391                     uinfo->value.enumerated.items - 1;
3392         strcpy(uinfo->value.enumerated.name,
3393                texts[uinfo->value.enumerated.item]);
3394
3395         return 0;
3396 }
3397
3398 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3399                                  struct snd_ctl_elem_value *ucontrol)
3400 {
3401         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3402
3403         spin_lock_irq(&hdspm->lock);
3404         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3405         spin_unlock_irq(&hdspm->lock);
3406         return 0;
3407 }
3408
3409 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3410                                  struct snd_ctl_elem_value *ucontrol)
3411 {
3412         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3413         int change;
3414         unsigned int val;
3415
3416         if (!snd_hdspm_use_is_exclusive(hdspm))
3417                 return -EBUSY;
3418         val = ucontrol->value.integer.value[0] & 1;
3419         spin_lock_irq(&hdspm->lock);
3420         change = (int) val != hdspm_ds_wire(hdspm);
3421         hdspm_set_ds_wire(hdspm, val);
3422         spin_unlock_irq(&hdspm->lock);
3423         return change;
3424 }
3425
3426
3427 #define HDSPM_QS_WIRE(xname, xindex) \
3428 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3429         .name = xname, \
3430         .index = xindex, \
3431         .info = snd_hdspm_info_qs_wire, \
3432         .get = snd_hdspm_get_qs_wire, \
3433         .put = snd_hdspm_put_qs_wire \
3434 }
3435
3436 static int hdspm_qs_wire(struct hdspm * hdspm)
3437 {
3438         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3439                 return 1;
3440         if (hdspm->control_register & HDSPM_QS_QuadWire)
3441                 return 2;
3442         return 0;
3443 }
3444
3445 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3446 {
3447         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3448         switch (mode) {
3449         case 0:
3450                 break;
3451         case 1:
3452                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3453                 break;
3454         case 2:
3455                 hdspm->control_register |= HDSPM_QS_QuadWire;
3456                 break;
3457         }
3458         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3459
3460         return 0;
3461 }
3462
3463 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3464                                        struct snd_ctl_elem_info *uinfo)
3465 {
3466         static char *texts[] = { "Single", "Double", "Quad" };
3467
3468         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3469         uinfo->count = 1;
3470         uinfo->value.enumerated.items = 3;
3471
3472         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3473                 uinfo->value.enumerated.item =
3474                     uinfo->value.enumerated.items - 1;
3475         strcpy(uinfo->value.enumerated.name,
3476                texts[uinfo->value.enumerated.item]);
3477
3478         return 0;
3479 }
3480
3481 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3482                                       struct snd_ctl_elem_value *ucontrol)
3483 {
3484         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3485
3486         spin_lock_irq(&hdspm->lock);
3487         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3488         spin_unlock_irq(&hdspm->lock);
3489         return 0;
3490 }
3491
3492 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3493                                       struct snd_ctl_elem_value *ucontrol)
3494 {
3495         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3496         int change;
3497         int val;
3498
3499         if (!snd_hdspm_use_is_exclusive(hdspm))
3500                 return -EBUSY;
3501         val = ucontrol->value.integer.value[0];
3502         if (val < 0)
3503                 val = 0;
3504         if (val > 2)
3505                 val = 2;
3506         spin_lock_irq(&hdspm->lock);
3507         change = val != hdspm_qs_wire(hdspm);
3508         hdspm_set_qs_wire(hdspm, val);
3509         spin_unlock_irq(&hdspm->lock);
3510         return change;
3511 }
3512
3513 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3514 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3515         .name = xname, \
3516         .index = xindex, \
3517         .info = snd_hdspm_info_madi_speedmode, \
3518         .get = snd_hdspm_get_madi_speedmode, \
3519         .put = snd_hdspm_put_madi_speedmode \
3520 }
3521
3522 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3523 {
3524         if (hdspm->control_register & HDSPM_QuadSpeed)
3525                 return 2;
3526         if (hdspm->control_register & HDSPM_DoubleSpeed)
3527                 return 1;
3528         return 0;
3529 }
3530
3531 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3532 {
3533         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3534         switch (mode) {
3535         case 0:
3536                 break;
3537         case 1:
3538                 hdspm->control_register |= HDSPM_DoubleSpeed;
3539                 break;
3540         case 2:
3541                 hdspm->control_register |= HDSPM_QuadSpeed;
3542                 break;
3543         }
3544         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3545
3546         return 0;
3547 }
3548
3549 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3550                                        struct snd_ctl_elem_info *uinfo)
3551 {
3552         static char *texts[] = { "Single", "Double", "Quad" };
3553
3554         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3555         uinfo->count = 1;
3556         uinfo->value.enumerated.items = 3;
3557
3558         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3559                 uinfo->value.enumerated.item =
3560                     uinfo->value.enumerated.items - 1;
3561         strcpy(uinfo->value.enumerated.name,
3562                texts[uinfo->value.enumerated.item]);
3563
3564         return 0;
3565 }
3566
3567 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3568                                       struct snd_ctl_elem_value *ucontrol)
3569 {
3570         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3571
3572         spin_lock_irq(&hdspm->lock);
3573         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3574         spin_unlock_irq(&hdspm->lock);
3575         return 0;
3576 }
3577
3578 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3579                                       struct snd_ctl_elem_value *ucontrol)
3580 {
3581         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3582         int change;
3583         int val;
3584
3585         if (!snd_hdspm_use_is_exclusive(hdspm))
3586                 return -EBUSY;
3587         val = ucontrol->value.integer.value[0];
3588         if (val < 0)
3589                 val = 0;
3590         if (val > 2)
3591                 val = 2;
3592         spin_lock_irq(&hdspm->lock);
3593         change = val != hdspm_madi_speedmode(hdspm);
3594         hdspm_set_madi_speedmode(hdspm, val);
3595         spin_unlock_irq(&hdspm->lock);
3596         return change;
3597 }
3598
3599 #define HDSPM_MIXER(xname, xindex) \
3600 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3601         .name = xname, \
3602         .index = xindex, \
3603         .device = 0, \
3604         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3605                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3606         .info = snd_hdspm_info_mixer, \
3607         .get = snd_hdspm_get_mixer, \
3608         .put = snd_hdspm_put_mixer \
3609 }
3610
3611 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3612                                 struct snd_ctl_elem_info *uinfo)
3613 {
3614         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3615         uinfo->count = 3;
3616         uinfo->value.integer.min = 0;
3617         uinfo->value.integer.max = 65535;
3618         uinfo->value.integer.step = 1;
3619         return 0;
3620 }
3621
3622 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3623                                struct snd_ctl_elem_value *ucontrol)
3624 {
3625         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3626         int source;
3627         int destination;
3628
3629         source = ucontrol->value.integer.value[0];
3630         if (source < 0)
3631                 source = 0;
3632         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3633                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3634
3635         destination = ucontrol->value.integer.value[1];
3636         if (destination < 0)
3637                 destination = 0;
3638         else if (destination >= HDSPM_MAX_CHANNELS)
3639                 destination = HDSPM_MAX_CHANNELS - 1;
3640
3641         spin_lock_irq(&hdspm->lock);
3642         if (source >= HDSPM_MAX_CHANNELS)
3643                 ucontrol->value.integer.value[2] =
3644                     hdspm_read_pb_gain(hdspm, destination,
3645                                        source - HDSPM_MAX_CHANNELS);
3646         else
3647                 ucontrol->value.integer.value[2] =
3648                     hdspm_read_in_gain(hdspm, destination, source);
3649
3650         spin_unlock_irq(&hdspm->lock);
3651
3652         return 0;
3653 }
3654
3655 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3656                                struct snd_ctl_elem_value *ucontrol)
3657 {
3658         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3659         int change;
3660         int source;
3661         int destination;
3662         int gain;
3663
3664         if (!snd_hdspm_use_is_exclusive(hdspm))
3665                 return -EBUSY;
3666
3667         source = ucontrol->value.integer.value[0];
3668         destination = ucontrol->value.integer.value[1];
3669
3670         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3671                 return -1;
3672         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3673                 return -1;
3674
3675         gain = ucontrol->value.integer.value[2];
3676
3677         spin_lock_irq(&hdspm->lock);
3678
3679         if (source >= HDSPM_MAX_CHANNELS)
3680                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3681                                                     source -
3682                                                     HDSPM_MAX_CHANNELS);
3683         else
3684                 change = gain != hdspm_read_in_gain(hdspm, destination,
3685                                                     source);
3686
3687         if (change) {
3688                 if (source >= HDSPM_MAX_CHANNELS)
3689                         hdspm_write_pb_gain(hdspm, destination,
3690                                             source - HDSPM_MAX_CHANNELS,
3691                                             gain);
3692                 else
3693                         hdspm_write_in_gain(hdspm, destination, source,
3694                                             gain);
3695         }
3696         spin_unlock_irq(&hdspm->lock);
3697
3698         return change;
3699 }
3700
3701 /* The simple mixer control(s) provide gain control for the
3702    basic 1:1 mappings of playback streams to output
3703    streams.
3704 */
3705
3706 #define HDSPM_PLAYBACK_MIXER \
3707 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3708         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3709                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3710         .info = snd_hdspm_info_playback_mixer, \
3711         .get = snd_hdspm_get_playback_mixer, \
3712         .put = snd_hdspm_put_playback_mixer \
3713 }
3714
3715 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3716                                          struct snd_ctl_elem_info *uinfo)
3717 {
3718         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3719         uinfo->count = 1;
3720         uinfo->value.integer.min = 0;
3721         uinfo->value.integer.max = 64;
3722         uinfo->value.integer.step = 1;
3723         return 0;
3724 }
3725
3726 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3727                                         struct snd_ctl_elem_value *ucontrol)
3728 {
3729         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3730         int channel;
3731
3732         channel = ucontrol->id.index - 1;
3733
3734         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3735                 return -EINVAL;
3736
3737         spin_lock_irq(&hdspm->lock);
3738         ucontrol->value.integer.value[0] =
3739           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3740         spin_unlock_irq(&hdspm->lock);
3741
3742         return 0;
3743 }
3744
3745 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3746                                         struct snd_ctl_elem_value *ucontrol)
3747 {
3748         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3749         int change;
3750         int channel;
3751         int gain;
3752
3753         if (!snd_hdspm_use_is_exclusive(hdspm))
3754                 return -EBUSY;
3755
3756         channel = ucontrol->id.index - 1;
3757
3758         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3759                 return -EINVAL;
3760
3761         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3762
3763         spin_lock_irq(&hdspm->lock);
3764         change =
3765             gain != hdspm_read_pb_gain(hdspm, channel,
3766                                        channel);
3767         if (change)
3768                 hdspm_write_pb_gain(hdspm, channel, channel,
3769                                     gain);
3770         spin_unlock_irq(&hdspm->lock);
3771         return change;
3772 }
3773
3774 #define HDSPM_SYNC_CHECK(xname, xindex) \
3775 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3776         .name = xname, \
3777         .private_value = xindex, \
3778         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3779         .info = snd_hdspm_info_sync_check, \
3780         .get = snd_hdspm_get_sync_check \
3781 }
3782
3783
3784 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3785                                      struct snd_ctl_elem_info *uinfo)
3786 {
3787         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3788         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3789         uinfo->count = 1;
3790         uinfo->value.enumerated.items = 4;
3791         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3792                 uinfo->value.enumerated.item =
3793                         uinfo->value.enumerated.items - 1;
3794         strcpy(uinfo->value.enumerated.name,
3795                         texts[uinfo->value.enumerated.item]);
3796         return 0;
3797 }
3798
3799 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3800 {
3801         int status, status2;
3802
3803         switch (hdspm->io_type) {
3804         case AES32:
3805                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3806                 if (status & HDSPM_wcSync)
3807                         return 2;
3808                 else if (status & HDSPM_wcLock)
3809                         return 1;
3810                 return 0;
3811                 break;
3812
3813         case MADI:
3814                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3815                 if (status2 & HDSPM_wcLock) {
3816                         if (status2 & HDSPM_wcSync)
3817                                 return 2;
3818                         else
3819                                 return 1;
3820                 }
3821                 return 0;
3822                 break;
3823
3824         case RayDAT:
3825         case AIO:
3826                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3827
3828                 if (status & 0x2000000)
3829                         return 2;
3830                 else if (status & 0x1000000)
3831                         return 1;
3832                 return 0;
3833
3834                 break;
3835
3836         case MADIface:
3837                 break;
3838         }
3839
3840
3841         return 3;
3842 }
3843
3844
3845 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3846 {
3847         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3848         if (status & HDSPM_madiLock) {
3849                 if (status & HDSPM_madiSync)
3850                         return 2;
3851                 else
3852                         return 1;
3853         }
3854         return 0;
3855 }
3856
3857
3858 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3859 {
3860         int status, lock, sync;
3861
3862         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3863
3864         lock = (status & (0x1<<idx)) ? 1 : 0;
3865         sync = (status & (0x100<<idx)) ? 1 : 0;
3866
3867         if (lock && sync)
3868                 return 2;
3869         else if (lock)
3870                 return 1;
3871         return 0;
3872 }
3873
3874
3875 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3876 {
3877         int status, lock = 0, sync = 0;
3878
3879         switch (hdspm->io_type) {
3880         case RayDAT:
3881         case AIO:
3882                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3883                 lock = (status & 0x400) ? 1 : 0;
3884                 sync = (status & 0x800) ? 1 : 0;
3885                 break;
3886
3887         case MADI:
3888                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3889                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3890                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3891                 break;
3892
3893         case AES32:
3894                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3895                 lock = (status & 0x100000) ? 1 : 0;
3896                 sync = (status & 0x200000) ? 1 : 0;
3897                 break;
3898
3899         case MADIface:
3900                 break;
3901         }
3902
3903         if (lock && sync)
3904                 return 2;
3905         else if (lock)
3906                 return 1;
3907
3908         return 0;
3909 }
3910
3911 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3912 {
3913         int status2, lock, sync;
3914         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3915
3916         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3917         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3918
3919         if (sync)
3920                 return 2;
3921         else if (lock)
3922                 return 1;
3923         return 0;
3924 }
3925
3926
3927 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3928 {
3929         int status;
3930
3931         if (hdspm->tco) {
3932                 switch (hdspm->io_type) {
3933                 case MADI:
3934                 case AES32:
3935                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3936                         if (status & HDSPM_tcoLock) {
3937                                 if (status & HDSPM_tcoSync)
3938                                         return 2;
3939                                 else
3940                                         return 1;
3941                         }
3942                         return 0;
3943
3944                         break;
3945
3946                 case RayDAT:
3947                 case AIO:
3948                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3949
3950                         if (status & 0x8000000)
3951                                 return 2; /* Sync */
3952                         if (status & 0x4000000)
3953                                 return 1; /* Lock */
3954                         return 0; /* No signal */
3955                         break;
3956
3957                 default:
3958                         break;
3959                 }
3960         }
3961
3962         return 3; /* N/A */
3963 }
3964
3965
3966 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3967                                     struct snd_ctl_elem_value *ucontrol)
3968 {
3969         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3970         int val = -1;
3971
3972         switch (hdspm->io_type) {
3973         case RayDAT:
3974                 switch (kcontrol->private_value) {
3975                 case 0: /* WC */
3976                         val = hdspm_wc_sync_check(hdspm); break;
3977                 case 7: /* TCO */
3978                         val = hdspm_tco_sync_check(hdspm); break;
3979                 case 8: /* SYNC IN */
3980                         val = hdspm_sync_in_sync_check(hdspm); break;
3981                 default:
3982                         val = hdspm_s1_sync_check(hdspm,
3983                                         kcontrol->private_value-1);
3984                 }
3985                 break;
3986
3987         case AIO:
3988                 switch (kcontrol->private_value) {
3989                 case 0: /* WC */
3990                         val = hdspm_wc_sync_check(hdspm); break;
3991                 case 4: /* TCO */
3992                         val = hdspm_tco_sync_check(hdspm); break;
3993                 case 5: /* SYNC IN */
3994                         val = hdspm_sync_in_sync_check(hdspm); break;
3995                 default:
3996                         val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3997                 }
3998                 break;
3999
4000         case MADI:
4001                 switch (kcontrol->private_value) {
4002                 case 0: /* WC */
4003                         val = hdspm_wc_sync_check(hdspm); break;
4004                 case 1: /* MADI */
4005                         val = hdspm_madi_sync_check(hdspm); break;
4006                 case 2: /* TCO */
4007                         val = hdspm_tco_sync_check(hdspm); break;
4008                 case 3: /* SYNC_IN */
4009                         val = hdspm_sync_in_sync_check(hdspm); break;
4010                 }
4011                 break;
4012
4013         case MADIface:
4014                 val = hdspm_madi_sync_check(hdspm); /* MADI */
4015                 break;
4016
4017         case AES32:
4018                 switch (kcontrol->private_value) {
4019                 case 0: /* WC */
4020                         val = hdspm_wc_sync_check(hdspm); break;
4021                 case 9: /* TCO */
4022                         val = hdspm_tco_sync_check(hdspm); break;
4023                 case 10 /* SYNC IN */:
4024                         val = hdspm_sync_in_sync_check(hdspm); break;
4025                 default: /* AES1 to AES8 */
4026                          val = hdspm_aes_sync_check(hdspm,
4027                                          kcontrol->private_value-1);
4028                 }
4029                 break;
4030
4031         }
4032
4033         if (-1 == val)
4034                 val = 3;
4035
4036         ucontrol->value.enumerated.item[0] = val;
4037         return 0;
4038 }
4039
4040
4041
4042 /**
4043  * TCO controls
4044  **/
4045 static void hdspm_tco_write(struct hdspm *hdspm)
4046 {
4047         unsigned int tc[4] = { 0, 0, 0, 0};
4048
4049         switch (hdspm->tco->input) {
4050         case 0:
4051                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4052                 break;
4053         case 1:
4054                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4055                 break;
4056         default:
4057                 break;
4058         }
4059
4060         switch (hdspm->tco->framerate) {
4061         case 1:
4062                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4063                 break;
4064         case 2:
4065                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4066                 break;
4067         case 3:
4068                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4069                         HDSPM_TCO1_set_drop_frame_flag;
4070                 break;
4071         case 4:
4072                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4073                         HDSPM_TCO1_LTC_Format_MSB;
4074                 break;
4075         case 5:
4076                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4077                         HDSPM_TCO1_LTC_Format_MSB +
4078                         HDSPM_TCO1_set_drop_frame_flag;
4079                 break;
4080         default:
4081                 break;
4082         }
4083
4084         switch (hdspm->tco->wordclock) {
4085         case 1:
4086                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4087                 break;
4088         case 2:
4089                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4090                 break;
4091         default:
4092                 break;
4093         }
4094
4095         switch (hdspm->tco->samplerate) {
4096         case 1:
4097                 tc[2] |= HDSPM_TCO2_set_freq;
4098                 break;
4099         case 2:
4100                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4101                 break;
4102         default:
4103                 break;
4104         }
4105
4106         switch (hdspm->tco->pull) {
4107         case 1:
4108                 tc[2] |= HDSPM_TCO2_set_pull_up;
4109                 break;
4110         case 2:
4111                 tc[2] |= HDSPM_TCO2_set_pull_down;
4112                 break;
4113         case 3:
4114                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4115                 break;
4116         case 4:
4117                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4118                 break;
4119         default:
4120                 break;
4121         }
4122
4123         if (1 == hdspm->tco->term) {
4124                 tc[2] |= HDSPM_TCO2_set_term_75R;
4125         }
4126
4127         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4128         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4129         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4130         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4131 }
4132
4133
4134 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4135 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4136         .name = xname, \
4137         .index = xindex, \
4138         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4139                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4140         .info = snd_hdspm_info_tco_sample_rate, \
4141         .get = snd_hdspm_get_tco_sample_rate, \
4142         .put = snd_hdspm_put_tco_sample_rate \
4143 }
4144
4145 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4146                                           struct snd_ctl_elem_info *uinfo)
4147 {
4148         static char *texts[] = { "44.1 kHz", "48 kHz" };
4149         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4150         uinfo->count = 1;
4151         uinfo->value.enumerated.items = 2;
4152
4153         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4154                 uinfo->value.enumerated.item =
4155                         uinfo->value.enumerated.items - 1;
4156
4157         strcpy(uinfo->value.enumerated.name,
4158                         texts[uinfo->value.enumerated.item]);
4159
4160         return 0;
4161 }
4162
4163 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4164                                       struct snd_ctl_elem_value *ucontrol)
4165 {
4166         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4167
4168         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4169
4170         return 0;
4171 }
4172
4173 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4174                                          struct snd_ctl_elem_value *ucontrol)
4175 {
4176         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4177
4178         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4179                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4180
4181                 hdspm_tco_write(hdspm);
4182
4183                 return 1;
4184         }
4185
4186         return 0;
4187 }
4188
4189
4190 #define HDSPM_TCO_PULL(xname, xindex) \
4191 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4192         .name = xname, \
4193         .index = xindex, \
4194         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4195                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4196         .info = snd_hdspm_info_tco_pull, \
4197         .get = snd_hdspm_get_tco_pull, \
4198         .put = snd_hdspm_put_tco_pull \
4199 }
4200
4201 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4202                                    struct snd_ctl_elem_info *uinfo)
4203 {
4204         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4205         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4206         uinfo->count = 1;
4207         uinfo->value.enumerated.items = 5;
4208
4209         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4210                 uinfo->value.enumerated.item =
4211                         uinfo->value.enumerated.items - 1;
4212
4213         strcpy(uinfo->value.enumerated.name,
4214                         texts[uinfo->value.enumerated.item]);
4215
4216         return 0;
4217 }
4218
4219 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4220                                   struct snd_ctl_elem_value *ucontrol)
4221 {
4222         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4223
4224         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4225
4226         return 0;
4227 }
4228
4229 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4230                                   struct snd_ctl_elem_value *ucontrol)
4231 {
4232         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4233
4234         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4235                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4236
4237                 hdspm_tco_write(hdspm);
4238
4239                 return 1;
4240         }
4241
4242         return 0;
4243 }
4244
4245 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4246 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4247         .name = xname, \
4248         .index = xindex, \
4249         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4250                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4251         .info = snd_hdspm_info_tco_wck_conversion, \
4252         .get = snd_hdspm_get_tco_wck_conversion, \
4253         .put = snd_hdspm_put_tco_wck_conversion \
4254 }
4255
4256 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4257                                              struct snd_ctl_elem_info *uinfo)
4258 {
4259         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4260         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4261         uinfo->count = 1;
4262         uinfo->value.enumerated.items = 3;
4263
4264         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4265                 uinfo->value.enumerated.item =
4266                         uinfo->value.enumerated.items - 1;
4267
4268         strcpy(uinfo->value.enumerated.name,
4269                         texts[uinfo->value.enumerated.item]);
4270
4271         return 0;
4272 }
4273
4274 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4275                                             struct snd_ctl_elem_value *ucontrol)
4276 {
4277         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4278
4279         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4280
4281         return 0;
4282 }
4283
4284 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4285                                             struct snd_ctl_elem_value *ucontrol)
4286 {
4287         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4288
4289         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4290                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4291
4292                 hdspm_tco_write(hdspm);
4293
4294                 return 1;
4295         }
4296
4297         return 0;
4298 }
4299
4300
4301 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4302 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4303         .name = xname, \
4304         .index = xindex, \
4305         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4306                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4307         .info = snd_hdspm_info_tco_frame_rate, \
4308         .get = snd_hdspm_get_tco_frame_rate, \
4309         .put = snd_hdspm_put_tco_frame_rate \
4310 }
4311
4312 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4313                                           struct snd_ctl_elem_info *uinfo)
4314 {
4315         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4316                 "29.97 dfps", "30 fps", "30 dfps" };
4317         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4318         uinfo->count = 1;
4319         uinfo->value.enumerated.items = 6;
4320
4321         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4322                 uinfo->value.enumerated.item =
4323                         uinfo->value.enumerated.items - 1;
4324
4325         strcpy(uinfo->value.enumerated.name,
4326                         texts[uinfo->value.enumerated.item]);
4327
4328         return 0;
4329 }
4330
4331 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4332                                         struct snd_ctl_elem_value *ucontrol)
4333 {
4334         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4335
4336         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4337
4338         return 0;
4339 }
4340
4341 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4342                                         struct snd_ctl_elem_value *ucontrol)
4343 {
4344         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4345
4346         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4347                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4348
4349                 hdspm_tco_write(hdspm);
4350
4351                 return 1;
4352         }
4353
4354         return 0;
4355 }
4356
4357
4358 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4359 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4360         .name = xname, \
4361         .index = xindex, \
4362         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4363                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4364         .info = snd_hdspm_info_tco_sync_source, \
4365         .get = snd_hdspm_get_tco_sync_source, \
4366         .put = snd_hdspm_put_tco_sync_source \
4367 }
4368
4369 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4370                                           struct snd_ctl_elem_info *uinfo)
4371 {
4372         static char *texts[] = { "LTC", "Video", "WCK" };
4373         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4374         uinfo->count = 1;
4375         uinfo->value.enumerated.items = 3;
4376
4377         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4378                 uinfo->value.enumerated.item =
4379                         uinfo->value.enumerated.items - 1;
4380
4381         strcpy(uinfo->value.enumerated.name,
4382                         texts[uinfo->value.enumerated.item]);
4383
4384         return 0;
4385 }
4386
4387 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4388                                          struct snd_ctl_elem_value *ucontrol)
4389 {
4390         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4391
4392         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4393
4394         return 0;
4395 }
4396
4397 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4398                                          struct snd_ctl_elem_value *ucontrol)
4399 {
4400         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401
4402         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4403                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4404
4405                 hdspm_tco_write(hdspm);
4406
4407                 return 1;
4408         }
4409
4410         return 0;
4411 }
4412
4413
4414 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4415 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4416         .name = xname, \
4417         .index = xindex, \
4418         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4419                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4420         .info = snd_hdspm_info_tco_word_term, \
4421         .get = snd_hdspm_get_tco_word_term, \
4422         .put = snd_hdspm_put_tco_word_term \
4423 }
4424
4425 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4426                                         struct snd_ctl_elem_info *uinfo)
4427 {
4428         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4429         uinfo->count = 1;
4430         uinfo->value.integer.min = 0;
4431         uinfo->value.integer.max = 1;
4432
4433         return 0;
4434 }
4435
4436
4437 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4438                                        struct snd_ctl_elem_value *ucontrol)
4439 {
4440         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4441
4442         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4443
4444         return 0;
4445 }
4446
4447
4448 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4449                                        struct snd_ctl_elem_value *ucontrol)
4450 {
4451         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4452
4453         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4454                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4455
4456                 hdspm_tco_write(hdspm);
4457
4458                 return 1;
4459         }
4460
4461         return 0;
4462 }
4463
4464
4465
4466
4467 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4468         HDSPM_MIXER("Mixer", 0),
4469         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4470         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4471         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4472         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4473         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4474         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4475         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4476         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4477         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4478         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4479         HDSPM_LINE_OUT("Line Out", 0),
4480         HDSPM_TX_64("TX 64 channels mode", 0),
4481         HDSPM_C_TMS("Clear Track Marker", 0),
4482         HDSPM_SAFE_MODE("Safe Mode", 0),
4483         HDSPM_INPUT_SELECT("Input Select", 0),
4484         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4485 };
4486
4487
4488 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4489         HDSPM_MIXER("Mixer", 0),
4490         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4491         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4492         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4493         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4494         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4495         HDSPM_TX_64("TX 64 channels mode", 0),
4496         HDSPM_C_TMS("Clear Track Marker", 0),
4497         HDSPM_SAFE_MODE("Safe Mode", 0),
4498         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4499 };
4500
4501 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4502         HDSPM_MIXER("Mixer", 0),
4503         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4504         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4505         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4506         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4507         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4508         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4509         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4510         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4511         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4512         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4513         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4514         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4515         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4516         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4517         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4518         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4519         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4520         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4521
4522                 /*
4523                    HDSPM_INPUT_SELECT("Input Select", 0),
4524                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4525                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4526                    HDSPM_SPDIF_IN("SPDIF In", 0);
4527                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4528                    HDSPM_INPUT_LEVEL("Input Level", 0);
4529                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4530                    HDSPM_PHONES("Phones", 0);
4531                    */
4532 };
4533
4534 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4535         HDSPM_MIXER("Mixer", 0),
4536         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4537         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4538         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4539         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4540         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4541         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4542         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4543         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4544         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4545         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4546         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4547         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4548         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4549         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4550         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4551         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4552         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4553         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4554         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4555         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4556         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4557         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4558 };
4559
4560 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4561         HDSPM_MIXER("Mixer", 0),
4562         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4563         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4564         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4565         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4566         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4567         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4568         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4569         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4570         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4571         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4572         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4573         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4574         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4575         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4576         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4577         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4578         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4579         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4580         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4581         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4582         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4583         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4584         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4585         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4586         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4587         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4588         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4589         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4590         HDSPM_LINE_OUT("Line Out", 0),
4591         HDSPM_EMPHASIS("Emphasis", 0),
4592         HDSPM_DOLBY("Non Audio", 0),
4593         HDSPM_PROFESSIONAL("Professional", 0),
4594         HDSPM_C_TMS("Clear Track Marker", 0),
4595         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4596         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4597 };
4598
4599
4600
4601 /* Control elements for the optional TCO module */
4602 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4603         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4604         HDSPM_TCO_PULL("TCO Pull", 0),
4605         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4606         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4607         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4608         HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4609 };
4610
4611
4612 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4613
4614
4615 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4616 {
4617         int i;
4618
4619         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4620                 if (hdspm->system_sample_rate > 48000) {
4621                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4622                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4623                                 SNDRV_CTL_ELEM_ACCESS_READ |
4624                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4625                 } else {
4626                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4627                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4628                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4629                 }
4630                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4631                                 SNDRV_CTL_EVENT_MASK_INFO,
4632                                 &hdspm->playback_mixer_ctls[i]->id);
4633         }
4634
4635         return 0;
4636 }
4637
4638
4639 static int snd_hdspm_create_controls(struct snd_card *card,
4640                                         struct hdspm *hdspm)
4641 {
4642         unsigned int idx, limit;
4643         int err;
4644         struct snd_kcontrol *kctl;
4645         struct snd_kcontrol_new *list = NULL;
4646
4647         switch (hdspm->io_type) {
4648         case MADI:
4649                 list = snd_hdspm_controls_madi;
4650                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4651                 break;
4652         case MADIface:
4653                 list = snd_hdspm_controls_madiface;
4654                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4655                 break;
4656         case AIO:
4657                 list = snd_hdspm_controls_aio;
4658                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4659                 break;
4660         case RayDAT:
4661                 list = snd_hdspm_controls_raydat;
4662                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4663                 break;
4664         case AES32:
4665                 list = snd_hdspm_controls_aes32;
4666                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4667                 break;
4668         }
4669
4670         if (NULL != list) {
4671                 for (idx = 0; idx < limit; idx++) {
4672                         err = snd_ctl_add(card,
4673                                         snd_ctl_new1(&list[idx], hdspm));
4674                         if (err < 0)
4675                                 return err;
4676                 }
4677         }
4678
4679
4680         /* create simple 1:1 playback mixer controls */
4681         snd_hdspm_playback_mixer.name = "Chn";
4682         if (hdspm->system_sample_rate >= 128000) {
4683                 limit = hdspm->qs_out_channels;
4684         } else if (hdspm->system_sample_rate >= 64000) {
4685                 limit = hdspm->ds_out_channels;
4686         } else {
4687                 limit = hdspm->ss_out_channels;
4688         }
4689         for (idx = 0; idx < limit; ++idx) {
4690                 snd_hdspm_playback_mixer.index = idx + 1;
4691                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4692                 err = snd_ctl_add(card, kctl);
4693                 if (err < 0)
4694                         return err;
4695                 hdspm->playback_mixer_ctls[idx] = kctl;
4696         }
4697
4698
4699         if (hdspm->tco) {
4700                 /* add tco control elements */
4701                 list = snd_hdspm_controls_tco;
4702                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4703                 for (idx = 0; idx < limit; idx++) {
4704                         err = snd_ctl_add(card,
4705                                         snd_ctl_new1(&list[idx], hdspm));
4706                         if (err < 0)
4707                                 return err;
4708                 }
4709         }
4710
4711         return 0;
4712 }
4713
4714 /*------------------------------------------------------------
4715    /proc interface
4716  ------------------------------------------------------------*/
4717
4718 static void
4719 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4720                          struct snd_info_buffer *buffer)
4721 {
4722         struct hdspm *hdspm = entry->private_data;
4723         unsigned int status, status2, control, freq;
4724
4725         char *pref_sync_ref;
4726         char *autosync_ref;
4727         char *system_clock_mode;
4728         char *insel;
4729         int x, x2;
4730
4731         /* TCO stuff */
4732         int a, ltc, frames, seconds, minutes, hours;
4733         unsigned int period;
4734         u64 freq_const = 0;
4735         u32 rate;
4736
4737         status = hdspm_read(hdspm, HDSPM_statusRegister);
4738         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4739         control = hdspm->control_register;
4740         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4741
4742         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4743                         hdspm->card_name, hdspm->card->number + 1,
4744                         hdspm->firmware_rev,
4745                         (status2 & HDSPM_version0) |
4746                         (status2 & HDSPM_version1) | (status2 &
4747                                 HDSPM_version2));
4748
4749         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4750                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4751                         hdspm->serial);
4752
4753         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4754                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4755
4756         snd_iprintf(buffer, "--- System ---\n");
4757
4758         snd_iprintf(buffer,
4759                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4760                 status & HDSPM_audioIRQPending,
4761                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4762                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4763                 hdspm->irq_count);
4764         snd_iprintf(buffer,
4765                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4766                 "estimated= %ld (bytes)\n",
4767                 ((status & HDSPM_BufferID) ? 1 : 0),
4768                 (status & HDSPM_BufferPositionMask),
4769                 (status & HDSPM_BufferPositionMask) %
4770                 (2 * (int)hdspm->period_bytes),
4771                 ((status & HDSPM_BufferPositionMask) - 64) %
4772                 (2 * (int)hdspm->period_bytes),
4773                 (long) hdspm_hw_pointer(hdspm) * 4);
4774
4775         snd_iprintf(buffer,
4776                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4777                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4778                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4779                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4780                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4781         snd_iprintf(buffer,
4782                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4783                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4784                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4785         snd_iprintf(buffer,
4786                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4787                 "status2=0x%x\n",
4788                 hdspm->control_register, hdspm->control2_register,
4789                 status, status2);
4790         if (status & HDSPM_tco_detect) {
4791                 snd_iprintf(buffer, "TCO module detected.\n");
4792                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4793                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4794                         snd_iprintf(buffer, "  LTC valid, ");
4795                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4796                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4797                         case 0:
4798                                 snd_iprintf(buffer, "24 fps, ");
4799                                 break;
4800                         case HDSPM_TCO1_LTC_Format_LSB:
4801                                 snd_iprintf(buffer, "25 fps, ");
4802                                 break;
4803                         case HDSPM_TCO1_LTC_Format_MSB:
4804                                 snd_iprintf(buffer, "29.97 fps, ");
4805                                 break;
4806                         default:
4807                                 snd_iprintf(buffer, "30 fps, ");
4808                                 break;
4809                         }
4810                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4811                                 snd_iprintf(buffer, "drop frame\n");
4812                         } else {
4813                                 snd_iprintf(buffer, "full frame\n");
4814                         }
4815                 } else {
4816                         snd_iprintf(buffer, "  no LTC\n");
4817                 }
4818                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4819                         snd_iprintf(buffer, "  Video: NTSC\n");
4820                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4821                         snd_iprintf(buffer, "  Video: PAL\n");
4822                 } else {
4823                         snd_iprintf(buffer, "  No video\n");
4824                 }
4825                 if (a & HDSPM_TCO1_TCO_lock) {
4826                         snd_iprintf(buffer, "  Sync: lock\n");
4827                 } else {
4828                         snd_iprintf(buffer, "  Sync: no lock\n");
4829                 }
4830
4831                 switch (hdspm->io_type) {
4832                 case MADI:
4833                 case AES32:
4834                         freq_const = 110069313433624ULL;
4835                         break;
4836                 case RayDAT:
4837                 case AIO:
4838                         freq_const = 104857600000000ULL;
4839                         break;
4840                 case MADIface:
4841                         break; /* no TCO possible */
4842                 }
4843
4844                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4845                 snd_iprintf(buffer, "    period: %u\n", period);
4846
4847
4848                 /* rate = freq_const/period; */
4849                 rate = div_u64(freq_const, period);
4850
4851                 if (control & HDSPM_QuadSpeed) {
4852                         rate *= 4;
4853                 } else if (control & HDSPM_DoubleSpeed) {
4854                         rate *= 2;
4855                 }
4856
4857                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4858                                 (unsigned int) rate);
4859
4860                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4861                 frames = ltc & 0xF;
4862                 ltc >>= 4;
4863                 frames += (ltc & 0x3) * 10;
4864                 ltc >>= 4;
4865                 seconds = ltc & 0xF;
4866                 ltc >>= 4;
4867                 seconds += (ltc & 0x7) * 10;
4868                 ltc >>= 4;
4869                 minutes = ltc & 0xF;
4870                 ltc >>= 4;
4871                 minutes += (ltc & 0x7) * 10;
4872                 ltc >>= 4;
4873                 hours = ltc & 0xF;
4874                 ltc >>= 4;
4875                 hours += (ltc & 0x3) * 10;
4876                 snd_iprintf(buffer,
4877                         "  LTC In: %02d:%02d:%02d:%02d\n",
4878                         hours, minutes, seconds, frames);
4879
4880         } else {
4881                 snd_iprintf(buffer, "No TCO module detected.\n");
4882         }
4883
4884         snd_iprintf(buffer, "--- Settings ---\n");
4885
4886         x = hdspm_get_latency(hdspm);
4887
4888         snd_iprintf(buffer,
4889                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4890                 x, (unsigned long) hdspm->period_bytes);
4891
4892         snd_iprintf(buffer, "Line out: %s\n",
4893                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4894
4895         switch (hdspm->control_register & HDSPM_InputMask) {
4896         case HDSPM_InputOptical:
4897                 insel = "Optical";
4898                 break;
4899         case HDSPM_InputCoaxial:
4900                 insel = "Coaxial";
4901                 break;
4902         default:
4903                 insel = "Unknown";
4904         }
4905
4906         snd_iprintf(buffer,
4907                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4908                 "Auto Input %s\n",
4909                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4910                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4911                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4912
4913
4914         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4915                 system_clock_mode = "AutoSync";
4916         else
4917                 system_clock_mode = "Master";
4918         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4919
4920         switch (hdspm_pref_sync_ref(hdspm)) {
4921         case HDSPM_SYNC_FROM_WORD:
4922                 pref_sync_ref = "Word Clock";
4923                 break;
4924         case HDSPM_SYNC_FROM_MADI:
4925                 pref_sync_ref = "MADI Sync";
4926                 break;
4927         case HDSPM_SYNC_FROM_TCO:
4928                 pref_sync_ref = "TCO";
4929                 break;
4930         case HDSPM_SYNC_FROM_SYNC_IN:
4931                 pref_sync_ref = "Sync In";
4932                 break;
4933         default:
4934                 pref_sync_ref = "XXXX Clock";
4935                 break;
4936         }
4937         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4938                         pref_sync_ref);
4939
4940         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4941                         hdspm->system_sample_rate);
4942
4943
4944         snd_iprintf(buffer, "--- Status:\n");
4945
4946         x = status & HDSPM_madiSync;
4947         x2 = status2 & HDSPM_wcSync;
4948
4949         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4950                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4951                         "NoLock",
4952                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4953                         "NoLock");
4954
4955         switch (hdspm_autosync_ref(hdspm)) {
4956         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4957                 autosync_ref = "Sync In";
4958                 break;
4959         case HDSPM_AUTOSYNC_FROM_TCO:
4960                 autosync_ref = "TCO";
4961                 break;
4962         case HDSPM_AUTOSYNC_FROM_WORD:
4963                 autosync_ref = "Word Clock";
4964                 break;
4965         case HDSPM_AUTOSYNC_FROM_MADI:
4966                 autosync_ref = "MADI Sync";
4967                 break;
4968         case HDSPM_AUTOSYNC_FROM_NONE:
4969                 autosync_ref = "Input not valid";
4970                 break;
4971         default:
4972                 autosync_ref = "---";
4973                 break;
4974         }
4975         snd_iprintf(buffer,
4976                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4977                 autosync_ref, hdspm_external_sample_rate(hdspm),
4978                 (status & HDSPM_madiFreqMask) >> 22,
4979                 (status2 & HDSPM_wcFreqMask) >> 5);
4980
4981         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4982                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4983                 (status & HDSPM_RX_64ch) ? "64 channels" :
4984                 "56 channels");
4985
4986         snd_iprintf(buffer, "\n");
4987 }
4988
4989 static void
4990 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4991                           struct snd_info_buffer *buffer)
4992 {
4993         struct hdspm *hdspm = entry->private_data;
4994         unsigned int status;
4995         unsigned int status2;
4996         unsigned int timecode;
4997         int pref_syncref;
4998         char *autosync_ref;
4999         int x;
5000
5001         status = hdspm_read(hdspm, HDSPM_statusRegister);
5002         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5003         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5004
5005         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5006                     hdspm->card_name, hdspm->card->number + 1,
5007                     hdspm->firmware_rev);
5008
5009         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5010                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5011
5012         snd_iprintf(buffer, "--- System ---\n");
5013
5014         snd_iprintf(buffer,
5015                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5016                     status & HDSPM_audioIRQPending,
5017                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5018                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5019                     hdspm->irq_count);
5020         snd_iprintf(buffer,
5021                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5022                     "estimated= %ld (bytes)\n",
5023                     ((status & HDSPM_BufferID) ? 1 : 0),
5024                     (status & HDSPM_BufferPositionMask),
5025                     (status & HDSPM_BufferPositionMask) %
5026                     (2 * (int)hdspm->period_bytes),
5027                     ((status & HDSPM_BufferPositionMask) - 64) %
5028                     (2 * (int)hdspm->period_bytes),
5029                     (long) hdspm_hw_pointer(hdspm) * 4);
5030
5031         snd_iprintf(buffer,
5032                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5033                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5034                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5035                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5036                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5037         snd_iprintf(buffer,
5038                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5039                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5040                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5041         snd_iprintf(buffer,
5042                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5043                     "status2=0x%x\n",
5044                     hdspm->control_register, hdspm->control2_register,
5045                     status, status2);
5046
5047         snd_iprintf(buffer, "--- Settings ---\n");
5048
5049         x = hdspm_get_latency(hdspm);
5050
5051         snd_iprintf(buffer,
5052                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5053                     x, (unsigned long) hdspm->period_bytes);
5054
5055         snd_iprintf(buffer, "Line out: %s\n",
5056                     (hdspm->
5057                      control_register & HDSPM_LineOut) ? "on " : "off");
5058
5059         snd_iprintf(buffer,
5060                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5061                     (hdspm->
5062                      control_register & HDSPM_clr_tms) ? "on" : "off",
5063                     (hdspm->
5064                      control_register & HDSPM_Emphasis) ? "on" : "off",
5065                     (hdspm->
5066                      control_register & HDSPM_Dolby) ? "on" : "off");
5067
5068
5069         pref_syncref = hdspm_pref_sync_ref(hdspm);
5070         if (pref_syncref == 0)
5071                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5072         else
5073                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5074                                 pref_syncref);
5075
5076         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5077                     hdspm->system_sample_rate);
5078
5079         snd_iprintf(buffer, "Double speed: %s\n",
5080                         hdspm->control_register & HDSPM_DS_DoubleWire?
5081                         "Double wire" : "Single wire");
5082         snd_iprintf(buffer, "Quad speed: %s\n",
5083                         hdspm->control_register & HDSPM_QS_DoubleWire?
5084                         "Double wire" :
5085                         hdspm->control_register & HDSPM_QS_QuadWire?
5086                         "Quad wire" : "Single wire");
5087
5088         snd_iprintf(buffer, "--- Status:\n");
5089
5090         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5091                     (status & HDSPM_AES32_wcLock) ? "Sync   " : "No Lock",
5092                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5093
5094         for (x = 0; x < 8; x++) {
5095                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5096                             x+1,
5097                             (status2 & (HDSPM_LockAES >> x)) ?
5098                             "Sync   " : "No Lock",
5099                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5100         }
5101
5102         switch (hdspm_autosync_ref(hdspm)) {
5103         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5104                 autosync_ref = "None"; break;
5105         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5106                 autosync_ref = "Word Clock"; break;
5107         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5108                 autosync_ref = "AES1"; break;
5109         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5110                 autosync_ref = "AES2"; break;
5111         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5112                 autosync_ref = "AES3"; break;
5113         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5114                 autosync_ref = "AES4"; break;
5115         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5116                 autosync_ref = "AES5"; break;
5117         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5118                 autosync_ref = "AES6"; break;
5119         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5120                 autosync_ref = "AES7"; break;
5121         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5122                 autosync_ref = "AES8"; break;
5123         default:
5124                 autosync_ref = "---"; break;
5125         }
5126         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5127
5128         snd_iprintf(buffer, "\n");
5129 }
5130
5131 static void
5132 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5133                          struct snd_info_buffer *buffer)
5134 {
5135         struct hdspm *hdspm = entry->private_data;
5136         unsigned int status1, status2, status3, control, i;
5137         unsigned int lock, sync;
5138
5139         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5140         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5141         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5142
5143         control = hdspm->control_register;
5144
5145         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5146         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5147         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5148
5149
5150         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5151
5152         snd_iprintf(buffer, "Clock mode      : %s\n",
5153                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5154         snd_iprintf(buffer, "System frequency: %d Hz\n",
5155                 hdspm_get_system_sample_rate(hdspm));
5156
5157         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5158
5159         lock = 0x1;
5160         sync = 0x100;
5161
5162         for (i = 0; i < 8; i++) {
5163                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5164                                 i,
5165                                 (status1 & lock) ? 1 : 0,
5166                                 (status1 & sync) ? 1 : 0,
5167                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5168
5169                 lock = lock<<1;
5170                 sync = sync<<1;
5171         }
5172
5173         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5174                         (status1 & 0x1000000) ? 1 : 0,
5175                         (status1 & 0x2000000) ? 1 : 0,
5176                         texts_freq[(status1 >> 16) & 0xF]);
5177
5178         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5179                         (status1 & 0x4000000) ? 1 : 0,
5180                         (status1 & 0x8000000) ? 1 : 0,
5181                         texts_freq[(status1 >> 20) & 0xF]);
5182
5183         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5184                         (status3 & 0x400) ? 1 : 0,
5185                         (status3 & 0x800) ? 1 : 0,
5186                         texts_freq[(status2 >> 12) & 0xF]);
5187
5188 }
5189
5190 #ifdef CONFIG_SND_DEBUG
5191 static void
5192 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5193                           struct snd_info_buffer *buffer)
5194 {
5195         struct hdspm *hdspm = entry->private_data;
5196
5197         int j,i;
5198
5199         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5200                 snd_iprintf(buffer, "0x%08X: ", i);
5201                 for (j = 0; j < 16; j += 4)
5202                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5203                 snd_iprintf(buffer, "\n");
5204         }
5205 }
5206 #endif
5207
5208
5209 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5210                           struct snd_info_buffer *buffer)
5211 {
5212         struct hdspm *hdspm = entry->private_data;
5213         int i;
5214
5215         snd_iprintf(buffer, "# generated by hdspm\n");
5216
5217         for (i = 0; i < hdspm->max_channels_in; i++) {
5218                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5219         }
5220 }
5221
5222 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5223                           struct snd_info_buffer *buffer)
5224 {
5225         struct hdspm *hdspm = entry->private_data;
5226         int i;
5227
5228         snd_iprintf(buffer, "# generated by hdspm\n");
5229
5230         for (i = 0; i < hdspm->max_channels_out; i++) {
5231                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5232         }
5233 }
5234
5235
5236 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5237 {
5238         struct snd_info_entry *entry;
5239
5240         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5241                 switch (hdspm->io_type) {
5242                 case AES32:
5243                         snd_info_set_text_ops(entry, hdspm,
5244                                         snd_hdspm_proc_read_aes32);
5245                         break;
5246                 case MADI:
5247                         snd_info_set_text_ops(entry, hdspm,
5248                                         snd_hdspm_proc_read_madi);
5249                         break;
5250                 case MADIface:
5251                         /* snd_info_set_text_ops(entry, hdspm,
5252                          snd_hdspm_proc_read_madiface); */
5253                         break;
5254                 case RayDAT:
5255                         snd_info_set_text_ops(entry, hdspm,
5256                                         snd_hdspm_proc_read_raydat);
5257                         break;
5258                 case AIO:
5259                         break;
5260                 }
5261         }
5262
5263         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5264                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5265         }
5266
5267         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5268                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5269         }
5270
5271 #ifdef CONFIG_SND_DEBUG
5272         /* debug file to read all hdspm registers */
5273         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5274                 snd_info_set_text_ops(entry, hdspm,
5275                                 snd_hdspm_proc_read_debug);
5276 #endif
5277 }
5278
5279 /*------------------------------------------------------------
5280    hdspm intitialize
5281  ------------------------------------------------------------*/
5282
5283 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5284 {
5285         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5286            hold it (e.g. during module initialization).
5287            */
5288
5289         /* set defaults:       */
5290
5291         hdspm->settings_register = 0;
5292
5293         switch (hdspm->io_type) {
5294         case MADI:
5295         case MADIface:
5296                 hdspm->control_register =
5297                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5298                 break;
5299
5300         case RayDAT:
5301         case AIO:
5302                 hdspm->settings_register = 0x1 + 0x1000;
5303                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5304                  * line_out */
5305                 hdspm->control_register =
5306                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5307                 break;
5308
5309         case AES32:
5310                 hdspm->control_register =
5311                         HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5312                         hdspm_encode_latency(7) | /* latency max=8192samples */
5313                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5314                         HDSPM_LineOut | /* Analog output in */
5315                         HDSPM_Professional;  /* Professional mode */
5316                 break;
5317         }
5318
5319         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5320
5321         if (AES32 == hdspm->io_type) {
5322                 /* No control2 register for AES32 */
5323 #ifdef SNDRV_BIG_ENDIAN
5324                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5325 #else
5326                 hdspm->control2_register = 0;
5327 #endif
5328
5329                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5330         }
5331         hdspm_compute_period_size(hdspm);
5332
5333         /* silence everything */
5334
5335         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5336
5337         if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5338                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5339         }
5340
5341         /* set a default rate so that the channel map is set up. */
5342         hdspm_set_rate(hdspm, 48000, 1);
5343
5344         return 0;
5345 }
5346
5347
5348 /*------------------------------------------------------------
5349    interrupt
5350  ------------------------------------------------------------*/
5351
5352 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5353 {
5354         struct hdspm *hdspm = (struct hdspm *) dev_id;
5355         unsigned int status;
5356         int i, audio, midi, schedule = 0;
5357         /* cycles_t now; */
5358
5359         status = hdspm_read(hdspm, HDSPM_statusRegister);
5360
5361         audio = status & HDSPM_audioIRQPending;
5362         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5363                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5364
5365         /* now = get_cycles(); */
5366         /**
5367          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5368          *          6       4096   ~256053425     ~514672358
5369          *          5       2048   ~128024983     ~257373821
5370          *          4       1024    ~64023706     ~128718089
5371          *          3        512    ~32005945      ~64385999
5372          *          2        256    ~16003039      ~32260176
5373          *          1        128     ~7998738      ~16194507
5374          *          0         64     ~3998231       ~8191558
5375          **/
5376         /*
5377            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5378            now-hdspm->last_interrupt, status & 0xFFC0);
5379            hdspm->last_interrupt = now;
5380         */
5381
5382         if (!audio && !midi)
5383                 return IRQ_NONE;
5384
5385         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5386         hdspm->irq_count++;
5387
5388
5389         if (audio) {
5390                 if (hdspm->capture_substream)
5391                         snd_pcm_period_elapsed(hdspm->capture_substream);
5392
5393                 if (hdspm->playback_substream)
5394                         snd_pcm_period_elapsed(hdspm->playback_substream);
5395         }
5396
5397         if (midi) {
5398                 i = 0;
5399                 while (i < hdspm->midiPorts) {
5400                         if ((hdspm_read(hdspm,
5401                                 hdspm->midi[i].statusIn) & 0xff) &&
5402                                         (status & hdspm->midi[i].irq)) {
5403                                 /* we disable interrupts for this input until
5404                                  * processing is done
5405                                  */
5406                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5407                                 hdspm_write(hdspm, HDSPM_controlRegister,
5408                                                 hdspm->control_register);
5409                                 hdspm->midi[i].pending = 1;
5410                                 schedule = 1;
5411                         }
5412
5413                         i++;
5414                 }
5415
5416                 if (schedule)
5417                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5418         }
5419
5420         return IRQ_HANDLED;
5421 }
5422
5423 /*------------------------------------------------------------
5424    pcm interface
5425   ------------------------------------------------------------*/
5426
5427
5428 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5429                                               *substream)
5430 {
5431         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5432         return hdspm_hw_pointer(hdspm);
5433 }
5434
5435
5436 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5437 {
5438         struct snd_pcm_runtime *runtime = substream->runtime;
5439         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5440         struct snd_pcm_substream *other;
5441
5442         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5443                 other = hdspm->capture_substream;
5444         else
5445                 other = hdspm->playback_substream;
5446
5447         if (hdspm->running)
5448                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5449         else
5450                 runtime->status->hw_ptr = 0;
5451         if (other) {
5452                 struct snd_pcm_substream *s;
5453                 struct snd_pcm_runtime *oruntime = other->runtime;
5454                 snd_pcm_group_for_each_entry(s, substream) {
5455                         if (s == other) {
5456                                 oruntime->status->hw_ptr =
5457                                         runtime->status->hw_ptr;
5458                                 break;
5459                         }
5460                 }
5461         }
5462         return 0;
5463 }
5464
5465 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5466                                struct snd_pcm_hw_params *params)
5467 {
5468         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5469         int err;
5470         int i;
5471         pid_t this_pid;
5472         pid_t other_pid;
5473
5474         spin_lock_irq(&hdspm->lock);
5475
5476         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5477                 this_pid = hdspm->playback_pid;
5478                 other_pid = hdspm->capture_pid;
5479         } else {
5480                 this_pid = hdspm->capture_pid;
5481                 other_pid = hdspm->playback_pid;
5482         }
5483
5484         if (other_pid > 0 && this_pid != other_pid) {
5485
5486                 /* The other stream is open, and not by the same
5487                    task as this one. Make sure that the parameters
5488                    that matter are the same.
5489                    */
5490
5491                 if (params_rate(params) != hdspm->system_sample_rate) {
5492                         spin_unlock_irq(&hdspm->lock);
5493                         _snd_pcm_hw_param_setempty(params,
5494                                         SNDRV_PCM_HW_PARAM_RATE);
5495                         return -EBUSY;
5496                 }
5497
5498                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5499                         spin_unlock_irq(&hdspm->lock);
5500                         _snd_pcm_hw_param_setempty(params,
5501                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5502                         return -EBUSY;
5503                 }
5504
5505         }
5506         /* We're fine. */
5507         spin_unlock_irq(&hdspm->lock);
5508
5509         /* how to make sure that the rate matches an externally-set one ?   */
5510
5511         spin_lock_irq(&hdspm->lock);
5512         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5513         if (err < 0) {
5514                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5515                 spin_unlock_irq(&hdspm->lock);
5516                 _snd_pcm_hw_param_setempty(params,
5517                                 SNDRV_PCM_HW_PARAM_RATE);
5518                 return err;
5519         }
5520         spin_unlock_irq(&hdspm->lock);
5521
5522         err = hdspm_set_interrupt_interval(hdspm,
5523                         params_period_size(params));
5524         if (err < 0) {
5525                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5526                 _snd_pcm_hw_param_setempty(params,
5527                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5528                 return err;
5529         }
5530
5531         /* Memory allocation, takashi's method, dont know if we should
5532          * spinlock
5533          */
5534         /* malloc all buffer even if not enabled to get sure */
5535         /* Update for MADI rev 204: we need to allocate for all channels,
5536          * otherwise it doesn't work at 96kHz */
5537
5538         err =
5539                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5540         if (err < 0) {
5541                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5542                 return err;
5543         }
5544
5545         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5546
5547                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5548                                 params_channels(params));
5549
5550                 for (i = 0; i < params_channels(params); ++i)
5551                         snd_hdspm_enable_out(hdspm, i, 1);
5552
5553                 hdspm->playback_buffer =
5554                         (unsigned char *) substream->runtime->dma_area;
5555                 snd_printdd("Allocated sample buffer for playback at %p\n",
5556                                 hdspm->playback_buffer);
5557         } else {
5558                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5559                                 params_channels(params));
5560
5561                 for (i = 0; i < params_channels(params); ++i)
5562                         snd_hdspm_enable_in(hdspm, i, 1);
5563
5564                 hdspm->capture_buffer =
5565                         (unsigned char *) substream->runtime->dma_area;
5566                 snd_printdd("Allocated sample buffer for capture at %p\n",
5567                                 hdspm->capture_buffer);
5568         }
5569
5570         /*
5571            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5572            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5573            "playback" : "capture",
5574            snd_pcm_sgbuf_get_addr(substream, 0));
5575            */
5576         /*
5577            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5578            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5579            "playback" : "capture",
5580            params_rate(params), params_channels(params),
5581            params_buffer_size(params));
5582            */
5583
5584
5585         /* Switch to native float format if requested */
5586         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5587                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5588                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5589
5590                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5591         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5592                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5593                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5594
5595                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5596         }
5597         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5598
5599         return 0;
5600 }
5601
5602 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5603 {
5604         int i;
5605         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5606
5607         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5608
5609                 /* params_channels(params) should be enough,
5610                    but to get sure in case of error */
5611                 for (i = 0; i < hdspm->max_channels_out; ++i)
5612                         snd_hdspm_enable_out(hdspm, i, 0);
5613
5614                 hdspm->playback_buffer = NULL;
5615         } else {
5616                 for (i = 0; i < hdspm->max_channels_in; ++i)
5617                         snd_hdspm_enable_in(hdspm, i, 0);
5618
5619                 hdspm->capture_buffer = NULL;
5620
5621         }
5622
5623         snd_pcm_lib_free_pages(substream);
5624
5625         return 0;
5626 }
5627
5628
5629 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5630                 struct snd_pcm_channel_info *info)
5631 {
5632         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5633
5634         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5635                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5636                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5637                         return -EINVAL;
5638                 }
5639
5640                 if (hdspm->channel_map_out[info->channel] < 0) {
5641                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5642                         return -EINVAL;
5643                 }
5644
5645                 info->offset = hdspm->channel_map_out[info->channel] *
5646                         HDSPM_CHANNEL_BUFFER_BYTES;
5647         } else {
5648                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5649                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5650                         return -EINVAL;
5651                 }
5652
5653                 if (hdspm->channel_map_in[info->channel] < 0) {
5654                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5655                         return -EINVAL;
5656                 }
5657
5658                 info->offset = hdspm->channel_map_in[info->channel] *
5659                         HDSPM_CHANNEL_BUFFER_BYTES;
5660         }
5661
5662         info->first = 0;
5663         info->step = 32;
5664         return 0;
5665 }
5666
5667
5668 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5669                 unsigned int cmd, void *arg)
5670 {
5671         switch (cmd) {
5672         case SNDRV_PCM_IOCTL1_RESET:
5673                 return snd_hdspm_reset(substream);
5674
5675         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5676                 {
5677                         struct snd_pcm_channel_info *info = arg;
5678                         return snd_hdspm_channel_info(substream, info);
5679                 }
5680         default:
5681                 break;
5682         }
5683
5684         return snd_pcm_lib_ioctl(substream, cmd, arg);
5685 }
5686
5687 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5688 {
5689         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5690         struct snd_pcm_substream *other;
5691         int running;
5692
5693         spin_lock(&hdspm->lock);
5694         running = hdspm->running;
5695         switch (cmd) {
5696         case SNDRV_PCM_TRIGGER_START:
5697                 running |= 1 << substream->stream;
5698                 break;
5699         case SNDRV_PCM_TRIGGER_STOP:
5700                 running &= ~(1 << substream->stream);
5701                 break;
5702         default:
5703                 snd_BUG();
5704                 spin_unlock(&hdspm->lock);
5705                 return -EINVAL;
5706         }
5707         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5708                 other = hdspm->capture_substream;
5709         else
5710                 other = hdspm->playback_substream;
5711
5712         if (other) {
5713                 struct snd_pcm_substream *s;
5714                 snd_pcm_group_for_each_entry(s, substream) {
5715                         if (s == other) {
5716                                 snd_pcm_trigger_done(s, substream);
5717                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5718                                         running |= 1 << s->stream;
5719                                 else
5720                                         running &= ~(1 << s->stream);
5721                                 goto _ok;
5722                         }
5723                 }
5724                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5725                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5726                                         && substream->stream ==
5727                                         SNDRV_PCM_STREAM_CAPTURE)
5728                                 hdspm_silence_playback(hdspm);
5729                 } else {
5730                         if (running &&
5731                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5732                                 hdspm_silence_playback(hdspm);
5733                 }
5734         } else {
5735                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5736                         hdspm_silence_playback(hdspm);
5737         }
5738 _ok:
5739         snd_pcm_trigger_done(substream, substream);
5740         if (!hdspm->running && running)
5741                 hdspm_start_audio(hdspm);
5742         else if (hdspm->running && !running)
5743                 hdspm_stop_audio(hdspm);
5744         hdspm->running = running;
5745         spin_unlock(&hdspm->lock);
5746
5747         return 0;
5748 }
5749
5750 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5751 {
5752         return 0;
5753 }
5754
5755 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5756         .info = (SNDRV_PCM_INFO_MMAP |
5757                  SNDRV_PCM_INFO_MMAP_VALID |
5758                  SNDRV_PCM_INFO_NONINTERLEAVED |
5759                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5760         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5761         .rates = (SNDRV_PCM_RATE_32000 |
5762                   SNDRV_PCM_RATE_44100 |
5763                   SNDRV_PCM_RATE_48000 |
5764                   SNDRV_PCM_RATE_64000 |
5765                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5766                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5767         .rate_min = 32000,
5768         .rate_max = 192000,
5769         .channels_min = 1,
5770         .channels_max = HDSPM_MAX_CHANNELS,
5771         .buffer_bytes_max =
5772             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5773         .period_bytes_min = (32 * 4),
5774         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5775         .periods_min = 2,
5776         .periods_max = 512,
5777         .fifo_size = 0
5778 };
5779
5780 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5781         .info = (SNDRV_PCM_INFO_MMAP |
5782                  SNDRV_PCM_INFO_MMAP_VALID |
5783                  SNDRV_PCM_INFO_NONINTERLEAVED |
5784                  SNDRV_PCM_INFO_SYNC_START),
5785         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5786         .rates = (SNDRV_PCM_RATE_32000 |
5787                   SNDRV_PCM_RATE_44100 |
5788                   SNDRV_PCM_RATE_48000 |
5789                   SNDRV_PCM_RATE_64000 |
5790                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5791                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5792         .rate_min = 32000,
5793         .rate_max = 192000,
5794         .channels_min = 1,
5795         .channels_max = HDSPM_MAX_CHANNELS,
5796         .buffer_bytes_max =
5797             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5798         .period_bytes_min = (32 * 4),
5799         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5800         .periods_min = 2,
5801         .periods_max = 512,
5802         .fifo_size = 0
5803 };
5804
5805 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5806                                            struct snd_pcm_hw_rule *rule)
5807 {
5808         struct hdspm *hdspm = rule->private;
5809         struct snd_interval *c =
5810             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5811         struct snd_interval *r =
5812             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5813
5814         if (r->min > 96000 && r->max <= 192000) {
5815                 struct snd_interval t = {
5816                         .min = hdspm->qs_in_channels,
5817                         .max = hdspm->qs_in_channels,
5818                         .integer = 1,
5819                 };
5820                 return snd_interval_refine(c, &t);
5821         } else if (r->min > 48000 && r->max <= 96000) {
5822                 struct snd_interval t = {
5823                         .min = hdspm->ds_in_channels,
5824                         .max = hdspm->ds_in_channels,
5825                         .integer = 1,
5826                 };
5827                 return snd_interval_refine(c, &t);
5828         } else if (r->max < 64000) {
5829                 struct snd_interval t = {
5830                         .min = hdspm->ss_in_channels,
5831                         .max = hdspm->ss_in_channels,
5832                         .integer = 1,
5833                 };
5834                 return snd_interval_refine(c, &t);
5835         }
5836
5837         return 0;
5838 }
5839
5840 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5841                                            struct snd_pcm_hw_rule * rule)
5842 {
5843         struct hdspm *hdspm = rule->private;
5844         struct snd_interval *c =
5845             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5846         struct snd_interval *r =
5847             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5848
5849         if (r->min > 96000 && r->max <= 192000) {
5850                 struct snd_interval t = {
5851                         .min = hdspm->qs_out_channels,
5852                         .max = hdspm->qs_out_channels,
5853                         .integer = 1,
5854                 };
5855                 return snd_interval_refine(c, &t);
5856         } else if (r->min > 48000 && r->max <= 96000) {
5857                 struct snd_interval t = {
5858                         .min = hdspm->ds_out_channels,
5859                         .max = hdspm->ds_out_channels,
5860                         .integer = 1,
5861                 };
5862                 return snd_interval_refine(c, &t);
5863         } else if (r->max < 64000) {
5864                 struct snd_interval t = {
5865                         .min = hdspm->ss_out_channels,
5866                         .max = hdspm->ss_out_channels,
5867                         .integer = 1,
5868                 };
5869                 return snd_interval_refine(c, &t);
5870         } else {
5871         }
5872         return 0;
5873 }
5874
5875 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5876                                            struct snd_pcm_hw_rule * rule)
5877 {
5878         struct hdspm *hdspm = rule->private;
5879         struct snd_interval *c =
5880             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5881         struct snd_interval *r =
5882             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5883
5884         if (c->min >= hdspm->ss_in_channels) {
5885                 struct snd_interval t = {
5886                         .min = 32000,
5887                         .max = 48000,
5888                         .integer = 1,
5889                 };
5890                 return snd_interval_refine(r, &t);
5891         } else if (c->max <= hdspm->qs_in_channels) {
5892                 struct snd_interval t = {
5893                         .min = 128000,
5894                         .max = 192000,
5895                         .integer = 1,
5896                 };
5897                 return snd_interval_refine(r, &t);
5898         } else if (c->max <= hdspm->ds_in_channels) {
5899                 struct snd_interval t = {
5900                         .min = 64000,
5901                         .max = 96000,
5902                         .integer = 1,
5903                 };
5904                 return snd_interval_refine(r, &t);
5905         }
5906
5907         return 0;
5908 }
5909 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5910                                            struct snd_pcm_hw_rule *rule)
5911 {
5912         struct hdspm *hdspm = rule->private;
5913         struct snd_interval *c =
5914             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5915         struct snd_interval *r =
5916             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5917
5918         if (c->min >= hdspm->ss_out_channels) {
5919                 struct snd_interval t = {
5920                         .min = 32000,
5921                         .max = 48000,
5922                         .integer = 1,
5923                 };
5924                 return snd_interval_refine(r, &t);
5925         } else if (c->max <= hdspm->qs_out_channels) {
5926                 struct snd_interval t = {
5927                         .min = 128000,
5928                         .max = 192000,
5929                         .integer = 1,
5930                 };
5931                 return snd_interval_refine(r, &t);
5932         } else if (c->max <= hdspm->ds_out_channels) {
5933                 struct snd_interval t = {
5934                         .min = 64000,
5935                         .max = 96000,
5936                         .integer = 1,
5937                 };
5938                 return snd_interval_refine(r, &t);
5939         }
5940
5941         return 0;
5942 }
5943
5944 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5945                                       struct snd_pcm_hw_rule *rule)
5946 {
5947         unsigned int list[3];
5948         struct hdspm *hdspm = rule->private;
5949         struct snd_interval *c = hw_param_interval(params,
5950                         SNDRV_PCM_HW_PARAM_CHANNELS);
5951
5952         list[0] = hdspm->qs_in_channels;
5953         list[1] = hdspm->ds_in_channels;
5954         list[2] = hdspm->ss_in_channels;
5955         return snd_interval_list(c, 3, list, 0);
5956 }
5957
5958 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5959                                       struct snd_pcm_hw_rule *rule)
5960 {
5961         unsigned int list[3];
5962         struct hdspm *hdspm = rule->private;
5963         struct snd_interval *c = hw_param_interval(params,
5964                         SNDRV_PCM_HW_PARAM_CHANNELS);
5965
5966         list[0] = hdspm->qs_out_channels;
5967         list[1] = hdspm->ds_out_channels;
5968         list[2] = hdspm->ss_out_channels;
5969         return snd_interval_list(c, 3, list, 0);
5970 }
5971
5972
5973 static unsigned int hdspm_aes32_sample_rates[] = {
5974         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5975 };
5976
5977 static struct snd_pcm_hw_constraint_list
5978 hdspm_hw_constraints_aes32_sample_rates = {
5979         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5980         .list = hdspm_aes32_sample_rates,
5981         .mask = 0
5982 };
5983
5984 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5985 {
5986         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5987         struct snd_pcm_runtime *runtime = substream->runtime;
5988
5989         spin_lock_irq(&hdspm->lock);
5990
5991         snd_pcm_set_sync(substream);
5992
5993
5994         runtime->hw = snd_hdspm_playback_subinfo;
5995
5996         if (hdspm->capture_substream == NULL)
5997                 hdspm_stop_audio(hdspm);
5998
5999         hdspm->playback_pid = current->pid;
6000         hdspm->playback_substream = substream;
6001
6002         spin_unlock_irq(&hdspm->lock);
6003
6004         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6005         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6006
6007         switch (hdspm->io_type) {
6008         case AIO:
6009         case RayDAT:
6010                 snd_pcm_hw_constraint_minmax(runtime,
6011                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6012                                              32, 4096);
6013                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6014                 snd_pcm_hw_constraint_minmax(runtime,
6015                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6016                                              16384, 16384);
6017                 break;
6018
6019         default:
6020                 snd_pcm_hw_constraint_minmax(runtime,
6021                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6022                                              64, 8192);
6023                 break;
6024         }
6025
6026         if (AES32 == hdspm->io_type) {
6027                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6028                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6029                                 &hdspm_hw_constraints_aes32_sample_rates);
6030         } else {
6031                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6032                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6033                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6034         }
6035
6036         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6037                         snd_hdspm_hw_rule_out_channels, hdspm,
6038                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6039
6040         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6041                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6042                         SNDRV_PCM_HW_PARAM_RATE, -1);
6043
6044         return 0;
6045 }
6046
6047 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6048 {
6049         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6050
6051         spin_lock_irq(&hdspm->lock);
6052
6053         hdspm->playback_pid = -1;
6054         hdspm->playback_substream = NULL;
6055
6056         spin_unlock_irq(&hdspm->lock);
6057
6058         return 0;
6059 }
6060
6061
6062 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6063 {
6064         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6065         struct snd_pcm_runtime *runtime = substream->runtime;
6066
6067         spin_lock_irq(&hdspm->lock);
6068         snd_pcm_set_sync(substream);
6069         runtime->hw = snd_hdspm_capture_subinfo;
6070
6071         if (hdspm->playback_substream == NULL)
6072                 hdspm_stop_audio(hdspm);
6073
6074         hdspm->capture_pid = current->pid;
6075         hdspm->capture_substream = substream;
6076
6077         spin_unlock_irq(&hdspm->lock);
6078
6079         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6080         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6081
6082         switch (hdspm->io_type) {
6083         case AIO:
6084         case RayDAT:
6085                 snd_pcm_hw_constraint_minmax(runtime,
6086                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6087                                              32, 4096);
6088                 snd_pcm_hw_constraint_minmax(runtime,
6089                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6090                                              16384, 16384);
6091                 break;
6092
6093         default:
6094                 snd_pcm_hw_constraint_minmax(runtime,
6095                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6096                                              64, 8192);
6097                 break;
6098         }
6099
6100         if (AES32 == hdspm->io_type) {
6101                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6102                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6103                                 &hdspm_hw_constraints_aes32_sample_rates);
6104         } else {
6105                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6106                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6107                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6108         }
6109
6110         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6111                         snd_hdspm_hw_rule_in_channels, hdspm,
6112                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6113
6114         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6115                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6116                         SNDRV_PCM_HW_PARAM_RATE, -1);
6117
6118         return 0;
6119 }
6120
6121 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6122 {
6123         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6124
6125         spin_lock_irq(&hdspm->lock);
6126
6127         hdspm->capture_pid = -1;
6128         hdspm->capture_substream = NULL;
6129
6130         spin_unlock_irq(&hdspm->lock);
6131         return 0;
6132 }
6133
6134 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6135 {
6136         /* we have nothing to initialize but the call is required */
6137         return 0;
6138 }
6139
6140 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6141 {
6142         u32 val = readl(src);
6143         return copy_to_user(dest, &val, 4);
6144 }
6145
6146 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6147                 unsigned int cmd, unsigned long arg)
6148 {
6149         void __user *argp = (void __user *)arg;
6150         struct hdspm *hdspm = hw->private_data;
6151         struct hdspm_mixer_ioctl mixer;
6152         struct hdspm_config info;
6153         struct hdspm_status status;
6154         struct hdspm_version hdspm_version;
6155         struct hdspm_peak_rms *levels;
6156         struct hdspm_ltc ltc;
6157         unsigned int statusregister;
6158         long unsigned int s;
6159         int i = 0;
6160
6161         switch (cmd) {
6162
6163         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6164                 levels = &hdspm->peak_rms;
6165                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6166                         levels->input_peaks[i] =
6167                                 readl(hdspm->iobase +
6168                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6169                         levels->playback_peaks[i] =
6170                                 readl(hdspm->iobase +
6171                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6172                         levels->output_peaks[i] =
6173                                 readl(hdspm->iobase +
6174                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6175
6176                         levels->input_rms[i] =
6177                                 ((uint64_t) readl(hdspm->iobase +
6178                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6179                                 (uint64_t) readl(hdspm->iobase +
6180                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6181                         levels->playback_rms[i] =
6182                                 ((uint64_t)readl(hdspm->iobase +
6183                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6184                                 (uint64_t)readl(hdspm->iobase +
6185                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6186                         levels->output_rms[i] =
6187                                 ((uint64_t)readl(hdspm->iobase +
6188                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6189                                 (uint64_t)readl(hdspm->iobase +
6190                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6191                 }
6192
6193                 if (hdspm->system_sample_rate > 96000) {
6194                         levels->speed = qs;
6195                 } else if (hdspm->system_sample_rate > 48000) {
6196                         levels->speed = ds;
6197                 } else {
6198                         levels->speed = ss;
6199                 }
6200                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6201
6202                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6203                 if (0 != s) {
6204                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6205                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6206                          */
6207                         return -EFAULT;
6208                 }
6209                 break;
6210
6211         case SNDRV_HDSPM_IOCTL_GET_LTC:
6212                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6213                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6214                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6215                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6216                                 HDSPM_TCO1_LTC_Format_MSB)) {
6217                         case 0:
6218                                 ltc.format = fps_24;
6219                                 break;
6220                         case HDSPM_TCO1_LTC_Format_LSB:
6221                                 ltc.format = fps_25;
6222                                 break;
6223                         case HDSPM_TCO1_LTC_Format_MSB:
6224                                 ltc.format = fps_2997;
6225                                 break;
6226                         default:
6227                                 ltc.format = 30;
6228                                 break;
6229                         }
6230                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6231                                 ltc.frame = drop_frame;
6232                         } else {
6233                                 ltc.frame = full_frame;
6234                         }
6235                 } else {
6236                         ltc.format = format_invalid;
6237                         ltc.frame = frame_invalid;
6238                 }
6239                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6240                         ltc.input_format = ntsc;
6241                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6242                         ltc.input_format = pal;
6243                 } else {
6244                         ltc.input_format = no_video;
6245                 }
6246
6247                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6248                 if (0 != s) {
6249                         /*
6250                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6251                         return -EFAULT;
6252                 }
6253
6254                 break;
6255
6256         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6257
6258                 memset(&info, 0, sizeof(info));
6259                 spin_lock_irq(&hdspm->lock);
6260                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6261                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6262
6263                 info.system_sample_rate = hdspm->system_sample_rate;
6264                 info.autosync_sample_rate =
6265                         hdspm_external_sample_rate(hdspm);
6266                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6267                 info.clock_source = hdspm_clock_source(hdspm);
6268                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6269                 info.line_out = hdspm_line_out(hdspm);
6270                 info.passthru = 0;
6271                 spin_unlock_irq(&hdspm->lock);
6272                 if (copy_to_user(argp, &info, sizeof(info)))
6273                         return -EFAULT;
6274                 break;
6275
6276         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6277                 memset(&status, 0, sizeof(status));
6278
6279                 status.card_type = hdspm->io_type;
6280
6281                 status.autosync_source = hdspm_autosync_ref(hdspm);
6282
6283                 status.card_clock = 110069313433624ULL;
6284                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6285
6286                 switch (hdspm->io_type) {
6287                 case MADI:
6288                 case MADIface:
6289                         status.card_specific.madi.sync_wc =
6290                                 hdspm_wc_sync_check(hdspm);
6291                         status.card_specific.madi.sync_madi =
6292                                 hdspm_madi_sync_check(hdspm);
6293                         status.card_specific.madi.sync_tco =
6294                                 hdspm_tco_sync_check(hdspm);
6295                         status.card_specific.madi.sync_in =
6296                                 hdspm_sync_in_sync_check(hdspm);
6297
6298                         statusregister =
6299                                 hdspm_read(hdspm, HDSPM_statusRegister);
6300                         status.card_specific.madi.madi_input =
6301                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6302                         status.card_specific.madi.channel_format =
6303                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6304                         /* TODO: Mac driver sets it when f_s>48kHz */
6305                         status.card_specific.madi.frame_format = 0;
6306
6307                 default:
6308                         break;
6309                 }
6310
6311                 if (copy_to_user(argp, &status, sizeof(status)))
6312                         return -EFAULT;
6313
6314
6315                 break;
6316
6317         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6318                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6319
6320                 hdspm_version.card_type = hdspm->io_type;
6321                 strncpy(hdspm_version.cardname, hdspm->card_name,
6322                                 sizeof(hdspm_version.cardname));
6323                 hdspm_version.serial = hdspm->serial;
6324                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6325                 hdspm_version.addons = 0;
6326                 if (hdspm->tco)
6327                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6328
6329                 if (copy_to_user(argp, &hdspm_version,
6330                                         sizeof(hdspm_version)))
6331                         return -EFAULT;
6332                 break;
6333
6334         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6335                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6336                         return -EFAULT;
6337                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6338                                         sizeof(struct hdspm_mixer)))
6339                         return -EFAULT;
6340                 break;
6341
6342         default:
6343                 return -EINVAL;
6344         }
6345         return 0;
6346 }
6347
6348 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6349         .open = snd_hdspm_playback_open,
6350         .close = snd_hdspm_playback_release,
6351         .ioctl = snd_hdspm_ioctl,
6352         .hw_params = snd_hdspm_hw_params,
6353         .hw_free = snd_hdspm_hw_free,
6354         .prepare = snd_hdspm_prepare,
6355         .trigger = snd_hdspm_trigger,
6356         .pointer = snd_hdspm_hw_pointer,
6357         .page = snd_pcm_sgbuf_ops_page,
6358 };
6359
6360 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6361         .open = snd_hdspm_capture_open,
6362         .close = snd_hdspm_capture_release,
6363         .ioctl = snd_hdspm_ioctl,
6364         .hw_params = snd_hdspm_hw_params,
6365         .hw_free = snd_hdspm_hw_free,
6366         .prepare = snd_hdspm_prepare,
6367         .trigger = snd_hdspm_trigger,
6368         .pointer = snd_hdspm_hw_pointer,
6369         .page = snd_pcm_sgbuf_ops_page,
6370 };
6371
6372 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6373                                             struct hdspm * hdspm)
6374 {
6375         struct snd_hwdep *hw;
6376         int err;
6377
6378         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6379         if (err < 0)
6380                 return err;
6381
6382         hdspm->hwdep = hw;
6383         hw->private_data = hdspm;
6384         strcpy(hw->name, "HDSPM hwdep interface");
6385
6386         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6387         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6388         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6389         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6390
6391         return 0;
6392 }
6393
6394
6395 /*------------------------------------------------------------
6396    memory interface
6397  ------------------------------------------------------------*/
6398 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6399 {
6400         int err;
6401         struct snd_pcm *pcm;
6402         size_t wanted;
6403
6404         pcm = hdspm->pcm;
6405
6406         wanted = HDSPM_DMA_AREA_BYTES;
6407
6408         err =
6409              snd_pcm_lib_preallocate_pages_for_all(pcm,
6410                                                    SNDRV_DMA_TYPE_DEV_SG,
6411                                                    snd_dma_pci_data(hdspm->pci),
6412                                                    wanted,
6413                                                    wanted);
6414         if (err < 0) {
6415                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6416
6417                 return err;
6418         } else
6419                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6420
6421         return 0;
6422 }
6423
6424
6425 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6426                             struct snd_pcm_substream *substream,
6427                              unsigned int reg, int channels)
6428 {
6429         int i;
6430
6431         /* continuous memory segment */
6432         for (i = 0; i < (channels * 16); i++)
6433                 hdspm_write(hdspm, reg + 4 * i,
6434                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6435 }
6436
6437
6438 /* ------------- ALSA Devices ---------------------------- */
6439 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6440                                           struct hdspm *hdspm)
6441 {
6442         struct snd_pcm *pcm;
6443         int err;
6444
6445         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6446         if (err < 0)
6447                 return err;
6448
6449         hdspm->pcm = pcm;
6450         pcm->private_data = hdspm;
6451         strcpy(pcm->name, hdspm->card_name);
6452
6453         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6454                         &snd_hdspm_playback_ops);
6455         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6456                         &snd_hdspm_capture_ops);
6457
6458         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6459
6460         err = snd_hdspm_preallocate_memory(hdspm);
6461         if (err < 0)
6462                 return err;
6463
6464         return 0;
6465 }
6466
6467 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6468 {
6469         int i;
6470
6471         for (i = 0; i < hdspm->midiPorts; i++)
6472                 snd_hdspm_flush_midi_input(hdspm, i);
6473 }
6474
6475 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6476                                                    struct hdspm * hdspm)
6477 {
6478         int err, i;
6479
6480         snd_printdd("Create card...\n");
6481         err = snd_hdspm_create_pcm(card, hdspm);
6482         if (err < 0)
6483                 return err;
6484
6485         i = 0;
6486         while (i < hdspm->midiPorts) {
6487                 err = snd_hdspm_create_midi(card, hdspm, i);
6488                 if (err < 0) {
6489                         return err;
6490                 }
6491                 i++;
6492         }
6493
6494         err = snd_hdspm_create_controls(card, hdspm);
6495         if (err < 0)
6496                 return err;
6497
6498         err = snd_hdspm_create_hwdep(card, hdspm);
6499         if (err < 0)
6500                 return err;
6501
6502         snd_printdd("proc init...\n");
6503         snd_hdspm_proc_init(hdspm);
6504
6505         hdspm->system_sample_rate = -1;
6506         hdspm->last_external_sample_rate = -1;
6507         hdspm->last_internal_sample_rate = -1;
6508         hdspm->playback_pid = -1;
6509         hdspm->capture_pid = -1;
6510         hdspm->capture_substream = NULL;
6511         hdspm->playback_substream = NULL;
6512
6513         snd_printdd("Set defaults...\n");
6514         err = snd_hdspm_set_defaults(hdspm);
6515         if (err < 0)
6516                 return err;
6517
6518         snd_printdd("Update mixer controls...\n");
6519         hdspm_update_simple_mixer_controls(hdspm);
6520
6521         snd_printdd("Initializeing complete ???\n");
6522
6523         err = snd_card_register(card);
6524         if (err < 0) {
6525                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6526                 return err;
6527         }
6528
6529         snd_printdd("... yes now\n");
6530
6531         return 0;
6532 }
6533
6534 static int __devinit snd_hdspm_create(struct snd_card *card,
6535                 struct hdspm *hdspm) {
6536
6537         struct pci_dev *pci = hdspm->pci;
6538         int err;
6539         unsigned long io_extent;
6540
6541         hdspm->irq = -1;
6542         hdspm->card = card;
6543
6544         spin_lock_init(&hdspm->lock);
6545
6546         pci_read_config_word(hdspm->pci,
6547                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6548
6549         strcpy(card->mixername, "Xilinx FPGA");
6550         strcpy(card->driver, "HDSPM");
6551
6552         switch (hdspm->firmware_rev) {
6553         case HDSPM_RAYDAT_REV:
6554                 hdspm->io_type = RayDAT;
6555                 hdspm->card_name = "RME RayDAT";
6556                 hdspm->midiPorts = 2;
6557                 break;
6558         case HDSPM_AIO_REV:
6559                 hdspm->io_type = AIO;
6560                 hdspm->card_name = "RME AIO";
6561                 hdspm->midiPorts = 1;
6562                 break;
6563         case HDSPM_MADIFACE_REV:
6564                 hdspm->io_type = MADIface;
6565                 hdspm->card_name = "RME MADIface";
6566                 hdspm->midiPorts = 1;
6567                 break;
6568         default:
6569                 if ((hdspm->firmware_rev == 0xf0) ||
6570                         ((hdspm->firmware_rev >= 0xe6) &&
6571                                         (hdspm->firmware_rev <= 0xea))) {
6572                         hdspm->io_type = AES32;
6573                         hdspm->card_name = "RME AES32";
6574                         hdspm->midiPorts = 2;
6575                 } else if ((hdspm->firmware_rev == 0xd2) ||
6576                         ((hdspm->firmware_rev >= 0xc8)  &&
6577                                 (hdspm->firmware_rev <= 0xcf))) {
6578                         hdspm->io_type = MADI;
6579                         hdspm->card_name = "RME MADI";
6580                         hdspm->midiPorts = 3;
6581                 } else {
6582                         snd_printk(KERN_ERR
6583                                 "HDSPM: unknown firmware revision %x\n",
6584                                 hdspm->firmware_rev);
6585                         return -ENODEV;
6586                 }
6587         }
6588
6589         err = pci_enable_device(pci);
6590         if (err < 0)
6591                 return err;
6592
6593         pci_set_master(hdspm->pci);
6594
6595         err = pci_request_regions(pci, "hdspm");
6596         if (err < 0)
6597                 return err;
6598
6599         hdspm->port = pci_resource_start(pci, 0);
6600         io_extent = pci_resource_len(pci, 0);
6601
6602         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6603                         hdspm->port, hdspm->port + io_extent - 1);
6604
6605         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6606         if (!hdspm->iobase) {
6607                 snd_printk(KERN_ERR "HDSPM: "
6608                                 "unable to remap region 0x%lx-0x%lx\n",
6609                                 hdspm->port, hdspm->port + io_extent - 1);
6610                 return -EBUSY;
6611         }
6612         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6613                         (unsigned long)hdspm->iobase, hdspm->port,
6614                         hdspm->port + io_extent - 1);
6615
6616         if (request_irq(pci->irq, snd_hdspm_interrupt,
6617                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6618                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6619                 return -EBUSY;
6620         }
6621
6622         snd_printdd("use IRQ %d\n", pci->irq);
6623
6624         hdspm->irq = pci->irq;
6625
6626         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6627                         sizeof(struct hdspm_mixer));
6628         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6629         if (!hdspm->mixer) {
6630                 snd_printk(KERN_ERR "HDSPM: "
6631                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6632                                 (int)sizeof(struct hdspm_mixer));
6633                 return -ENOMEM;
6634         }
6635
6636         hdspm->port_names_in = NULL;
6637         hdspm->port_names_out = NULL;
6638
6639         switch (hdspm->io_type) {
6640         case AES32:
6641                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6642                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6643                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6644
6645                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6646                         channel_map_aes32;
6647                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6648                         channel_map_aes32;
6649                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6650                         channel_map_aes32;
6651                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6652                         texts_ports_aes32;
6653                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6654                         texts_ports_aes32;
6655                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6656                         texts_ports_aes32;
6657
6658                 hdspm->max_channels_out = hdspm->max_channels_in =
6659                         AES32_CHANNELS;
6660                 hdspm->port_names_in = hdspm->port_names_out =
6661                         texts_ports_aes32;
6662                 hdspm->channel_map_in = hdspm->channel_map_out =
6663                         channel_map_aes32;
6664
6665                 break;
6666
6667         case MADI:
6668         case MADIface:
6669                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6670                         MADI_SS_CHANNELS;
6671                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6672                         MADI_DS_CHANNELS;
6673                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6674                         MADI_QS_CHANNELS;
6675
6676                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6677                         channel_map_unity_ss;
6678                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6679                         channel_map_unity_ss;
6680                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6681                         channel_map_unity_ss;
6682
6683                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6684                         texts_ports_madi;
6685                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6686                         texts_ports_madi;
6687                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6688                         texts_ports_madi;
6689                 break;
6690
6691         case AIO:
6692                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6693                         snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6694                 }
6695
6696                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6697                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6698                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6699                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6700                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6701                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6702
6703                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6704                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6705                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6706
6707                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6708                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6709                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6710
6711                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6712                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6713                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6714                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6715                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6716                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6717
6718                 break;
6719
6720         case RayDAT:
6721                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6722                         RAYDAT_SS_CHANNELS;
6723                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6724                         RAYDAT_DS_CHANNELS;
6725                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6726                         RAYDAT_QS_CHANNELS;
6727
6728                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6729                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6730
6731                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6732                         channel_map_raydat_ss;
6733                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6734                         channel_map_raydat_ds;
6735                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6736                         channel_map_raydat_qs;
6737                 hdspm->channel_map_in = hdspm->channel_map_out =
6738                         channel_map_raydat_ss;
6739
6740                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6741                         texts_ports_raydat_ss;
6742                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6743                         texts_ports_raydat_ds;
6744                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6745                         texts_ports_raydat_qs;
6746
6747
6748                 break;
6749
6750         }
6751
6752         /* TCO detection */
6753         switch (hdspm->io_type) {
6754         case AIO:
6755         case RayDAT:
6756                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6757                                 HDSPM_s2_tco_detect) {
6758                         hdspm->midiPorts++;
6759                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6760                                         GFP_KERNEL);
6761                         if (NULL != hdspm->tco) {
6762                                 hdspm_tco_write(hdspm);
6763                         }
6764                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6765                 } else {
6766                         hdspm->tco = NULL;
6767                 }
6768                 break;
6769
6770         case MADI:
6771                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6772                         hdspm->midiPorts++;
6773                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6774                                         GFP_KERNEL);
6775                         if (NULL != hdspm->tco) {
6776                                 hdspm_tco_write(hdspm);
6777                         }
6778                         snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6779                 } else {
6780                         hdspm->tco = NULL;
6781                 }
6782                 break;
6783
6784         default:
6785                 hdspm->tco = NULL;
6786         }
6787
6788         /* texts */
6789         switch (hdspm->io_type) {
6790         case AES32:
6791                 if (hdspm->tco) {
6792                         hdspm->texts_autosync = texts_autosync_aes_tco;
6793                         hdspm->texts_autosync_items = 10;
6794                 } else {
6795                         hdspm->texts_autosync = texts_autosync_aes;
6796                         hdspm->texts_autosync_items = 9;
6797                 }
6798                 break;
6799
6800         case MADI:
6801                 if (hdspm->tco) {
6802                         hdspm->texts_autosync = texts_autosync_madi_tco;
6803                         hdspm->texts_autosync_items = 4;
6804                 } else {
6805                         hdspm->texts_autosync = texts_autosync_madi;
6806                         hdspm->texts_autosync_items = 3;
6807                 }
6808                 break;
6809
6810         case MADIface:
6811
6812                 break;
6813
6814         case RayDAT:
6815                 if (hdspm->tco) {
6816                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6817                         hdspm->texts_autosync_items = 9;
6818                 } else {
6819                         hdspm->texts_autosync = texts_autosync_raydat;
6820                         hdspm->texts_autosync_items = 8;
6821                 }
6822                 break;
6823
6824         case AIO:
6825                 if (hdspm->tco) {
6826                         hdspm->texts_autosync = texts_autosync_aio_tco;
6827                         hdspm->texts_autosync_items = 6;
6828                 } else {
6829                         hdspm->texts_autosync = texts_autosync_aio;
6830                         hdspm->texts_autosync_items = 5;
6831                 }
6832                 break;
6833
6834         }
6835
6836         tasklet_init(&hdspm->midi_tasklet,
6837                         hdspm_midi_tasklet, (unsigned long) hdspm);
6838
6839
6840         if (hdspm->io_type != MADIface) {
6841                 hdspm->serial = (hdspm_read(hdspm,
6842                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6843                 /* id contains either a user-provided value or the default
6844                  * NULL. If it's the default, we're safe to
6845                  * fill card->id with the serial number.
6846                  *
6847                  * If the serial number is 0xFFFFFF, then we're dealing with
6848                  * an old PCI revision that comes without a sane number. In
6849                  * this case, we don't set card->id to avoid collisions
6850                  * when running with multiple cards.
6851                  */
6852                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6853                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6854                         snd_card_set_id(card, card->id);
6855                 }
6856         }
6857
6858         snd_printdd("create alsa devices.\n");
6859         err = snd_hdspm_create_alsa_devices(card, hdspm);
6860         if (err < 0)
6861                 return err;
6862
6863         snd_hdspm_initialize_midi_flush(hdspm);
6864
6865         return 0;
6866 }
6867
6868
6869 static int snd_hdspm_free(struct hdspm * hdspm)
6870 {
6871
6872         if (hdspm->port) {
6873
6874                 /* stop th audio, and cancel all interrupts */
6875                 hdspm->control_register &=
6876                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6877                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6878                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6879                 hdspm_write(hdspm, HDSPM_controlRegister,
6880                             hdspm->control_register);
6881         }
6882
6883         if (hdspm->irq >= 0)
6884                 free_irq(hdspm->irq, (void *) hdspm);
6885
6886         kfree(hdspm->mixer);
6887
6888         if (hdspm->iobase)
6889                 iounmap(hdspm->iobase);
6890
6891         if (hdspm->port)
6892                 pci_release_regions(hdspm->pci);
6893
6894         pci_disable_device(hdspm->pci);
6895         return 0;
6896 }
6897
6898
6899 static void snd_hdspm_card_free(struct snd_card *card)
6900 {
6901         struct hdspm *hdspm = card->private_data;
6902
6903         if (hdspm)
6904                 snd_hdspm_free(hdspm);
6905 }
6906
6907
6908 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6909                                      const struct pci_device_id *pci_id)
6910 {
6911         static int dev;
6912         struct hdspm *hdspm;
6913         struct snd_card *card;
6914         int err;
6915
6916         if (dev >= SNDRV_CARDS)
6917                 return -ENODEV;
6918         if (!enable[dev]) {
6919                 dev++;
6920                 return -ENOENT;
6921         }
6922
6923         err = snd_card_create(index[dev], id[dev],
6924                         THIS_MODULE, sizeof(struct hdspm), &card);
6925         if (err < 0)
6926                 return err;
6927
6928         hdspm = card->private_data;
6929         card->private_free = snd_hdspm_card_free;
6930         hdspm->dev = dev;
6931         hdspm->pci = pci;
6932
6933         snd_card_set_dev(card, &pci->dev);
6934
6935         err = snd_hdspm_create(card, hdspm);
6936         if (err < 0) {
6937                 snd_card_free(card);
6938                 return err;
6939         }
6940
6941         if (hdspm->io_type != MADIface) {
6942                 sprintf(card->shortname, "%s_%x",
6943                         hdspm->card_name,
6944                         hdspm->serial);
6945                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6946                         hdspm->card_name,
6947                         hdspm->serial,
6948                         hdspm->port, hdspm->irq);
6949         } else {
6950                 sprintf(card->shortname, "%s", hdspm->card_name);
6951                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6952                                 hdspm->card_name, hdspm->port, hdspm->irq);
6953         }
6954
6955         err = snd_card_register(card);
6956         if (err < 0) {
6957                 snd_card_free(card);
6958                 return err;
6959         }
6960
6961         pci_set_drvdata(pci, card);
6962
6963         dev++;
6964         return 0;
6965 }
6966
6967 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6968 {
6969         snd_card_free(pci_get_drvdata(pci));
6970         pci_set_drvdata(pci, NULL);
6971 }
6972
6973 static struct pci_driver hdspm_driver = {
6974         .name = KBUILD_MODNAME,
6975         .id_table = snd_hdspm_ids,
6976         .probe = snd_hdspm_probe,
6977         .remove = __devexit_p(snd_hdspm_remove),
6978 };
6979
6980 module_pci_driver(hdspm_driver);