arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/platform_data/gpio-omap.h>
  32
  33 #include <trace/events/power.h>
  34
  35 #include <asm/fncpy.h>
  36 #include <asm/suspend.h>
  37 #include <asm/system_misc.h>
  38
  39 #include "clockdomain.h"
  40 #include "powerdomain.h"
  41 #include <plat-omap/dma-omap.h>
  42
  43 #include "soc.h"
  44 #include "common.h"
  45 #include "cm3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "gpmc.h"
  48 #include "prm-regbits-34xx.h"
  49 #include "prm3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "sram.h"
  53 #include "control.h"
  54
  55 /* pm34xx errata defined in pm.h */
  56 u16 pm34xx_errata;
  57
  58 struct power_state {
  59         struct powerdomain *pwrdm;
  60         u32 next_state;
  61 #ifdef CONFIG_SUSPEND
  62         u32 saved_state;
  63 #endif
  64         struct list_head node;
  65 };
  66
  67 static LIST_HEAD(pwrst_list);
  68
  69 static int (*_omap_save_secure_sram)(u32 *addr);
  70 void (*omap3_do_wfi_sram)(void);
  71
  72 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  73 static struct powerdomain *core_pwrdm, *per_pwrdm;
  74
  75 static void omap3_core_save_context(void)
  76 {
  77         omap3_ctrl_save_padconf();
  78
  79         /*
  80          * Force write last pad into memory, as this can fail in some
  81          * cases according to errata 1.157, 1.185
  82          */
  83         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
  84                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
  85
  86         /* Save the Interrupt controller context */
  87         omap_intc_save_context();
  88         /* Save the GPMC context */
  89         omap3_gpmc_save_context();
  90         /* Save the system control module context, padconf already save above*/
  91         omap3_control_save_context();
  92         omap_dma_global_context_save();
  93 }
  94
  95 static void omap3_core_restore_context(void)
  96 {
  97         /* Restore the control module context, padconf restored by h/w */
  98         omap3_control_restore_context();
  99         /* Restore the GPMC context */
 100         omap3_gpmc_restore_context();
 101         /* Restore the interrupt controller context */
 102         omap_intc_restore_context();
 103         omap_dma_global_context_restore();
 104 }
 105
 106 /*
 107  * FIXME: This function should be called before entering off-mode after
 108  * OMAP3 secure services have been accessed. Currently it is only called
 109  * once during boot sequence, but this works as we are not using secure
 110  * services.
 111  */
 112 static void omap3_save_secure_ram_context(void)
 113 {
 114         u32 ret;
 115         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 116
 117         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 118                 /*
 119                  * MPU next state must be set to POWER_ON temporarily,
 120                  * otherwise the WFI executed inside the ROM code
 121                  * will hang the system.
 122                  */
 123                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 124                 ret = _omap_save_secure_sram((u32 *)
 125                                 __pa(omap3_secure_ram_storage));
 126                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 127                 /* Following is for error tracking, it should not happen */
 128                 if (ret) {
 129                         pr_err("save_secure_sram() returns %08x\n", ret);
 130                         while (1)
 131                                 ;
 132                 }
 133         }
 134 }
 135
 136 /*
 137  * PRCM Interrupt Handler Helper Function
 138  *
 139  * The purpose of this function is to clear any wake-up events latched
 140  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 141  * may occur whilst attempting to clear a PM_WKST_x register and thus
 142  * set another bit in this register. A while loop is used to ensure
 143  * that any peripheral wake-up events occurring while attempting to
 144  * clear the PM_WKST_x are detected and cleared.
 145  */
 146 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 147 {
 148         u32 wkst, fclk, iclk, clken;
 149         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 150         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 151         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 152         u16 grpsel_off = (regs == 3) ?
 153                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 154         int c = 0;
 155
 156         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 157         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 158         wkst &= ~ignore_bits;
 159         if (wkst) {
 160                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 161                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 162                 while (wkst) {
 163                         clken = wkst;
 164                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 165                         /*
 166                          * For USBHOST, we don't know whether HOST1 or
 167                          * HOST2 woke us up, so enable both f-clocks
 168                          */
 169                         if (module == OMAP3430ES2_USBHOST_MOD)
 170                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 171                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 172                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 173                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 174                         wkst &= ~ignore_bits;
 175                         c++;
 176                 }
 177                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 178                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 179         }
 180
 181         return c;
 182 }
 183
 184 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 185 {
 186         int c;
 187
 188         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 189                 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
 190
 191         return c ? IRQ_HANDLED : IRQ_NONE;
 192 }
 193
 194 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 195 {
 196         int c;
 197
 198         /*
 199          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 200          * these are handled in a separate handler to avoid acking
 201          * IO events before parsing in mux code
 202          */
 203         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 204                 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
 205         c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
 206         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
 207         if (omap_rev() > OMAP3430_REV_ES1_0) {
 208                 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
 209                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
 210         }
 211
 212         return c ? IRQ_HANDLED : IRQ_NONE;
 213 }
 214
 215 static void omap34xx_save_context(u32 *save)
 216 {
 217         u32 val;
 218
 219         /* Read Auxiliary Control Register */
 220         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 221         *save++ = 1;
 222         *save++ = val;
 223
 224         /* Read L2 AUX ctrl register */
 225         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 226         *save++ = 1;
 227         *save++ = val;
 228 }
 229
 230 static int omap34xx_do_sram_idle(unsigned long save_state)
 231 {
 232         omap34xx_cpu_suspend(save_state);
 233         return 0;
 234 }
 235
 236 void omap_sram_idle(void)
 237 {
 238         /* Variable to tell what needs to be saved and restored
 239          * in omap_sram_idle*/
 240         /* save_state = 0 => Nothing to save and restored */
 241         /* save_state = 1 => Only L1 and logic lost */
 242         /* save_state = 2 => Only L2 lost */
 243         /* save_state = 3 => L1, L2 and logic lost */
 244         int save_state = 0;
 245         int mpu_next_state = PWRDM_POWER_ON;
 246         int per_next_state = PWRDM_POWER_ON;
 247         int core_next_state = PWRDM_POWER_ON;
 248         int per_going_off;
 249         int core_prev_state;
 250         u32 sdrc_pwr = 0;
 251
 252         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 253         switch (mpu_next_state) {
 254         case PWRDM_POWER_ON:
 255         case PWRDM_POWER_RET:
 256                 /* No need to save context */
 257                 save_state = 0;
 258                 break;
 259         case PWRDM_POWER_OFF:
 260                 save_state = 3;
 261                 break;
 262         default:
 263                 /* Invalid state */
 264                 pr_err("Invalid mpu state in sram_idle\n");
 265                 return;
 266         }
 267
 268         /* NEON control */
 269         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 270                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 271
 272         /* Enable IO-PAD and IO-CHAIN wakeups */
 273         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 274         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 275
 276         pwrdm_pre_transition(NULL);
 277
 278         /* PER */
 279         if (per_next_state < PWRDM_POWER_ON) {
 280                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 281                 omap2_gpio_prepare_for_idle(per_going_off);
 282         }
 283
 284         /* CORE */
 285         if (core_next_state < PWRDM_POWER_ON) {
 286                 if (core_next_state == PWRDM_POWER_OFF) {
 287                         omap3_core_save_context();
 288                         omap3_cm_save_context();
 289                 }
 290         }
 291
 292         omap3_intc_prepare_idle();
 293
 294         /*
 295          * On EMU/HS devices ROM code restores a SRDC value
 296          * from scratchpad which has automatic self refresh on timeout
 297          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 298          * Hence store/restore the SDRC_POWER register here.
 299          */
 300         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 301             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 302              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 303             core_next_state == PWRDM_POWER_OFF)
 304                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 305
 306         /*
 307          * omap3_arm_context is the location where some ARM context
 308          * get saved. The rest is placed on the stack, and restored
 309          * from there before resuming.
 310          */
 311         if (save_state)
 312                 omap34xx_save_context(omap3_arm_context);
 313         if (save_state == 1 || save_state == 3)
 314                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 315         else
 316                 omap34xx_do_sram_idle(save_state);
 317
 318         /* Restore normal SDRC POWER settings */
 319         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 320             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 321              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 322             core_next_state == PWRDM_POWER_OFF)
 323                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 324
 325         /* CORE */
 326         if (core_next_state < PWRDM_POWER_ON) {
 327                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 328                 if (core_prev_state == PWRDM_POWER_OFF) {
 329                         omap3_core_restore_context();
 330                         omap3_cm_restore_context();
 331                         omap3_sram_restore_context();
 332                         omap2_sms_restore_context();
 333                 }
 334                 if (core_next_state == PWRDM_POWER_OFF)
 335                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 336                                                OMAP3430_GR_MOD,
 337                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 338         }
 339         omap3_intc_resume_idle();
 340
 341         pwrdm_post_transition(NULL);
 342
 343         /* PER */
 344         if (per_next_state < PWRDM_POWER_ON)
 345                 omap2_gpio_resume_after_idle();
 346 }
 347
 348 static void omap3_pm_idle(void)
 349 {
 350         local_fiq_disable();
 351
 352         if (omap_irq_pending())
 353                 goto out;
 354
 355         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 356         trace_cpu_idle(1, smp_processor_id());
 357
 358         omap_sram_idle();
 359
 360         trace_power_end(smp_processor_id());
 361         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 362
 363 out:
 364         local_fiq_enable();
 365 }
 366
 367 #ifdef CONFIG_SUSPEND
 368 static int omap3_pm_suspend(void)
 369 {
 370         struct power_state *pwrst;
 371         int state, ret = 0;
 372
 373         /* Read current next_pwrsts */
 374         list_for_each_entry(pwrst, &pwrst_list, node)
 375                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 376         /* Set ones wanted by suspend */
 377         list_for_each_entry(pwrst, &pwrst_list, node) {
 378                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 379                         goto restore;
 380                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 381                         goto restore;
 382         }
 383
 384         omap3_intc_suspend();
 385
 386         omap_sram_idle();
 387
 388 restore:
 389         /* Restore next_pwrsts */
 390         list_for_each_entry(pwrst, &pwrst_list, node) {
 391                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 392                 if (state > pwrst->next_state) {
 393                         pr_info("Powerdomain (%s) didn't enter target state %d\n",
 394                                 pwrst->pwrdm->name, pwrst->next_state);
 395                         ret = -1;
 396                 }
 397                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 398         }
 399         if (ret)
 400                 pr_err("Could not enter target state in pm_suspend\n");
 401         else
 402                 pr_info("Successfully put all powerdomains to target state\n");
 403
 404         return ret;
 405 }
 406
 407 #endif /* CONFIG_SUSPEND */
 408
 409
 410 /**
 411  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 412  *                   retention
 413  *
 414  * In cases where IVA2 is activated by bootcode, it may prevent
 415  * full-chip retention or off-mode because it is not idle.  This
 416  * function forces the IVA2 into idle state so it can go
 417  * into retention/off and thus allow full-chip retention/off.
 418  *
 419  **/
 420 static void __init omap3_iva_idle(void)
 421 {
 422         /* ensure IVA2 clock is disabled */
 423         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 424
 425         /* if no clock activity, nothing else to do */
 426         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 427               OMAP3430_CLKACTIVITY_IVA2_MASK))
 428                 return;
 429
 430         /* Reset IVA2 */
 431         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 432                           OMAP3430_RST2_IVA2_MASK |
 433                           OMAP3430_RST3_IVA2_MASK,
 434                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 435
 436         /* Enable IVA2 clock */
 437         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 438                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 439
 440         /* Set IVA2 boot mode to 'idle' */
 441         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 442                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 443
 444         /* Un-reset IVA2 */
 445         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 446
 447         /* Disable IVA2 clock */
 448         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 449
 450         /* Reset IVA2 */
 451         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 452                           OMAP3430_RST2_IVA2_MASK |
 453                           OMAP3430_RST3_IVA2_MASK,
 454                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 455 }
 456
 457 static void __init omap3_d2d_idle(void)
 458 {
 459         u16 mask, padconf;
 460
 461         /* In a stand alone OMAP3430 where there is not a stacked
 462          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 463          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 464          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 465         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 466         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 467         padconf |= mask;
 468         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 469
 470         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 471         padconf |= mask;
 472         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 473
 474         /* reset modem */
 475         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 476                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 477                           CORE_MOD, OMAP2_RM_RSTCTRL);
 478         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 479 }
 480
 481 static void __init prcm_setup_regs(void)
 482 {
 483         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 484                                         OMAP3630_EN_UART4_MASK : 0;
 485         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 486                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 487
 488         /* XXX This should be handled by hwmod code or SCM init code */
 489         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 490
 491         /*
 492          * Enable control of expternal oscillator through
 493          * sys_clkreq. In the long run clock framework should
 494          * take care of this.
 495          */
 496         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 497                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 498                              OMAP3430_GR_MOD,
 499                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 500
 501         /* setup wakup source */
 502         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 503                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 504                           WKUP_MOD, PM_WKEN);
 505         /* No need to write EN_IO, that is always enabled */
 506         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 507                           OMAP3430_GRPSEL_GPT1_MASK |
 508                           OMAP3430_GRPSEL_GPT12_MASK,
 509                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 510
 511         /* Enable PM_WKEN to support DSS LPR */
 512         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 513                                 OMAP3430_DSS_MOD, PM_WKEN);
 514
 515         /* Enable wakeups in PER */
 516         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 517                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 518                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 519                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 520                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 521                           OMAP3430_EN_MCBSP4_MASK,
 522                           OMAP3430_PER_MOD, PM_WKEN);
 523         /* and allow them to wake up MPU */
 524         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 525                           OMAP3430_GRPSEL_GPIO2_MASK |
 526                           OMAP3430_GRPSEL_GPIO3_MASK |
 527                           OMAP3430_GRPSEL_GPIO4_MASK |
 528                           OMAP3430_GRPSEL_GPIO5_MASK |
 529                           OMAP3430_GRPSEL_GPIO6_MASK |
 530                           OMAP3430_GRPSEL_UART3_MASK |
 531                           OMAP3430_GRPSEL_MCBSP2_MASK |
 532                           OMAP3430_GRPSEL_MCBSP3_MASK |
 533                           OMAP3430_GRPSEL_MCBSP4_MASK,
 534                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 535
 536         /* Don't attach IVA interrupts */
 537         if (omap3_has_iva()) {
 538                 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 539                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 540                 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 541                 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
 542                                         OMAP3430_PM_IVAGRPSEL);
 543         }
 544
 545         /* Clear any pending 'reset' flags */
 546         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 547         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 548         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 549         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 550         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 551         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 552         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 553
 554         /* Clear any pending PRCM interrupts */
 555         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 556
 557         if (omap3_has_iva())
 558                 omap3_iva_idle();
 559
 560         omap3_d2d_idle();
 561 }
 562
 563 void omap3_pm_off_mode_enable(int enable)
 564 {
 565         struct power_state *pwrst;
 566         u32 state;
 567
 568         if (enable)
 569                 state = PWRDM_POWER_OFF;
 570         else
 571                 state = PWRDM_POWER_RET;
 572
 573         list_for_each_entry(pwrst, &pwrst_list, node) {
 574                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 575                                 pwrst->pwrdm == core_pwrdm &&
 576                                 state == PWRDM_POWER_OFF) {
 577                         pwrst->next_state = PWRDM_POWER_RET;
 578                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 579                                 __func__);
 580                 } else {
 581                         pwrst->next_state = state;
 582                 }
 583                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 584         }
 585 }
 586
 587 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 588 {
 589         struct power_state *pwrst;
 590
 591         list_for_each_entry(pwrst, &pwrst_list, node) {
 592                 if (pwrst->pwrdm == pwrdm)
 593                         return pwrst->next_state;
 594         }
 595         return -EINVAL;
 596 }
 597
 598 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 599 {
 600         struct power_state *pwrst;
 601
 602         list_for_each_entry(pwrst, &pwrst_list, node) {
 603                 if (pwrst->pwrdm == pwrdm) {
 604                         pwrst->next_state = state;
 605                         return 0;
 606                 }
 607         }
 608         return -EINVAL;
 609 }
 610
 611 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 612 {
 613         struct power_state *pwrst;
 614
 615         if (!pwrdm->pwrsts)
 616                 return 0;
 617
 618         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 619         if (!pwrst)
 620                 return -ENOMEM;
 621         pwrst->pwrdm = pwrdm;
 622         pwrst->next_state = PWRDM_POWER_RET;
 623         list_add(&pwrst->node, &pwrst_list);
 624
 625         if (pwrdm_has_hdwr_sar(pwrdm))
 626                 pwrdm_enable_hdwr_sar(pwrdm);
 627
 628         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 629 }
 630
 631 /*
 632  * Push functions to SRAM
 633  *
 634  * The minimum set of functions is pushed to SRAM for execution:
 635  * - omap3_do_wfi for erratum i581 WA,
 636  * - save_secure_ram_context for security extensions.
 637  */
 638 void omap_push_sram_idle(void)
 639 {
 640         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 641
 642         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 643                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 644                                 save_secure_ram_context_sz);
 645 }
 646
 647 static void __init pm_errata_configure(void)
 648 {
 649         if (cpu_is_omap3630()) {
 650                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 651                 /* Enable the l2 cache toggling in sleep logic */
 652                 enable_omap3630_toggle_l2_on_restore();
 653                 if (omap_rev() < OMAP3630_REV_ES1_2)
 654                         pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
 655                                           PM_PER_MEMORIES_ERRATUM_i582);
 656         } else if (cpu_is_omap34xx()) {
 657                 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
 658         }
 659 }
 660
 661 int __init omap3_pm_init(void)
 662 {
 663         struct power_state *pwrst, *tmp;
 664         struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
 665         int ret;
 666
 667         if (!omap3_has_io_chain_ctrl())
 668                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 669
 670         pm_errata_configure();
 671
 672         /* XXX prcm_setup_regs needs to be before enabling hw
 673          * supervised mode for powerdomains */
 674         prcm_setup_regs();
 675
 676         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 677                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 678
 679         if (ret) {
 680                 pr_err("pm: Failed to request pm_wkup irq\n");
 681                 goto err1;
 682         }
 683
 684         /* IO interrupt is shared with mux code */
 685         ret = request_irq(omap_prcm_event_to_irq("io"),
 686                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 687                 omap3_pm_init);
 688         enable_irq(omap_prcm_event_to_irq("io"));
 689
 690         if (ret) {
 691                 pr_err("pm: Failed to request pm_io irq\n");
 692                 goto err2;
 693         }
 694
 695         ret = pwrdm_for_each(pwrdms_setup, NULL);
 696         if (ret) {
 697                 pr_err("Failed to setup powerdomains\n");
 698                 goto err3;
 699         }
 700
 701         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
 702
 703         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 704         if (mpu_pwrdm == NULL) {
 705                 pr_err("Failed to get mpu_pwrdm\n");
 706                 ret = -EINVAL;
 707                 goto err3;
 708         }
 709
 710         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 711         per_pwrdm = pwrdm_lookup("per_pwrdm");
 712         core_pwrdm = pwrdm_lookup("core_pwrdm");
 713
 714         neon_clkdm = clkdm_lookup("neon_clkdm");
 715         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 716         per_clkdm = clkdm_lookup("per_clkdm");
 717         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 718
 719 #ifdef CONFIG_SUSPEND
 720         omap_pm_suspend = omap3_pm_suspend;
 721 #endif
 722
 723         arm_pm_idle = omap3_pm_idle;
 724         omap3_idle_init();
 725
 726         /*
 727          * RTA is disabled during initialization as per erratum i608
 728          * it is safer to disable RTA by the bootloader, but we would like
 729          * to be doubly sure here and prevent any mishaps.
 730          */
 731         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 732                 omap3630_ctrl_disable_rta();
 733
 734         /*
 735          * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
 736          * not correctly reset when the PER powerdomain comes back
 737          * from OFF or OSWR when the CORE powerdomain is kept active.
 738          * See OMAP36xx Erratum i582 "PER Domain reset issue after
 739          * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
 740          * complete workaround.  The kernel must also prevent the PER
 741          * powerdomain from going to OSWR/OFF while the CORE
 742          * powerdomain is not going to OSWR/OFF.  And if PER last
 743          * power state was off while CORE last power state was ON, the
 744          * UART3/4 and McBSP2/3 SIDETONE devices need to run a
 745          * self-test using their loopback tests; if that fails, those
 746          * devices are unusable until the PER/CORE can complete a transition
 747          * from ON to OSWR/OFF and then back to ON.
 748          *
 749          * XXX Technically this workaround is only needed if off-mode
 750          * or OSWR is enabled.
 751          */
 752         if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
 753                 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
 754
 755         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 756         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 757                 omap3_secure_ram_storage =
 758                         kmalloc(0x803F, GFP_KERNEL);
 759                 if (!omap3_secure_ram_storage)
 760                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 761
 762                 local_irq_disable();
 763                 local_fiq_disable();
 764
 765                 omap_dma_global_context_save();
 766                 omap3_save_secure_ram_context();
 767                 omap_dma_global_context_restore();
 768
 769                 local_irq_enable();
 770                 local_fiq_enable();
 771         }
 772
 773         omap3_save_scratchpad_contents();
 774         return ret;
 775
 776 err3:
 777         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 778                 list_del(&pwrst->node);
 779                 kfree(pwrst);
 780         }
 781         free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
 782 err2:
 783         free_irq(omap_prcm_event_to_irq("wkup"), NULL);
 784 err1:
 785         return ret;
 786 }