4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 /* Include the ID list */
36 #include <linux/pci_ids.h>
38 /* pci_slot represents a physical slot */
40 struct pci_bus *bus; /* The bus this slot is on */
41 struct list_head list; /* node in list of slots on this bus */
42 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
43 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
47 static inline const char *pci_slot_name(const struct pci_slot *slot)
49 return kobject_name(&slot->kobj);
52 /* File state for mmap()s on /proc/bus/pci/X/Y */
58 /* This defines the direction arg to the DMA mapping routines. */
59 #define PCI_DMA_BIDIRECTIONAL 0
60 #define PCI_DMA_TODEVICE 1
61 #define PCI_DMA_FROMDEVICE 2
62 #define PCI_DMA_NONE 3
65 * For PCI devices, the region numbers are assigned this way:
68 /* #0-5: standard PCI resources */
70 PCI_STD_RESOURCE_END = 5,
72 /* #6: expansion ROM resource */
75 /* device specific resources */
78 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
81 /* resources assigned to buses behind the bridge */
82 #define PCI_BRIDGE_RESOURCE_NUM 4
85 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
86 PCI_BRIDGE_RESOURCE_NUM - 1,
88 /* total resources associated with a PCI device */
91 /* preserve this for compatibility */
92 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
95 typedef int __bitwise pci_power_t;
97 #define PCI_D0 ((pci_power_t __force) 0)
98 #define PCI_D1 ((pci_power_t __force) 1)
99 #define PCI_D2 ((pci_power_t __force) 2)
100 #define PCI_D3hot ((pci_power_t __force) 3)
101 #define PCI_D3cold ((pci_power_t __force) 4)
102 #define PCI_UNKNOWN ((pci_power_t __force) 5)
103 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
105 /* Remember to update this when the list above changes! */
106 extern const char *pci_power_names[];
108 static inline const char *pci_power_name(pci_power_t state)
110 return pci_power_names[1 + (int) state];
113 #define PCI_PM_D2_DELAY 200
114 #define PCI_PM_D3_WAIT 10
115 #define PCI_PM_D3COLD_WAIT 100
116 #define PCI_PM_BUS_WAIT 50
118 /** The pci_channel state describes connectivity between the CPU and
119 * the pci device. If some PCI bus between here and the pci device
120 * has crashed or locked up, this info is reflected here.
122 typedef unsigned int __bitwise pci_channel_state_t;
124 enum pci_channel_state {
125 /* I/O channel is in normal state */
126 pci_channel_io_normal = (__force pci_channel_state_t) 1,
128 /* I/O to channel is blocked */
129 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
131 /* PCI card is dead */
132 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
135 typedef unsigned int __bitwise pcie_reset_state_t;
137 enum pcie_reset_state {
138 /* Reset is NOT asserted (Use to deassert reset) */
139 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
141 /* Use #PERST to reset PCI-E device */
142 pcie_warm_reset = (__force pcie_reset_state_t) 2,
144 /* Use PCI-E Hot Reset to reset device */
145 pcie_hot_reset = (__force pcie_reset_state_t) 3
148 typedef unsigned short __bitwise pci_dev_flags_t;
150 /* INTX_DISABLE in PCI_COMMAND register disables MSI
153 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
154 /* Device configuration is irrevocably lost if disabled into D3 */
155 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
156 /* Provide indication device is assigned by a Virtual Machine Manager */
157 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
160 enum pci_irq_reroute_variant {
161 INTEL_IRQ_REROUTE_VARIANT = 1,
162 MAX_IRQ_REROUTE_VARIANTS = 3
165 typedef unsigned short __bitwise pci_bus_flags_t;
167 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
168 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
171 /* Based on the PCI Hotplug Spec, but some values are made up by us */
173 PCI_SPEED_33MHz = 0x00,
174 PCI_SPEED_66MHz = 0x01,
175 PCI_SPEED_66MHz_PCIX = 0x02,
176 PCI_SPEED_100MHz_PCIX = 0x03,
177 PCI_SPEED_133MHz_PCIX = 0x04,
178 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
179 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
180 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
181 PCI_SPEED_66MHz_PCIX_266 = 0x09,
182 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
183 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
189 PCI_SPEED_66MHz_PCIX_533 = 0x11,
190 PCI_SPEED_100MHz_PCIX_533 = 0x12,
191 PCI_SPEED_133MHz_PCIX_533 = 0x13,
192 PCIE_SPEED_2_5GT = 0x14,
193 PCIE_SPEED_5_0GT = 0x15,
194 PCIE_SPEED_8_0GT = 0x16,
195 PCI_SPEED_UNKNOWN = 0xff,
198 struct pci_cap_saved_data {
204 struct pci_cap_saved_state {
205 struct hlist_node next;
206 struct pci_cap_saved_data cap;
209 struct pcie_link_state;
215 * The pci_dev structure is used to describe PCI devices.
218 struct list_head bus_list; /* node in per-bus list */
219 struct pci_bus *bus; /* bus this device is on */
220 struct pci_bus *subordinate; /* bus this device bridges to */
222 void *sysdata; /* hook for sys-specific extension */
223 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
224 struct pci_slot *slot; /* Physical slot this device is in */
226 unsigned int devfn; /* encoded device & function index */
227 unsigned short vendor;
228 unsigned short device;
229 unsigned short subsystem_vendor;
230 unsigned short subsystem_device;
231 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
232 u8 revision; /* PCI revision, low byte of class word */
233 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
234 u8 pcie_cap; /* PCI-E capability offset */
235 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
236 u8 rom_base_reg; /* which config register controls the ROM */
237 u8 pin; /* which interrupt pin this device uses */
238 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
240 struct pci_driver *driver; /* which driver has allocated this device */
241 u64 dma_mask; /* Mask of the bits of bus address this
242 device implements. Normally this is
243 0xffffffff. You only need to change
244 this if your device has broken DMA
245 or supports 64-bit transfers. */
247 struct device_dma_parameters dma_parms;
249 pci_power_t current_state; /* Current operating state. In ACPI-speak,
250 this is D0-D3, D0 being fully functional,
252 int pm_cap; /* PM capability offset in the
253 configuration space */
254 unsigned int pme_support:5; /* Bitmask of states from which PME#
256 unsigned int pme_interrupt:1;
257 unsigned int pme_poll:1; /* Poll device's PME status bit */
258 unsigned int d1_support:1; /* Low power state D1 is supported */
259 unsigned int d2_support:1; /* Low power state D2 is supported */
260 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
261 unsigned int no_d3cold:1; /* D3cold is forbidden */
262 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
263 unsigned int mmio_always_on:1; /* disallow turning off io/mem
264 decoding during bar sizing */
265 unsigned int wakeup_prepared:1;
266 unsigned int runtime_d3cold:1; /* whether go through runtime
267 D3cold, not set for devices
268 powered on/off by the
269 corresponding bridge */
270 unsigned int d3_delay; /* D3->D0 transition time in ms */
271 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
273 #ifdef CONFIG_PCIEASPM
274 struct pcie_link_state *link_state; /* ASPM link state. */
277 pci_channel_state_t error_state; /* current connectivity state */
278 struct device dev; /* Generic device interface */
280 int cfg_size; /* Size of configuration space */
283 * Instead of touching interrupt line and base address registers
284 * directly, use the values stored here. They might be different!
287 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
289 /* These fields are used by common fixups */
290 unsigned int transparent:1; /* Transparent PCI bridge */
291 unsigned int multifunction:1;/* Part of multi-function device */
292 /* keep track of device state */
293 unsigned int is_added:1;
294 unsigned int is_busmaster:1; /* device is busmaster */
295 unsigned int no_msi:1; /* device may not use msi */
296 unsigned int block_cfg_access:1; /* config space access is blocked */
297 unsigned int broken_parity_status:1; /* Device generates false positive parity */
298 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
299 unsigned int msi_enabled:1;
300 unsigned int msix_enabled:1;
301 unsigned int ari_enabled:1; /* ARI forwarding */
302 unsigned int is_managed:1;
303 unsigned int is_pcie:1; /* Obsolete. Will be removed.
304 Use pci_is_pcie() instead */
305 unsigned int needs_freset:1; /* Dev requires fundamental reset */
306 unsigned int state_saved:1;
307 unsigned int is_physfn:1;
308 unsigned int is_virtfn:1;
309 unsigned int reset_fn:1;
310 unsigned int is_hotplug_bridge:1;
311 unsigned int __aer_firmware_first_valid:1;
312 unsigned int __aer_firmware_first:1;
313 unsigned int broken_intx_masking:1;
314 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
315 pci_dev_flags_t dev_flags;
316 atomic_t enable_cnt; /* pci_enable_device has been called */
318 u32 saved_config_space[16]; /* config space saved at suspend time */
319 struct hlist_head saved_cap_space;
320 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
321 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
322 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
323 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
324 #ifdef CONFIG_PCI_MSI
325 struct list_head msi_list;
326 struct kset *msi_kset;
329 #ifdef CONFIG_PCI_ATS
331 struct pci_sriov *sriov; /* SR-IOV capability related */
332 struct pci_dev *physfn; /* the PF this VF is associated with */
334 struct pci_ats *ats; /* Address Translation Service */
338 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
340 #ifdef CONFIG_PCI_IOV
348 extern struct pci_dev *alloc_pci_dev(void);
350 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
351 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
353 static inline int pci_channel_offline(struct pci_dev *pdev)
355 return (pdev->error_state != pci_channel_io_normal);
358 extern struct resource busn_resource;
360 struct pci_host_bridge_window {
361 struct list_head list;
362 struct resource *res; /* host bridge aperture (CPU address) */
363 resource_size_t offset; /* bus address + offset = CPU address */
366 struct pci_host_bridge {
368 struct pci_bus *bus; /* root bus */
369 struct list_head windows; /* pci_host_bridge_windows */
370 void (*release_fn)(struct pci_host_bridge *);
374 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
375 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
376 void (*release_fn)(struct pci_host_bridge *),
380 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
381 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
382 * buses below host bridges or subtractive decode bridges) go in the list.
383 * Use pci_bus_for_each_resource() to iterate through all the resources.
387 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
388 * and there's no way to program the bridge with the details of the window.
389 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
390 * decode bit set, because they are explicit and can be programmed with _SRS.
392 #define PCI_SUBTRACTIVE_DECODE 0x1
394 struct pci_bus_resource {
395 struct list_head list;
396 struct resource *res;
400 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
403 struct list_head node; /* node in list of buses */
404 struct pci_bus *parent; /* parent bus this bridge is on */
405 struct list_head children; /* list of child buses */
406 struct list_head devices; /* list of devices on this bus */
407 struct pci_dev *self; /* bridge device as seen by parent */
408 struct list_head slots; /* list of slots on this bus */
409 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
410 struct list_head resources; /* address space routed to this bus */
411 struct resource busn_res; /* bus numbers routed to this bus */
413 struct pci_ops *ops; /* configuration access functions */
414 void *sysdata; /* hook for sys-specific extension */
415 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
417 unsigned char number; /* bus number */
418 unsigned char primary; /* number of primary bridge */
419 unsigned char max_bus_speed; /* enum pci_bus_speed */
420 unsigned char cur_bus_speed; /* enum pci_bus_speed */
424 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
425 pci_bus_flags_t bus_flags; /* Inherited by child busses */
426 struct device *bridge;
428 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
429 struct bin_attribute *legacy_mem; /* legacy mem */
430 unsigned int is_added:1;
433 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
434 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
437 * Returns true if the pci bus is root (behind host-pci bridge),
440 static inline bool pci_is_root_bus(struct pci_bus *pbus)
442 return !(pbus->parent);
445 #ifdef CONFIG_PCI_MSI
446 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
448 return pci_dev->msi_enabled || pci_dev->msix_enabled;
451 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
455 * Error values that may be returned by PCI functions.
457 #define PCIBIOS_SUCCESSFUL 0x00
458 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
459 #define PCIBIOS_BAD_VENDOR_ID 0x83
460 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
461 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
462 #define PCIBIOS_SET_FAILED 0x88
463 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
466 * Translate above to generic errno for passing back through non-pci.
468 static inline int pcibios_err_to_errno(int err)
470 if (err <= PCIBIOS_SUCCESSFUL)
471 return err; /* Assume already errno */
474 case PCIBIOS_FUNC_NOT_SUPPORTED:
476 case PCIBIOS_BAD_VENDOR_ID:
478 case PCIBIOS_DEVICE_NOT_FOUND:
480 case PCIBIOS_BAD_REGISTER_NUMBER:
482 case PCIBIOS_SET_FAILED:
484 case PCIBIOS_BUFFER_TOO_SMALL:
491 /* Low-level architecture-dependent routines */
494 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
495 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
499 * ACPI needs to be able to access PCI config space before we've done a
500 * PCI bus scan and created pci_bus structures.
502 extern int raw_pci_read(unsigned int domain, unsigned int bus,
503 unsigned int devfn, int reg, int len, u32 *val);
504 extern int raw_pci_write(unsigned int domain, unsigned int bus,
505 unsigned int devfn, int reg, int len, u32 val);
507 struct pci_bus_region {
508 resource_size_t start;
513 spinlock_t lock; /* protects list, index */
514 struct list_head list; /* for IDs added at runtime */
517 /* ---------------------------------------------------------------- */
518 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
519 * a set of callbacks in struct pci_error_handlers, then that device driver
520 * will be notified of PCI bus errors, and will be driven to recovery
521 * when an error occurs.
524 typedef unsigned int __bitwise pci_ers_result_t;
526 enum pci_ers_result {
527 /* no result/none/not supported in device driver */
528 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
530 /* Device driver can recover without slot reset */
531 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
533 /* Device driver wants slot to be reset. */
534 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
536 /* Device has completely failed, is unrecoverable */
537 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
539 /* Device driver is fully recovered and operational */
540 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
543 /* PCI bus error event callbacks */
544 struct pci_error_handlers {
545 /* PCI bus error detected on this device */
546 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
547 enum pci_channel_state error);
549 /* MMIO has been re-enabled, but not DMA */
550 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
552 /* PCI Express link has been reset */
553 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
555 /* PCI slot has been reset */
556 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
558 /* Device driver may resume normal operations */
559 void (*resume)(struct pci_dev *dev);
562 /* ---------------------------------------------------------------- */
566 struct list_head node;
568 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
569 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
570 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
571 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
572 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
573 int (*resume_early) (struct pci_dev *dev);
574 int (*resume) (struct pci_dev *dev); /* Device woken up */
575 void (*shutdown) (struct pci_dev *dev);
576 const struct pci_error_handlers *err_handler;
577 struct device_driver driver;
578 struct pci_dynids dynids;
581 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
584 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
585 * @_table: device table name
587 * This macro is used to create a struct pci_device_id array (a device table)
588 * in a generic manner.
590 #define DEFINE_PCI_DEVICE_TABLE(_table) \
591 const struct pci_device_id _table[]
594 * PCI_DEVICE - macro used to describe a specific pci device
595 * @vend: the 16 bit PCI Vendor ID
596 * @dev: the 16 bit PCI Device ID
598 * This macro is used to create a struct pci_device_id that matches a
599 * specific device. The subvendor and subdevice fields will be set to
602 #define PCI_DEVICE(vend,dev) \
603 .vendor = (vend), .device = (dev), \
604 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
607 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
608 * @vend: the 16 bit PCI Vendor ID
609 * @dev: the 16 bit PCI Device ID
610 * @subvend: the 16 bit PCI Subvendor ID
611 * @subdev: the 16 bit PCI Subdevice ID
613 * This macro is used to create a struct pci_device_id that matches a
614 * specific device with subsystem information.
616 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
617 .vendor = (vend), .device = (dev), \
618 .subvendor = (subvend), .subdevice = (subdev)
621 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
622 * @dev_class: the class, subclass, prog-if triple for this device
623 * @dev_class_mask: the class mask for this device
625 * This macro is used to create a struct pci_device_id that matches a
626 * specific PCI class. The vendor, device, subvendor, and subdevice
627 * fields will be set to PCI_ANY_ID.
629 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
630 .class = (dev_class), .class_mask = (dev_class_mask), \
631 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
632 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
635 * PCI_VDEVICE - macro used to describe a specific pci device in short form
636 * @vendor: the vendor name
637 * @device: the 16 bit PCI Device ID
639 * This macro is used to create a struct pci_device_id that matches a
640 * specific PCI device. The subvendor, and subdevice fields will be set
641 * to PCI_ANY_ID. The macro allows the next field to follow as the device
645 #define PCI_VDEVICE(vendor, device) \
646 PCI_VENDOR_ID_##vendor, (device), \
647 PCI_ANY_ID, PCI_ANY_ID, 0, 0
649 /* these external functions are only available when PCI support is enabled */
652 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
654 enum pcie_bus_config_types {
657 PCIE_BUS_PERFORMANCE,
661 extern enum pcie_bus_config_types pcie_bus_config;
663 extern struct bus_type pci_bus_type;
665 /* Do NOT directly access these two variables, unless you are arch specific pci
666 * code, or pci core code. */
667 extern struct list_head pci_root_buses; /* list of all known PCI buses */
668 /* Some device drivers need know if pci is initiated */
669 extern int no_pci_devices(void);
671 void pcibios_fixup_bus(struct pci_bus *);
672 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
673 /* Architecture specific versions may override this (weak) */
674 char *pcibios_setup(char *str);
676 /* Used only when drivers/pci/setup.c is used */
677 resource_size_t pcibios_align_resource(void *, const struct resource *,
680 void pcibios_update_irq(struct pci_dev *, int irq);
682 /* Weak but can be overriden by arch */
683 void pci_fixup_cardbus(struct pci_bus *);
685 /* Generic PCI functions used internally */
687 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
688 struct resource *res);
689 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
690 struct pci_bus_region *region);
691 void pcibios_scan_specific_bus(int busn);
692 extern struct pci_bus *pci_find_bus(int domain, int busnr);
693 void pci_bus_add_devices(const struct pci_bus *bus);
694 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
695 struct pci_ops *ops, void *sysdata);
696 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
697 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
698 struct pci_ops *ops, void *sysdata,
699 struct list_head *resources);
700 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
701 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
702 void pci_bus_release_busn_res(struct pci_bus *b);
703 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
704 struct pci_ops *ops, void *sysdata,
705 struct list_head *resources);
706 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
708 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
709 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
711 struct hotplug_slot *hotplug);
712 void pci_destroy_slot(struct pci_slot *slot);
713 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
714 int pci_scan_slot(struct pci_bus *bus, int devfn);
715 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
716 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
717 unsigned int pci_scan_child_bus(struct pci_bus *bus);
718 int __must_check pci_bus_add_device(struct pci_dev *dev);
719 void pci_read_bridge_bases(struct pci_bus *child);
720 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
721 struct resource *res);
722 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
723 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
724 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
725 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
726 extern void pci_dev_put(struct pci_dev *dev);
727 extern void pci_remove_bus(struct pci_bus *b);
728 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
729 void pci_setup_cardbus(struct pci_bus *bus);
730 extern void pci_sort_breadthfirst(void);
731 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
732 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
733 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
735 /* Generic PCI functions exported to card drivers */
737 enum pci_lost_interrupt_reason {
738 PCI_LOST_IRQ_NO_INFORMATION = 0,
739 PCI_LOST_IRQ_DISABLE_MSI,
740 PCI_LOST_IRQ_DISABLE_MSIX,
741 PCI_LOST_IRQ_DISABLE_ACPI,
743 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
744 int pci_find_capability(struct pci_dev *dev, int cap);
745 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
746 int pci_find_ext_capability(struct pci_dev *dev, int cap);
747 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
748 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
749 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
750 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
752 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
753 struct pci_dev *from);
754 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
755 unsigned int ss_vendor, unsigned int ss_device,
756 struct pci_dev *from);
757 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
758 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
760 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
763 return pci_get_domain_bus_and_slot(0, bus, devfn);
765 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
766 int pci_dev_present(const struct pci_device_id *ids);
768 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
770 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
771 int where, u16 *val);
772 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
773 int where, u32 *val);
774 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
776 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
778 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
780 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
782 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
784 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
786 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
788 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
790 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
793 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
795 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
797 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
799 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
801 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
803 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
806 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
809 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
810 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
811 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
812 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
813 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
815 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
818 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
821 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
824 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
827 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
830 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
833 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
836 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
839 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
842 /* user-space driven config access */
843 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
844 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
845 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
846 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
847 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
848 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
850 int __must_check pci_enable_device(struct pci_dev *dev);
851 int __must_check pci_enable_device_io(struct pci_dev *dev);
852 int __must_check pci_enable_device_mem(struct pci_dev *dev);
853 int __must_check pci_reenable_device(struct pci_dev *);
854 int __must_check pcim_enable_device(struct pci_dev *pdev);
855 void pcim_pin_device(struct pci_dev *pdev);
857 static inline int pci_is_enabled(struct pci_dev *pdev)
859 return (atomic_read(&pdev->enable_cnt) > 0);
862 static inline int pci_is_managed(struct pci_dev *pdev)
864 return pdev->is_managed;
867 void pci_disable_device(struct pci_dev *dev);
869 extern unsigned int pcibios_max_latency;
870 void pci_set_master(struct pci_dev *dev);
871 void pci_clear_master(struct pci_dev *dev);
873 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
874 int pci_set_cacheline_size(struct pci_dev *dev);
875 #define HAVE_PCI_SET_MWI
876 int __must_check pci_set_mwi(struct pci_dev *dev);
877 int pci_try_set_mwi(struct pci_dev *dev);
878 void pci_clear_mwi(struct pci_dev *dev);
879 void pci_intx(struct pci_dev *dev, int enable);
880 bool pci_intx_mask_supported(struct pci_dev *dev);
881 bool pci_check_and_mask_intx(struct pci_dev *dev);
882 bool pci_check_and_unmask_intx(struct pci_dev *dev);
883 void pci_msi_off(struct pci_dev *dev);
884 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
885 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
886 int pcix_get_max_mmrbc(struct pci_dev *dev);
887 int pcix_get_mmrbc(struct pci_dev *dev);
888 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
889 int pcie_get_readrq(struct pci_dev *dev);
890 int pcie_set_readrq(struct pci_dev *dev, int rq);
891 int pcie_get_mps(struct pci_dev *dev);
892 int pcie_set_mps(struct pci_dev *dev, int mps);
893 int __pci_reset_function(struct pci_dev *dev);
894 int __pci_reset_function_locked(struct pci_dev *dev);
895 int pci_reset_function(struct pci_dev *dev);
896 void pci_update_resource(struct pci_dev *dev, int resno);
897 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
898 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
899 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
901 /* ROM control related routines */
902 int pci_enable_rom(struct pci_dev *pdev);
903 void pci_disable_rom(struct pci_dev *pdev);
904 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
905 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
906 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
908 /* Power management related routines */
909 int pci_save_state(struct pci_dev *dev);
910 void pci_restore_state(struct pci_dev *dev);
911 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
912 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
913 int pci_load_and_free_saved_state(struct pci_dev *dev,
914 struct pci_saved_state **state);
915 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
916 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
917 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
918 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
919 void pci_pme_active(struct pci_dev *dev, bool enable);
920 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
921 bool runtime, bool enable);
922 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
923 pci_power_t pci_target_state(struct pci_dev *dev);
924 int pci_prepare_to_sleep(struct pci_dev *dev);
925 int pci_back_from_sleep(struct pci_dev *dev);
926 bool pci_dev_run_wake(struct pci_dev *dev);
927 bool pci_check_pme_status(struct pci_dev *dev);
928 void pci_pme_wakeup_bus(struct pci_bus *bus);
930 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
933 return __pci_enable_wake(dev, state, false, enable);
936 #define PCI_EXP_IDO_REQUEST (1<<0)
937 #define PCI_EXP_IDO_COMPLETION (1<<1)
938 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
939 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
941 enum pci_obff_signal_type {
942 PCI_EXP_OBFF_SIGNAL_L0 = 0,
943 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
945 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
946 void pci_disable_obff(struct pci_dev *dev);
948 int pci_enable_ltr(struct pci_dev *dev);
949 void pci_disable_ltr(struct pci_dev *dev);
950 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
952 /* For use by arch with custom probe code */
953 void set_pcie_port_type(struct pci_dev *pdev);
954 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
956 /* Functions for PCI Hotplug drivers to use */
957 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
958 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
959 unsigned int pci_rescan_bus(struct pci_bus *bus);
961 /* Vital product data routines */
962 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
963 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
964 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
966 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
967 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
968 void pci_bus_assign_resources(const struct pci_bus *bus);
969 void pci_bus_size_bridges(struct pci_bus *bus);
970 int pci_claim_resource(struct pci_dev *, int);
971 void pci_assign_unassigned_resources(void);
972 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
973 void pdev_enable_device(struct pci_dev *);
974 int pci_enable_resources(struct pci_dev *, int mask);
975 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
976 int (*)(const struct pci_dev *, u8, u8));
977 #define HAVE_PCI_REQ_REGIONS 2
978 int __must_check pci_request_regions(struct pci_dev *, const char *);
979 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
980 void pci_release_regions(struct pci_dev *);
981 int __must_check pci_request_region(struct pci_dev *, int, const char *);
982 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
983 void pci_release_region(struct pci_dev *, int);
984 int pci_request_selected_regions(struct pci_dev *, int, const char *);
985 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
986 void pci_release_selected_regions(struct pci_dev *, int);
988 /* drivers/pci/bus.c */
989 void pci_add_resource(struct list_head *resources, struct resource *res);
990 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
991 resource_size_t offset);
992 void pci_free_resource_list(struct list_head *resources);
993 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
994 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
995 void pci_bus_remove_resources(struct pci_bus *bus);
997 #define pci_bus_for_each_resource(bus, res, i) \
999 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1002 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1003 struct resource *res, resource_size_t size,
1004 resource_size_t align, resource_size_t min,
1005 unsigned int type_mask,
1006 resource_size_t (*alignf)(void *,
1007 const struct resource *,
1011 void pci_enable_bridges(struct pci_bus *bus);
1013 /* Proper probing supporting hot-pluggable devices */
1014 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1015 const char *mod_name);
1018 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1020 #define pci_register_driver(driver) \
1021 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1023 void pci_unregister_driver(struct pci_driver *dev);
1026 * module_pci_driver() - Helper macro for registering a PCI driver
1027 * @__pci_driver: pci_driver struct
1029 * Helper macro for PCI drivers which do not do anything special in module
1030 * init/exit. This eliminates a lot of boilerplate. Each module may only
1031 * use this macro once, and calling it replaces module_init() and module_exit()
1033 #define module_pci_driver(__pci_driver) \
1034 module_driver(__pci_driver, pci_register_driver, \
1035 pci_unregister_driver)
1037 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1038 int pci_add_dynid(struct pci_driver *drv,
1039 unsigned int vendor, unsigned int device,
1040 unsigned int subvendor, unsigned int subdevice,
1041 unsigned int class, unsigned int class_mask,
1042 unsigned long driver_data);
1043 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1044 struct pci_dev *dev);
1045 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1048 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1050 int pci_cfg_space_size_ext(struct pci_dev *dev);
1051 int pci_cfg_space_size(struct pci_dev *dev);
1052 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1053 void pci_setup_bridge(struct pci_bus *bus);
1054 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1055 unsigned long type);
1057 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1058 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1060 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1061 unsigned int command_bits, u32 flags);
1062 /* kmem_cache style wrapper around pci_alloc_consistent() */
1064 #include <linux/pci-dma.h>
1065 #include <linux/dmapool.h>
1067 #define pci_pool dma_pool
1068 #define pci_pool_create(name, pdev, size, align, allocation) \
1069 dma_pool_create(name, &pdev->dev, size, align, allocation)
1070 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1071 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1072 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1074 enum pci_dma_burst_strategy {
1075 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1076 strategy_parameter is N/A */
1077 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1079 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1080 strategy_parameter byte boundaries */
1084 u32 vector; /* kernel uses to write allocated vector */
1085 u16 entry; /* driver uses to specify entry, OS writes */
1089 #ifndef CONFIG_PCI_MSI
1090 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1095 static inline void pci_msi_shutdown(struct pci_dev *dev)
1097 static inline void pci_disable_msi(struct pci_dev *dev)
1100 static inline int pci_msix_table_size(struct pci_dev *dev)
1104 static inline int pci_enable_msix(struct pci_dev *dev,
1105 struct msix_entry *entries, int nvec)
1110 static inline void pci_msix_shutdown(struct pci_dev *dev)
1112 static inline void pci_disable_msix(struct pci_dev *dev)
1115 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1118 static inline void pci_restore_msi_state(struct pci_dev *dev)
1120 static inline int pci_msi_enabled(void)
1125 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1126 extern void pci_msi_shutdown(struct pci_dev *dev);
1127 extern void pci_disable_msi(struct pci_dev *dev);
1128 extern int pci_msix_table_size(struct pci_dev *dev);
1129 extern int pci_enable_msix(struct pci_dev *dev,
1130 struct msix_entry *entries, int nvec);
1131 extern void pci_msix_shutdown(struct pci_dev *dev);
1132 extern void pci_disable_msix(struct pci_dev *dev);
1133 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1134 extern void pci_restore_msi_state(struct pci_dev *dev);
1135 extern int pci_msi_enabled(void);
1138 #ifdef CONFIG_PCIEPORTBUS
1139 extern bool pcie_ports_disabled;
1140 extern bool pcie_ports_auto;
1142 #define pcie_ports_disabled true
1143 #define pcie_ports_auto false
1146 #ifndef CONFIG_PCIEASPM
1147 static inline int pcie_aspm_enabled(void) { return 0; }
1148 static inline bool pcie_aspm_support_enabled(void) { return false; }
1150 extern int pcie_aspm_enabled(void);
1151 extern bool pcie_aspm_support_enabled(void);
1154 #ifdef CONFIG_PCIEAER
1155 void pci_no_aer(void);
1156 bool pci_aer_available(void);
1158 static inline void pci_no_aer(void) { }
1159 static inline bool pci_aer_available(void) { return false; }
1162 #ifndef CONFIG_PCIE_ECRC
1163 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1167 static inline void pcie_ecrc_get_policy(char *str) {};
1169 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1170 extern void pcie_ecrc_get_policy(char *str);
1173 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1175 #ifdef CONFIG_HT_IRQ
1176 /* The functions a driver should call */
1177 int ht_create_irq(struct pci_dev *dev, int idx);
1178 void ht_destroy_irq(unsigned int irq);
1179 #endif /* CONFIG_HT_IRQ */
1181 extern void pci_cfg_access_lock(struct pci_dev *dev);
1182 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1183 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1186 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1187 * a PCI domain is defined to be a set of PCI busses which share
1188 * configuration space.
1190 #ifdef CONFIG_PCI_DOMAINS
1191 extern int pci_domains_supported;
1193 enum { pci_domains_supported = 0 };
1194 static inline int pci_domain_nr(struct pci_bus *bus)
1199 static inline int pci_proc_domain(struct pci_bus *bus)
1203 #endif /* CONFIG_PCI_DOMAINS */
1205 /* some architectures require additional setup to direct VGA traffic */
1206 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1207 unsigned int command_bits, u32 flags);
1208 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1210 #else /* CONFIG_PCI is not enabled */
1213 * If the system does not have PCI, clearly these return errors. Define
1214 * these as simple inline functions to avoid hair in drivers.
1217 #define _PCI_NOP(o, s, t) \
1218 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1220 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1222 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1223 _PCI_NOP(o, word, u16 x) \
1224 _PCI_NOP(o, dword, u32 x)
1225 _PCI_NOP_ALL(read, *)
1226 _PCI_NOP_ALL(write,)
1228 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1229 unsigned int device,
1230 struct pci_dev *from)
1235 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1236 unsigned int device,
1237 unsigned int ss_vendor,
1238 unsigned int ss_device,
1239 struct pci_dev *from)
1244 static inline struct pci_dev *pci_get_class(unsigned int class,
1245 struct pci_dev *from)
1250 #define pci_dev_present(ids) (0)
1251 #define no_pci_devices() (1)
1252 #define pci_dev_put(dev) do { } while (0)
1254 static inline void pci_set_master(struct pci_dev *dev)
1257 static inline int pci_enable_device(struct pci_dev *dev)
1262 static inline void pci_disable_device(struct pci_dev *dev)
1265 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1270 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1275 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1281 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1287 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1292 static inline int __pci_register_driver(struct pci_driver *drv,
1293 struct module *owner)
1298 static inline int pci_register_driver(struct pci_driver *drv)
1303 static inline void pci_unregister_driver(struct pci_driver *drv)
1306 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1311 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1317 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1322 /* Power management related routines */
1323 static inline int pci_save_state(struct pci_dev *dev)
1328 static inline void pci_restore_state(struct pci_dev *dev)
1331 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1336 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1341 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1347 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1353 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1357 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1361 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1366 static inline void pci_disable_obff(struct pci_dev *dev)
1370 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1375 static inline void pci_release_regions(struct pci_dev *dev)
1378 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1380 static inline void pci_block_cfg_access(struct pci_dev *dev)
1383 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1386 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1389 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1392 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1396 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1400 static inline int pci_domain_nr(struct pci_bus *bus)
1403 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1406 #define dev_is_pci(d) (false)
1407 #define dev_is_pf(d) (false)
1408 #define dev_num_vf(d) (0)
1409 #endif /* CONFIG_PCI */
1411 /* Include architecture-dependent settings and functions */
1413 #include <asm/pci.h>
1415 #ifndef PCIBIOS_MAX_MEM_32
1416 #define PCIBIOS_MAX_MEM_32 (-1)
1419 /* these helpers provide future and backwards compatibility
1420 * for accessing popular PCI BAR info */
1421 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1422 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1423 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1424 #define pci_resource_len(dev,bar) \
1425 ((pci_resource_start((dev), (bar)) == 0 && \
1426 pci_resource_end((dev), (bar)) == \
1427 pci_resource_start((dev), (bar))) ? 0 : \
1429 (pci_resource_end((dev), (bar)) - \
1430 pci_resource_start((dev), (bar)) + 1))
1432 /* Similar to the helpers above, these manipulate per-pci_dev
1433 * driver-specific data. They are really just a wrapper around
1434 * the generic device structure functions of these calls.
1436 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1438 return dev_get_drvdata(&pdev->dev);
1441 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1443 dev_set_drvdata(&pdev->dev, data);
1446 /* If you want to know what to call your pci_dev, ask this function.
1447 * Again, it's a wrapper around the generic device.
1449 static inline const char *pci_name(const struct pci_dev *pdev)
1451 return dev_name(&pdev->dev);
1455 /* Some archs don't want to expose struct resource to userland as-is
1456 * in sysfs and /proc
1458 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1459 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1460 const struct resource *rsrc, resource_size_t *start,
1461 resource_size_t *end)
1463 *start = rsrc->start;
1466 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1470 * The world is not perfect and supplies us with broken PCI devices.
1471 * For at least a part of these bugs we need a work-around, so both
1472 * generic (drivers/pci/quirks.c) and per-architecture code can define
1473 * fixup hooks to be called for particular buggy devices.
1477 u16 vendor; /* You can use PCI_ANY_ID here of course */
1478 u16 device; /* You can use PCI_ANY_ID here of course */
1479 u32 class; /* You can use PCI_ANY_ID here too */
1480 unsigned int class_shift; /* should be 0, 8, 16 */
1481 void (*hook)(struct pci_dev *dev);
1484 enum pci_fixup_pass {
1485 pci_fixup_early, /* Before probing BARs */
1486 pci_fixup_header, /* After reading configuration header */
1487 pci_fixup_final, /* Final phase of device fixups */
1488 pci_fixup_enable, /* pci_enable_device() time */
1489 pci_fixup_resume, /* pci_device_resume() */
1490 pci_fixup_suspend, /* pci_device_suspend */
1491 pci_fixup_resume_early, /* pci_device_resume_early() */
1494 /* Anonymous variables would be nice... */
1495 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1496 class_shift, hook) \
1497 static const struct pci_fixup __pci_fixup_##name __used \
1498 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1499 = { vendor, device, class, class_shift, hook };
1501 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1502 class_shift, hook) \
1503 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1504 vendor##device##hook, vendor, device, class, class_shift, hook)
1505 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1506 class_shift, hook) \
1507 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1508 vendor##device##hook, vendor, device, class, class_shift, hook)
1509 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1510 class_shift, hook) \
1511 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1512 vendor##device##hook, vendor, device, class, class_shift, hook)
1513 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1514 class_shift, hook) \
1515 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1516 vendor##device##hook, vendor, device, class, class_shift, hook)
1517 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1518 class_shift, hook) \
1519 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1520 resume##vendor##device##hook, vendor, device, class, \
1522 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1523 class_shift, hook) \
1524 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1525 resume_early##vendor##device##hook, vendor, device, \
1526 class, class_shift, hook)
1527 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1528 class_shift, hook) \
1529 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1530 suspend##vendor##device##hook, vendor, device, class, \
1533 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1534 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1535 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1536 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1537 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1538 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1539 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1540 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1541 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1542 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1543 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1544 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1545 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1546 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1547 resume##vendor##device##hook, vendor, device, \
1548 PCI_ANY_ID, 0, hook)
1549 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1551 resume_early##vendor##device##hook, vendor, device, \
1552 PCI_ANY_ID, 0, hook)
1553 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1554 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1555 suspend##vendor##device##hook, vendor, device, \
1556 PCI_ANY_ID, 0, hook)
1558 #ifdef CONFIG_PCI_QUIRKS
1559 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1560 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1561 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1563 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1564 struct pci_dev *dev) {}
1565 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1567 return pci_dev_get(dev);
1569 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1576 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1577 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1578 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1579 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1580 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1582 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1584 extern int pci_pci_problems;
1585 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1586 #define PCIPCI_TRITON 2
1587 #define PCIPCI_NATOMA 4
1588 #define PCIPCI_VIAETBF 8
1589 #define PCIPCI_VSFX 16
1590 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1591 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1593 extern unsigned long pci_cardbus_io_size;
1594 extern unsigned long pci_cardbus_mem_size;
1595 extern u8 pci_dfl_cache_line_size;
1596 extern u8 pci_cache_line_size;
1598 extern unsigned long pci_hotplug_io_size;
1599 extern unsigned long pci_hotplug_mem_size;
1601 /* Architecture specific versions may override these (weak) */
1602 int pcibios_add_platform_entries(struct pci_dev *dev);
1603 void pcibios_disable_device(struct pci_dev *dev);
1604 void pcibios_set_master(struct pci_dev *dev);
1605 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1606 enum pcie_reset_state state);
1608 #ifdef CONFIG_PCI_MMCONFIG
1609 extern void __init pci_mmcfg_early_init(void);
1610 extern void __init pci_mmcfg_late_init(void);
1612 static inline void pci_mmcfg_early_init(void) { }
1613 static inline void pci_mmcfg_late_init(void) { }
1616 int pci_ext_cfg_avail(struct pci_dev *dev);
1618 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1620 #ifdef CONFIG_PCI_IOV
1621 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1622 extern void pci_disable_sriov(struct pci_dev *dev);
1623 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1624 extern int pci_num_vf(struct pci_dev *dev);
1626 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1630 static inline void pci_disable_sriov(struct pci_dev *dev)
1633 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1637 static inline int pci_num_vf(struct pci_dev *dev)
1643 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1644 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1645 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1649 * pci_pcie_cap - get the saved PCIe capability offset
1652 * PCIe capability offset is calculated at PCI device initialization
1653 * time and saved in the data structure. This function returns saved
1654 * PCIe capability offset. Using this instead of pci_find_capability()
1655 * reduces unnecessary search in the PCI configuration space. If you
1656 * need to calculate PCIe capability offset from raw device for some
1657 * reasons, please use pci_find_capability() instead.
1659 static inline int pci_pcie_cap(struct pci_dev *dev)
1661 return dev->pcie_cap;
1665 * pci_is_pcie - check if the PCI device is PCI Express capable
1668 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1670 static inline bool pci_is_pcie(struct pci_dev *dev)
1672 return !!pci_pcie_cap(dev);
1676 * pci_pcie_type - get the PCIe device/port type
1679 static inline int pci_pcie_type(const struct pci_dev *dev)
1681 return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4;
1684 void pci_request_acs(void);
1685 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1686 bool pci_acs_path_enabled(struct pci_dev *start,
1687 struct pci_dev *end, u16 acs_flags);
1689 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1690 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1692 /* Large Resource Data Type Tag Item Names */
1693 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1694 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1695 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1697 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1698 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1699 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1701 /* Small Resource Data Type Tag Item Names */
1702 #define PCI_VPD_STIN_END 0x78 /* End */
1704 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1706 #define PCI_VPD_SRDT_TIN_MASK 0x78
1707 #define PCI_VPD_SRDT_LEN_MASK 0x07
1709 #define PCI_VPD_LRDT_TAG_SIZE 3
1710 #define PCI_VPD_SRDT_TAG_SIZE 1
1712 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1714 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1715 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1716 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1717 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1720 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1721 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1723 * Returns the extracted Large Resource Data Type length.
1725 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1727 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1731 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1732 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1734 * Returns the extracted Small Resource Data Type length.
1736 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1738 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1742 * pci_vpd_info_field_size - Extracts the information field length
1743 * @lrdt: Pointer to the beginning of an information field header
1745 * Returns the extracted information field length.
1747 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1749 return info_field[2];
1753 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1754 * @buf: Pointer to buffered vpd data
1755 * @off: The offset into the buffer at which to begin the search
1756 * @len: The length of the vpd buffer
1757 * @rdt: The Resource Data Type to search for
1759 * Returns the index where the Resource Data Type was found or
1760 * -ENOENT otherwise.
1762 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1765 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1766 * @buf: Pointer to buffered vpd data
1767 * @off: The offset into the buffer at which to begin the search
1768 * @len: The length of the buffer area, relative to off, in which to search
1769 * @kw: The keyword to search for
1771 * Returns the index where the information field keyword was found or
1772 * -ENOENT otherwise.
1774 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1775 unsigned int len, const char *kw);
1777 /* PCI <-> OF binding helpers */
1780 extern void pci_set_of_node(struct pci_dev *dev);
1781 extern void pci_release_of_node(struct pci_dev *dev);
1782 extern void pci_set_bus_of_node(struct pci_bus *bus);
1783 extern void pci_release_bus_of_node(struct pci_bus *bus);
1785 /* Arch may override this (weak) */
1786 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1788 static inline struct device_node *
1789 pci_device_to_OF_node(const struct pci_dev *pdev)
1791 return pdev ? pdev->dev.of_node : NULL;
1794 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1796 return bus ? bus->dev.of_node : NULL;
1799 #else /* CONFIG_OF */
1800 static inline void pci_set_of_node(struct pci_dev *dev) { }
1801 static inline void pci_release_of_node(struct pci_dev *dev) { }
1802 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1803 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1804 #endif /* CONFIG_OF */
1807 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1809 return pdev->dev.archdata.edev;
1814 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1815 * @pdev: the PCI device
1817 * if the device is PCIE, return NULL
1818 * if the device isn't connected to a PCIe bridge (that is its parent is a
1819 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1822 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1824 #endif /* LINUX_PCI_H */