arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         tzic: tz-interrupt-controller@0fffc000 {
  32                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  33                 interrupt-controller;
  34                 #interrupt-cells = <1>;
  35                 reg = <0x0fffc000 0x4000>;
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 ckil {
  43                         compatible = "fsl,imx-ckil", "fixed-clock";
  44                         clock-frequency = <32768>;
  45                 };
  46
  47                 ckih1 {
  48                         compatible = "fsl,imx-ckih1", "fixed-clock";
  49                         clock-frequency = <22579200>;
  50                 };
  51
  52                 ckih2 {
  53                         compatible = "fsl,imx-ckih2", "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 osc {
  58                         compatible = "fsl,imx-osc", "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61         };
  62
  63         soc {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "simple-bus";
  67                 interrupt-parent = <&tzic>;
  68                 ranges;
  69
  70                 aips@50000000 { /* AIPS1 */
  71                         compatible = "fsl,aips-bus", "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         reg = <0x50000000 0x10000000>;
  75                         ranges;
  76
  77                         spba@50000000 {
  78                                 compatible = "fsl,spba-bus", "simple-bus";
  79                                 #address-cells = <1>;
  80                                 #size-cells = <1>;
  81                                 reg = <0x50000000 0x40000>;
  82                                 ranges;
  83
  84                                 esdhc1: esdhc@50004000 {
  85                                         compatible = "fsl,imx53-esdhc";
  86                                         reg = <0x50004000 0x4000>;
  87                                         interrupts = <1>;
  88                                         bus-width = <4>;
  89                                         status = "disabled";
  90                                 };
  91
  92                                 esdhc2: esdhc@50008000 {
  93                                         compatible = "fsl,imx53-esdhc";
  94                                         reg = <0x50008000 0x4000>;
  95                                         interrupts = <2>;
  96                                         bus-width = <4>;
  97                                         status = "disabled";
  98                                 };
  99
 100                                 uart3: serial@5000c000 {
 101                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 102                                         reg = <0x5000c000 0x4000>;
 103                                         interrupts = <33>;
 104                                         status = "disabled";
 105                                 };
 106
 107                                 ecspi1: ecspi@50010000 {
 108                                         #address-cells = <1>;
 109                                         #size-cells = <0>;
 110                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 111                                         reg = <0x50010000 0x4000>;
 112                                         interrupts = <36>;
 113                                         status = "disabled";
 114                                 };
 115
 116                                 ssi2: ssi@50014000 {
 117                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 118                                         reg = <0x50014000 0x4000>;
 119                                         interrupts = <30>;
 120                                         fsl,fifo-depth = <15>;
 121                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 122                                         status = "disabled";
 123                                 };
 124
 125                                 esdhc3: esdhc@50020000 {
 126                                         compatible = "fsl,imx53-esdhc";
 127                                         reg = <0x50020000 0x4000>;
 128                                         interrupts = <3>;
 129                                         bus-width = <4>;
 130                                         status = "disabled";
 131                                 };
 132
 133                                 esdhc4: esdhc@50024000 {
 134                                         compatible = "fsl,imx53-esdhc";
 135                                         reg = <0x50024000 0x4000>;
 136                                         interrupts = <4>;
 137                                         bus-width = <4>;
 138                                         status = "disabled";
 139                                 };
 140                         };
 141
 142                         usbotg: usb@53f80000 {
 143                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 144                                 reg = <0x53f80000 0x0200>;
 145                                 interrupts = <18>;
 146                                 status = "disabled";
 147                         };
 148
 149                         usbh1: usb@53f80200 {
 150                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 151                                 reg = <0x53f80200 0x0200>;
 152                                 interrupts = <14>;
 153                                 status = "disabled";
 154                         };
 155
 156                         usbh2: usb@53f80400 {
 157                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 158                                 reg = <0x53f80400 0x0200>;
 159                                 interrupts = <16>;
 160                                 status = "disabled";
 161                         };
 162
 163                         usbh3: usb@53f80600 {
 164                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 165                                 reg = <0x53f80600 0x0200>;
 166                                 interrupts = <17>;
 167                                 status = "disabled";
 168                         };
 169
 170                         gpio1: gpio@53f84000 {
 171                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 172                                 reg = <0x53f84000 0x4000>;
 173                                 interrupts = <50 51>;
 174                                 gpio-controller;
 175                                 #gpio-cells = <2>;
 176                                 interrupt-controller;
 177                                 #interrupt-cells = <2>;
 178                         };
 179
 180                         gpio2: gpio@53f88000 {
 181                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 182                                 reg = <0x53f88000 0x4000>;
 183                                 interrupts = <52 53>;
 184                                 gpio-controller;
 185                                 #gpio-cells = <2>;
 186                                 interrupt-controller;
 187                                 #interrupt-cells = <2>;
 188                         };
 189
 190                         gpio3: gpio@53f8c000 {
 191                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 192                                 reg = <0x53f8c000 0x4000>;
 193                                 interrupts = <54 55>;
 194                                 gpio-controller;
 195                                 #gpio-cells = <2>;
 196                                 interrupt-controller;
 197                                 #interrupt-cells = <2>;
 198                         };
 199
 200                         gpio4: gpio@53f90000 {
 201                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 202                                 reg = <0x53f90000 0x4000>;
 203                                 interrupts = <56 57>;
 204                                 gpio-controller;
 205                                 #gpio-cells = <2>;
 206                                 interrupt-controller;
 207                                 #interrupt-cells = <2>;
 208                         };
 209
 210                         wdog1: wdog@53f98000 {
 211                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 212                                 reg = <0x53f98000 0x4000>;
 213                                 interrupts = <58>;
 214                         };
 215
 216                         wdog2: wdog@53f9c000 {
 217                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 218                                 reg = <0x53f9c000 0x4000>;
 219                                 interrupts = <59>;
 220                                 status = "disabled";
 221                         };
 222
 223                         iomuxc: iomuxc@53fa8000 {
 224                                 compatible = "fsl,imx53-iomuxc";
 225                                 reg = <0x53fa8000 0x4000>;
 226
 227                                 audmux {
 228                                         pinctrl_audmux_1: audmuxgrp-1 {
 229                                                 fsl,pins = <
 230                                                         10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
 231                                                         17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
 232                                                         23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
 233                                                         30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
 234                                                 >;
 235                                         };
 236                                 };
 237
 238                                 fec {
 239                                         pinctrl_fec_1: fecgrp-1 {
 240                                                 fsl,pins = <
 241                                                         820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
 242                                                         779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
 243                                                         786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
 244                                                         791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
 245                                                         796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
 246                                                         799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
 247                                                         804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
 248                                                         808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
 249                                                         811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
 250                                                         816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
 251                                                 >;
 252                                         };
 253                                 };
 254
 255                                 ecspi1 {
 256                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 257                                                 fsl,pins = <
 258                                                         433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
 259                                                         439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
 260                                                         445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
 261                                                 >;
 262                                         };
 263                                 };
 264
 265                                 esdhc1 {
 266                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 267                                                 fsl,pins = <
 268                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 269                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 270                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 271                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 272                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 273                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 274                                                 >;
 275                                         };
 276
 277                                         pinctrl_esdhc1_2: esdhc1grp-2 {
 278                                                 fsl,pins = <
 279                                                         995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
 280                                                         1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
 281                                                         1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
 282                                                         1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
 283                                                         941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
 284                                                         948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
 285                                                         955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
 286                                                         962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
 287                                                         1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
 288                                                         1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
 289                                                 >;
 290                                         };
 291                                 };
 292
 293                                 esdhc2 {
 294                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 295                                                 fsl,pins = <
 296                                                         1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
 297                                                         1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
 298                                                         1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
 299                                                         1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
 300                                                         1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
 301                                                         1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
 302                                                 >;
 303                                         };
 304                                 };
 305
 306                                 esdhc3 {
 307                                         pinctrl_esdhc3_1: esdhc3grp-1 {
 308                                                 fsl,pins = <
 309                                                         943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
 310                                                         950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
 311                                                         957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
 312                                                         964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
 313                                                         893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
 314                                                         900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
 315                                                         906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
 316                                                         912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
 317                                                         857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
 318                                                         863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
 319                                                 >;
 320                                         };
 321                                 };
 322
 323                                 can1 {
 324                                         pinctrl_can1_1: can1grp-1 {
 325                                                 fsl,pins = <
 326                                                         847 0x80000000  /* MX53_PAD_PATA_INTRQ__CAN1_TXCAN */
 327                                                         853 0x80000000  /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
 328                                                 >;
 329                                         };
 330                                 };
 331
 332                                 can2 {
 333                                         pinctrl_can2_1: can2grp-1 {
 334                                                 fsl,pins = <
 335                                                         67  0x80000000  /* MX53_PAD_KEY_COL4__CAN2_TXCAN */
 336                                                         74  0x80000000  /* MX53_PAD_KEY_ROW4__CAN2_RXCAN */
 337                                                 >;
 338                                         };
 339                                 };
 340
 341                                 i2c1 {
 342                                         pinctrl_i2c1_1: i2c1grp-1 {
 343                                                 fsl,pins = <
 344                                                         333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
 345                                                         341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
 346                                                 >;
 347                                         };
 348                                 };
 349
 350                                 i2c2 {
 351                                         pinctrl_i2c2_1: i2c2grp-1 {
 352                                                 fsl,pins = <
 353                                                         61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
 354                                                         53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
 355                                                 >;
 356                                         };
 357                                 };
 358
 359                                 i2c3 {
 360                                         pinctrl_i2c3_1: i2c3grp-1 {
 361                                                 fsl,pins = <
 362                                                         1102 0xc0000000 /* MX53_PAD_GPIO_6__I2C3_SDA */
 363                                                         1130 0xc0000000 /* MX53_PAD_GPIO_5__I2C3_SCL */
 364                                                 >;
 365                                         };
 366                                 };
 367
 368                                 uart1 {
 369                                         pinctrl_uart1_1: uart1grp-1 {
 370                                                 fsl,pins = <
 371                                                         346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
 372                                                         354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
 373                                                 >;
 374                                         };
 375
 376                                         pinctrl_uart1_2: uart1grp-2 {
 377                                                 fsl,pins = <
 378                                                         828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
 379                                                         832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
 380                                                 >;
 381                                         };
 382                                 };
 383
 384                                 uart2 {
 385                                         pinctrl_uart2_1: uart2grp-1 {
 386                                                 fsl,pins = <
 387                                                         841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
 388                                                         836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
 389                                                 >;
 390                                         };
 391                                 };
 392
 393                                 uart3 {
 394                                         pinctrl_uart3_1: uart3grp-1 {
 395                                                 fsl,pins = <
 396                                                         884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
 397                                                         888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
 398                                                         875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
 399                                                         880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
 400                                                 >;
 401                                         };
 402                                 };
 403
 404                                 uart4 {
 405                                         pinctrl_uart4_1: uart4grp-1 {
 406                                                 fsl,pins = <
 407                                                         11 0x1c5        /* MX53_PAD_KEY_COL0__UART4_TXD_MUX */
 408                                                         18 0x1c5        /* MX53_PAD_KEY_ROW0__UART4_RXD_MUX */
 409                                                 >;
 410                                         };
 411                                 };
 412
 413                                 uart5 {
 414                                         pinctrl_uart5_1: uart5grp-1 {
 415                                                 fsl,pins = <
 416                                                         24 0x1c5        /* MX53_PAD_KEY_COL1__UART5_TXD_MUX */
 417                                                         31 0x1c5        /* MX53_PAD_KEY_ROW1__UART5_RXD_MUX */
 418                                                 >;
 419                                         };
 420                                 };
 421
 422                         };
 423
 424                         uart1: serial@53fbc000 {
 425                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 426                                 reg = <0x53fbc000 0x4000>;
 427                                 interrupts = <31>;
 428                                 status = "disabled";
 429                         };
 430
 431                         uart2: serial@53fc0000 {
 432                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 433                                 reg = <0x53fc0000 0x4000>;
 434                                 interrupts = <32>;
 435                                 status = "disabled";
 436                         };
 437
 438                         can1: can@53fc8000 {
 439                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 440                                 reg = <0x53fc8000 0x4000>;
 441                                 interrupts = <82>;
 442                                 status = "disabled";
 443                         };
 444
 445                         can2: can@53fcc000 {
 446                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 447                                 reg = <0x53fcc000 0x4000>;
 448                                 interrupts = <83>;
 449                                 status = "disabled";
 450                         };
 451
 452                         gpio5: gpio@53fdc000 {
 453                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 454                                 reg = <0x53fdc000 0x4000>;
 455                                 interrupts = <103 104>;
 456                                 gpio-controller;
 457                                 #gpio-cells = <2>;
 458                                 interrupt-controller;
 459                                 #interrupt-cells = <2>;
 460                         };
 461
 462                         gpio6: gpio@53fe0000 {
 463                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 464                                 reg = <0x53fe0000 0x4000>;
 465                                 interrupts = <105 106>;
 466                                 gpio-controller;
 467                                 #gpio-cells = <2>;
 468                                 interrupt-controller;
 469                                 #interrupt-cells = <2>;
 470                         };
 471
 472                         gpio7: gpio@53fe4000 {
 473                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 474                                 reg = <0x53fe4000 0x4000>;
 475                                 interrupts = <107 108>;
 476                                 gpio-controller;
 477                                 #gpio-cells = <2>;
 478                                 interrupt-controller;
 479                                 #interrupt-cells = <2>;
 480                         };
 481
 482                         i2c3: i2c@53fec000 {
 483                                 #address-cells = <1>;
 484                                 #size-cells = <0>;
 485                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 486                                 reg = <0x53fec000 0x4000>;
 487                                 interrupts = <64>;
 488                                 status = "disabled";
 489                         };
 490
 491                         uart4: serial@53ff0000 {
 492                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 493                                 reg = <0x53ff0000 0x4000>;
 494                                 interrupts = <13>;
 495                                 status = "disabled";
 496                         };
 497                 };
 498
 499                 aips@60000000 { /* AIPS2 */
 500                         compatible = "fsl,aips-bus", "simple-bus";
 501                         #address-cells = <1>;
 502                         #size-cells = <1>;
 503                         reg = <0x60000000 0x10000000>;
 504                         ranges;
 505
 506                         uart5: serial@63f90000 {
 507                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 508                                 reg = <0x63f90000 0x4000>;
 509                                 interrupts = <86>;
 510                                 status = "disabled";
 511                         };
 512
 513                         ecspi2: ecspi@63fac000 {
 514                                 #address-cells = <1>;
 515                                 #size-cells = <0>;
 516                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 517                                 reg = <0x63fac000 0x4000>;
 518                                 interrupts = <37>;
 519                                 status = "disabled";
 520                         };
 521
 522                         sdma: sdma@63fb0000 {
 523                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 524                                 reg = <0x63fb0000 0x4000>;
 525                                 interrupts = <6>;
 526                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 527                         };
 528
 529                         cspi: cspi@63fc0000 {
 530                                 #address-cells = <1>;
 531                                 #size-cells = <0>;
 532                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 533                                 reg = <0x63fc0000 0x4000>;
 534                                 interrupts = <38>;
 535                                 status = "disabled";
 536                         };
 537
 538                         i2c2: i2c@63fc4000 {
 539                                 #address-cells = <1>;
 540                                 #size-cells = <0>;
 541                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 542                                 reg = <0x63fc4000 0x4000>;
 543                                 interrupts = <63>;
 544                                 status = "disabled";
 545                         };
 546
 547                         i2c1: i2c@63fc8000 {
 548                                 #address-cells = <1>;
 549                                 #size-cells = <0>;
 550                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 551                                 reg = <0x63fc8000 0x4000>;
 552                                 interrupts = <62>;
 553                                 status = "disabled";
 554                         };
 555
 556                         ssi1: ssi@63fcc000 {
 557                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 558                                 reg = <0x63fcc000 0x4000>;
 559                                 interrupts = <29>;
 560                                 fsl,fifo-depth = <15>;
 561                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 562                                 status = "disabled";
 563                         };
 564
 565                         audmux: audmux@63fd0000 {
 566                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 567                                 reg = <0x63fd0000 0x4000>;
 568                                 status = "disabled";
 569                         };
 570
 571                         nfc: nand@63fdb000 {
 572                                 compatible = "fsl,imx53-nand";
 573                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 574                                 interrupts = <8>;
 575                                 status = "disabled";
 576                         };
 577
 578                         ssi3: ssi@63fe8000 {
 579                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 580                                 reg = <0x63fe8000 0x4000>;
 581                                 interrupts = <96>;
 582                                 fsl,fifo-depth = <15>;
 583                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 584                                 status = "disabled";
 585                         };
 586
 587                         fec: ethernet@63fec000 {
 588                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 589                                 reg = <0x63fec000 0x4000>;
 590                                 interrupts = <87>;
 591                                 status = "disabled";
 592                         };
 593                 };
 594         };
 595 };