arch/arm/mach-spear3xx/spear320.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear320.c
   3  *
   4  * SPEAr320 machine source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/ptrace.h>
  15 #include <asm/irq.h>
  16 #include <plat/shirq.h>
  17 #include <mach/generic.h>
  18 #include <mach/hardware.h>
  19 #include <mach/spear.h>
  20
  21 /* pad multiplexing support */
  22 /* muxing registers */
  23 #define PAD_MUX_CONFIG_REG      0x0C
  24 #define MODE_CONFIG_REG         0x10
  25
  26 /* modes */
  27 #define AUTO_NET_SMII_MODE      (1 << 0)
  28 #define AUTO_NET_MII_MODE       (1 << 1)
  29 #define AUTO_EXP_MODE           (1 << 2)
  30 #define SMALL_PRINTERS_MODE     (1 << 3)
  31 #define ALL_MODES               0xF
  32
  33 struct pmx_mode spear320_auto_net_smii_mode = {
  34         .id = AUTO_NET_SMII_MODE,
  35         .name = "Automation Networking SMII Mode",
  36         .mask = 0x00,
  37 };
  38
  39 struct pmx_mode spear320_auto_net_mii_mode = {
  40         .id = AUTO_NET_MII_MODE,
  41         .name = "Automation Networking MII Mode",
  42         .mask = 0x01,
  43 };
  44
  45 struct pmx_mode spear320_auto_exp_mode = {
  46         .id = AUTO_EXP_MODE,
  47         .name = "Automation Expanded Mode",
  48         .mask = 0x02,
  49 };
  50
  51 struct pmx_mode spear320_small_printers_mode = {
  52         .id = SMALL_PRINTERS_MODE,
  53         .name = "Small Printers Mode",
  54         .mask = 0x03,
  55 };
  56
  57 /* devices */
  58 static struct pmx_dev_mode pmx_clcd_modes[] = {
  59         {
  60                 .ids = AUTO_NET_SMII_MODE,
  61                 .mask = 0x0,
  62         },
  63 };
  64
  65 struct pmx_dev spear320_pmx_clcd = {
  66         .name = "clcd",
  67         .modes = pmx_clcd_modes,
  68         .mode_count = ARRAY_SIZE(pmx_clcd_modes),
  69         .enb_on_reset = 1,
  70 };
  71
  72 static struct pmx_dev_mode pmx_emi_modes[] = {
  73         {
  74                 .ids = AUTO_EXP_MODE,
  75                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
  76         },
  77 };
  78
  79 struct pmx_dev spear320_pmx_emi = {
  80         .name = "emi",
  81         .modes = pmx_emi_modes,
  82         .mode_count = ARRAY_SIZE(pmx_emi_modes),
  83         .enb_on_reset = 1,
  84 };
  85
  86 static struct pmx_dev_mode pmx_fsmc_modes[] = {
  87         {
  88                 .ids = ALL_MODES,
  89                 .mask = 0x0,
  90         },
  91 };
  92
  93 struct pmx_dev spear320_pmx_fsmc = {
  94         .name = "fsmc",
  95         .modes = pmx_fsmc_modes,
  96         .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
  97         .enb_on_reset = 1,
  98 };
  99
 100 static struct pmx_dev_mode pmx_spp_modes[] = {
 101         {
 102                 .ids = SMALL_PRINTERS_MODE,
 103                 .mask = 0x0,
 104         },
 105 };
 106
 107 struct pmx_dev spear320_pmx_spp = {
 108         .name = "spp",
 109         .modes = pmx_spp_modes,
 110         .mode_count = ARRAY_SIZE(pmx_spp_modes),
 111         .enb_on_reset = 1,
 112 };
 113
 114 static struct pmx_dev_mode pmx_sdhci_modes[] = {
 115         {
 116                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
 117                         SMALL_PRINTERS_MODE,
 118                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
 119         },
 120 };
 121
 122 struct pmx_dev spear320_pmx_sdhci = {
 123         .name = "sdhci",
 124         .modes = pmx_sdhci_modes,
 125         .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
 126         .enb_on_reset = 1,
 127 };
 128
 129 static struct pmx_dev_mode pmx_i2s_modes[] = {
 130         {
 131                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 132                 .mask = PMX_UART0_MODEM_MASK,
 133         },
 134 };
 135
 136 struct pmx_dev spear320_pmx_i2s = {
 137         .name = "i2s",
 138         .modes = pmx_i2s_modes,
 139         .mode_count = ARRAY_SIZE(pmx_i2s_modes),
 140         .enb_on_reset = 1,
 141 };
 142
 143 static struct pmx_dev_mode pmx_uart1_modes[] = {
 144         {
 145                 .ids = ALL_MODES,
 146                 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
 147         },
 148 };
 149
 150 struct pmx_dev spear320_pmx_uart1 = {
 151         .name = "uart1",
 152         .modes = pmx_uart1_modes,
 153         .mode_count = ARRAY_SIZE(pmx_uart1_modes),
 154         .enb_on_reset = 1,
 155 };
 156
 157 static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
 158         {
 159                 .ids = AUTO_EXP_MODE,
 160                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
 161                         PMX_SSP_CS_MASK,
 162         }, {
 163                 .ids = SMALL_PRINTERS_MODE,
 164                 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
 165                         PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
 166         },
 167 };
 168
 169 struct pmx_dev spear320_pmx_uart1_modem = {
 170         .name = "uart1_modem",
 171         .modes = pmx_uart1_modem_modes,
 172         .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
 173         .enb_on_reset = 1,
 174 };
 175
 176 static struct pmx_dev_mode pmx_uart2_modes[] = {
 177         {
 178                 .ids = ALL_MODES,
 179                 .mask = PMX_FIRDA_MASK,
 180         },
 181 };
 182
 183 struct pmx_dev spear320_pmx_uart2 = {
 184         .name = "uart2",
 185         .modes = pmx_uart2_modes,
 186         .mode_count = ARRAY_SIZE(pmx_uart2_modes),
 187         .enb_on_reset = 1,
 188 };
 189
 190 static struct pmx_dev_mode pmx_touchscreen_modes[] = {
 191         {
 192                 .ids = AUTO_NET_SMII_MODE,
 193                 .mask = PMX_SSP_CS_MASK,
 194         },
 195 };
 196
 197 struct pmx_dev spear320_pmx_touchscreen = {
 198         .name = "touchscreen",
 199         .modes = pmx_touchscreen_modes,
 200         .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
 201         .enb_on_reset = 1,
 202 };
 203
 204 static struct pmx_dev_mode pmx_can_modes[] = {
 205         {
 206                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
 207                 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
 208                         PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
 209         },
 210 };
 211
 212 struct pmx_dev spear320_pmx_can = {
 213         .name = "can",
 214         .modes = pmx_can_modes,
 215         .mode_count = ARRAY_SIZE(pmx_can_modes),
 216         .enb_on_reset = 1,
 217 };
 218
 219 static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
 220         {
 221                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 222                 .mask = PMX_SSP_CS_MASK,
 223         },
 224 };
 225
 226 struct pmx_dev spear320_pmx_sdhci_led = {
 227         .name = "sdhci_led",
 228         .modes = pmx_sdhci_led_modes,
 229         .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
 230         .enb_on_reset = 1,
 231 };
 232
 233 static struct pmx_dev_mode pmx_pwm0_modes[] = {
 234         {
 235                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 236                 .mask = PMX_UART0_MODEM_MASK,
 237         }, {
 238                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 239                 .mask = PMX_MII_MASK,
 240         },
 241 };
 242
 243 struct pmx_dev spear320_pmx_pwm0 = {
 244         .name = "pwm0",
 245         .modes = pmx_pwm0_modes,
 246         .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
 247         .enb_on_reset = 1,
 248 };
 249
 250 static struct pmx_dev_mode pmx_pwm1_modes[] = {
 251         {
 252                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 253                 .mask = PMX_UART0_MODEM_MASK,
 254         }, {
 255                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 256                 .mask = PMX_MII_MASK,
 257         },
 258 };
 259
 260 struct pmx_dev spear320_pmx_pwm1 = {
 261         .name = "pwm1",
 262         .modes = pmx_pwm1_modes,
 263         .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
 264         .enb_on_reset = 1,
 265 };
 266
 267 static struct pmx_dev_mode pmx_pwm2_modes[] = {
 268         {
 269                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 270                 .mask = PMX_SSP_CS_MASK,
 271         }, {
 272                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 273                 .mask = PMX_MII_MASK,
 274         },
 275 };
 276
 277 struct pmx_dev spear320_pmx_pwm2 = {
 278         .name = "pwm2",
 279         .modes = pmx_pwm2_modes,
 280         .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
 281         .enb_on_reset = 1,
 282 };
 283
 284 static struct pmx_dev_mode pmx_pwm3_modes[] = {
 285         {
 286                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 287                 .mask = PMX_MII_MASK,
 288         },
 289 };
 290
 291 struct pmx_dev spear320_pmx_pwm3 = {
 292         .name = "pwm3",
 293         .modes = pmx_pwm3_modes,
 294         .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
 295         .enb_on_reset = 1,
 296 };
 297
 298 static struct pmx_dev_mode pmx_ssp1_modes[] = {
 299         {
 300                 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 301                 .mask = PMX_MII_MASK,
 302         },
 303 };
 304
 305 struct pmx_dev spear320_pmx_ssp1 = {
 306         .name = "ssp1",
 307         .modes = pmx_ssp1_modes,
 308         .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
 309         .enb_on_reset = 1,
 310 };
 311
 312 static struct pmx_dev_mode pmx_ssp2_modes[] = {
 313         {
 314                 .ids = AUTO_NET_SMII_MODE,
 315                 .mask = PMX_MII_MASK,
 316         },
 317 };
 318
 319 struct pmx_dev spear320_pmx_ssp2 = {
 320         .name = "ssp2",
 321         .modes = pmx_ssp2_modes,
 322         .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
 323         .enb_on_reset = 1,
 324 };
 325
 326 static struct pmx_dev_mode pmx_mii1_modes[] = {
 327         {
 328                 .ids = AUTO_NET_MII_MODE,
 329                 .mask = 0x0,
 330         },
 331 };
 332
 333 struct pmx_dev spear320_pmx_mii1 = {
 334         .name = "mii1",
 335         .modes = pmx_mii1_modes,
 336         .mode_count = ARRAY_SIZE(pmx_mii1_modes),
 337         .enb_on_reset = 1,
 338 };
 339
 340 static struct pmx_dev_mode pmx_smii0_modes[] = {
 341         {
 342                 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 343                 .mask = PMX_MII_MASK,
 344         },
 345 };
 346
 347 struct pmx_dev spear320_pmx_smii0 = {
 348         .name = "smii0",
 349         .modes = pmx_smii0_modes,
 350         .mode_count = ARRAY_SIZE(pmx_smii0_modes),
 351         .enb_on_reset = 1,
 352 };
 353
 354 static struct pmx_dev_mode pmx_smii1_modes[] = {
 355         {
 356                 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
 357                 .mask = PMX_MII_MASK,
 358         },
 359 };
 360
 361 struct pmx_dev spear320_pmx_smii1 = {
 362         .name = "smii1",
 363         .modes = pmx_smii1_modes,
 364         .mode_count = ARRAY_SIZE(pmx_smii1_modes),
 365         .enb_on_reset = 1,
 366 };
 367
 368 static struct pmx_dev_mode pmx_i2c1_modes[] = {
 369         {
 370                 .ids = AUTO_EXP_MODE,
 371                 .mask = 0x0,
 372         },
 373 };
 374
 375 struct pmx_dev spear320_pmx_i2c1 = {
 376         .name = "i2c1",
 377         .modes = pmx_i2c1_modes,
 378         .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
 379         .enb_on_reset = 1,
 380 };
 381
 382 /* pmx driver structure */
 383 static struct pmx_driver pmx_driver = {
 384         .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
 385         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 386 };
 387
 388 /* spear3xx shared irq */
 389 static struct shirq_dev_config shirq_ras1_config[] = {
 390         {
 391                 .virq = SPEAR320_VIRQ_EMI,
 392                 .status_mask = SPEAR320_EMI_IRQ_MASK,
 393                 .clear_mask = SPEAR320_EMI_IRQ_MASK,
 394         }, {
 395                 .virq = SPEAR320_VIRQ_CLCD,
 396                 .status_mask = SPEAR320_CLCD_IRQ_MASK,
 397                 .clear_mask = SPEAR320_CLCD_IRQ_MASK,
 398         }, {
 399                 .virq = SPEAR320_VIRQ_SPP,
 400                 .status_mask = SPEAR320_SPP_IRQ_MASK,
 401                 .clear_mask = SPEAR320_SPP_IRQ_MASK,
 402         },
 403 };
 404
 405 static struct spear_shirq shirq_ras1 = {
 406         .irq = SPEAR3XX_IRQ_GEN_RAS_1,
 407         .dev_config = shirq_ras1_config,
 408         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 409         .regs = {
 410                 .enb_reg = -1,
 411                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 412                 .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
 413                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 414                 .reset_to_clear = 1,
 415         },
 416 };
 417
 418 static struct shirq_dev_config shirq_ras3_config[] = {
 419         {
 420                 .virq = SPEAR320_VIRQ_PLGPIO,
 421                 .enb_mask = SPEAR320_GPIO_IRQ_MASK,
 422                 .status_mask = SPEAR320_GPIO_IRQ_MASK,
 423                 .clear_mask = SPEAR320_GPIO_IRQ_MASK,
 424         }, {
 425                 .virq = SPEAR320_VIRQ_I2S_PLAY,
 426                 .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 427                 .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 428                 .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 429         }, {
 430                 .virq = SPEAR320_VIRQ_I2S_REC,
 431                 .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
 432                 .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
 433                 .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
 434         },
 435 };
 436
 437 static struct spear_shirq shirq_ras3 = {
 438         .irq = SPEAR3XX_IRQ_GEN_RAS_3,
 439         .dev_config = shirq_ras3_config,
 440         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 441         .regs = {
 442                 .enb_reg = SPEAR320_INT_ENB_MASK_REG,
 443                 .reset_to_enb = 1,
 444                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 445                 .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
 446                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 447                 .reset_to_clear = 1,
 448         },
 449 };
 450
 451 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 452         {
 453                 .virq = SPEAR320_VIRQ_CANU,
 454                 .status_mask = SPEAR320_CAN_U_IRQ_MASK,
 455                 .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
 456         }, {
 457                 .virq = SPEAR320_VIRQ_CANL,
 458                 .status_mask = SPEAR320_CAN_L_IRQ_MASK,
 459                 .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
 460         }, {
 461                 .virq = SPEAR320_VIRQ_UART1,
 462                 .status_mask = SPEAR320_UART1_IRQ_MASK,
 463                 .clear_mask = SPEAR320_UART1_IRQ_MASK,
 464         }, {
 465                 .virq = SPEAR320_VIRQ_UART2,
 466                 .status_mask = SPEAR320_UART2_IRQ_MASK,
 467                 .clear_mask = SPEAR320_UART2_IRQ_MASK,
 468         }, {
 469                 .virq = SPEAR320_VIRQ_SSP1,
 470                 .status_mask = SPEAR320_SSP1_IRQ_MASK,
 471                 .clear_mask = SPEAR320_SSP1_IRQ_MASK,
 472         }, {
 473                 .virq = SPEAR320_VIRQ_SSP2,
 474                 .status_mask = SPEAR320_SSP2_IRQ_MASK,
 475                 .clear_mask = SPEAR320_SSP2_IRQ_MASK,
 476         }, {
 477                 .virq = SPEAR320_VIRQ_SMII0,
 478                 .status_mask = SPEAR320_SMII0_IRQ_MASK,
 479                 .clear_mask = SPEAR320_SMII0_IRQ_MASK,
 480         }, {
 481                 .virq = SPEAR320_VIRQ_MII1_SMII1,
 482                 .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 483                 .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 484         }, {
 485                 .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
 486                 .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 487                 .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 488         }, {
 489                 .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
 490                 .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 491                 .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 492         }, {
 493                 .virq = SPEAR320_VIRQ_I2C1,
 494                 .status_mask = SPEAR320_I2C1_IRQ_MASK,
 495                 .clear_mask = SPEAR320_I2C1_IRQ_MASK,
 496         },
 497 };
 498
 499 static struct spear_shirq shirq_intrcomm_ras = {
 500         .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 501         .dev_config = shirq_intrcomm_ras_config,
 502         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 503         .regs = {
 504                 .enb_reg = -1,
 505                 .status_reg = SPEAR320_INT_STS_MASK_REG,
 506                 .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
 507                 .clear_reg = SPEAR320_INT_CLR_MASK_REG,
 508                 .reset_to_clear = 1,
 509         },
 510 };
 511
 512 /* Add spear320 specific devices here */
 513
 514 /* spear320 routines */
 515 void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
 516                 u8 pmx_dev_count)
 517 {
 518         void __iomem *base;
 519         int ret = 0;
 520
 521         /* call spear3xx family common init function */
 522         spear3xx_init();
 523
 524         /* shared irq registration */
 525         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
 526         if (base) {
 527                 /* shirq 1 */
 528                 shirq_ras1.regs.base = base;
 529                 ret = spear_shirq_register(&shirq_ras1);
 530                 if (ret)
 531                         printk(KERN_ERR "Error registering Shared IRQ 1\n");
 532
 533                 /* shirq 3 */
 534                 shirq_ras3.regs.base = base;
 535                 ret = spear_shirq_register(&shirq_ras3);
 536                 if (ret)
 537                         printk(KERN_ERR "Error registering Shared IRQ 3\n");
 538
 539                 /* shirq 4 */
 540                 shirq_intrcomm_ras.regs.base = base;
 541                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 542                 if (ret)
 543                         printk(KERN_ERR "Error registering Shared IRQ 4\n");
 544         }
 545
 546         /* pmx initialization */
 547         pmx_driver.base = base;
 548         pmx_driver.mode = pmx_mode;
 549         pmx_driver.devs = pmx_devs;
 550         pmx_driver.devs_count = pmx_dev_count;
 551
 552         ret = pmx_register(&pmx_driver);
 553         if (ret)
 554                 printk(KERN_ERR "padmux: registration failed. err no: %d\n",
 555                                 ret);
 556 }