1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
7 cache-controller@50043000 {
8 compatible = "arm,pl310-cache";
9 reg = <0x50043000 0x1000>;
10 arm,data-latency = <5 5 2>;
11 arm,tag-latency = <4 4 2>;
16 intc: interrupt-controller {
17 compatible = "arm,cortex-a9-gic";
18 reg = <0x50041000 0x1000
21 #interrupt-cells = <3>;
25 compatible = "nvidia,tegra20-apbdma";
26 reg = <0x6000a000 0x1200>;
27 interrupts = <0 104 0x04
46 compatible = "nvidia,tegra20-ahb";
47 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
51 compatible = "nvidia,tegra20-gpio";
52 reg = <0x6000d000 0x1000>;
53 interrupts = <0 32 0x04
62 #interrupt-cells = <2>;
67 compatible = "nvidia,tegra20-pinmux";
68 reg = <0x70000014 0x10 /* Tri-state registers */
69 0x70000080 0x20 /* Mux registers */
70 0x700000a0 0x14 /* Pull-up/down registers */
71 0x70000868 0xa8>; /* Pad control registers */
75 compatible = "nvidia,tegra20-das";
76 reg = <0x70000c00 0x80>;
79 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>;
82 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = <&apbdma 2>;
87 tegra_i2s2: i2s@70002a00 {
88 compatible = "nvidia,tegra20-i2s";
89 reg = <0x70002a00 0x200>;
90 interrupts = <0 3 0x04>;
91 nvidia,dma-request-selector = <&apbdma 1>;
96 compatible = "nvidia,tegra20-uart";
97 reg = <0x70006000 0x40>;
99 interrupts = <0 36 0x04>;
104 compatible = "nvidia,tegra20-uart";
105 reg = <0x70006040 0x40>;
107 interrupts = <0 37 0x04>;
112 compatible = "nvidia,tegra20-uart";
113 reg = <0x70006200 0x100>;
115 interrupts = <0 46 0x04>;
120 compatible = "nvidia,tegra20-uart";
121 reg = <0x70006300 0x100>;
123 interrupts = <0 90 0x04>;
128 compatible = "nvidia,tegra20-uart";
129 reg = <0x70006400 0x100>;
131 interrupts = <0 91 0x04>;
136 compatible = "nvidia,tegra20-pwm";
137 reg = <0x7000a000 0x100>;
142 compatible = "nvidia,tegra20-i2c";
143 reg = <0x7000c000 0x100>;
144 interrupts = <0 38 0x04>;
145 #address-cells = <1>;
151 compatible = "nvidia,tegra20-i2c";
152 reg = <0x7000c400 0x100>;
153 interrupts = <0 84 0x04>;
154 #address-cells = <1>;
160 compatible = "nvidia,tegra20-i2c";
161 reg = <0x7000c500 0x100>;
162 interrupts = <0 92 0x04>;
163 #address-cells = <1>;
169 compatible = "nvidia,tegra20-i2c-dvc";
170 reg = <0x7000d000 0x200>;
171 interrupts = <0 53 0x04>;
172 #address-cells = <1>;
178 compatible = "nvidia,tegra20-pmc";
179 reg = <0x7000e400 0x400>;
182 memory-controller@7000f000 {
183 compatible = "nvidia,tegra20-mc";
184 reg = <0x7000f000 0x024
186 interrupts = <0 77 0x04>;
190 compatible = "nvidia,tegra20-gart";
191 reg = <0x7000f024 0x00000018 /* controller registers */
192 0x58000000 0x02000000>; /* GART aperture */
195 memory-controller@7000f400 {
196 compatible = "nvidia,tegra20-emc";
197 reg = <0x7000f400 0x200>;
198 #address-cells = <1>;
203 compatible = "nvidia,tegra20-ehci", "usb-ehci";
204 reg = <0xc5000000 0x4000>;
205 interrupts = <0 20 0x04>;
207 nvidia,has-legacy-mode;
212 compatible = "nvidia,tegra20-ehci", "usb-ehci";
213 reg = <0xc5004000 0x4000>;
214 interrupts = <0 21 0x04>;
220 compatible = "nvidia,tegra20-ehci", "usb-ehci";
221 reg = <0xc5008000 0x4000>;
222 interrupts = <0 97 0x04>;
228 compatible = "nvidia,tegra20-sdhci";
229 reg = <0xc8000000 0x200>;
230 interrupts = <0 14 0x04>;
235 compatible = "nvidia,tegra20-sdhci";
236 reg = <0xc8000200 0x200>;
237 interrupts = <0 15 0x04>;
242 compatible = "nvidia,tegra20-sdhci";
243 reg = <0xc8000400 0x200>;
244 interrupts = <0 19 0x04>;
249 compatible = "nvidia,tegra20-sdhci";
250 reg = <0xc8000600 0x200>;
251 interrupts = <0 31 0x04>;
256 compatible = "arm,cortex-a9-pmu";
257 interrupts = <0 56 0x04