drivers/staging/comedi/drivers/ni_labpc.c

   1 /*
   2     comedi/drivers/ni_labpc.c
   3     Driver for National Instruments Lab-PC series boards and compatibles
   4     Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 ************************************************************************
  21 */
  22 /*
  23 Driver: ni_labpc
  24 Description: National Instruments Lab-PC (& compatibles)
  25 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  26 Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
  27   Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
  28 Status: works
  29
  30 Tested with lab-pc-1200.  For the older Lab-PC+, not all input ranges
  31 and analog references will work, the available ranges/arefs will
  32 depend on how you have configured the jumpers on your board
  33 (see your owner's manual).
  34
  35 Kernel-level ISA plug-and-play support for the lab-pc-1200
  36 boards has not
  37 yet been added to the driver, mainly due to the fact that
  38 I don't know the device id numbers.  If you have one
  39 of these boards,
  40 please file a bug report at http://comedi.org/
  41 so I can get the necessary information from you.
  42
  43 The 1200 series boards have onboard calibration dacs for correcting
  44 analog input/output offsets and gains.  The proper settings for these
  45 caldacs are stored on the board's eeprom.  To read the caldac values
  46 from the eeprom and store them into a file that can be then be used by
  47 comedilib, use the comedi_calibrate program.
  48
  49 Configuration options - ISA boards:
  50   [0] - I/O port base address
  51   [1] - IRQ (optional, required for timed or externally triggered conversions)
  52   [2] - DMA channel (optional)
  53
  54 Configuration options - PCI boards:
  55   [0] - bus (optional)
  56   [1] - slot (optional)
  57
  58 The Lab-pc+ has quirky chanlist requirements
  59 when scanning multiple channels.  Multiple channel scan
  60 sequence must start at highest channel, then decrement down to
  61 channel 0.  The rest of the cards can scan down like lab-pc+ or scan
  62 up from channel zero.  Chanlists consisting of all one channel
  63 are also legal, and allow you to pace conversions in bursts.
  64
  65 */
  66
  67 /*
  68
  69 NI manuals:
  70 341309a (labpc-1200 register manual)
  71 340914a (pci-1200)
  72 320502b (lab-pc+)
  73
  74 */
  75
  76 #include <linux/interrupt.h>
  77 #include <linux/slab.h>
  78 #include <linux/io.h>
  79 #include "../comedidev.h"
  80
  81 #include <linux/delay.h>
  82 #include <asm/dma.h>
  83
  84 #include "8253.h"
  85 #include "8255.h"
  86 #include "mite.h"
  87 #include "comedi_fc.h"
  88 #include "ni_labpc.h"
  89
  90 #define DRV_NAME "ni_labpc"
  91
  92 /* size of io region used by board */
  93 #define LABPC_SIZE           32
  94 /* 2 MHz master clock */
  95 #define LABPC_TIMER_BASE            500
  96
  97 /* Registers for the lab-pc+ */
  98
  99 /* write-only registers */
 100 #define COMMAND1_REG    0x0
 101 #define   ADC_GAIN_MASK (0x7 << 4)
 102 #define   ADC_CHAN_BITS(x)      ((x) & 0x7)
 103 /* enables multi channel scans */
 104 #define   ADC_SCAN_EN_BIT       0x80
 105 #define COMMAND2_REG    0x1
 106 /* enable pretriggering (used in conjunction with SWTRIG) */
 107 #define   PRETRIG_BIT   0x1
 108 /* enable paced conversions on external trigger */
 109 #define   HWTRIG_BIT    0x2
 110 /* enable paced conversions */
 111 #define   SWTRIG_BIT    0x4
 112 /* use two cascaded counters for pacing */
 113 #define   CASCADE_BIT   0x8
 114 #define   DAC_PACED_BIT(channel)        (0x40 << ((channel) & 0x1))
 115 #define COMMAND3_REG    0x2
 116 /* enable dma transfers */
 117 #define   DMA_EN_BIT    0x1
 118 /* enable interrupts for 8255 */
 119 #define   DIO_INTR_EN_BIT       0x2
 120 /* enable dma terminal count interrupt */
 121 #define   DMATC_INTR_EN_BIT     0x4
 122 /* enable timer interrupt */
 123 #define   TIMER_INTR_EN_BIT     0x8
 124 /* enable error interrupt */
 125 #define   ERR_INTR_EN_BIT       0x10
 126 /* enable fifo not empty interrupt */
 127 #define   ADC_FNE_INTR_EN_BIT   0x20
 128 #define ADC_CONVERT_REG 0x3
 129 #define DAC_LSB_REG(channel)    (0x4 + 2 * ((channel) & 0x1))
 130 #define DAC_MSB_REG(channel)    (0x5 + 2 * ((channel) & 0x1))
 131 #define ADC_CLEAR_REG   0x8
 132 #define DMATC_CLEAR_REG 0xa
 133 #define TIMER_CLEAR_REG 0xc
 134 /* 1200 boards only */
 135 #define COMMAND6_REG    0xe
 136 /* select ground or common-mode reference */
 137 #define   ADC_COMMON_BIT        0x1
 138 /*  adc unipolar */
 139 #define   ADC_UNIP_BIT  0x2
 140 /*  dac unipolar */
 141 #define   DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
 142 /* enable fifo half full interrupt */
 143 #define   ADC_FHF_INTR_EN_BIT   0x20
 144 /* enable interrupt on end of hardware count */
 145 #define   A1_INTR_EN_BIT        0x40
 146 /* scan up from channel zero instead of down to zero */
 147 #define   ADC_SCAN_UP_BIT 0x80
 148 #define COMMAND4_REG    0xf
 149 /* enables 'interval' scanning */
 150 #define   INTERVAL_SCAN_EN_BIT  0x1
 151 /* enables external signal on counter b1 output to trigger scan */
 152 #define   EXT_SCAN_EN_BIT       0x2
 153 /* chooses direction (output or input) for EXTCONV* line */
 154 #define   EXT_CONVERT_OUT_BIT   0x4
 155 /* chooses differential inputs for adc (in conjunction with board jumper) */
 156 #define   ADC_DIFF_BIT  0x8
 157 #define   EXT_CONVERT_DISABLE_BIT       0x10
 158 /* 1200 boards only, calibration stuff */
 159 #define COMMAND5_REG    0x1c
 160 /* enable eeprom for write */
 161 #define   EEPROM_WRITE_UNPROTECT_BIT    0x4
 162 /* enable dithering */
 163 #define   DITHER_EN_BIT 0x8
 164 /* load calibration dac */
 165 #define   CALDAC_LOAD_BIT       0x10
 166 /* serial clock - rising edge writes, falling edge reads */
 167 #define   SCLOCK_BIT    0x20
 168 /* serial data bit for writing to eeprom or calibration dacs */
 169 #define   SDATA_BIT     0x40
 170 /* enable eeprom for read/write */
 171 #define   EEPROM_EN_BIT 0x80
 172 #define INTERVAL_COUNT_REG      0x1e
 173 #define INTERVAL_LOAD_REG       0x1f
 174 #define   INTERVAL_LOAD_BITS    0x1
 175
 176 /* read-only registers */
 177 #define STATUS1_REG     0x0
 178 /* data is available in fifo */
 179 #define   DATA_AVAIL_BIT        0x1
 180 /* overrun has occurred */
 181 #define   OVERRUN_BIT   0x2
 182 /* fifo overflow */
 183 #define   OVERFLOW_BIT  0x4
 184 /* timer interrupt has occurred */
 185 #define   TIMER_BIT     0x8
 186 /* dma terminal count has occurred */
 187 #define   DMATC_BIT     0x10
 188 /* external trigger has occurred */
 189 #define   EXT_TRIG_BIT  0x40
 190 /* 1200 boards only */
 191 #define STATUS2_REG     0x1d
 192 /* programmable eeprom serial output */
 193 #define   EEPROM_OUT_BIT        0x1
 194 /* counter A1 terminal count */
 195 #define   A1_TC_BIT     0x2
 196 /* fifo not half full */
 197 #define   FNHF_BIT      0x4
 198 #define ADC_FIFO_REG    0xa
 199
 200 #define DIO_BASE_REG    0x10
 201 #define COUNTER_A_BASE_REG      0x14
 202 #define COUNTER_A_CONTROL_REG   (COUNTER_A_BASE_REG + 0x3)
 203 /* check modes put conversion pacer output in harmless state (a0 mode 2) */
 204 #define   INIT_A0_BITS  0x14
 205 /* put hardware conversion counter output in harmless state (a1 mode 0) */
 206 #define   INIT_A1_BITS  0x70
 207 #define COUNTER_B_BASE_REG      0x18
 208
 209 enum scan_mode {
 210         MODE_SINGLE_CHAN,
 211         MODE_SINGLE_CHAN_INTERVAL,
 212         MODE_MULT_CHAN_UP,
 213         MODE_MULT_CHAN_DOWN,
 214 };
 215
 216 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
 217 static irqreturn_t labpc_interrupt(int irq, void *d);
 218 static int labpc_drain_fifo(struct comedi_device *dev);
 219 #ifdef CONFIG_ISA_DMA_API
 220 static void labpc_drain_dma(struct comedi_device *dev);
 221 static void handle_isa_dma(struct comedi_device *dev);
 222 #endif
 223 static void labpc_drain_dregs(struct comedi_device *dev);
 224 static int labpc_ai_cmdtest(struct comedi_device *dev,
 225                             struct comedi_subdevice *s, struct comedi_cmd *cmd);
 226 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
 227 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 228                           struct comedi_insn *insn, unsigned int *data);
 229 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
 230                           struct comedi_insn *insn, unsigned int *data);
 231 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 232                           struct comedi_insn *insn, unsigned int *data);
 233 static int labpc_calib_read_insn(struct comedi_device *dev,
 234                                  struct comedi_subdevice *s,
 235                                  struct comedi_insn *insn, unsigned int *data);
 236 static int labpc_calib_write_insn(struct comedi_device *dev,
 237                                   struct comedi_subdevice *s,
 238                                   struct comedi_insn *insn, unsigned int *data);
 239 static int labpc_eeprom_read_insn(struct comedi_device *dev,
 240                                   struct comedi_subdevice *s,
 241                                   struct comedi_insn *insn, unsigned int *data);
 242 static int labpc_eeprom_write_insn(struct comedi_device *dev,
 243                                    struct comedi_subdevice *s,
 244                                    struct comedi_insn *insn,
 245                                    unsigned int *data);
 246 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
 247                              enum scan_mode scan_mode);
 248 #ifdef CONFIG_ISA_DMA_API
 249 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd);
 250 #endif
 251 static int labpc_dio_mem_callback(int dir, int port, int data,
 252                                   unsigned long arg);
 253 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
 254                              unsigned int num_bits);
 255 static unsigned int labpc_serial_in(struct comedi_device *dev);
 256 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
 257                                       unsigned int address);
 258 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
 259 static int labpc_eeprom_write(struct comedi_device *dev,
 260                                        unsigned int address,
 261                                        unsigned int value);
 262 static void write_caldac(struct comedi_device *dev, unsigned int channel,
 263                          unsigned int value);
 264
 265 /* analog input ranges */
 266 #define NUM_LABPC_PLUS_AI_RANGES 16
 267 /* indicates unipolar ranges */
 268 static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
 269         0,
 270         0,
 271         0,
 272         0,
 273         0,
 274         0,
 275         0,
 276         0,
 277         1,
 278         1,
 279         1,
 280         1,
 281         1,
 282         1,
 283         1,
 284         1,
 285 };
 286
 287 /* map range index to gain bits */
 288 static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
 289         0x00,
 290         0x10,
 291         0x20,
 292         0x30,
 293         0x40,
 294         0x50,
 295         0x60,
 296         0x70,
 297         0x00,
 298         0x10,
 299         0x20,
 300         0x30,
 301         0x40,
 302         0x50,
 303         0x60,
 304         0x70,
 305 };
 306
 307 static const struct comedi_lrange range_labpc_plus_ai = {
 308         NUM_LABPC_PLUS_AI_RANGES,
 309         {
 310          BIP_RANGE(5),
 311          BIP_RANGE(4),
 312          BIP_RANGE(2.5),
 313          BIP_RANGE(1),
 314          BIP_RANGE(0.5),
 315          BIP_RANGE(0.25),
 316          BIP_RANGE(0.1),
 317          BIP_RANGE(0.05),
 318          UNI_RANGE(10),
 319          UNI_RANGE(8),
 320          UNI_RANGE(5),
 321          UNI_RANGE(2),
 322          UNI_RANGE(1),
 323          UNI_RANGE(0.5),
 324          UNI_RANGE(0.2),
 325          UNI_RANGE(0.1),
 326          }
 327 };
 328
 329 #define NUM_LABPC_1200_AI_RANGES 14
 330 /* indicates unipolar ranges */
 331 const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
 332         0,
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         1,
 340         1,
 341         1,
 342         1,
 343         1,
 344         1,
 345         1,
 346 };
 347 EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
 348
 349 /* map range index to gain bits */
 350 const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
 351         0x00,
 352         0x20,
 353         0x30,
 354         0x40,
 355         0x50,
 356         0x60,
 357         0x70,
 358         0x00,
 359         0x20,
 360         0x30,
 361         0x40,
 362         0x50,
 363         0x60,
 364         0x70,
 365 };
 366 EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
 367
 368 const struct comedi_lrange range_labpc_1200_ai = {
 369         NUM_LABPC_1200_AI_RANGES,
 370         {
 371          BIP_RANGE(5),
 372          BIP_RANGE(2.5),
 373          BIP_RANGE(1),
 374          BIP_RANGE(0.5),
 375          BIP_RANGE(0.25),
 376          BIP_RANGE(0.1),
 377          BIP_RANGE(0.05),
 378          UNI_RANGE(10),
 379          UNI_RANGE(5),
 380          UNI_RANGE(2),
 381          UNI_RANGE(1),
 382          UNI_RANGE(0.5),
 383          UNI_RANGE(0.2),
 384          UNI_RANGE(0.1),
 385          }
 386 };
 387 EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
 388
 389 /* analog output ranges */
 390 #define AO_RANGE_IS_UNIPOLAR 0x1
 391 static const struct comedi_lrange range_labpc_ao = {
 392         2,
 393         {
 394          BIP_RANGE(5),
 395          UNI_RANGE(10),
 396          }
 397 };
 398
 399 /* functions that do inb/outb and readb/writeb so we can use
 400  * function pointers to decide which to use */
 401 static inline unsigned int labpc_inb(unsigned long address)
 402 {
 403         return inb(address);
 404 }
 405
 406 static inline void labpc_outb(unsigned int byte, unsigned long address)
 407 {
 408         outb(byte, address);
 409 }
 410
 411 static inline unsigned int labpc_readb(unsigned long address)
 412 {
 413         return readb((void __iomem *)address);
 414 }
 415
 416 static inline void labpc_writeb(unsigned int byte, unsigned long address)
 417 {
 418         writeb(byte, (void __iomem *)address);
 419 }
 420
 421 static const struct labpc_board_struct labpc_boards[] = {
 422         {
 423          .name = "lab-pc-1200",
 424          .ai_speed = 10000,
 425          .bustype = isa_bustype,
 426          .register_layout = labpc_1200_layout,
 427          .has_ao = 1,
 428          .ai_range_table = &range_labpc_1200_ai,
 429          .ai_range_code = labpc_1200_ai_gain_bits,
 430          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 431          .ai_scan_up = 1,
 432          .memory_mapped_io = 0,
 433          },
 434         {
 435          .name = "lab-pc-1200ai",
 436          .ai_speed = 10000,
 437          .bustype = isa_bustype,
 438          .register_layout = labpc_1200_layout,
 439          .has_ao = 0,
 440          .ai_range_table = &range_labpc_1200_ai,
 441          .ai_range_code = labpc_1200_ai_gain_bits,
 442          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 443          .ai_scan_up = 1,
 444          .memory_mapped_io = 0,
 445          },
 446         {
 447          .name = "lab-pc+",
 448          .ai_speed = 12000,
 449          .bustype = isa_bustype,
 450          .register_layout = labpc_plus_layout,
 451          .has_ao = 1,
 452          .ai_range_table = &range_labpc_plus_ai,
 453          .ai_range_code = labpc_plus_ai_gain_bits,
 454          .ai_range_is_unipolar = labpc_plus_is_unipolar,
 455          .ai_scan_up = 0,
 456          .memory_mapped_io = 0,
 457          },
 458 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 459         {
 460          .name = "pci-1200",
 461          .device_id = 0x161,
 462          .ai_speed = 10000,
 463          .bustype = pci_bustype,
 464          .register_layout = labpc_1200_layout,
 465          .has_ao = 1,
 466          .ai_range_table = &range_labpc_1200_ai,
 467          .ai_range_code = labpc_1200_ai_gain_bits,
 468          .ai_range_is_unipolar = labpc_1200_is_unipolar,
 469          .ai_scan_up = 1,
 470          .memory_mapped_io = 1,
 471          },
 472 /* dummy entry so pci board works when comedi_config is passed driver name */
 473         {
 474          .name = DRV_NAME,
 475          .bustype = pci_bustype,
 476          },
 477 #endif
 478 };
 479
 480 /*
 481  * Useful for shorthand access to the particular board structure
 482  */
 483 #define thisboard ((struct labpc_board_struct *)dev->board_ptr)
 484
 485 /* size in bytes of dma buffer */
 486 static const int dma_buffer_size = 0xff00;
 487 /* 2 bytes per sample */
 488 static const int sample_size = 2;
 489
 490 #define devpriv ((struct labpc_private *)dev->private)
 491
 492 static inline int labpc_counter_load(struct comedi_device *dev,
 493                                      unsigned long base_address,
 494                                      unsigned int counter_number,
 495                                      unsigned int count, unsigned int mode)
 496 {
 497         if (thisboard->memory_mapped_io)
 498                 return i8254_mm_load((void __iomem *)base_address, 0,
 499                                      counter_number, count, mode);
 500         else
 501                 return i8254_load(base_address, 0, counter_number, count, mode);
 502 }
 503
 504 int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
 505                         unsigned int irq, unsigned int dma_chan)
 506 {
 507         struct comedi_subdevice *s;
 508         int i;
 509         unsigned long isr_flags;
 510 #ifdef CONFIG_ISA_DMA_API
 511         unsigned long dma_flags;
 512 #endif
 513         short lsb, msb;
 514         int ret;
 515
 516         dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name);
 517         if (iobase == 0) {
 518                 dev_err(dev->class_dev, "io base address is zero!\n");
 519                 return -EINVAL;
 520         }
 521         /*  request io regions for isa boards */
 522         if (thisboard->bustype == isa_bustype) {
 523                 /* check if io addresses are available */
 524                 if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) {
 525                         dev_err(dev->class_dev, "I/O port conflict\n");
 526                         return -EIO;
 527                 }
 528         }
 529         dev->iobase = iobase;
 530
 531         if (thisboard->memory_mapped_io) {
 532                 devpriv->read_byte = labpc_readb;
 533                 devpriv->write_byte = labpc_writeb;
 534         } else {
 535                 devpriv->read_byte = labpc_inb;
 536                 devpriv->write_byte = labpc_outb;
 537         }
 538         /* initialize board's command registers */
 539         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
 540         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 541         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 542         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
 543         if (thisboard->register_layout == labpc_1200_layout) {
 544                 devpriv->write_byte(devpriv->command5_bits,
 545                                     dev->iobase + COMMAND5_REG);
 546                 devpriv->write_byte(devpriv->command6_bits,
 547                                     dev->iobase + COMMAND6_REG);
 548         }
 549
 550         /* grab our IRQ */
 551         if (irq) {
 552                 isr_flags = 0;
 553                 if (thisboard->bustype == pci_bustype
 554                     || thisboard->bustype == pcmcia_bustype)
 555                         isr_flags |= IRQF_SHARED;
 556                 if (request_irq(irq, labpc_interrupt, isr_flags,
 557                                 DRV_NAME, dev)) {
 558                         dev_err(dev->class_dev, "unable to allocate irq %u\n",
 559                                 irq);
 560                         return -EINVAL;
 561                 }
 562         }
 563         dev->irq = irq;
 564
 565 #ifdef CONFIG_ISA_DMA_API
 566         /* grab dma channel */
 567         if (dma_chan > 3) {
 568                 dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan);
 569                 return -EINVAL;
 570         } else if (dma_chan) {
 571                 /* allocate dma buffer */
 572                 devpriv->dma_buffer =
 573                     kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
 574                 if (devpriv->dma_buffer == NULL) {
 575                         dev_err(dev->class_dev,
 576                                 "failed to allocate dma buffer\n");
 577                         return -ENOMEM;
 578                 }
 579                 if (request_dma(dma_chan, DRV_NAME)) {
 580                         dev_err(dev->class_dev,
 581                                 "failed to allocate dma channel %u\n",
 582                                 dma_chan);
 583                         return -EINVAL;
 584                 }
 585                 devpriv->dma_chan = dma_chan;
 586                 dma_flags = claim_dma_lock();
 587                 disable_dma(devpriv->dma_chan);
 588                 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
 589                 release_dma_lock(dma_flags);
 590         }
 591 #endif
 592
 593         dev->board_name = thisboard->name;
 594
 595         ret = comedi_alloc_subdevices(dev, 5);
 596         if (ret)
 597                 return ret;
 598
 599         /* analog input subdevice */
 600         s = &dev->subdevices[0];
 601         dev->read_subdev = s;
 602         s->type = COMEDI_SUBD_AI;
 603         s->subdev_flags =
 604             SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
 605         s->n_chan = 8;
 606         s->len_chanlist = 8;
 607         s->maxdata = (1 << 12) - 1;     /* 12 bit resolution */
 608         s->range_table = thisboard->ai_range_table;
 609         s->do_cmd = labpc_ai_cmd;
 610         s->do_cmdtest = labpc_ai_cmdtest;
 611         s->insn_read = labpc_ai_rinsn;
 612         s->cancel = labpc_cancel;
 613
 614         /* analog output */
 615         s = &dev->subdevices[1];
 616         if (thisboard->has_ao) {
 617                 /*
 618                  * Could provide command support, except it only has a
 619                  * one sample hardware buffer for analog output and no
 620                  * underrun flag.
 621                  */
 622                 s->type = COMEDI_SUBD_AO;
 623                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
 624                 s->n_chan = NUM_AO_CHAN;
 625                 s->maxdata = (1 << 12) - 1;     /*  12 bit resolution */
 626                 s->range_table = &range_labpc_ao;
 627                 s->insn_read = labpc_ao_rinsn;
 628                 s->insn_write = labpc_ao_winsn;
 629                 /* initialize analog outputs to a known value */
 630                 for (i = 0; i < s->n_chan; i++) {
 631                         devpriv->ao_value[i] = s->maxdata / 2;
 632                         lsb = devpriv->ao_value[i] & 0xff;
 633                         msb = (devpriv->ao_value[i] >> 8) & 0xff;
 634                         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
 635                         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
 636                 }
 637         } else {
 638                 s->type = COMEDI_SUBD_UNUSED;
 639         }
 640
 641         /* 8255 dio */
 642         s = &dev->subdevices[2];
 643         /*  if board uses io memory we have to give a custom callback
 644          * function to the 8255 driver */
 645         if (thisboard->memory_mapped_io)
 646                 subdev_8255_init(dev, s, labpc_dio_mem_callback,
 647                                  (unsigned long)(dev->iobase + DIO_BASE_REG));
 648         else
 649                 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
 650
 651         /*  calibration subdevices for boards that have one */
 652         s = &dev->subdevices[3];
 653         if (thisboard->register_layout == labpc_1200_layout) {
 654                 s->type = COMEDI_SUBD_CALIB;
 655                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 656                 s->n_chan = 16;
 657                 s->maxdata = 0xff;
 658                 s->insn_read = labpc_calib_read_insn;
 659                 s->insn_write = labpc_calib_write_insn;
 660
 661                 for (i = 0; i < s->n_chan; i++)
 662                         write_caldac(dev, i, s->maxdata / 2);
 663         } else
 664                 s->type = COMEDI_SUBD_UNUSED;
 665
 666         /* EEPROM */
 667         s = &dev->subdevices[4];
 668         if (thisboard->register_layout == labpc_1200_layout) {
 669                 s->type = COMEDI_SUBD_MEMORY;
 670                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
 671                 s->n_chan = EEPROM_SIZE;
 672                 s->maxdata = 0xff;
 673                 s->insn_read = labpc_eeprom_read_insn;
 674                 s->insn_write = labpc_eeprom_write_insn;
 675
 676                 for (i = 0; i < EEPROM_SIZE; i++)
 677                         devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
 678         } else
 679                 s->type = COMEDI_SUBD_UNUSED;
 680
 681         return 0;
 682 }
 683 EXPORT_SYMBOL_GPL(labpc_common_attach);
 684
 685 static const struct labpc_board_struct *
 686 labpc_pci_find_boardinfo(struct pci_dev *pcidev)
 687 {
 688         unsigned int device_id = pcidev->device;
 689         unsigned int n;
 690
 691         for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) {
 692                 const struct labpc_board_struct *board = &labpc_boards[n];
 693                 if (board->bustype == pci_bustype &&
 694                     board->device_id == device_id)
 695                         return board;
 696         }
 697         return NULL;
 698 }
 699
 700 static int __devinit labpc_attach_pci(struct comedi_device *dev,
 701                                       struct pci_dev *pcidev)
 702 {
 703         unsigned long iobase;
 704         unsigned int irq;
 705         int ret;
 706
 707         if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS))
 708                 return -ENODEV;
 709         ret = alloc_private(dev, sizeof(struct labpc_private));
 710         if (ret < 0)
 711                 return ret;
 712         dev->board_ptr = labpc_pci_find_boardinfo(pcidev);
 713         if (!dev->board_ptr)
 714                 return -ENODEV;
 715         devpriv->mite = mite_alloc(pcidev);
 716         if (!devpriv->mite)
 717                 return -ENOMEM;
 718         ret = mite_setup(devpriv->mite);
 719         if (ret < 0)
 720                 return ret;
 721         iobase = (unsigned long)devpriv->mite->daq_io_addr;
 722         irq = mite_irq(devpriv->mite);
 723         return labpc_common_attach(dev, iobase, irq, 0);
 724 }
 725
 726 static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
 727 {
 728         unsigned long iobase = 0;
 729         unsigned int irq = 0;
 730         unsigned int dma_chan = 0;
 731
 732         /* allocate and initialize dev->private */
 733         if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
 734                 return -ENOMEM;
 735
 736         /* get base address, irq etc. based on bustype */
 737         switch (thisboard->bustype) {
 738         case isa_bustype:
 739 #ifdef CONFIG_ISA_DMA_API
 740                 iobase = it->options[0];
 741                 irq = it->options[1];
 742                 dma_chan = it->options[2];
 743 #else
 744                 dev_err(dev->class_dev,
 745                         "ni_labpc driver has not been built with ISA DMA support.\n");
 746                 return -EINVAL;
 747 #endif
 748                 break;
 749         case pci_bustype:
 750 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 751                 dev_err(dev->class_dev,
 752                         "manual configuration of PCI board '%s' is not supported\n",
 753                         thisboard->name);
 754                 return -EINVAL;
 755 #else
 756                 dev_err(dev->class_dev,
 757                         "ni_labpc driver has not been built with PCI support.\n");
 758                 return -EINVAL;
 759 #endif
 760                 break;
 761         default:
 762                 dev_err(dev->class_dev,
 763                         "ni_labpc: bug! couldn't determine board type\n");
 764                 return -EINVAL;
 765                 break;
 766         }
 767
 768         return labpc_common_attach(dev, iobase, irq, dma_chan);
 769 }
 770
 771 void labpc_common_detach(struct comedi_device *dev)
 772 {
 773         struct comedi_subdevice *s;
 774
 775         if (dev->subdevices) {
 776                 s = &dev->subdevices[2];
 777                 subdev_8255_cleanup(dev, s);
 778         }
 779 #ifdef CONFIG_ISA_DMA_API
 780         /* only free stuff if it has been allocated by _attach */
 781         kfree(devpriv->dma_buffer);
 782         if (devpriv->dma_chan)
 783                 free_dma(devpriv->dma_chan);
 784 #endif
 785         if (dev->irq)
 786                 free_irq(dev->irq, dev);
 787         if (thisboard->bustype == isa_bustype && dev->iobase)
 788                 release_region(dev->iobase, LABPC_SIZE);
 789 #ifdef CONFIG_COMEDI_PCI_DRIVERS
 790         if (devpriv->mite) {
 791                 mite_unsetup(devpriv->mite);
 792                 mite_free(devpriv->mite);
 793         }
 794 #endif
 795 };
 796 EXPORT_SYMBOL_GPL(labpc_common_detach);
 797
 798 static void labpc_clear_adc_fifo(const struct comedi_device *dev)
 799 {
 800         devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
 801         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 802         devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
 803 }
 804
 805 static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 806 {
 807         unsigned long flags;
 808
 809         spin_lock_irqsave(&dev->spinlock, flags);
 810         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
 811         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
 812         spin_unlock_irqrestore(&dev->spinlock, flags);
 813
 814         devpriv->command3_bits = 0;
 815         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
 816
 817         return 0;
 818 }
 819
 820 static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
 821 {
 822         if (cmd->chanlist_len == 1)
 823                 return MODE_SINGLE_CHAN;
 824
 825         /* chanlist may be NULL during cmdtest. */
 826         if (cmd->chanlist == NULL)
 827                 return MODE_MULT_CHAN_UP;
 828
 829         if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
 830                 return MODE_SINGLE_CHAN_INTERVAL;
 831
 832         if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
 833                 return MODE_MULT_CHAN_UP;
 834
 835         if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
 836                 return MODE_MULT_CHAN_DOWN;
 837
 838         pr_err("ni_labpc: bug! cannot determine AI scan mode\n");
 839         return 0;
 840 }
 841
 842 static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
 843                                      const struct comedi_cmd *cmd,
 844                                      enum scan_mode mode)
 845 {
 846         int channel, range, aref, i;
 847
 848         if (cmd->chanlist == NULL)
 849                 return 0;
 850
 851         if (mode == MODE_SINGLE_CHAN)
 852                 return 0;
 853
 854         if (mode == MODE_SINGLE_CHAN_INTERVAL) {
 855                 if (cmd->chanlist_len > 0xff) {
 856                         comedi_error(dev,
 857                                      "ni_labpc: chanlist too long for single channel interval mode\n");
 858                         return 1;
 859                 }
 860         }
 861
 862         channel = CR_CHAN(cmd->chanlist[0]);
 863         range = CR_RANGE(cmd->chanlist[0]);
 864         aref = CR_AREF(cmd->chanlist[0]);
 865
 866         for (i = 0; i < cmd->chanlist_len; i++) {
 867
 868                 switch (mode) {
 869                 case MODE_SINGLE_CHAN_INTERVAL:
 870                         if (CR_CHAN(cmd->chanlist[i]) != channel) {
 871                                 comedi_error(dev,
 872                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 873                                 return 1;
 874                         }
 875                         break;
 876                 case MODE_MULT_CHAN_UP:
 877                         if (CR_CHAN(cmd->chanlist[i]) != i) {
 878                                 comedi_error(dev,
 879                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 880                                 return 1;
 881                         }
 882                         break;
 883                 case MODE_MULT_CHAN_DOWN:
 884                         if (CR_CHAN(cmd->chanlist[i]) !=
 885                             cmd->chanlist_len - i - 1) {
 886                                 comedi_error(dev,
 887                                              "channel scanning order specified in chanlist is not supported by hardware.\n");
 888                                 return 1;
 889                         }
 890                         break;
 891                 default:
 892                         dev_err(dev->class_dev,
 893                                 "ni_labpc: bug! in chanlist check\n");
 894                         return 1;
 895                         break;
 896                 }
 897
 898                 if (CR_RANGE(cmd->chanlist[i]) != range) {
 899                         comedi_error(dev,
 900                                      "entries in chanlist must all have the same range\n");
 901                         return 1;
 902                 }
 903
 904                 if (CR_AREF(cmd->chanlist[i]) != aref) {
 905                         comedi_error(dev,
 906                                      "entries in chanlist must all have the same reference\n");
 907                         return 1;
 908                 }
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int labpc_use_continuous_mode(const struct comedi_cmd *cmd,
 915                                      enum scan_mode mode)
 916 {
 917         if (mode == MODE_SINGLE_CHAN)
 918                 return 1;
 919
 920         if (cmd->scan_begin_src == TRIG_FOLLOW)
 921                 return 1;
 922
 923         return 0;
 924 }
 925
 926 static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd,
 927                                             enum scan_mode mode)
 928 {
 929         if (cmd->convert_src != TRIG_TIMER)
 930                 return 0;
 931
 932         if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER)
 933                 return cmd->scan_begin_arg;
 934
 935         return cmd->convert_arg;
 936 }
 937
 938 static void labpc_set_ai_convert_period(struct comedi_cmd *cmd,
 939                                         enum scan_mode mode, unsigned int ns)
 940 {
 941         if (cmd->convert_src != TRIG_TIMER)
 942                 return;
 943
 944         if (mode == MODE_SINGLE_CHAN &&
 945             cmd->scan_begin_src == TRIG_TIMER) {
 946                 cmd->scan_begin_arg = ns;
 947                 if (cmd->convert_arg > cmd->scan_begin_arg)
 948                         cmd->convert_arg = cmd->scan_begin_arg;
 949         } else
 950                 cmd->convert_arg = ns;
 951 }
 952
 953 static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd,
 954                                         enum scan_mode mode)
 955 {
 956         if (cmd->scan_begin_src != TRIG_TIMER)
 957                 return 0;
 958
 959         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 960                 return 0;
 961
 962         return cmd->scan_begin_arg;
 963 }
 964
 965 static void labpc_set_ai_scan_period(struct comedi_cmd *cmd,
 966                                      enum scan_mode mode, unsigned int ns)
 967 {
 968         if (cmd->scan_begin_src != TRIG_TIMER)
 969                 return;
 970
 971         if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER)
 972                 return;
 973
 974         cmd->scan_begin_arg = ns;
 975 }
 976
 977 static int labpc_ai_cmdtest(struct comedi_device *dev,
 978                             struct comedi_subdevice *s, struct comedi_cmd *cmd)
 979 {
 980         int err = 0;
 981         int tmp, tmp2;
 982         unsigned int stop_mask;
 983         enum scan_mode mode;
 984
 985         /* Step 1 : check if triggers are trivially valid */
 986
 987         err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
 988         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 989                                         TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT);
 990         err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
 991         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 992
 993         stop_mask = TRIG_COUNT | TRIG_NONE;
 994         if (thisboard->register_layout == labpc_1200_layout)
 995                 stop_mask |= TRIG_EXT;
 996         err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask);
 997
 998         if (err)
 999                 return 1;
1000
1001         /* Step 2a : make sure trigger sources are unique */
1002
1003         err |= cfc_check_trigger_is_unique(cmd->start_src);
1004         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1005         err |= cfc_check_trigger_is_unique(cmd->convert_src);
1006         err |= cfc_check_trigger_is_unique(cmd->stop_src);
1007
1008         /* Step 2b : and mutually compatible */
1009
1010         /* can't have external stop and start triggers at once */
1011         if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1012                 err++;
1013
1014         if (err)
1015                 return 2;
1016
1017         /* step 3: make sure arguments are trivially compatible */
1018
1019         if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1020                 cmd->start_arg = 0;
1021                 err++;
1022         }
1023
1024         if (!cmd->chanlist_len)
1025                 err++;
1026
1027         if (cmd->scan_end_arg != cmd->chanlist_len) {
1028                 cmd->scan_end_arg = cmd->chanlist_len;
1029                 err++;
1030         }
1031
1032         if (cmd->convert_src == TRIG_TIMER) {
1033                 if (cmd->convert_arg < thisboard->ai_speed) {
1034                         cmd->convert_arg = thisboard->ai_speed;
1035                         err++;
1036                 }
1037         }
1038         /* make sure scan timing is not too fast */
1039         if (cmd->scan_begin_src == TRIG_TIMER) {
1040                 if (cmd->convert_src == TRIG_TIMER &&
1041                     cmd->scan_begin_arg <
1042                     cmd->convert_arg * cmd->chanlist_len) {
1043                         cmd->scan_begin_arg =
1044                             cmd->convert_arg * cmd->chanlist_len;
1045                         err++;
1046                 }
1047                 if (cmd->scan_begin_arg <
1048                     thisboard->ai_speed * cmd->chanlist_len) {
1049                         cmd->scan_begin_arg =
1050                             thisboard->ai_speed * cmd->chanlist_len;
1051                         err++;
1052                 }
1053         }
1054         /* stop source */
1055         switch (cmd->stop_src) {
1056         case TRIG_COUNT:
1057                 if (!cmd->stop_arg) {
1058                         cmd->stop_arg = 1;
1059                         err++;
1060                 }
1061                 break;
1062         case TRIG_NONE:
1063                 if (cmd->stop_arg != 0) {
1064                         cmd->stop_arg = 0;
1065                         err++;
1066                 }
1067                 break;
1068                 /*
1069                  * TRIG_EXT doesn't care since it doesn't
1070                  * trigger off a numbered channel
1071                  */
1072         default:
1073                 break;
1074         }
1075
1076         if (err)
1077                 return 3;
1078
1079         /* step 4: fix up any arguments */
1080
1081         tmp = cmd->convert_arg;
1082         tmp2 = cmd->scan_begin_arg;
1083         mode = labpc_ai_scan_mode(cmd);
1084         labpc_adc_timing(dev, cmd, mode);
1085         if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1086                 err++;
1087
1088         if (err)
1089                 return 4;
1090
1091         if (labpc_ai_chanlist_invalid(dev, cmd, mode))
1092                 return 5;
1093
1094         return 0;
1095 }
1096
1097 static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1098 {
1099         int channel, range, aref;
1100 #ifdef CONFIG_ISA_DMA_API
1101         unsigned long irq_flags;
1102 #endif
1103         int ret;
1104         struct comedi_async *async = s->async;
1105         struct comedi_cmd *cmd = &async->cmd;
1106         enum transfer_type xfer;
1107         enum scan_mode mode;
1108         unsigned long flags;
1109
1110         if (!dev->irq) {
1111                 comedi_error(dev, "no irq assigned, cannot perform command");
1112                 return -1;
1113         }
1114
1115         range = CR_RANGE(cmd->chanlist[0]);
1116         aref = CR_AREF(cmd->chanlist[0]);
1117
1118         /* make sure board is disabled before setting up acquisition */
1119         spin_lock_irqsave(&dev->spinlock, flags);
1120         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1121         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1122         spin_unlock_irqrestore(&dev->spinlock, flags);
1123
1124         devpriv->command3_bits = 0;
1125         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1126
1127         /*  initialize software conversion count */
1128         if (cmd->stop_src == TRIG_COUNT)
1129                 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
1130
1131         /*  setup hardware conversion counter */
1132         if (cmd->stop_src == TRIG_EXT) {
1133                 /*
1134                  * load counter a1 with count of 3
1135                  * (pc+ manual says this is minimum allowed) using mode 0
1136                  */
1137                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1138                                          1, 3, 0);
1139                 if (ret < 0) {
1140                         comedi_error(dev, "error loading counter a1");
1141                         return -1;
1142                 }
1143         } else                  /*
1144                                  * otherwise, just put a1 in mode 0
1145                                  * with no count to set its output low
1146                                  */
1147                 devpriv->write_byte(INIT_A1_BITS,
1148                                     dev->iobase + COUNTER_A_CONTROL_REG);
1149
1150 #ifdef CONFIG_ISA_DMA_API
1151         /*  figure out what method we will use to transfer data */
1152         if (devpriv->dma_chan &&        /*  need a dma channel allocated */
1153                 /*
1154                  * dma unsafe at RT priority,
1155                  * and too much setup time for TRIG_WAKE_EOS for
1156                  */
1157             (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1158             /*  only available on the isa boards */
1159             thisboard->bustype == isa_bustype) {
1160                 xfer = isa_dma_transfer;
1161                 /* pc-plus has no fifo-half full interrupt */
1162         } else
1163 #endif
1164         if (thisboard->register_layout == labpc_1200_layout &&
1165                    /*  wake-end-of-scan should interrupt on fifo not empty */
1166                    (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1167                    /*  make sure we are taking more than just a few points */
1168                    (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
1169                 xfer = fifo_half_full_transfer;
1170         } else
1171                 xfer = fifo_not_empty_transfer;
1172         devpriv->current_transfer = xfer;
1173         mode = labpc_ai_scan_mode(cmd);
1174
1175         /*  setup command6 register for 1200 boards */
1176         if (thisboard->register_layout == labpc_1200_layout) {
1177                 /*  reference inputs to ground or common? */
1178                 if (aref != AREF_GROUND)
1179                         devpriv->command6_bits |= ADC_COMMON_BIT;
1180                 else
1181                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1182                 /*  bipolar or unipolar range? */
1183                 if (thisboard->ai_range_is_unipolar[range])
1184                         devpriv->command6_bits |= ADC_UNIP_BIT;
1185                 else
1186                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1187                 /*  interrupt on fifo half full? */
1188                 if (xfer == fifo_half_full_transfer)
1189                         devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1190                 else
1191                         devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1192                 /*  enable interrupt on counter a1 terminal count? */
1193                 if (cmd->stop_src == TRIG_EXT)
1194                         devpriv->command6_bits |= A1_INTR_EN_BIT;
1195                 else
1196                         devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1197                 /*  are we scanning up or down through channels? */
1198                 if (mode == MODE_MULT_CHAN_UP)
1199                         devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1200                 else
1201                         devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
1202                 /*  write to register */
1203                 devpriv->write_byte(devpriv->command6_bits,
1204                                     dev->iobase + COMMAND6_REG);
1205         }
1206
1207         /* setup channel list, etc (command1 register) */
1208         devpriv->command1_bits = 0;
1209         if (mode == MODE_MULT_CHAN_UP)
1210                 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1211         else
1212                 channel = CR_CHAN(cmd->chanlist[0]);
1213         /* munge channel bits for differential / scan disabled mode */
1214         if (mode != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1215                 channel *= 2;
1216         devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1217         devpriv->command1_bits |= thisboard->ai_range_code[range];
1218         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1219         /* manual says to set scan enable bit on second pass */
1220         if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) {
1221                 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
1222                 /* need a brief delay before enabling scan, or scan
1223                  * list will get screwed when you switch
1224                  * between scan up to scan down mode - dunno why */
1225                 udelay(1);
1226                 devpriv->write_byte(devpriv->command1_bits,
1227                                     dev->iobase + COMMAND1_REG);
1228         }
1229         /*  setup any external triggering/pacing (command4 register) */
1230         devpriv->command4_bits = 0;
1231         if (cmd->convert_src != TRIG_EXT)
1232                 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1233         /* XXX should discard first scan when using interval scanning
1234          * since manual says it is not synced with scan clock */
1235         if (labpc_use_continuous_mode(cmd, mode) == 0) {
1236                 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1237                 if (cmd->scan_begin_src == TRIG_EXT)
1238                         devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1239         }
1240         /*  single-ended/differential */
1241         if (aref == AREF_DIFF)
1242                 devpriv->command4_bits |= ADC_DIFF_BIT;
1243         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1244
1245         devpriv->write_byte(cmd->chanlist_len,
1246                             dev->iobase + INTERVAL_COUNT_REG);
1247         /*  load count */
1248         devpriv->write_byte(INTERVAL_LOAD_BITS,
1249                             dev->iobase + INTERVAL_LOAD_REG);
1250
1251         if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
1252                 /*  set up pacing */
1253                 labpc_adc_timing(dev, cmd, mode);
1254                 /*  load counter b0 in mode 3 */
1255                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1256                                          0, devpriv->divisor_b0, 3);
1257                 if (ret < 0) {
1258                         comedi_error(dev, "error loading counter b0");
1259                         return -1;
1260                 }
1261         }
1262         /*  set up conversion pacing */
1263         if (labpc_ai_convert_period(cmd, mode)) {
1264                 /*  load counter a0 in mode 2 */
1265                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
1266                                          0, devpriv->divisor_a0, 2);
1267                 if (ret < 0) {
1268                         comedi_error(dev, "error loading counter a0");
1269                         return -1;
1270                 }
1271         } else
1272                 devpriv->write_byte(INIT_A0_BITS,
1273                                     dev->iobase + COUNTER_A_CONTROL_REG);
1274
1275         /*  set up scan pacing */
1276         if (labpc_ai_scan_period(cmd, mode)) {
1277                 /*  load counter b1 in mode 2 */
1278                 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
1279                                          1, devpriv->divisor_b1, 2);
1280                 if (ret < 0) {
1281                         comedi_error(dev, "error loading counter b1");
1282                         return -1;
1283                 }
1284         }
1285
1286         labpc_clear_adc_fifo(dev);
1287
1288 #ifdef CONFIG_ISA_DMA_API
1289         /*  set up dma transfer */
1290         if (xfer == isa_dma_transfer) {
1291                 irq_flags = claim_dma_lock();
1292                 disable_dma(devpriv->dma_chan);
1293                 /* clear flip-flop to make sure 2-byte registers for
1294                  * count and address get set correctly */
1295                 clear_dma_ff(devpriv->dma_chan);
1296                 set_dma_addr(devpriv->dma_chan,
1297                              virt_to_bus(devpriv->dma_buffer));
1298                 /*  set appropriate size of transfer */
1299                 devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd);
1300                 if (cmd->stop_src == TRIG_COUNT &&
1301                     devpriv->count * sample_size < devpriv->dma_transfer_size) {
1302                         devpriv->dma_transfer_size =
1303                             devpriv->count * sample_size;
1304                 }
1305                 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1306                 enable_dma(devpriv->dma_chan);
1307                 release_dma_lock(irq_flags);
1308                 /*  enable board's dma */
1309                 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1310         } else
1311                 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1312 #endif
1313
1314         /*  enable error interrupts */
1315         devpriv->command3_bits |= ERR_INTR_EN_BIT;
1316         /*  enable fifo not empty interrupt? */
1317         if (xfer == fifo_not_empty_transfer)
1318                 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1319         else
1320                 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1321         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1322
1323         /*  startup acquisition */
1324
1325         /*  command2 reg */
1326         /*  use 2 cascaded counters for pacing */
1327         spin_lock_irqsave(&dev->spinlock, flags);
1328         devpriv->command2_bits |= CASCADE_BIT;
1329         switch (cmd->start_src) {
1330         case TRIG_EXT:
1331                 devpriv->command2_bits |= HWTRIG_BIT;
1332                 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1333                 break;
1334         case TRIG_NOW:
1335                 devpriv->command2_bits |= SWTRIG_BIT;
1336                 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1337                 break;
1338         default:
1339                 comedi_error(dev, "bug with start_src");
1340                 spin_unlock_irqrestore(&dev->spinlock, flags);
1341                 return -1;
1342                 break;
1343         }
1344         switch (cmd->stop_src) {
1345         case TRIG_EXT:
1346                 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1347                 break;
1348         case TRIG_COUNT:
1349         case TRIG_NONE:
1350                 break;
1351         default:
1352                 comedi_error(dev, "bug with stop_src");
1353                 spin_unlock_irqrestore(&dev->spinlock, flags);
1354                 return -1;
1355         }
1356         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1357         spin_unlock_irqrestore(&dev->spinlock, flags);
1358
1359         return 0;
1360 }
1361
1362 /* interrupt service routine */
1363 static irqreturn_t labpc_interrupt(int irq, void *d)
1364 {
1365         struct comedi_device *dev = d;
1366         struct comedi_subdevice *s = dev->read_subdev;
1367         struct comedi_async *async;
1368         struct comedi_cmd *cmd;
1369
1370         if (dev->attached == 0) {
1371                 comedi_error(dev, "premature interrupt");
1372                 return IRQ_HANDLED;
1373         }
1374
1375         async = s->async;
1376         cmd = &async->cmd;
1377         async->events = 0;
1378
1379         /* read board status */
1380         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1381         if (thisboard->register_layout == labpc_1200_layout)
1382                 devpriv->status2_bits =
1383                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1384
1385         if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
1386                                       OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1387             && (devpriv->status2_bits & A1_TC_BIT) == 0
1388             && (devpriv->status2_bits & FNHF_BIT)) {
1389                 return IRQ_NONE;
1390         }
1391
1392         if (devpriv->status1_bits & OVERRUN_BIT) {
1393                 /* clear error interrupt */
1394                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1395                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1396                 comedi_event(dev, s);
1397                 comedi_error(dev, "overrun");
1398                 return IRQ_HANDLED;
1399         }
1400
1401 #ifdef CONFIG_ISA_DMA_API
1402         if (devpriv->current_transfer == isa_dma_transfer) {
1403                 /*
1404                  * if a dma terminal count of external stop trigger
1405                  * has occurred
1406                  */
1407                 if (devpriv->status1_bits & DMATC_BIT ||
1408                     (thisboard->register_layout == labpc_1200_layout
1409                      && devpriv->status2_bits & A1_TC_BIT)) {
1410                         handle_isa_dma(dev);
1411                 }
1412         } else
1413 #endif
1414                 labpc_drain_fifo(dev);
1415
1416         if (devpriv->status1_bits & TIMER_BIT) {
1417                 comedi_error(dev, "handled timer interrupt?");
1418                 /*  clear it */
1419                 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1420         }
1421
1422         if (devpriv->status1_bits & OVERFLOW_BIT) {
1423                 /*  clear error interrupt */
1424                 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1425                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1426                 comedi_event(dev, s);
1427                 comedi_error(dev, "overflow");
1428                 return IRQ_HANDLED;
1429         }
1430         /*  handle external stop trigger */
1431         if (cmd->stop_src == TRIG_EXT) {
1432                 if (devpriv->status2_bits & A1_TC_BIT) {
1433                         labpc_drain_dregs(dev);
1434                         labpc_cancel(dev, s);
1435                         async->events |= COMEDI_CB_EOA;
1436                 }
1437         }
1438
1439         /* TRIG_COUNT end of acquisition */
1440         if (cmd->stop_src == TRIG_COUNT) {
1441                 if (devpriv->count == 0) {
1442                         labpc_cancel(dev, s);
1443                         async->events |= COMEDI_CB_EOA;
1444                 }
1445         }
1446
1447         comedi_event(dev, s);
1448         return IRQ_HANDLED;
1449 }
1450
1451 /* read all available samples from ai fifo */
1452 static int labpc_drain_fifo(struct comedi_device *dev)
1453 {
1454         unsigned int lsb, msb;
1455         short data;
1456         struct comedi_async *async = dev->read_subdev->async;
1457         const int timeout = 10000;
1458         unsigned int i;
1459
1460         devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1461
1462         for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
1463              i++) {
1464                 /*  quit if we have all the data we want */
1465                 if (async->cmd.stop_src == TRIG_COUNT) {
1466                         if (devpriv->count == 0)
1467                                 break;
1468                         devpriv->count--;
1469                 }
1470                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1471                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1472                 data = (msb << 8) | lsb;
1473                 cfc_write_to_buffer(dev->read_subdev, data);
1474                 devpriv->status1_bits =
1475                     devpriv->read_byte(dev->iobase + STATUS1_REG);
1476         }
1477         if (i == timeout) {
1478                 comedi_error(dev, "ai timeout, fifo never empties");
1479                 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1480                 return -1;
1481         }
1482
1483         return 0;
1484 }
1485
1486 #ifdef CONFIG_ISA_DMA_API
1487 static void labpc_drain_dma(struct comedi_device *dev)
1488 {
1489         struct comedi_subdevice *s = dev->read_subdev;
1490         struct comedi_async *async = s->async;
1491         int status;
1492         unsigned long flags;
1493         unsigned int max_points, num_points, residue, leftover;
1494         int i;
1495
1496         status = devpriv->status1_bits;
1497
1498         flags = claim_dma_lock();
1499         disable_dma(devpriv->dma_chan);
1500         /* clear flip-flop to make sure 2-byte registers for
1501          * count and address get set correctly */
1502         clear_dma_ff(devpriv->dma_chan);
1503
1504         /*  figure out how many points to read */
1505         max_points = devpriv->dma_transfer_size / sample_size;
1506         /* residue is the number of points left to be done on the dma
1507          * transfer.  It should always be zero at this point unless
1508          * the stop_src is set to external triggering.
1509          */
1510         residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1511         num_points = max_points - residue;
1512         if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1513                 num_points = devpriv->count;
1514
1515         /*  figure out how many points will be stored next time */
1516         leftover = 0;
1517         if (async->cmd.stop_src != TRIG_COUNT) {
1518                 leftover = devpriv->dma_transfer_size / sample_size;
1519         } else if (devpriv->count > num_points) {
1520                 leftover = devpriv->count - num_points;
1521                 if (leftover > max_points)
1522                         leftover = max_points;
1523         }
1524
1525         /* write data to comedi buffer */
1526         for (i = 0; i < num_points; i++)
1527                 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
1528
1529         if (async->cmd.stop_src == TRIG_COUNT)
1530                 devpriv->count -= num_points;
1531
1532         /*  set address and count for next transfer */
1533         set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1534         set_dma_count(devpriv->dma_chan, leftover * sample_size);
1535         release_dma_lock(flags);
1536
1537         async->events |= COMEDI_CB_BLOCK;
1538 }
1539
1540 static void handle_isa_dma(struct comedi_device *dev)
1541 {
1542         labpc_drain_dma(dev);
1543
1544         enable_dma(devpriv->dma_chan);
1545
1546         /*  clear dma tc interrupt */
1547         devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1548 }
1549 #endif
1550
1551 /* makes sure all data acquired by board is transferred to comedi (used
1552  * when acquisition is terminated by stop_src == TRIG_EXT). */
1553 static void labpc_drain_dregs(struct comedi_device *dev)
1554 {
1555 #ifdef CONFIG_ISA_DMA_API
1556         if (devpriv->current_transfer == isa_dma_transfer)
1557                 labpc_drain_dma(dev);
1558 #endif
1559
1560         labpc_drain_fifo(dev);
1561 }
1562
1563 static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1564                           struct comedi_insn *insn, unsigned int *data)
1565 {
1566         int i, n;
1567         int chan, range;
1568         int lsb, msb;
1569         int timeout = 1000;
1570         unsigned long flags;
1571
1572         /*  disable timed conversions */
1573         spin_lock_irqsave(&dev->spinlock, flags);
1574         devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1575         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1576         spin_unlock_irqrestore(&dev->spinlock, flags);
1577
1578         /*  disable interrupt generation and dma */
1579         devpriv->command3_bits = 0;
1580         devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1581
1582         /* set gain and channel */
1583         devpriv->command1_bits = 0;
1584         chan = CR_CHAN(insn->chanspec);
1585         range = CR_RANGE(insn->chanspec);
1586         devpriv->command1_bits |= thisboard->ai_range_code[range];
1587         /* munge channel bits for differential/scan disabled mode */
1588         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1589                 chan *= 2;
1590         devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1591         devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1592
1593         /* setup command6 register for 1200 boards */
1594         if (thisboard->register_layout == labpc_1200_layout) {
1595                 /*  reference inputs to ground or common? */
1596                 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1597                         devpriv->command6_bits |= ADC_COMMON_BIT;
1598                 else
1599                         devpriv->command6_bits &= ~ADC_COMMON_BIT;
1600                 /* bipolar or unipolar range? */
1601                 if (thisboard->ai_range_is_unipolar[range])
1602                         devpriv->command6_bits |= ADC_UNIP_BIT;
1603                 else
1604                         devpriv->command6_bits &= ~ADC_UNIP_BIT;
1605                 /* don't interrupt on fifo half full */
1606                 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
1607                 /* don't enable interrupt on counter a1 terminal count? */
1608                 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
1609                 /* write to register */
1610                 devpriv->write_byte(devpriv->command6_bits,
1611                                     dev->iobase + COMMAND6_REG);
1612         }
1613         /* setup command4 register */
1614         devpriv->command4_bits = 0;
1615         devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1616         /* single-ended/differential */
1617         if (CR_AREF(insn->chanspec) == AREF_DIFF)
1618                 devpriv->command4_bits |= ADC_DIFF_BIT;
1619         devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1620
1621         /*
1622          * initialize pacer counter output to make sure it doesn't
1623          * cause any problems
1624          */
1625         devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1626
1627         labpc_clear_adc_fifo(dev);
1628
1629         for (n = 0; n < insn->n; n++) {
1630                 /* trigger conversion */
1631                 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1632
1633                 for (i = 0; i < timeout; i++) {
1634                         if (devpriv->read_byte(dev->iobase +
1635                                                STATUS1_REG) & DATA_AVAIL_BIT)
1636                                 break;
1637                         udelay(1);
1638                 }
1639                 if (i == timeout) {
1640                         comedi_error(dev, "timeout");
1641                         return -ETIME;
1642                 }
1643                 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1644                 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1645                 data[n] = (msb << 8) | lsb;
1646         }
1647
1648         return n;
1649 }
1650
1651 /* analog output insn */
1652 static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1653                           struct comedi_insn *insn, unsigned int *data)
1654 {
1655         int channel, range;
1656         unsigned long flags;
1657         int lsb, msb;
1658
1659         channel = CR_CHAN(insn->chanspec);
1660
1661         /* turn off pacing of analog output channel */
1662         /* note: hardware bug in daqcard-1200 means pacing cannot
1663          * be independently enabled/disabled for its the two channels */
1664         spin_lock_irqsave(&dev->spinlock, flags);
1665         devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1666         devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
1667         spin_unlock_irqrestore(&dev->spinlock, flags);
1668
1669         /* set range */
1670         if (thisboard->register_layout == labpc_1200_layout) {
1671                 range = CR_RANGE(insn->chanspec);
1672                 if (range & AO_RANGE_IS_UNIPOLAR)
1673                         devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1674                 else
1675                         devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
1676                 /*  write to register */
1677                 devpriv->write_byte(devpriv->command6_bits,
1678                                     dev->iobase + COMMAND6_REG);
1679         }
1680         /* send data */
1681         lsb = data[0] & 0xff;
1682         msb = (data[0] >> 8) & 0xff;
1683         devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1684         devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1685
1686         /* remember value for readback */
1687         devpriv->ao_value[channel] = data[0];
1688
1689         return 1;
1690 }
1691
1692 /* analog output readback insn */
1693 static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1694                           struct comedi_insn *insn, unsigned int *data)
1695 {
1696         data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1697
1698         return 1;
1699 }
1700
1701 static int labpc_calib_read_insn(struct comedi_device *dev,
1702                                  struct comedi_subdevice *s,
1703                                  struct comedi_insn *insn, unsigned int *data)
1704 {
1705         data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1706
1707         return 1;
1708 }
1709
1710 static int labpc_calib_write_insn(struct comedi_device *dev,
1711                                   struct comedi_subdevice *s,
1712                                   struct comedi_insn *insn, unsigned int *data)
1713 {
1714         int channel = CR_CHAN(insn->chanspec);
1715
1716         write_caldac(dev, channel, data[0]);
1717         return 1;
1718 }
1719
1720 static int labpc_eeprom_read_insn(struct comedi_device *dev,
1721                                   struct comedi_subdevice *s,
1722                                   struct comedi_insn *insn, unsigned int *data)
1723 {
1724         data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1725
1726         return 1;
1727 }
1728
1729 static int labpc_eeprom_write_insn(struct comedi_device *dev,
1730                                    struct comedi_subdevice *s,
1731                                    struct comedi_insn *insn, unsigned int *data)
1732 {
1733         int channel = CR_CHAN(insn->chanspec);
1734         int ret;
1735
1736         /*  only allow writes to user area of eeprom */
1737         if (channel < 16 || channel > 127) {
1738                 dev_dbg(dev->class_dev,
1739                         "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n");
1740                 return -EINVAL;
1741         }
1742
1743         ret = labpc_eeprom_write(dev, channel, data[0]);
1744         if (ret < 0)
1745                 return ret;
1746
1747         return 1;
1748 }
1749
1750 #ifdef CONFIG_ISA_DMA_API
1751 /* utility function that suggests a dma transfer size in bytes */
1752 static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd)
1753 {
1754         unsigned int size;
1755         unsigned int freq;
1756
1757         if (cmd->convert_src == TRIG_TIMER)
1758                 freq = 1000000000 / cmd->convert_arg;
1759         /* return some default value */
1760         else
1761                 freq = 0xffffffff;
1762
1763         /* make buffer fill in no more than 1/3 second */
1764         size = (freq / 3) * sample_size;
1765
1766         /* set a minimum and maximum size allowed */
1767         if (size > dma_buffer_size)
1768                 size = dma_buffer_size - dma_buffer_size % sample_size;
1769         else if (size < sample_size)
1770                 size = sample_size;
1771
1772         return size;
1773 }
1774 #endif
1775
1776 /* figures out what counter values to use based on command */
1777 static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd,
1778                              enum scan_mode mode)
1779 {
1780         /* max value for 16 bit counter in mode 2 */
1781         const int max_counter_value = 0x10000;
1782         /* min value for 16 bit counter in mode 2 */
1783         const int min_counter_value = 2;
1784         unsigned int base_period;
1785         unsigned int scan_period;
1786         unsigned int convert_period;
1787
1788         /*
1789          * if both convert and scan triggers are TRIG_TIMER, then they
1790          * both rely on counter b0
1791          */
1792         convert_period = labpc_ai_convert_period(cmd, mode);
1793         scan_period = labpc_ai_scan_period(cmd, mode);
1794         if (convert_period && scan_period) {
1795                 /*
1796                  * pick the lowest b0 divisor value we can (for maximum input
1797                  * clock speed on convert and scan counters)
1798                  */
1799                 devpriv->divisor_b0 = (scan_period - 1) /
1800                     (LABPC_TIMER_BASE * max_counter_value) + 1;
1801                 if (devpriv->divisor_b0 < min_counter_value)
1802                         devpriv->divisor_b0 = min_counter_value;
1803                 if (devpriv->divisor_b0 > max_counter_value)
1804                         devpriv->divisor_b0 = max_counter_value;
1805
1806                 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1807
1808                 /*  set a0 for conversion frequency and b1 for scan frequency */
1809                 switch (cmd->flags & TRIG_ROUND_MASK) {
1810                 default:
1811                 case TRIG_ROUND_NEAREST:
1812                         devpriv->divisor_a0 =
1813                             (convert_period + (base_period / 2)) / base_period;
1814                         devpriv->divisor_b1 =
1815                             (scan_period + (base_period / 2)) / base_period;
1816                         break;
1817                 case TRIG_ROUND_UP:
1818                         devpriv->divisor_a0 =
1819                             (convert_period + (base_period - 1)) / base_period;
1820                         devpriv->divisor_b1 =
1821                             (scan_period + (base_period - 1)) / base_period;
1822                         break;
1823                 case TRIG_ROUND_DOWN:
1824                         devpriv->divisor_a0 = convert_period / base_period;
1825                         devpriv->divisor_b1 = scan_period / base_period;
1826                         break;
1827                 }
1828                 /*  make sure a0 and b1 values are acceptable */
1829                 if (devpriv->divisor_a0 < min_counter_value)
1830                         devpriv->divisor_a0 = min_counter_value;
1831                 if (devpriv->divisor_a0 > max_counter_value)
1832                         devpriv->divisor_a0 = max_counter_value;
1833                 if (devpriv->divisor_b1 < min_counter_value)
1834                         devpriv->divisor_b1 = min_counter_value;
1835                 if (devpriv->divisor_b1 > max_counter_value)
1836                         devpriv->divisor_b1 = max_counter_value;
1837                 /*  write corrected timings to command */
1838                 labpc_set_ai_convert_period(cmd, mode,
1839                                             base_period * devpriv->divisor_a0);
1840                 labpc_set_ai_scan_period(cmd, mode,
1841                                          base_period * devpriv->divisor_b1);
1842                 /*
1843                  * if only one TRIG_TIMER is used, we can employ the generic
1844                  * cascaded timing functions
1845                  */
1846         } else if (scan_period) {
1847                 /*
1848                  * calculate cascaded counter values
1849                  * that give desired scan timing
1850                  */
1851                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1852                                                &(devpriv->divisor_b1),
1853                                                &(devpriv->divisor_b0),
1854                                                &scan_period,
1855                                                cmd->flags & TRIG_ROUND_MASK);
1856                 labpc_set_ai_scan_period(cmd, mode, scan_period);
1857         } else if (convert_period) {
1858                 /*
1859                  * calculate cascaded counter values
1860                  * that give desired conversion timing
1861                  */
1862                 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
1863                                                &(devpriv->divisor_a0),
1864                                                &(devpriv->divisor_b0),
1865                                                &convert_period,
1866                                                cmd->flags & TRIG_ROUND_MASK);
1867                 labpc_set_ai_convert_period(cmd, mode, convert_period);
1868         }
1869 }
1870
1871 static int labpc_dio_mem_callback(int dir, int port, int data,
1872                                   unsigned long iobase)
1873 {
1874         if (dir) {
1875                 writeb(data, (void __iomem *)(iobase + port));
1876                 return 0;
1877         } else {
1878                 return readb((void __iomem *)(iobase + port));
1879         }
1880 }
1881
1882 /* lowlevel write to eeprom/dac */
1883 static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
1884                              unsigned int value_width)
1885 {
1886         int i;
1887
1888         for (i = 1; i <= value_width; i++) {
1889                 /*  clear serial clock */
1890                 devpriv->command5_bits &= ~SCLOCK_BIT;
1891                 /*  send bits most significant bit first */
1892                 if (value & (1 << (value_width - i)))
1893                         devpriv->command5_bits |= SDATA_BIT;
1894                 else
1895                         devpriv->command5_bits &= ~SDATA_BIT;
1896                 udelay(1);
1897                 devpriv->write_byte(devpriv->command5_bits,
1898                                     dev->iobase + COMMAND5_REG);
1899                 /*  set clock to load bit */
1900                 devpriv->command5_bits |= SCLOCK_BIT;
1901                 udelay(1);
1902                 devpriv->write_byte(devpriv->command5_bits,
1903                                     dev->iobase + COMMAND5_REG);
1904         }
1905 }
1906
1907 /* lowlevel read from eeprom */
1908 static unsigned int labpc_serial_in(struct comedi_device *dev)
1909 {
1910         unsigned int value = 0;
1911         int i;
1912         const int value_width = 8;      /*  number of bits wide values are */
1913
1914         for (i = 1; i <= value_width; i++) {
1915                 /*  set serial clock */
1916                 devpriv->command5_bits |= SCLOCK_BIT;
1917                 udelay(1);
1918                 devpriv->write_byte(devpriv->command5_bits,
1919                                     dev->iobase + COMMAND5_REG);
1920                 /*  clear clock bit */
1921                 devpriv->command5_bits &= ~SCLOCK_BIT;
1922                 udelay(1);
1923                 devpriv->write_byte(devpriv->command5_bits,
1924                                     dev->iobase + COMMAND5_REG);
1925                 /*  read bits most significant bit first */
1926                 udelay(1);
1927                 devpriv->status2_bits =
1928                     devpriv->read_byte(dev->iobase + STATUS2_REG);
1929                 if (devpriv->status2_bits & EEPROM_OUT_BIT)
1930                         value |= 1 << (value_width - i);
1931         }
1932
1933         return value;
1934 }
1935
1936 static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1937                                       unsigned int address)
1938 {
1939         unsigned int value;
1940         /*  bits to tell eeprom to expect a read */
1941         const int read_instruction = 0x3;
1942         /*  8 bit write lengths to eeprom */
1943         const int write_length = 8;
1944
1945         /*  enable read/write to eeprom */
1946         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1947         udelay(1);
1948         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1949         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1950         udelay(1);
1951         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1952
1953         /*  send read instruction */
1954         labpc_serial_out(dev, read_instruction, write_length);
1955         /*  send 8 bit address to read from */
1956         labpc_serial_out(dev, address, write_length);
1957         /*  read result */
1958         value = labpc_serial_in(dev);
1959
1960         /*  disable read/write to eeprom */
1961         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
1962         udelay(1);
1963         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1964
1965         return value;
1966 }
1967
1968 static int labpc_eeprom_write(struct comedi_device *dev,
1969                                 unsigned int address, unsigned int value)
1970 {
1971         const int write_enable_instruction = 0x6;
1972         const int write_instruction = 0x2;
1973         const int write_length = 8;     /*  8 bit write lengths to eeprom */
1974         const int write_in_progress_bit = 0x1;
1975         const int timeout = 10000;
1976         int i;
1977
1978         /*  make sure there isn't already a write in progress */
1979         for (i = 0; i < timeout; i++) {
1980                 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
1981                     0)
1982                         break;
1983         }
1984         if (i == timeout) {
1985                 comedi_error(dev, "eeprom write timed out");
1986                 return -ETIME;
1987         }
1988         /*  update software copy of eeprom */
1989         devpriv->eeprom_data[address] = value;
1990
1991         /*  enable read/write to eeprom */
1992         devpriv->command5_bits &= ~EEPROM_EN_BIT;
1993         udelay(1);
1994         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1995         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
1996         udelay(1);
1997         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1998
1999         /*  send write_enable instruction */
2000         labpc_serial_out(dev, write_enable_instruction, write_length);
2001         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2002         udelay(1);
2003         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2004
2005         /*  send write instruction */
2006         devpriv->command5_bits |= EEPROM_EN_BIT;
2007         udelay(1);
2008         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2009         labpc_serial_out(dev, write_instruction, write_length);
2010         /*  send 8 bit address to write to */
2011         labpc_serial_out(dev, address, write_length);
2012         /*  write value */
2013         labpc_serial_out(dev, value, write_length);
2014         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2015         udelay(1);
2016         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2017
2018         /*  disable read/write to eeprom */
2019         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2020         udelay(1);
2021         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2022
2023         return 0;
2024 }
2025
2026 static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
2027 {
2028         unsigned int value;
2029         const int read_status_instruction = 0x5;
2030         const int write_length = 8;     /*  8 bit write lengths to eeprom */
2031
2032         /*  enable read/write to eeprom */
2033         devpriv->command5_bits &= ~EEPROM_EN_BIT;
2034         udelay(1);
2035         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2036         devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
2037         udelay(1);
2038         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2039
2040         /*  send read status instruction */
2041         labpc_serial_out(dev, read_status_instruction, write_length);
2042         /*  read result */
2043         value = labpc_serial_in(dev);
2044
2045         /*  disable read/write to eeprom */
2046         devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2047         udelay(1);
2048         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2049
2050         return value;
2051 }
2052
2053 /* writes to 8 bit calibration dacs */
2054 static void write_caldac(struct comedi_device *dev, unsigned int channel,
2055                          unsigned int value)
2056 {
2057         if (value == devpriv->caldac[channel])
2058                 return;
2059         devpriv->caldac[channel] = value;
2060
2061         /*  clear caldac load bit and make sure we don't write to eeprom */
2062         devpriv->command5_bits &=
2063             ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
2064         udelay(1);
2065         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2066
2067         /*  write 4 bit channel */
2068         labpc_serial_out(dev, channel, 4);
2069         /*  write 8 bit caldac value */
2070         labpc_serial_out(dev, value, 8);
2071
2072         /*  set and clear caldac bit to load caldac value */
2073         devpriv->command5_bits |= CALDAC_LOAD_BIT;
2074         udelay(1);
2075         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2076         devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
2077         udelay(1);
2078         devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2079 }
2080
2081 static struct comedi_driver labpc_driver = {
2082         .driver_name = DRV_NAME,
2083         .module = THIS_MODULE,
2084         .attach = labpc_attach,
2085         .attach_pci = labpc_attach_pci,
2086         .detach = labpc_common_detach,
2087         .num_names = ARRAY_SIZE(labpc_boards),
2088         .board_name = &labpc_boards[0].name,
2089         .offset = sizeof(struct labpc_board_struct),
2090 };
2091
2092 #ifdef CONFIG_COMEDI_PCI_DRIVERS
2093 static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
2094         {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
2095         {0}
2096 };
2097 MODULE_DEVICE_TABLE(pci, labpc_pci_table);
2098
2099 static int __devinit labpc_pci_probe(struct pci_dev *dev,
2100                                      const struct pci_device_id *ent)
2101 {
2102         return comedi_pci_auto_config(dev, &labpc_driver);
2103 }
2104
2105 static void __devexit labpc_pci_remove(struct pci_dev *dev)
2106 {
2107         comedi_pci_auto_unconfig(dev);
2108 }
2109
2110 static struct pci_driver labpc_pci_driver = {
2111         .name = DRV_NAME,
2112         .id_table = labpc_pci_table,
2113         .probe = labpc_pci_probe,
2114         .remove = __devexit_p(labpc_pci_remove)
2115 };
2116 module_comedi_pci_driver(labpc_driver, labpc_pci_driver);
2117 #else
2118 module_comedi_driver(labpc_driver);
2119 #endif
2120
2121
2122 MODULE_AUTHOR("Comedi http://www.comedi.org");
2123 MODULE_DESCRIPTION("Comedi low-level driver");
2124 MODULE_LICENSE("GPL");