arch/arm/mach-omap2/opp3xxx_data.c

   1 /*
   2  * OMAP3 OPP table definitions.
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Nishanth Menon
   6  *      Kevin Hilman
   7  * Copyright (C) 2010-2011 Nokia Corporation.
   8  *      Eduardo Valentin
   9  *      Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  16  * kind, whether express or implied; without even the implied warranty
  17  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20 #include <linux/module.h>
  21
  22 #include "control.h"
  23 #include "omap_opp_data.h"
  24 #include "pm.h"
  25
  26 /* 34xx */
  27
  28 /* VDD1 */
  29
  30 #define OMAP3430_VDD_MPU_OPP1_UV                975000
  31 #define OMAP3430_VDD_MPU_OPP2_UV                1075000
  32 #define OMAP3430_VDD_MPU_OPP3_UV                1200000
  33 #define OMAP3430_VDD_MPU_OPP4_UV                1270000
  34 #define OMAP3430_VDD_MPU_OPP5_UV                1350000
  35
  36 struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
  37         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
  38         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
  39         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
  40         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
  41         VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
  42         VOLT_DATA_DEFINE(0, 0, 0, 0),
  43 };
  44
  45 /* VDD2 */
  46
  47 #define OMAP3430_VDD_CORE_OPP1_UV               975000
  48 #define OMAP3430_VDD_CORE_OPP2_UV               1050000
  49 #define OMAP3430_VDD_CORE_OPP3_UV               1150000
  50
  51 struct omap_volt_data omap34xx_vddcore_volt_data[] = {
  52         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
  53         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
  54         VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
  55         VOLT_DATA_DEFINE(0, 0, 0, 0),
  56 };
  57
  58 /* 36xx */
  59
  60 /* VDD1 */
  61
  62 #define OMAP3630_VDD_MPU_OPP50_UV               1012500
  63 #define OMAP3630_VDD_MPU_OPP100_UV              1200000
  64 #define OMAP3630_VDD_MPU_OPP120_UV              1325000
  65 #define OMAP3630_VDD_MPU_OPP1G_UV               1375000
  66
  67 struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
  68         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
  69         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
  70         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
  71         VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
  72         VOLT_DATA_DEFINE(0, 0, 0, 0),
  73 };
  74
  75 /* VDD2 */
  76
  77 #define OMAP3630_VDD_CORE_OPP50_UV              1000000
  78 #define OMAP3630_VDD_CORE_OPP100_UV             1200000
  79
  80 struct omap_volt_data omap36xx_vddcore_volt_data[] = {
  81         VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
  82         VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
  83         VOLT_DATA_DEFINE(0, 0, 0, 0),
  84 };
  85
  86 /* OPP data */
  87
  88 static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
  89         /* MPU OPP1 */
  90         OPP_INITIALIZER("mpu", true, 125000000, OMAP3430_VDD_MPU_OPP1_UV),
  91         /* MPU OPP2 */
  92         OPP_INITIALIZER("mpu", true, 250000000, OMAP3430_VDD_MPU_OPP2_UV),
  93         /* MPU OPP3 */
  94         OPP_INITIALIZER("mpu", true, 500000000, OMAP3430_VDD_MPU_OPP3_UV),
  95         /* MPU OPP4 */
  96         OPP_INITIALIZER("mpu", true, 550000000, OMAP3430_VDD_MPU_OPP4_UV),
  97         /* MPU OPP5 */
  98         OPP_INITIALIZER("mpu", true, 600000000, OMAP3430_VDD_MPU_OPP5_UV),
  99
 100         /*
 101          * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
 102          * almost the same than the one at 83MHz thus providing very little
 103          * gain for the power point of view. In term of energy it will even
 104          * increase the consumption due to the very negative performance
 105          * impact that frequency will do to the MPU and the whole system in
 106          * general.
 107          */
 108         OPP_INITIALIZER("l3_main", false, 41500000, OMAP3430_VDD_CORE_OPP1_UV),
 109         /* L3 OPP2 */
 110         OPP_INITIALIZER("l3_main", true, 83000000, OMAP3430_VDD_CORE_OPP2_UV),
 111         /* L3 OPP3 */
 112         OPP_INITIALIZER("l3_main", true, 166000000, OMAP3430_VDD_CORE_OPP3_UV),
 113
 114         /* DSP OPP1 */
 115         OPP_INITIALIZER("iva", true, 90000000, OMAP3430_VDD_MPU_OPP1_UV),
 116         /* DSP OPP2 */
 117         OPP_INITIALIZER("iva", true, 180000000, OMAP3430_VDD_MPU_OPP2_UV),
 118         /* DSP OPP3 */
 119         OPP_INITIALIZER("iva", true, 360000000, OMAP3430_VDD_MPU_OPP3_UV),
 120         /* DSP OPP4 */
 121         OPP_INITIALIZER("iva", true, 400000000, OMAP3430_VDD_MPU_OPP4_UV),
 122         /* DSP OPP5 */
 123         OPP_INITIALIZER("iva", true, 430000000, OMAP3430_VDD_MPU_OPP5_UV),
 124 };
 125
 126 static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 127         /* MPU OPP1 - OPP50 */
 128         OPP_INITIALIZER("mpu", true,  300000000, OMAP3630_VDD_MPU_OPP50_UV),
 129         /* MPU OPP2 - OPP100 */
 130         OPP_INITIALIZER("mpu", true,  600000000, OMAP3630_VDD_MPU_OPP100_UV),
 131         /* MPU OPP3 - OPP-Turbo */
 132         OPP_INITIALIZER("mpu", false, 800000000, OMAP3630_VDD_MPU_OPP120_UV),
 133         /* MPU OPP4 - OPP-SB */
 134         OPP_INITIALIZER("mpu", false, 1000000000, OMAP3630_VDD_MPU_OPP1G_UV),
 135
 136         /* L3 OPP1 - OPP50 */
 137         OPP_INITIALIZER("l3_main", true, 100000000, OMAP3630_VDD_CORE_OPP50_UV),
 138         /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
 139         OPP_INITIALIZER("l3_main", true, 200000000, OMAP3630_VDD_CORE_OPP100_UV),
 140
 141         /* DSP OPP1 - OPP50 */
 142         OPP_INITIALIZER("iva", true,  260000000, OMAP3630_VDD_MPU_OPP50_UV),
 143         /* DSP OPP2 - OPP100 */
 144         OPP_INITIALIZER("iva", true,  520000000, OMAP3630_VDD_MPU_OPP100_UV),
 145         /* DSP OPP3 - OPP-Turbo */
 146         OPP_INITIALIZER("iva", false, 660000000, OMAP3630_VDD_MPU_OPP120_UV),
 147         /* DSP OPP4 - OPP-SB */
 148         OPP_INITIALIZER("iva", false, 800000000, OMAP3630_VDD_MPU_OPP1G_UV),
 149 };
 150
 151 /**
 152  * omap3_opp_init() - initialize omap3 opp table
 153  */
 154 int __init omap3_opp_init(void)
 155 {
 156         int r = -ENODEV;
 157
 158         if (!cpu_is_omap34xx())
 159                 return r;
 160
 161         if (cpu_is_omap3630())
 162                 r = omap_init_opp_table(omap36xx_opp_def_list,
 163                         ARRAY_SIZE(omap36xx_opp_def_list));
 164         else
 165                 r = omap_init_opp_table(omap34xx_opp_def_list,
 166                         ARRAY_SIZE(omap34xx_opp_def_list));
 167
 168         return r;
 169 }
 170 device_initcall(omap3_opp_init);