arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include <plat/sdrc.h>
  19
  20 #include "soc.h"
  21 #include "iomap.h"
  22 #include "common.h"
  23 #include "cm-regbits-34xx.h"
  24 #include "prm-regbits-34xx.h"
  25 #include "prm2xxx_3xxx.h"
  26 #include "cm2xxx_3xxx.h"
  27 #include "sdrc.h"
  28 #include "pm.h"
  29 #include "control.h"
  30
  31 /* Used by omap3_ctrl_save_padconf() */
  32 #define START_PADCONF_SAVE              0x2
  33 #define PADCONF_SAVE_DONE               0x1
  34
  35 static void __iomem *omap2_ctrl_base;
  36 static void __iomem *omap4_ctrl_pad_base;
  37
  38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  39 struct omap3_scratchpad {
  40         u32 boot_config_ptr;
  41         u32 public_restore_ptr;
  42         u32 secure_ram_restore_ptr;
  43         u32 sdrc_module_semaphore;
  44         u32 prcm_block_offset;
  45         u32 sdrc_block_offset;
  46 };
  47
  48 struct omap3_scratchpad_prcm_block {
  49         u32 prm_clksrc_ctrl;
  50         u32 prm_clksel;
  51         u32 cm_clksel_core;
  52         u32 cm_clksel_wkup;
  53         u32 cm_clken_pll;
  54         u32 cm_autoidle_pll;
  55         u32 cm_clksel1_pll;
  56         u32 cm_clksel2_pll;
  57         u32 cm_clksel3_pll;
  58         u32 cm_clken_pll_mpu;
  59         u32 cm_autoidle_pll_mpu;
  60         u32 cm_clksel1_pll_mpu;
  61         u32 cm_clksel2_pll_mpu;
  62         u32 prcm_block_size;
  63 };
  64
  65 struct omap3_scratchpad_sdrc_block {
  66         u16 sysconfig;
  67         u16 cs_cfg;
  68         u16 sharing;
  69         u16 err_type;
  70         u32 dll_a_ctrl;
  71         u32 dll_b_ctrl;
  72         u32 power;
  73         u32 cs_0;
  74         u32 mcfg_0;
  75         u16 mr_0;
  76         u16 emr_1_0;
  77         u16 emr_2_0;
  78         u16 emr_3_0;
  79         u32 actim_ctrla_0;
  80         u32 actim_ctrlb_0;
  81         u32 rfr_ctrl_0;
  82         u32 cs_1;
  83         u32 mcfg_1;
  84         u16 mr_1;
  85         u16 emr_1_1;
  86         u16 emr_2_1;
  87         u16 emr_3_1;
  88         u32 actim_ctrla_1;
  89         u32 actim_ctrlb_1;
  90         u32 rfr_ctrl_1;
  91         u16 dcdl_1_ctrl;
  92         u16 dcdl_2_ctrl;
  93         u32 flags;
  94         u32 block_size;
  95 };
  96
  97 void *omap3_secure_ram_storage;
  98
  99 /*
 100  * This is used to store ARM registers in SDRAM before attempting
 101  * an MPU OFF. The save and restore happens from the SRAM sleep code.
 102  * The address is stored in scratchpad, so that it can be used
 103  * during the restore path.
 104  */
 105 u32 omap3_arm_context[128];
 106
 107 struct omap3_control_regs {
 108         u32 sysconfig;
 109         u32 devconf0;
 110         u32 mem_dftrw0;
 111         u32 mem_dftrw1;
 112         u32 msuspendmux_0;
 113         u32 msuspendmux_1;
 114         u32 msuspendmux_2;
 115         u32 msuspendmux_3;
 116         u32 msuspendmux_4;
 117         u32 msuspendmux_5;
 118         u32 sec_ctrl;
 119         u32 devconf1;
 120         u32 csirxfe;
 121         u32 iva2_bootaddr;
 122         u32 iva2_bootmod;
 123         u32 debobs_0;
 124         u32 debobs_1;
 125         u32 debobs_2;
 126         u32 debobs_3;
 127         u32 debobs_4;
 128         u32 debobs_5;
 129         u32 debobs_6;
 130         u32 debobs_7;
 131         u32 debobs_8;
 132         u32 prog_io0;
 133         u32 prog_io1;
 134         u32 dss_dpll_spreading;
 135         u32 core_dpll_spreading;
 136         u32 per_dpll_spreading;
 137         u32 usbhost_dpll_spreading;
 138         u32 pbias_lite;
 139         u32 temp_sensor;
 140         u32 sramldo4;
 141         u32 sramldo5;
 142         u32 csi;
 143         u32 padconf_sys_nirq;
 144 };
 145
 146 static struct omap3_control_regs control_context;
 147 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 148
 149 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 150 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 151
 152 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
 153 {
 154         if (omap2_globals->ctrl)
 155                 omap2_ctrl_base = omap2_globals->ctrl;
 156
 157         if (omap2_globals->ctrl_pad)
 158                 omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
 159 }
 160
 161 void __iomem *omap_ctrl_base_get(void)
 162 {
 163         return omap2_ctrl_base;
 164 }
 165
 166 u8 omap_ctrl_readb(u16 offset)
 167 {
 168         return __raw_readb(OMAP_CTRL_REGADDR(offset));
 169 }
 170
 171 u16 omap_ctrl_readw(u16 offset)
 172 {
 173         return __raw_readw(OMAP_CTRL_REGADDR(offset));
 174 }
 175
 176 u32 omap_ctrl_readl(u16 offset)
 177 {
 178         return __raw_readl(OMAP_CTRL_REGADDR(offset));
 179 }
 180
 181 void omap_ctrl_writeb(u8 val, u16 offset)
 182 {
 183         __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
 184 }
 185
 186 void omap_ctrl_writew(u16 val, u16 offset)
 187 {
 188         __raw_writew(val, OMAP_CTRL_REGADDR(offset));
 189 }
 190
 191 void omap_ctrl_writel(u32 val, u16 offset)
 192 {
 193         __raw_writel(val, OMAP_CTRL_REGADDR(offset));
 194 }
 195
 196 /*
 197  * On OMAP4 control pad are not addressable from control
 198  * core base. So the common omap_ctrl_read/write APIs breaks
 199  * Hence export separate APIs to manage the omap4 pad control
 200  * registers. This APIs will work only for OMAP4
 201  */
 202
 203 u32 omap4_ctrl_pad_readl(u16 offset)
 204 {
 205         return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
 206 }
 207
 208 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 209 {
 210         __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
 211 }
 212
 213 #ifdef CONFIG_ARCH_OMAP3
 214
 215 /**
 216  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 217  * @bootmode: 8-bit value to pass to some boot code
 218  *
 219  * Set the bootmode in the scratchpad RAM.  This is used after the
 220  * system restarts.  Not sure what actually uses this - it may be the
 221  * bootloader, rather than the boot ROM - contrary to the preserved
 222  * comment below.  No return value.
 223  */
 224 void omap3_ctrl_write_boot_mode(u8 bootmode)
 225 {
 226         u32 l;
 227
 228         l = ('B' << 24) | ('M' << 16) | bootmode;
 229
 230         /*
 231          * Reserve the first word in scratchpad for communicating
 232          * with the boot ROM. A pointer to a data structure
 233          * describing the boot process can be stored there,
 234          * cf. OMAP34xx TRM, Initialization / Software Booting
 235          * Configuration.
 236          *
 237          * XXX This should use some omap_ctrl_writel()-type function
 238          */
 239         __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 240 }
 241
 242 #endif
 243
 244 /**
 245  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 246  * @bootaddr: physical address of the boot loader
 247  *
 248  * Set boot address for the boot loader of a supported processor
 249  * when a power ON sequence occurs.
 250  */
 251 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 252 {
 253         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 254                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 255                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 256                      0;
 257
 258         if (!offset) {
 259                 pr_err("%s: unsupported omap type\n", __func__);
 260                 return;
 261         }
 262
 263         omap_ctrl_writel(bootaddr, offset);
 264 }
 265
 266 /**
 267  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 268  * @bootmode: 8-bit value to pass to some boot code
 269  *
 270  * Sets boot mode for the boot loader of a supported processor
 271  * when a power ON sequence occurs.
 272  */
 273 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 274 {
 275         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 276                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 277                      0;
 278
 279         if (!offset) {
 280                 pr_err("%s: unsupported omap type\n", __func__);
 281                 return;
 282         }
 283
 284         omap_ctrl_writel(bootmode, offset);
 285 }
 286
 287 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 288 /*
 289  * Clears the scratchpad contents in case of cold boot-
 290  * called during bootup
 291  */
 292 void omap3_clear_scratchpad_contents(void)
 293 {
 294         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 295         void __iomem *v_addr;
 296         u32 offset = 0;
 297         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 298         if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
 299             OMAP3430_GLOBAL_COLD_RST_MASK) {
 300                 for ( ; offset <= max_offset; offset += 0x4)
 301                         __raw_writel(0x0, (v_addr + offset));
 302                 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
 303                                            OMAP3430_GR_MOD,
 304                                            OMAP3_PRM_RSTST_OFFSET);
 305         }
 306 }
 307
 308 /* Populate the scratchpad structure with restore structure */
 309 void omap3_save_scratchpad_contents(void)
 310 {
 311         void  __iomem *scratchpad_address;
 312         u32 arm_context_addr;
 313         struct omap3_scratchpad scratchpad_contents;
 314         struct omap3_scratchpad_prcm_block prcm_block_contents;
 315         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 316
 317         /*
 318          * Populate the Scratchpad contents
 319          *
 320          * The "get_*restore_pointer" functions are used to provide a
 321          * physical restore address where the ROM code jumps while waking
 322          * up from MPU OFF/OSWR state.
 323          * The restore pointer is stored into the scratchpad.
 324          */
 325         scratchpad_contents.boot_config_ptr = 0x0;
 326         if (cpu_is_omap3630())
 327                 scratchpad_contents.public_restore_ptr =
 328                         virt_to_phys(omap3_restore_3630);
 329         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 330                                         omap_rev() != OMAP3430_REV_ES3_1)
 331                 scratchpad_contents.public_restore_ptr =
 332                         virt_to_phys(omap3_restore);
 333         else
 334                 scratchpad_contents.public_restore_ptr =
 335                         virt_to_phys(omap3_restore_es3);
 336
 337         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 338                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 339         else
 340                 scratchpad_contents.secure_ram_restore_ptr =
 341                         (u32) __pa(omap3_secure_ram_storage);
 342         scratchpad_contents.sdrc_module_semaphore = 0x0;
 343         scratchpad_contents.prcm_block_offset = 0x2C;
 344         scratchpad_contents.sdrc_block_offset = 0x64;
 345
 346         /* Populate the PRCM block contents */
 347         prcm_block_contents.prm_clksrc_ctrl =
 348                 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
 349                                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 350         prcm_block_contents.prm_clksel =
 351                 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
 352                                        OMAP3_PRM_CLKSEL_OFFSET);
 353         prcm_block_contents.cm_clksel_core =
 354                         omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
 355         prcm_block_contents.cm_clksel_wkup =
 356                         omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
 357         prcm_block_contents.cm_clken_pll =
 358                         omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 359         /*
 360          * As per erratum i671, ROM code does not respect the PER DPLL
 361          * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
 362          * Then,  in anycase, clear these bits to avoid extra latencies.
 363          */
 364         prcm_block_contents.cm_autoidle_pll =
 365                         omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
 366                         ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
 367         prcm_block_contents.cm_clksel1_pll =
 368                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 369         prcm_block_contents.cm_clksel2_pll =
 370                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
 371         prcm_block_contents.cm_clksel3_pll =
 372                         omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
 373         prcm_block_contents.cm_clken_pll_mpu =
 374                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
 375         prcm_block_contents.cm_autoidle_pll_mpu =
 376                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 377         prcm_block_contents.cm_clksel1_pll_mpu =
 378                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
 379         prcm_block_contents.cm_clksel2_pll_mpu =
 380                         omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 381         prcm_block_contents.prcm_block_size = 0x0;
 382
 383         /* Populate the SDRC block contents */
 384         sdrc_block_contents.sysconfig =
 385                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 386         sdrc_block_contents.cs_cfg =
 387                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 388         sdrc_block_contents.sharing =
 389                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 390         sdrc_block_contents.err_type =
 391                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 392         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 393         sdrc_block_contents.dll_b_ctrl = 0x0;
 394         /*
 395          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 396          * be programed to issue automatic self refresh on timeout
 397          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 398          */
 399         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 400                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 401                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 402                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 403                                 SDRC_POWER_CLKCTRL_MASK)) |
 404                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 405                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 406         else
 407                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 408
 409         sdrc_block_contents.cs_0 = 0x0;
 410         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 411         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 412         sdrc_block_contents.emr_1_0 = 0x0;
 413         sdrc_block_contents.emr_2_0 = 0x0;
 414         sdrc_block_contents.emr_3_0 = 0x0;
 415         sdrc_block_contents.actim_ctrla_0 =
 416                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 417         sdrc_block_contents.actim_ctrlb_0 =
 418                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 419         sdrc_block_contents.rfr_ctrl_0 =
 420                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 421         sdrc_block_contents.cs_1 = 0x0;
 422         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 423         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 424         sdrc_block_contents.emr_1_1 = 0x0;
 425         sdrc_block_contents.emr_2_1 = 0x0;
 426         sdrc_block_contents.emr_3_1 = 0x0;
 427         sdrc_block_contents.actim_ctrla_1 =
 428                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 429         sdrc_block_contents.actim_ctrlb_1 =
 430                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 431         sdrc_block_contents.rfr_ctrl_1 =
 432                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 433         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 434         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 435         sdrc_block_contents.flags = 0x0;
 436         sdrc_block_contents.block_size = 0x0;
 437
 438         arm_context_addr = virt_to_phys(omap3_arm_context);
 439
 440         /* Copy all the contents to the scratchpad location */
 441         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 442         memcpy_toio(scratchpad_address, &scratchpad_contents,
 443                  sizeof(scratchpad_contents));
 444         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 445         memcpy_toio(scratchpad_address +
 446                 scratchpad_contents.prcm_block_offset,
 447                 &prcm_block_contents, sizeof(prcm_block_contents));
 448         memcpy_toio(scratchpad_address +
 449                 scratchpad_contents.sdrc_block_offset,
 450                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 451         /*
 452          * Copies the address of the location in SDRAM where ARM
 453          * registers get saved during a MPU OFF transition.
 454          */
 455         memcpy_toio(scratchpad_address +
 456                 scratchpad_contents.sdrc_block_offset +
 457                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 458 }
 459
 460 void omap3_control_save_context(void)
 461 {
 462         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 463         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 464         control_context.mem_dftrw0 =
 465                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 466         control_context.mem_dftrw1 =
 467                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 468         control_context.msuspendmux_0 =
 469                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 470         control_context.msuspendmux_1 =
 471                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 472         control_context.msuspendmux_2 =
 473                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 474         control_context.msuspendmux_3 =
 475                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 476         control_context.msuspendmux_4 =
 477                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 478         control_context.msuspendmux_5 =
 479                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 480         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 481         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 482         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 483         control_context.iva2_bootaddr =
 484                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 485         control_context.iva2_bootmod =
 486                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 487         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 488         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 489         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 490         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 491         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 492         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 493         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 494         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 495         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 496         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 497         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 498         control_context.dss_dpll_spreading =
 499                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 500         control_context.core_dpll_spreading =
 501                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 502         control_context.per_dpll_spreading =
 503                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 504         control_context.usbhost_dpll_spreading =
 505                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 506         control_context.pbias_lite =
 507                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 508         control_context.temp_sensor =
 509                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 510         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 511         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 512         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 513         control_context.padconf_sys_nirq =
 514                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 515         return;
 516 }
 517
 518 void omap3_control_restore_context(void)
 519 {
 520         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 521         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 522         omap_ctrl_writel(control_context.mem_dftrw0,
 523                                         OMAP343X_CONTROL_MEM_DFTRW0);
 524         omap_ctrl_writel(control_context.mem_dftrw1,
 525                                         OMAP343X_CONTROL_MEM_DFTRW1);
 526         omap_ctrl_writel(control_context.msuspendmux_0,
 527                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 528         omap_ctrl_writel(control_context.msuspendmux_1,
 529                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 530         omap_ctrl_writel(control_context.msuspendmux_2,
 531                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 532         omap_ctrl_writel(control_context.msuspendmux_3,
 533                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 534         omap_ctrl_writel(control_context.msuspendmux_4,
 535                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 536         omap_ctrl_writel(control_context.msuspendmux_5,
 537                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 538         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 539         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 540         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 541         omap_ctrl_writel(control_context.iva2_bootaddr,
 542                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 543         omap_ctrl_writel(control_context.iva2_bootmod,
 544                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 545         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 546         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 547         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 548         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 549         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 550         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 551         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 552         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 553         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 554         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 555         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 556         omap_ctrl_writel(control_context.dss_dpll_spreading,
 557                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 558         omap_ctrl_writel(control_context.core_dpll_spreading,
 559                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 560         omap_ctrl_writel(control_context.per_dpll_spreading,
 561                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 562         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 563                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 564         omap_ctrl_writel(control_context.pbias_lite,
 565                                         OMAP343X_CONTROL_PBIAS_LITE);
 566         omap_ctrl_writel(control_context.temp_sensor,
 567                                         OMAP343X_CONTROL_TEMP_SENSOR);
 568         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 569         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 570         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 571         omap_ctrl_writel(control_context.padconf_sys_nirq,
 572                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 573         return;
 574 }
 575
 576 void omap3630_ctrl_disable_rta(void)
 577 {
 578         if (!cpu_is_omap3630())
 579                 return;
 580         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 581 }
 582
 583 /**
 584  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 585  *
 586  * Tell the SCM to start saving the padconf registers, then wait for
 587  * the process to complete.  Returns 0 unconditionally, although it
 588  * should also eventually be able to return -ETIMEDOUT, if the save
 589  * does not complete.
 590  *
 591  * XXX This function is missing a timeout.  What should it be?
 592  */
 593 int omap3_ctrl_save_padconf(void)
 594 {
 595         u32 cpo;
 596
 597         /* Save the padconf registers */
 598         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 599         cpo |= START_PADCONF_SAVE;
 600         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 601
 602         /* wait for the save to complete */
 603         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 604                  & PADCONF_SAVE_DONE))
 605                 udelay(1);
 606
 607         return 0;
 608 }
 609
 610 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */