arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <plat-omap/dma-omap.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/iommu.h>
  33
  34 #include "../plat-omap/common.h"
  35
  36 #include "omap_hwmod.h"
  37 #include "omap_hwmod_common_data.h"
  38 #include "cm1_44xx.h"
  39 #include "cm2_44xx.h"
  40 #include "prm44xx.h"
  41 #include "prm-regbits-44xx.h"
  42 #include "i2c.h"
  43 #include "mmc.h"
  44 #include "wd_timer.h"
  45
  46 /* Base offset for all OMAP4 interrupts external to MPUSS */
  47 #define OMAP44XX_IRQ_GIC_START  32
  48
  49 /* Base offset for all OMAP4 dma requests */
  50 #define OMAP44XX_DMA_REQ_START  1
  51
  52 /*
  53  * IP blocks
  54  */
  55
  56 /*
  57  * 'c2c_target_fw' class
  58  * instance(s): c2c_target_fw
  59  */
  60 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  61         .name   = "c2c_target_fw",
  62 };
  63
  64 /* c2c_target_fw */
  65 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  66         .name           = "c2c_target_fw",
  67         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  68         .clkdm_name     = "d2d_clkdm",
  69         .prcm = {
  70                 .omap4 = {
  71                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  72                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  73                 },
  74         },
  75 };
  76
  77 /*
  78  * 'dmm' class
  79  * instance(s): dmm
  80  */
  81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  82         .name   = "dmm",
  83 };
  84
  85 /* dmm */
  86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  88         { .irq = -1 }
  89 };
  90
  91 static struct omap_hwmod omap44xx_dmm_hwmod = {
  92         .name           = "dmm",
  93         .class          = &omap44xx_dmm_hwmod_class,
  94         .clkdm_name     = "l3_emif_clkdm",
  95         .mpu_irqs       = omap44xx_dmm_irqs,
  96         .prcm = {
  97                 .omap4 = {
  98                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  99                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 100                 },
 101         },
 102 };
 103
 104 /*
 105  * 'emif_fw' class
 106  * instance(s): emif_fw
 107  */
 108 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 109         .name   = "emif_fw",
 110 };
 111
 112 /* emif_fw */
 113 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 114         .name           = "emif_fw",
 115         .class          = &omap44xx_emif_fw_hwmod_class,
 116         .clkdm_name     = "l3_emif_clkdm",
 117         .prcm = {
 118                 .omap4 = {
 119                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 120                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 121                 },
 122         },
 123 };
 124
 125 /*
 126  * 'l3' class
 127  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 128  */
 129 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 130         .name   = "l3",
 131 };
 132
 133 /* l3_instr */
 134 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 135         .name           = "l3_instr",
 136         .class          = &omap44xx_l3_hwmod_class,
 137         .clkdm_name     = "l3_instr_clkdm",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 141                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 142                         .modulemode   = MODULEMODE_HWCTRL,
 143                 },
 144         },
 145 };
 146
 147 /* l3_main_1 */
 148 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 149         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 150         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 151         { .irq = -1 }
 152 };
 153
 154 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 155         .name           = "l3_main_1",
 156         .class          = &omap44xx_l3_hwmod_class,
 157         .clkdm_name     = "l3_1_clkdm",
 158         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 159         .prcm = {
 160                 .omap4 = {
 161                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 162                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 163                 },
 164         },
 165 };
 166
 167 /* l3_main_2 */
 168 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 169         .name           = "l3_main_2",
 170         .class          = &omap44xx_l3_hwmod_class,
 171         .clkdm_name     = "l3_2_clkdm",
 172         .prcm = {
 173                 .omap4 = {
 174                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 175                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 176                 },
 177         },
 178 };
 179
 180 /* l3_main_3 */
 181 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 182         .name           = "l3_main_3",
 183         .class          = &omap44xx_l3_hwmod_class,
 184         .clkdm_name     = "l3_instr_clkdm",
 185         .prcm = {
 186                 .omap4 = {
 187                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 188                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 189                         .modulemode   = MODULEMODE_HWCTRL,
 190                 },
 191         },
 192 };
 193
 194 /*
 195  * 'l4' class
 196  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 197  */
 198 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 199         .name   = "l4",
 200 };
 201
 202 /* l4_abe */
 203 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 204         .name           = "l4_abe",
 205         .class          = &omap44xx_l4_hwmod_class,
 206         .clkdm_name     = "abe_clkdm",
 207         .prcm = {
 208                 .omap4 = {
 209                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 210                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 211                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 212                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 213                 },
 214         },
 215 };
 216
 217 /* l4_cfg */
 218 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 219         .name           = "l4_cfg",
 220         .class          = &omap44xx_l4_hwmod_class,
 221         .clkdm_name     = "l4_cfg_clkdm",
 222         .prcm = {
 223                 .omap4 = {
 224                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 225                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 226                 },
 227         },
 228 };
 229
 230 /* l4_per */
 231 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 232         .name           = "l4_per",
 233         .class          = &omap44xx_l4_hwmod_class,
 234         .clkdm_name     = "l4_per_clkdm",
 235         .prcm = {
 236                 .omap4 = {
 237                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 238                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 239                 },
 240         },
 241 };
 242
 243 /* l4_wkup */
 244 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 245         .name           = "l4_wkup",
 246         .class          = &omap44xx_l4_hwmod_class,
 247         .clkdm_name     = "l4_wkup_clkdm",
 248         .prcm = {
 249                 .omap4 = {
 250                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 251                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 252                 },
 253         },
 254 };
 255
 256 /*
 257  * 'mpu_bus' class
 258  * instance(s): mpu_private
 259  */
 260 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 261         .name   = "mpu_bus",
 262 };
 263
 264 /* mpu_private */
 265 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 266         .name           = "mpu_private",
 267         .class          = &omap44xx_mpu_bus_hwmod_class,
 268         .clkdm_name     = "mpuss_clkdm",
 269         .prcm = {
 270                 .omap4 = {
 271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'ocp_wp_noc' class
 278  * instance(s): ocp_wp_noc
 279  */
 280 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 281         .name   = "ocp_wp_noc",
 282 };
 283
 284 /* ocp_wp_noc */
 285 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 286         .name           = "ocp_wp_noc",
 287         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 288         .clkdm_name     = "l3_instr_clkdm",
 289         .prcm = {
 290                 .omap4 = {
 291                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 292                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 293                         .modulemode   = MODULEMODE_HWCTRL,
 294                 },
 295         },
 296 };
 297
 298 /*
 299  * Modules omap_hwmod structures
 300  *
 301  * The following IPs are excluded for the moment because:
 302  * - They do not need an explicit SW control using omap_hwmod API.
 303  * - They still need to be validated with the driver
 304  *   properly adapted to omap_hwmod / omap_device
 305  *
 306  * usim
 307  */
 308
 309 /*
 310  * 'aess' class
 311  * audio engine sub system
 312  */
 313
 314 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 315         .rev_offs       = 0x0000,
 316         .sysc_offs      = 0x0010,
 317         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 318         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 319                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 320                            MSTANDBY_SMART_WKUP),
 321         .sysc_fields    = &omap_hwmod_sysc_type2,
 322 };
 323
 324 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 325         .name   = "aess",
 326         .sysc   = &omap44xx_aess_sysc,
 327 };
 328
 329 /* aess */
 330 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 331         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 332         { .irq = -1 }
 333 };
 334
 335 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 336         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 342         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 343         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 344         { .dma_req = -1 }
 345 };
 346
 347 static struct omap_hwmod omap44xx_aess_hwmod = {
 348         .name           = "aess",
 349         .class          = &omap44xx_aess_hwmod_class,
 350         .clkdm_name     = "abe_clkdm",
 351         .mpu_irqs       = omap44xx_aess_irqs,
 352         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 353         .main_clk       = "aess_fck",
 354         .prcm = {
 355                 .omap4 = {
 356                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 357                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 358                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 359                         .modulemode   = MODULEMODE_SWCTRL,
 360                 },
 361         },
 362 };
 363
 364 /*
 365  * 'c2c' class
 366  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 367  * soc
 368  */
 369
 370 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 371         .name   = "c2c",
 372 };
 373
 374 /* c2c */
 375 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 376         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 377         { .irq = -1 }
 378 };
 379
 380 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 381         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 382         { .dma_req = -1 }
 383 };
 384
 385 static struct omap_hwmod omap44xx_c2c_hwmod = {
 386         .name           = "c2c",
 387         .class          = &omap44xx_c2c_hwmod_class,
 388         .clkdm_name     = "d2d_clkdm",
 389         .mpu_irqs       = omap44xx_c2c_irqs,
 390         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 391         .prcm = {
 392                 .omap4 = {
 393                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 394                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 395                 },
 396         },
 397 };
 398
 399 /*
 400  * 'counter' class
 401  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 402  */
 403
 404 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 405         .rev_offs       = 0x0000,
 406         .sysc_offs      = 0x0004,
 407         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 409         .sysc_fields    = &omap_hwmod_sysc_type1,
 410 };
 411
 412 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 413         .name   = "counter",
 414         .sysc   = &omap44xx_counter_sysc,
 415 };
 416
 417 /* counter_32k */
 418 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 419         .name           = "counter_32k",
 420         .class          = &omap44xx_counter_hwmod_class,
 421         .clkdm_name     = "l4_wkup_clkdm",
 422         .flags          = HWMOD_SWSUP_SIDLE,
 423         .main_clk       = "sys_32k_ck",
 424         .prcm = {
 425                 .omap4 = {
 426                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 427                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 428                 },
 429         },
 430 };
 431
 432 /*
 433  * 'ctrl_module' class
 434  * attila core control module + core pad control module + wkup pad control
 435  * module + attila wkup control module
 436  */
 437
 438 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 439         .rev_offs       = 0x0000,
 440         .sysc_offs      = 0x0010,
 441         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 442         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 443                            SIDLE_SMART_WKUP),
 444         .sysc_fields    = &omap_hwmod_sysc_type2,
 445 };
 446
 447 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 448         .name   = "ctrl_module",
 449         .sysc   = &omap44xx_ctrl_module_sysc,
 450 };
 451
 452 /* ctrl_module_core */
 453 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 454         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 455         { .irq = -1 }
 456 };
 457
 458 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 459         .name           = "ctrl_module_core",
 460         .class          = &omap44xx_ctrl_module_hwmod_class,
 461         .clkdm_name     = "l4_cfg_clkdm",
 462         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 463         .prcm = {
 464                 .omap4 = {
 465                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 466                 },
 467         },
 468 };
 469
 470 /* ctrl_module_pad_core */
 471 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 472         .name           = "ctrl_module_pad_core",
 473         .class          = &omap44xx_ctrl_module_hwmod_class,
 474         .clkdm_name     = "l4_cfg_clkdm",
 475         .prcm = {
 476                 .omap4 = {
 477                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 478                 },
 479         },
 480 };
 481
 482 /* ctrl_module_wkup */
 483 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 484         .name           = "ctrl_module_wkup",
 485         .class          = &omap44xx_ctrl_module_hwmod_class,
 486         .clkdm_name     = "l4_wkup_clkdm",
 487         .prcm = {
 488                 .omap4 = {
 489                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 490                 },
 491         },
 492 };
 493
 494 /* ctrl_module_pad_wkup */
 495 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 496         .name           = "ctrl_module_pad_wkup",
 497         .class          = &omap44xx_ctrl_module_hwmod_class,
 498         .clkdm_name     = "l4_wkup_clkdm",
 499         .prcm = {
 500                 .omap4 = {
 501                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 502                 },
 503         },
 504 };
 505
 506 /*
 507  * 'debugss' class
 508  * debug and emulation sub system
 509  */
 510
 511 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 512         .name   = "debugss",
 513 };
 514
 515 /* debugss */
 516 static struct omap_hwmod omap44xx_debugss_hwmod = {
 517         .name           = "debugss",
 518         .class          = &omap44xx_debugss_hwmod_class,
 519         .clkdm_name     = "emu_sys_clkdm",
 520         .main_clk       = "trace_clk_div_ck",
 521         .prcm = {
 522                 .omap4 = {
 523                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 524                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 525                 },
 526         },
 527 };
 528
 529 /*
 530  * 'dma' class
 531  * dma controller for data exchange between memory to memory (i.e. internal or
 532  * external memory) and gp peripherals to memory or memory to gp peripherals
 533  */
 534
 535 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 536         .rev_offs       = 0x0000,
 537         .sysc_offs      = 0x002c,
 538         .syss_offs      = 0x0028,
 539         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 540                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 541                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 542                            SYSS_HAS_RESET_STATUS),
 543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 544                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 545         .sysc_fields    = &omap_hwmod_sysc_type1,
 546 };
 547
 548 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 549         .name   = "dma",
 550         .sysc   = &omap44xx_dma_sysc,
 551 };
 552
 553 /* dma dev_attr */
 554 static struct omap_dma_dev_attr dma_dev_attr = {
 555         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 556                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 557         .lch_count      = 32,
 558 };
 559
 560 /* dma_system */
 561 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 562         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 564         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 565         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 566         { .irq = -1 }
 567 };
 568
 569 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 570         .name           = "dma_system",
 571         .class          = &omap44xx_dma_hwmod_class,
 572         .clkdm_name     = "l3_dma_clkdm",
 573         .mpu_irqs       = omap44xx_dma_system_irqs,
 574         .main_clk       = "l3_div_ck",
 575         .prcm = {
 576                 .omap4 = {
 577                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 578                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 579                 },
 580         },
 581         .dev_attr       = &dma_dev_attr,
 582 };
 583
 584 /*
 585  * 'dmic' class
 586  * digital microphone controller
 587  */
 588
 589 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 590         .rev_offs       = 0x0000,
 591         .sysc_offs      = 0x0010,
 592         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 595                            SIDLE_SMART_WKUP),
 596         .sysc_fields    = &omap_hwmod_sysc_type2,
 597 };
 598
 599 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 600         .name   = "dmic",
 601         .sysc   = &omap44xx_dmic_sysc,
 602 };
 603
 604 /* dmic */
 605 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 606         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 607         { .irq = -1 }
 608 };
 609
 610 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 611         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 612         { .dma_req = -1 }
 613 };
 614
 615 static struct omap_hwmod omap44xx_dmic_hwmod = {
 616         .name           = "dmic",
 617         .class          = &omap44xx_dmic_hwmod_class,
 618         .clkdm_name     = "abe_clkdm",
 619         .mpu_irqs       = omap44xx_dmic_irqs,
 620         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 621         .main_clk       = "dmic_fck",
 622         .prcm = {
 623                 .omap4 = {
 624                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 625                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 626                         .modulemode   = MODULEMODE_SWCTRL,
 627                 },
 628         },
 629 };
 630
 631 /*
 632  * 'dsp' class
 633  * dsp sub-system
 634  */
 635
 636 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 637         .name   = "dsp",
 638 };
 639
 640 /* dsp */
 641 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 642         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 643         { .irq = -1 }
 644 };
 645
 646 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 647         { .name = "dsp", .rst_shift = 0 },
 648 };
 649
 650 static struct omap_hwmod omap44xx_dsp_hwmod = {
 651         .name           = "dsp",
 652         .class          = &omap44xx_dsp_hwmod_class,
 653         .clkdm_name     = "tesla_clkdm",
 654         .mpu_irqs       = omap44xx_dsp_irqs,
 655         .rst_lines      = omap44xx_dsp_resets,
 656         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 657         .main_clk       = "dsp_fck",
 658         .prcm = {
 659                 .omap4 = {
 660                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 661                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 662                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 663                         .modulemode   = MODULEMODE_HWCTRL,
 664                 },
 665         },
 666 };
 667
 668 /*
 669  * 'dss' class
 670  * display sub-system
 671  */
 672
 673 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 674         .rev_offs       = 0x0000,
 675         .syss_offs      = 0x0014,
 676         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 677 };
 678
 679 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 680         .name   = "dss",
 681         .sysc   = &omap44xx_dss_sysc,
 682         .reset  = omap_dss_reset,
 683 };
 684
 685 /* dss */
 686 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 687         { .role = "sys_clk", .clk = "dss_sys_clk" },
 688         { .role = "tv_clk", .clk = "dss_tv_clk" },
 689         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 690 };
 691
 692 static struct omap_hwmod omap44xx_dss_hwmod = {
 693         .name           = "dss_core",
 694         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 695         .class          = &omap44xx_dss_hwmod_class,
 696         .clkdm_name     = "l3_dss_clkdm",
 697         .main_clk       = "dss_dss_clk",
 698         .prcm = {
 699                 .omap4 = {
 700                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 701                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 702                 },
 703         },
 704         .opt_clks       = dss_opt_clks,
 705         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 706 };
 707
 708 /*
 709  * 'dispc' class
 710  * display controller
 711  */
 712
 713 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 714         .rev_offs       = 0x0000,
 715         .sysc_offs      = 0x0010,
 716         .syss_offs      = 0x0014,
 717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 718                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 719                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 720                            SYSS_HAS_RESET_STATUS),
 721         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 722                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 723         .sysc_fields    = &omap_hwmod_sysc_type1,
 724 };
 725
 726 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 727         .name   = "dispc",
 728         .sysc   = &omap44xx_dispc_sysc,
 729 };
 730
 731 /* dss_dispc */
 732 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 733         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 734         { .irq = -1 }
 735 };
 736
 737 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 738         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 739         { .dma_req = -1 }
 740 };
 741
 742 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 743         .manager_count          = 3,
 744         .has_framedonetv_irq    = 1
 745 };
 746
 747 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 748         .name           = "dss_dispc",
 749         .class          = &omap44xx_dispc_hwmod_class,
 750         .clkdm_name     = "l3_dss_clkdm",
 751         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 752         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 753         .main_clk       = "dss_dss_clk",
 754         .prcm = {
 755                 .omap4 = {
 756                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 757                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 758                 },
 759         },
 760         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 761 };
 762
 763 /*
 764  * 'dsi' class
 765  * display serial interface controller
 766  */
 767
 768 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 769         .rev_offs       = 0x0000,
 770         .sysc_offs      = 0x0010,
 771         .syss_offs      = 0x0014,
 772         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 773                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 774                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 775         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 776         .sysc_fields    = &omap_hwmod_sysc_type1,
 777 };
 778
 779 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 780         .name   = "dsi",
 781         .sysc   = &omap44xx_dsi_sysc,
 782 };
 783
 784 /* dss_dsi1 */
 785 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 786         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 787         { .irq = -1 }
 788 };
 789
 790 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 791         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 792         { .dma_req = -1 }
 793 };
 794
 795 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 796         { .role = "sys_clk", .clk = "dss_sys_clk" },
 797 };
 798
 799 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 800         .name           = "dss_dsi1",
 801         .class          = &omap44xx_dsi_hwmod_class,
 802         .clkdm_name     = "l3_dss_clkdm",
 803         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 804         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 805         .main_clk       = "dss_dss_clk",
 806         .prcm = {
 807                 .omap4 = {
 808                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 809                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 810                 },
 811         },
 812         .opt_clks       = dss_dsi1_opt_clks,
 813         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 814 };
 815
 816 /* dss_dsi2 */
 817 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 818         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 819         { .irq = -1 }
 820 };
 821
 822 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 823         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 824         { .dma_req = -1 }
 825 };
 826
 827 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 828         { .role = "sys_clk", .clk = "dss_sys_clk" },
 829 };
 830
 831 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 832         .name           = "dss_dsi2",
 833         .class          = &omap44xx_dsi_hwmod_class,
 834         .clkdm_name     = "l3_dss_clkdm",
 835         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 836         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 837         .main_clk       = "dss_dss_clk",
 838         .prcm = {
 839                 .omap4 = {
 840                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 841                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 842                 },
 843         },
 844         .opt_clks       = dss_dsi2_opt_clks,
 845         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 846 };
 847
 848 /*
 849  * 'hdmi' class
 850  * hdmi controller
 851  */
 852
 853 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 854         .rev_offs       = 0x0000,
 855         .sysc_offs      = 0x0010,
 856         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 857                            SYSC_HAS_SOFTRESET),
 858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 859                            SIDLE_SMART_WKUP),
 860         .sysc_fields    = &omap_hwmod_sysc_type2,
 861 };
 862
 863 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 864         .name   = "hdmi",
 865         .sysc   = &omap44xx_hdmi_sysc,
 866 };
 867
 868 /* dss_hdmi */
 869 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 870         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 871         { .irq = -1 }
 872 };
 873
 874 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 875         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 876         { .dma_req = -1 }
 877 };
 878
 879 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 880         { .role = "sys_clk", .clk = "dss_sys_clk" },
 881 };
 882
 883 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 884         .name           = "dss_hdmi",
 885         .class          = &omap44xx_hdmi_hwmod_class,
 886         .clkdm_name     = "l3_dss_clkdm",
 887         /*
 888          * HDMI audio requires to use no-idle mode. Hence,
 889          * set idle mode by software.
 890          */
 891         .flags          = HWMOD_SWSUP_SIDLE,
 892         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 893         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 894         .main_clk       = "dss_48mhz_clk",
 895         .prcm = {
 896                 .omap4 = {
 897                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 898                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 899                 },
 900         },
 901         .opt_clks       = dss_hdmi_opt_clks,
 902         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 903 };
 904
 905 /*
 906  * 'rfbi' class
 907  * remote frame buffer interface
 908  */
 909
 910 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 911         .rev_offs       = 0x0000,
 912         .sysc_offs      = 0x0010,
 913         .syss_offs      = 0x0014,
 914         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 915                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 916         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 917         .sysc_fields    = &omap_hwmod_sysc_type1,
 918 };
 919
 920 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 921         .name   = "rfbi",
 922         .sysc   = &omap44xx_rfbi_sysc,
 923 };
 924
 925 /* dss_rfbi */
 926 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 927         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 928         { .dma_req = -1 }
 929 };
 930
 931 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 932         { .role = "ick", .clk = "dss_fck" },
 933 };
 934
 935 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 936         .name           = "dss_rfbi",
 937         .class          = &omap44xx_rfbi_hwmod_class,
 938         .clkdm_name     = "l3_dss_clkdm",
 939         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 940         .main_clk       = "dss_dss_clk",
 941         .prcm = {
 942                 .omap4 = {
 943                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 944                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 945                 },
 946         },
 947         .opt_clks       = dss_rfbi_opt_clks,
 948         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 949 };
 950
 951 /*
 952  * 'venc' class
 953  * video encoder
 954  */
 955
 956 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 957         .name   = "venc",
 958 };
 959
 960 /* dss_venc */
 961 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 962         .name           = "dss_venc",
 963         .class          = &omap44xx_venc_hwmod_class,
 964         .clkdm_name     = "l3_dss_clkdm",
 965         .main_clk       = "dss_tv_clk",
 966         .prcm = {
 967                 .omap4 = {
 968                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 969                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 970                 },
 971         },
 972 };
 973
 974 /*
 975  * 'elm' class
 976  * bch error location module
 977  */
 978
 979 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 980         .rev_offs       = 0x0000,
 981         .sysc_offs      = 0x0010,
 982         .syss_offs      = 0x0014,
 983         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 984                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 985                            SYSS_HAS_RESET_STATUS),
 986         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 987         .sysc_fields    = &omap_hwmod_sysc_type1,
 988 };
 989
 990 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 991         .name   = "elm",
 992         .sysc   = &omap44xx_elm_sysc,
 993 };
 994
 995 /* elm */
 996 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 997         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 998         { .irq = -1 }
 999 };
1000
1001 static struct omap_hwmod omap44xx_elm_hwmod = {
1002         .name           = "elm",
1003         .class          = &omap44xx_elm_hwmod_class,
1004         .clkdm_name     = "l4_per_clkdm",
1005         .mpu_irqs       = omap44xx_elm_irqs,
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1010                 },
1011         },
1012 };
1013
1014 /*
1015  * 'emif' class
1016  * external memory interface no1
1017  */
1018
1019 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1020         .rev_offs       = 0x0000,
1021 };
1022
1023 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1024         .name   = "emif",
1025         .sysc   = &omap44xx_emif_sysc,
1026 };
1027
1028 /* emif1 */
1029 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1030         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1031         { .irq = -1 }
1032 };
1033
1034 static struct omap_hwmod omap44xx_emif1_hwmod = {
1035         .name           = "emif1",
1036         .class          = &omap44xx_emif_hwmod_class,
1037         .clkdm_name     = "l3_emif_clkdm",
1038         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1039         .mpu_irqs       = omap44xx_emif1_irqs,
1040         .main_clk       = "ddrphy_ck",
1041         .prcm = {
1042                 .omap4 = {
1043                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1044                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1045                         .modulemode   = MODULEMODE_HWCTRL,
1046                 },
1047         },
1048 };
1049
1050 /* emif2 */
1051 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1052         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1053         { .irq = -1 }
1054 };
1055
1056 static struct omap_hwmod omap44xx_emif2_hwmod = {
1057         .name           = "emif2",
1058         .class          = &omap44xx_emif_hwmod_class,
1059         .clkdm_name     = "l3_emif_clkdm",
1060         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1061         .mpu_irqs       = omap44xx_emif2_irqs,
1062         .main_clk       = "ddrphy_ck",
1063         .prcm = {
1064                 .omap4 = {
1065                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1066                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1067                         .modulemode   = MODULEMODE_HWCTRL,
1068                 },
1069         },
1070 };
1071
1072 /*
1073  * 'fdif' class
1074  * face detection hw accelerator module
1075  */
1076
1077 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1078         .rev_offs       = 0x0000,
1079         .sysc_offs      = 0x0010,
1080         /*
1081          * FDIF needs 100 OCP clk cycles delay after a softreset before
1082          * accessing sysconfig again.
1083          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1084          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1085          *
1086          * TODO: Indicate errata when available.
1087          */
1088         .srst_udelay    = 2,
1089         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1090                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1091         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1092                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1093         .sysc_fields    = &omap_hwmod_sysc_type2,
1094 };
1095
1096 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1097         .name   = "fdif",
1098         .sysc   = &omap44xx_fdif_sysc,
1099 };
1100
1101 /* fdif */
1102 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1103         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1104         { .irq = -1 }
1105 };
1106
1107 static struct omap_hwmod omap44xx_fdif_hwmod = {
1108         .name           = "fdif",
1109         .class          = &omap44xx_fdif_hwmod_class,
1110         .clkdm_name     = "iss_clkdm",
1111         .mpu_irqs       = omap44xx_fdif_irqs,
1112         .main_clk       = "fdif_fck",
1113         .prcm = {
1114                 .omap4 = {
1115                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1116                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1117                         .modulemode   = MODULEMODE_SWCTRL,
1118                 },
1119         },
1120 };
1121
1122 /*
1123  * 'gpio' class
1124  * general purpose io module
1125  */
1126
1127 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1128         .rev_offs       = 0x0000,
1129         .sysc_offs      = 0x0010,
1130         .syss_offs      = 0x0114,
1131         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1132                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1133                            SYSS_HAS_RESET_STATUS),
1134         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1135                            SIDLE_SMART_WKUP),
1136         .sysc_fields    = &omap_hwmod_sysc_type1,
1137 };
1138
1139 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1140         .name   = "gpio",
1141         .sysc   = &omap44xx_gpio_sysc,
1142         .rev    = 2,
1143 };
1144
1145 /* gpio dev_attr */
1146 static struct omap_gpio_dev_attr gpio_dev_attr = {
1147         .bank_width     = 32,
1148         .dbck_flag      = true,
1149 };
1150
1151 /* gpio1 */
1152 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1153         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1154         { .irq = -1 }
1155 };
1156
1157 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1158         { .role = "dbclk", .clk = "gpio1_dbclk" },
1159 };
1160
1161 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1162         .name           = "gpio1",
1163         .class          = &omap44xx_gpio_hwmod_class,
1164         .clkdm_name     = "l4_wkup_clkdm",
1165         .mpu_irqs       = omap44xx_gpio1_irqs,
1166         .main_clk       = "gpio1_ick",
1167         .prcm = {
1168                 .omap4 = {
1169                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1170                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1171                         .modulemode   = MODULEMODE_HWCTRL,
1172                 },
1173         },
1174         .opt_clks       = gpio1_opt_clks,
1175         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1176         .dev_attr       = &gpio_dev_attr,
1177 };
1178
1179 /* gpio2 */
1180 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1181         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1182         { .irq = -1 }
1183 };
1184
1185 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1186         { .role = "dbclk", .clk = "gpio2_dbclk" },
1187 };
1188
1189 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1190         .name           = "gpio2",
1191         .class          = &omap44xx_gpio_hwmod_class,
1192         .clkdm_name     = "l4_per_clkdm",
1193         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1194         .mpu_irqs       = omap44xx_gpio2_irqs,
1195         .main_clk       = "gpio2_ick",
1196         .prcm = {
1197                 .omap4 = {
1198                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1199                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1200                         .modulemode   = MODULEMODE_HWCTRL,
1201                 },
1202         },
1203         .opt_clks       = gpio2_opt_clks,
1204         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1205         .dev_attr       = &gpio_dev_attr,
1206 };
1207
1208 /* gpio3 */
1209 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1210         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1211         { .irq = -1 }
1212 };
1213
1214 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1215         { .role = "dbclk", .clk = "gpio3_dbclk" },
1216 };
1217
1218 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1219         .name           = "gpio3",
1220         .class          = &omap44xx_gpio_hwmod_class,
1221         .clkdm_name     = "l4_per_clkdm",
1222         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1223         .mpu_irqs       = omap44xx_gpio3_irqs,
1224         .main_clk       = "gpio3_ick",
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1228                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1229                         .modulemode   = MODULEMODE_HWCTRL,
1230                 },
1231         },
1232         .opt_clks       = gpio3_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1234         .dev_attr       = &gpio_dev_attr,
1235 };
1236
1237 /* gpio4 */
1238 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1239         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1240         { .irq = -1 }
1241 };
1242
1243 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1244         { .role = "dbclk", .clk = "gpio4_dbclk" },
1245 };
1246
1247 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1248         .name           = "gpio4",
1249         .class          = &omap44xx_gpio_hwmod_class,
1250         .clkdm_name     = "l4_per_clkdm",
1251         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1252         .mpu_irqs       = omap44xx_gpio4_irqs,
1253         .main_clk       = "gpio4_ick",
1254         .prcm = {
1255                 .omap4 = {
1256                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1257                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1258                         .modulemode   = MODULEMODE_HWCTRL,
1259                 },
1260         },
1261         .opt_clks       = gpio4_opt_clks,
1262         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1263         .dev_attr       = &gpio_dev_attr,
1264 };
1265
1266 /* gpio5 */
1267 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1268         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1269         { .irq = -1 }
1270 };
1271
1272 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1273         { .role = "dbclk", .clk = "gpio5_dbclk" },
1274 };
1275
1276 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1277         .name           = "gpio5",
1278         .class          = &omap44xx_gpio_hwmod_class,
1279         .clkdm_name     = "l4_per_clkdm",
1280         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1281         .mpu_irqs       = omap44xx_gpio5_irqs,
1282         .main_clk       = "gpio5_ick",
1283         .prcm = {
1284                 .omap4 = {
1285                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1286                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1287                         .modulemode   = MODULEMODE_HWCTRL,
1288                 },
1289         },
1290         .opt_clks       = gpio5_opt_clks,
1291         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1292         .dev_attr       = &gpio_dev_attr,
1293 };
1294
1295 /* gpio6 */
1296 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1297         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1298         { .irq = -1 }
1299 };
1300
1301 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1302         { .role = "dbclk", .clk = "gpio6_dbclk" },
1303 };
1304
1305 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1306         .name           = "gpio6",
1307         .class          = &omap44xx_gpio_hwmod_class,
1308         .clkdm_name     = "l4_per_clkdm",
1309         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1310         .mpu_irqs       = omap44xx_gpio6_irqs,
1311         .main_clk       = "gpio6_ick",
1312         .prcm = {
1313                 .omap4 = {
1314                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1315                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1316                         .modulemode   = MODULEMODE_HWCTRL,
1317                 },
1318         },
1319         .opt_clks       = gpio6_opt_clks,
1320         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1321         .dev_attr       = &gpio_dev_attr,
1322 };
1323
1324 /*
1325  * 'gpmc' class
1326  * general purpose memory controller
1327  */
1328
1329 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1330         .rev_offs       = 0x0000,
1331         .sysc_offs      = 0x0010,
1332         .syss_offs      = 0x0014,
1333         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1334                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1335         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1336         .sysc_fields    = &omap_hwmod_sysc_type1,
1337 };
1338
1339 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1340         .name   = "gpmc",
1341         .sysc   = &omap44xx_gpmc_sysc,
1342 };
1343
1344 /* gpmc */
1345 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1346         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1347         { .irq = -1 }
1348 };
1349
1350 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1351         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1352         { .dma_req = -1 }
1353 };
1354
1355 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1356         .name           = "gpmc",
1357         .class          = &omap44xx_gpmc_hwmod_class,
1358         .clkdm_name     = "l3_2_clkdm",
1359         /*
1360          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1361          * block.  It is not being added due to any known bugs with
1362          * resetting the GPMC IP block, but rather because any timings
1363          * set by the bootloader are not being correctly programmed by
1364          * the kernel from the board file or DT data.
1365          * HWMOD_INIT_NO_RESET should be removed ASAP.
1366          */
1367         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1368         .mpu_irqs       = omap44xx_gpmc_irqs,
1369         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1370         .prcm = {
1371                 .omap4 = {
1372                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1373                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1374                         .modulemode   = MODULEMODE_HWCTRL,
1375                 },
1376         },
1377 };
1378
1379 /*
1380  * 'gpu' class
1381  * 2d/3d graphics accelerator
1382  */
1383
1384 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1385         .rev_offs       = 0x1fc00,
1386         .sysc_offs      = 0x1fc10,
1387         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1388         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1389                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1390                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1391         .sysc_fields    = &omap_hwmod_sysc_type2,
1392 };
1393
1394 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1395         .name   = "gpu",
1396         .sysc   = &omap44xx_gpu_sysc,
1397 };
1398
1399 /* gpu */
1400 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1401         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1402         { .irq = -1 }
1403 };
1404
1405 static struct omap_hwmod omap44xx_gpu_hwmod = {
1406         .name           = "gpu",
1407         .class          = &omap44xx_gpu_hwmod_class,
1408         .clkdm_name     = "l3_gfx_clkdm",
1409         .mpu_irqs       = omap44xx_gpu_irqs,
1410         .main_clk       = "gpu_fck",
1411         .prcm = {
1412                 .omap4 = {
1413                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1414                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1415                         .modulemode   = MODULEMODE_SWCTRL,
1416                 },
1417         },
1418 };
1419
1420 /*
1421  * 'hdq1w' class
1422  * hdq / 1-wire serial interface controller
1423  */
1424
1425 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1426         .rev_offs       = 0x0000,
1427         .sysc_offs      = 0x0014,
1428         .syss_offs      = 0x0018,
1429         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1430                            SYSS_HAS_RESET_STATUS),
1431         .sysc_fields    = &omap_hwmod_sysc_type1,
1432 };
1433
1434 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1435         .name   = "hdq1w",
1436         .sysc   = &omap44xx_hdq1w_sysc,
1437 };
1438
1439 /* hdq1w */
1440 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1441         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1442         { .irq = -1 }
1443 };
1444
1445 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1446         .name           = "hdq1w",
1447         .class          = &omap44xx_hdq1w_hwmod_class,
1448         .clkdm_name     = "l4_per_clkdm",
1449         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1450         .mpu_irqs       = omap44xx_hdq1w_irqs,
1451         .main_clk       = "hdq1w_fck",
1452         .prcm = {
1453                 .omap4 = {
1454                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1455                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1456                         .modulemode   = MODULEMODE_SWCTRL,
1457                 },
1458         },
1459 };
1460
1461 /*
1462  * 'hsi' class
1463  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1464  * serial if)
1465  */
1466
1467 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1468         .rev_offs       = 0x0000,
1469         .sysc_offs      = 0x0010,
1470         .syss_offs      = 0x0014,
1471         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1472                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1473                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1475                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1476                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1477         .sysc_fields    = &omap_hwmod_sysc_type1,
1478 };
1479
1480 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1481         .name   = "hsi",
1482         .sysc   = &omap44xx_hsi_sysc,
1483 };
1484
1485 /* hsi */
1486 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1487         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1488         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1489         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1490         { .irq = -1 }
1491 };
1492
1493 static struct omap_hwmod omap44xx_hsi_hwmod = {
1494         .name           = "hsi",
1495         .class          = &omap44xx_hsi_hwmod_class,
1496         .clkdm_name     = "l3_init_clkdm",
1497         .mpu_irqs       = omap44xx_hsi_irqs,
1498         .main_clk       = "hsi_fck",
1499         .prcm = {
1500                 .omap4 = {
1501                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1502                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1503                         .modulemode   = MODULEMODE_HWCTRL,
1504                 },
1505         },
1506 };
1507
1508 /*
1509  * 'i2c' class
1510  * multimaster high-speed i2c controller
1511  */
1512
1513 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1514         .sysc_offs      = 0x0010,
1515         .syss_offs      = 0x0090,
1516         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1517                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1518                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1519         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1520                            SIDLE_SMART_WKUP),
1521         .clockact       = CLOCKACT_TEST_ICLK,
1522         .sysc_fields    = &omap_hwmod_sysc_type1,
1523 };
1524
1525 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1526         .name   = "i2c",
1527         .sysc   = &omap44xx_i2c_sysc,
1528         .rev    = OMAP_I2C_IP_VERSION_2,
1529         .reset  = &omap_i2c_reset,
1530 };
1531
1532 static struct omap_i2c_dev_attr i2c_dev_attr = {
1533         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1534                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1535 };
1536
1537 /* i2c1 */
1538 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1539         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1540         { .irq = -1 }
1541 };
1542
1543 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1544         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1545         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1546         { .dma_req = -1 }
1547 };
1548
1549 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1550         .name           = "i2c1",
1551         .class          = &omap44xx_i2c_hwmod_class,
1552         .clkdm_name     = "l4_per_clkdm",
1553         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1554         .mpu_irqs       = omap44xx_i2c1_irqs,
1555         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1556         .main_clk       = "i2c1_fck",
1557         .prcm = {
1558                 .omap4 = {
1559                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1560                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1561                         .modulemode   = MODULEMODE_SWCTRL,
1562                 },
1563         },
1564         .dev_attr       = &i2c_dev_attr,
1565 };
1566
1567 /* i2c2 */
1568 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1569         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1570         { .irq = -1 }
1571 };
1572
1573 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1574         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1575         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1576         { .dma_req = -1 }
1577 };
1578
1579 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1580         .name           = "i2c2",
1581         .class          = &omap44xx_i2c_hwmod_class,
1582         .clkdm_name     = "l4_per_clkdm",
1583         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1584         .mpu_irqs       = omap44xx_i2c2_irqs,
1585         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1586         .main_clk       = "i2c2_fck",
1587         .prcm = {
1588                 .omap4 = {
1589                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1590                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1591                         .modulemode   = MODULEMODE_SWCTRL,
1592                 },
1593         },
1594         .dev_attr       = &i2c_dev_attr,
1595 };
1596
1597 /* i2c3 */
1598 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1599         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1600         { .irq = -1 }
1601 };
1602
1603 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1604         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1605         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1606         { .dma_req = -1 }
1607 };
1608
1609 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1610         .name           = "i2c3",
1611         .class          = &omap44xx_i2c_hwmod_class,
1612         .clkdm_name     = "l4_per_clkdm",
1613         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1614         .mpu_irqs       = omap44xx_i2c3_irqs,
1615         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1616         .main_clk       = "i2c3_fck",
1617         .prcm = {
1618                 .omap4 = {
1619                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1620                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1621                         .modulemode   = MODULEMODE_SWCTRL,
1622                 },
1623         },
1624         .dev_attr       = &i2c_dev_attr,
1625 };
1626
1627 /* i2c4 */
1628 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1629         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1630         { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1634         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1635         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1636         { .dma_req = -1 }
1637 };
1638
1639 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1640         .name           = "i2c4",
1641         .class          = &omap44xx_i2c_hwmod_class,
1642         .clkdm_name     = "l4_per_clkdm",
1643         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1644         .mpu_irqs       = omap44xx_i2c4_irqs,
1645         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1646         .main_clk       = "i2c4_fck",
1647         .prcm = {
1648                 .omap4 = {
1649                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1650                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1651                         .modulemode   = MODULEMODE_SWCTRL,
1652                 },
1653         },
1654         .dev_attr       = &i2c_dev_attr,
1655 };
1656
1657 /*
1658  * 'ipu' class
1659  * imaging processor unit
1660  */
1661
1662 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1663         .name   = "ipu",
1664 };
1665
1666 /* ipu */
1667 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1668         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1669         { .irq = -1 }
1670 };
1671
1672 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1673         { .name = "cpu0", .rst_shift = 0 },
1674         { .name = "cpu1", .rst_shift = 1 },
1675 };
1676
1677 static struct omap_hwmod omap44xx_ipu_hwmod = {
1678         .name           = "ipu",
1679         .class          = &omap44xx_ipu_hwmod_class,
1680         .clkdm_name     = "ducati_clkdm",
1681         .mpu_irqs       = omap44xx_ipu_irqs,
1682         .rst_lines      = omap44xx_ipu_resets,
1683         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1684         .main_clk       = "ipu_fck",
1685         .prcm = {
1686                 .omap4 = {
1687                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1688                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1689                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1690                         .modulemode   = MODULEMODE_HWCTRL,
1691                 },
1692         },
1693 };
1694
1695 /*
1696  * 'iss' class
1697  * external images sensor pixel data processor
1698  */
1699
1700 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1701         .rev_offs       = 0x0000,
1702         .sysc_offs      = 0x0010,
1703         /*
1704          * ISS needs 100 OCP clk cycles delay after a softreset before
1705          * accessing sysconfig again.
1706          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1707          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1708          *
1709          * TODO: Indicate errata when available.
1710          */
1711         .srst_udelay    = 2,
1712         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1713                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1714         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1715                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1716                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1717         .sysc_fields    = &omap_hwmod_sysc_type2,
1718 };
1719
1720 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1721         .name   = "iss",
1722         .sysc   = &omap44xx_iss_sysc,
1723 };
1724
1725 /* iss */
1726 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1727         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1728         { .irq = -1 }
1729 };
1730
1731 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1732         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1733         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1734         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1735         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1736         { .dma_req = -1 }
1737 };
1738
1739 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1740         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1741 };
1742
1743 static struct omap_hwmod omap44xx_iss_hwmod = {
1744         .name           = "iss",
1745         .class          = &omap44xx_iss_hwmod_class,
1746         .clkdm_name     = "iss_clkdm",
1747         .mpu_irqs       = omap44xx_iss_irqs,
1748         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1749         .main_clk       = "iss_fck",
1750         .prcm = {
1751                 .omap4 = {
1752                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1753                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1754                         .modulemode   = MODULEMODE_SWCTRL,
1755                 },
1756         },
1757         .opt_clks       = iss_opt_clks,
1758         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1759 };
1760
1761 /*
1762  * 'iva' class
1763  * multi-standard video encoder/decoder hardware accelerator
1764  */
1765
1766 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1767         .name   = "iva",
1768 };
1769
1770 /* iva */
1771 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1772         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1773         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1774         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1775         { .irq = -1 }
1776 };
1777
1778 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1779         { .name = "seq0", .rst_shift = 0 },
1780         { .name = "seq1", .rst_shift = 1 },
1781         { .name = "logic", .rst_shift = 2 },
1782 };
1783
1784 static struct omap_hwmod omap44xx_iva_hwmod = {
1785         .name           = "iva",
1786         .class          = &omap44xx_iva_hwmod_class,
1787         .clkdm_name     = "ivahd_clkdm",
1788         .mpu_irqs       = omap44xx_iva_irqs,
1789         .rst_lines      = omap44xx_iva_resets,
1790         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1791         .main_clk       = "iva_fck",
1792         .prcm = {
1793                 .omap4 = {
1794                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1795                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1796                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1797                         .modulemode   = MODULEMODE_HWCTRL,
1798                 },
1799         },
1800 };
1801
1802 /*
1803  * 'kbd' class
1804  * keyboard controller
1805  */
1806
1807 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1808         .rev_offs       = 0x0000,
1809         .sysc_offs      = 0x0010,
1810         .syss_offs      = 0x0014,
1811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1812                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1813                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1814                            SYSS_HAS_RESET_STATUS),
1815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1816         .sysc_fields    = &omap_hwmod_sysc_type1,
1817 };
1818
1819 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1820         .name   = "kbd",
1821         .sysc   = &omap44xx_kbd_sysc,
1822 };
1823
1824 /* kbd */
1825 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1826         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1827         { .irq = -1 }
1828 };
1829
1830 static struct omap_hwmod omap44xx_kbd_hwmod = {
1831         .name           = "kbd",
1832         .class          = &omap44xx_kbd_hwmod_class,
1833         .clkdm_name     = "l4_wkup_clkdm",
1834         .mpu_irqs       = omap44xx_kbd_irqs,
1835         .main_clk       = "kbd_fck",
1836         .prcm = {
1837                 .omap4 = {
1838                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1839                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1840                         .modulemode   = MODULEMODE_SWCTRL,
1841                 },
1842         },
1843 };
1844
1845 /*
1846  * 'mailbox' class
1847  * mailbox module allowing communication between the on-chip processors using a
1848  * queued mailbox-interrupt mechanism.
1849  */
1850
1851 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1852         .rev_offs       = 0x0000,
1853         .sysc_offs      = 0x0010,
1854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1855                            SYSC_HAS_SOFTRESET),
1856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1857         .sysc_fields    = &omap_hwmod_sysc_type2,
1858 };
1859
1860 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1861         .name   = "mailbox",
1862         .sysc   = &omap44xx_mailbox_sysc,
1863 };
1864
1865 /* mailbox */
1866 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1867         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1868         { .irq = -1 }
1869 };
1870
1871 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1872         .name           = "mailbox",
1873         .class          = &omap44xx_mailbox_hwmod_class,
1874         .clkdm_name     = "l4_cfg_clkdm",
1875         .mpu_irqs       = omap44xx_mailbox_irqs,
1876         .prcm = {
1877                 .omap4 = {
1878                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1879                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1880                 },
1881         },
1882 };
1883
1884 /*
1885  * 'mcasp' class
1886  * multi-channel audio serial port controller
1887  */
1888
1889 /* The IP is not compliant to type1 / type2 scheme */
1890 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1891         .sidle_shift    = 0,
1892 };
1893
1894 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1895         .sysc_offs      = 0x0004,
1896         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1897         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1898                            SIDLE_SMART_WKUP),
1899         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1900 };
1901
1902 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1903         .name   = "mcasp",
1904         .sysc   = &omap44xx_mcasp_sysc,
1905 };
1906
1907 /* mcasp */
1908 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1909         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1910         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1911         { .irq = -1 }
1912 };
1913
1914 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1915         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1916         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1917         { .dma_req = -1 }
1918 };
1919
1920 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1921         .name           = "mcasp",
1922         .class          = &omap44xx_mcasp_hwmod_class,
1923         .clkdm_name     = "abe_clkdm",
1924         .mpu_irqs       = omap44xx_mcasp_irqs,
1925         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1926         .main_clk       = "mcasp_fck",
1927         .prcm = {
1928                 .omap4 = {
1929                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1930                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1931                         .modulemode   = MODULEMODE_SWCTRL,
1932                 },
1933         },
1934 };
1935
1936 /*
1937  * 'mcbsp' class
1938  * multi channel buffered serial port controller
1939  */
1940
1941 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1942         .sysc_offs      = 0x008c,
1943         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1944                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1945         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1946         .sysc_fields    = &omap_hwmod_sysc_type1,
1947 };
1948
1949 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1950         .name   = "mcbsp",
1951         .sysc   = &omap44xx_mcbsp_sysc,
1952         .rev    = MCBSP_CONFIG_TYPE4,
1953 };
1954
1955 /* mcbsp1 */
1956 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1957         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1958         { .irq = -1 }
1959 };
1960
1961 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1962         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1963         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1964         { .dma_req = -1 }
1965 };
1966
1967 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1968         { .role = "pad_fck", .clk = "pad_clks_ck" },
1969         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1970 };
1971
1972 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1973         .name           = "mcbsp1",
1974         .class          = &omap44xx_mcbsp_hwmod_class,
1975         .clkdm_name     = "abe_clkdm",
1976         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1977         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1978         .main_clk       = "mcbsp1_fck",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1982                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1983                         .modulemode   = MODULEMODE_SWCTRL,
1984                 },
1985         },
1986         .opt_clks       = mcbsp1_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1988 };
1989
1990 /* mcbsp2 */
1991 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1992         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1993         { .irq = -1 }
1994 };
1995
1996 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1997         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1998         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1999         { .dma_req = -1 }
2000 };
2001
2002 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2003         { .role = "pad_fck", .clk = "pad_clks_ck" },
2004         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2005 };
2006
2007 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2008         .name           = "mcbsp2",
2009         .class          = &omap44xx_mcbsp_hwmod_class,
2010         .clkdm_name     = "abe_clkdm",
2011         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2012         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2013         .main_clk       = "mcbsp2_fck",
2014         .prcm = {
2015                 .omap4 = {
2016                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2017                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2018                         .modulemode   = MODULEMODE_SWCTRL,
2019                 },
2020         },
2021         .opt_clks       = mcbsp2_opt_clks,
2022         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2023 };
2024
2025 /* mcbsp3 */
2026 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2027         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2028         { .irq = -1 }
2029 };
2030
2031 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2032         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2033         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2034         { .dma_req = -1 }
2035 };
2036
2037 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2038         { .role = "pad_fck", .clk = "pad_clks_ck" },
2039         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2040 };
2041
2042 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2043         .name           = "mcbsp3",
2044         .class          = &omap44xx_mcbsp_hwmod_class,
2045         .clkdm_name     = "abe_clkdm",
2046         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2047         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2048         .main_clk       = "mcbsp3_fck",
2049         .prcm = {
2050                 .omap4 = {
2051                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2052                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2053                         .modulemode   = MODULEMODE_SWCTRL,
2054                 },
2055         },
2056         .opt_clks       = mcbsp3_opt_clks,
2057         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2058 };
2059
2060 /* mcbsp4 */
2061 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2062         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2063         { .irq = -1 }
2064 };
2065
2066 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2067         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2068         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2069         { .dma_req = -1 }
2070 };
2071
2072 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2073         { .role = "pad_fck", .clk = "pad_clks_ck" },
2074         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2075 };
2076
2077 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2078         .name           = "mcbsp4",
2079         .class          = &omap44xx_mcbsp_hwmod_class,
2080         .clkdm_name     = "l4_per_clkdm",
2081         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2082         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2083         .main_clk       = "mcbsp4_fck",
2084         .prcm = {
2085                 .omap4 = {
2086                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2087                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2088                         .modulemode   = MODULEMODE_SWCTRL,
2089                 },
2090         },
2091         .opt_clks       = mcbsp4_opt_clks,
2092         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2093 };
2094
2095 /*
2096  * 'mcpdm' class
2097  * multi channel pdm controller (proprietary interface with phoenix power
2098  * ic)
2099  */
2100
2101 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2102         .rev_offs       = 0x0000,
2103         .sysc_offs      = 0x0010,
2104         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2106         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2107                            SIDLE_SMART_WKUP),
2108         .sysc_fields    = &omap_hwmod_sysc_type2,
2109 };
2110
2111 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2112         .name   = "mcpdm",
2113         .sysc   = &omap44xx_mcpdm_sysc,
2114 };
2115
2116 /* mcpdm */
2117 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2118         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2119         { .irq = -1 }
2120 };
2121
2122 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2123         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2124         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2125         { .dma_req = -1 }
2126 };
2127
2128 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2129         .name           = "mcpdm",
2130         .class          = &omap44xx_mcpdm_hwmod_class,
2131         .clkdm_name     = "abe_clkdm",
2132         /*
2133          * It's suspected that the McPDM requires an off-chip main
2134          * functional clock, controlled via I2C.  This IP block is
2135          * currently reset very early during boot, before I2C is
2136          * available, so it doesn't seem that we have any choice in
2137          * the kernel other than to avoid resetting it.
2138          */
2139         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2140         .mpu_irqs       = omap44xx_mcpdm_irqs,
2141         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2142         .main_clk       = "mcpdm_fck",
2143         .prcm = {
2144                 .omap4 = {
2145                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2146                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2147                         .modulemode   = MODULEMODE_SWCTRL,
2148                 },
2149         },
2150 };
2151
2152 /*
2153  * 'mcspi' class
2154  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2155  * bus
2156  */
2157
2158 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2159         .rev_offs       = 0x0000,
2160         .sysc_offs      = 0x0010,
2161         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2162                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2164                            SIDLE_SMART_WKUP),
2165         .sysc_fields    = &omap_hwmod_sysc_type2,
2166 };
2167
2168 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2169         .name   = "mcspi",
2170         .sysc   = &omap44xx_mcspi_sysc,
2171         .rev    = OMAP4_MCSPI_REV,
2172 };
2173
2174 /* mcspi1 */
2175 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2176         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2177         { .irq = -1 }
2178 };
2179
2180 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2181         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2183         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2187         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2188         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2189         { .dma_req = -1 }
2190 };
2191
2192 /* mcspi1 dev_attr */
2193 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2194         .num_chipselect = 4,
2195 };
2196
2197 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2198         .name           = "mcspi1",
2199         .class          = &omap44xx_mcspi_hwmod_class,
2200         .clkdm_name     = "l4_per_clkdm",
2201         .mpu_irqs       = omap44xx_mcspi1_irqs,
2202         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2203         .main_clk       = "mcspi1_fck",
2204         .prcm = {
2205                 .omap4 = {
2206                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2207                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2208                         .modulemode   = MODULEMODE_SWCTRL,
2209                 },
2210         },
2211         .dev_attr       = &mcspi1_dev_attr,
2212 };
2213
2214 /* mcspi2 */
2215 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2216         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2217         { .irq = -1 }
2218 };
2219
2220 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2221         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2222         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2223         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2224         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2225         { .dma_req = -1 }
2226 };
2227
2228 /* mcspi2 dev_attr */
2229 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2230         .num_chipselect = 2,
2231 };
2232
2233 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2234         .name           = "mcspi2",
2235         .class          = &omap44xx_mcspi_hwmod_class,
2236         .clkdm_name     = "l4_per_clkdm",
2237         .mpu_irqs       = omap44xx_mcspi2_irqs,
2238         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2239         .main_clk       = "mcspi2_fck",
2240         .prcm = {
2241                 .omap4 = {
2242                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2243                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2244                         .modulemode   = MODULEMODE_SWCTRL,
2245                 },
2246         },
2247         .dev_attr       = &mcspi2_dev_attr,
2248 };
2249
2250 /* mcspi3 */
2251 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2252         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2253         { .irq = -1 }
2254 };
2255
2256 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2257         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2258         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2259         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2260         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2261         { .dma_req = -1 }
2262 };
2263
2264 /* mcspi3 dev_attr */
2265 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2266         .num_chipselect = 2,
2267 };
2268
2269 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2270         .name           = "mcspi3",
2271         .class          = &omap44xx_mcspi_hwmod_class,
2272         .clkdm_name     = "l4_per_clkdm",
2273         .mpu_irqs       = omap44xx_mcspi3_irqs,
2274         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2275         .main_clk       = "mcspi3_fck",
2276         .prcm = {
2277                 .omap4 = {
2278                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2279                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2280                         .modulemode   = MODULEMODE_SWCTRL,
2281                 },
2282         },
2283         .dev_attr       = &mcspi3_dev_attr,
2284 };
2285
2286 /* mcspi4 */
2287 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2288         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2289         { .irq = -1 }
2290 };
2291
2292 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2293         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2294         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2295         { .dma_req = -1 }
2296 };
2297
2298 /* mcspi4 dev_attr */
2299 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2300         .num_chipselect = 1,
2301 };
2302
2303 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2304         .name           = "mcspi4",
2305         .class          = &omap44xx_mcspi_hwmod_class,
2306         .clkdm_name     = "l4_per_clkdm",
2307         .mpu_irqs       = omap44xx_mcspi4_irqs,
2308         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2309         .main_clk       = "mcspi4_fck",
2310         .prcm = {
2311                 .omap4 = {
2312                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2313                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2314                         .modulemode   = MODULEMODE_SWCTRL,
2315                 },
2316         },
2317         .dev_attr       = &mcspi4_dev_attr,
2318 };
2319
2320 /*
2321  * 'mmc' class
2322  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2323  */
2324
2325 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2326         .rev_offs       = 0x0000,
2327         .sysc_offs      = 0x0010,
2328         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2329                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2330                            SYSC_HAS_SOFTRESET),
2331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2332                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2333                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2334         .sysc_fields    = &omap_hwmod_sysc_type2,
2335 };
2336
2337 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2338         .name   = "mmc",
2339         .sysc   = &omap44xx_mmc_sysc,
2340 };
2341
2342 /* mmc1 */
2343 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2344         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2345         { .irq = -1 }
2346 };
2347
2348 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2349         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2350         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2351         { .dma_req = -1 }
2352 };
2353
2354 /* mmc1 dev_attr */
2355 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2356         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2357 };
2358
2359 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2360         .name           = "mmc1",
2361         .class          = &omap44xx_mmc_hwmod_class,
2362         .clkdm_name     = "l3_init_clkdm",
2363         .mpu_irqs       = omap44xx_mmc1_irqs,
2364         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2365         .main_clk       = "mmc1_fck",
2366         .prcm = {
2367                 .omap4 = {
2368                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2369                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2370                         .modulemode   = MODULEMODE_SWCTRL,
2371                 },
2372         },
2373         .dev_attr       = &mmc1_dev_attr,
2374 };
2375
2376 /* mmc2 */
2377 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2378         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2379         { .irq = -1 }
2380 };
2381
2382 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2383         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2384         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2385         { .dma_req = -1 }
2386 };
2387
2388 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2389         .name           = "mmc2",
2390         .class          = &omap44xx_mmc_hwmod_class,
2391         .clkdm_name     = "l3_init_clkdm",
2392         .mpu_irqs       = omap44xx_mmc2_irqs,
2393         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2394         .main_clk       = "mmc2_fck",
2395         .prcm = {
2396                 .omap4 = {
2397                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2398                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2399                         .modulemode   = MODULEMODE_SWCTRL,
2400                 },
2401         },
2402 };
2403
2404 /* mmc3 */
2405 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2406         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2407         { .irq = -1 }
2408 };
2409
2410 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2411         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2412         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2413         { .dma_req = -1 }
2414 };
2415
2416 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2417         .name           = "mmc3",
2418         .class          = &omap44xx_mmc_hwmod_class,
2419         .clkdm_name     = "l4_per_clkdm",
2420         .mpu_irqs       = omap44xx_mmc3_irqs,
2421         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2422         .main_clk       = "mmc3_fck",
2423         .prcm = {
2424                 .omap4 = {
2425                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2426                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2427                         .modulemode   = MODULEMODE_SWCTRL,
2428                 },
2429         },
2430 };
2431
2432 /* mmc4 */
2433 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2434         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2435         { .irq = -1 }
2436 };
2437
2438 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2439         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2440         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2441         { .dma_req = -1 }
2442 };
2443
2444 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2445         .name           = "mmc4",
2446         .class          = &omap44xx_mmc_hwmod_class,
2447         .clkdm_name     = "l4_per_clkdm",
2448         .mpu_irqs       = omap44xx_mmc4_irqs,
2449         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2450         .main_clk       = "mmc4_fck",
2451         .prcm = {
2452                 .omap4 = {
2453                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2454                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2455                         .modulemode   = MODULEMODE_SWCTRL,
2456                 },
2457         },
2458 };
2459
2460 /* mmc5 */
2461 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2462         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2463         { .irq = -1 }
2464 };
2465
2466 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2467         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2468         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2469         { .dma_req = -1 }
2470 };
2471
2472 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2473         .name           = "mmc5",
2474         .class          = &omap44xx_mmc_hwmod_class,
2475         .clkdm_name     = "l4_per_clkdm",
2476         .mpu_irqs       = omap44xx_mmc5_irqs,
2477         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2478         .main_clk       = "mmc5_fck",
2479         .prcm = {
2480                 .omap4 = {
2481                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2482                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2483                         .modulemode   = MODULEMODE_SWCTRL,
2484                 },
2485         },
2486 };
2487
2488 /*
2489  * 'mmu' class
2490  * The memory management unit performs virtual to physical address translation
2491  * for its requestors.
2492  */
2493
2494 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2495         .rev_offs       = 0x000,
2496         .sysc_offs      = 0x010,
2497         .syss_offs      = 0x014,
2498         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2499                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2501         .sysc_fields    = &omap_hwmod_sysc_type1,
2502 };
2503
2504 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2505         .name = "mmu",
2506         .sysc = &mmu_sysc,
2507 };
2508
2509 /* mmu ipu */
2510
2511 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2512         .da_start       = 0x0,
2513         .da_end         = 0xfffff000,
2514         .nr_tlb_entries = 32,
2515 };
2516
2517 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2518 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2519         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2520         { .irq = -1 }
2521 };
2522
2523 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2524         { .name = "mmu_cache", .rst_shift = 2 },
2525 };
2526
2527 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2528         {
2529                 .pa_start       = 0x55082000,
2530                 .pa_end         = 0x550820ff,
2531                 .flags          = ADDR_TYPE_RT,
2532         },
2533         { }
2534 };
2535
2536 /* l3_main_2 -> mmu_ipu */
2537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2538         .master         = &omap44xx_l3_main_2_hwmod,
2539         .slave          = &omap44xx_mmu_ipu_hwmod,
2540         .clk            = "l3_div_ck",
2541         .addr           = omap44xx_mmu_ipu_addrs,
2542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2543 };
2544
2545 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2546         .name           = "mmu_ipu",
2547         .class          = &omap44xx_mmu_hwmod_class,
2548         .clkdm_name     = "ducati_clkdm",
2549         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2550         .rst_lines      = omap44xx_mmu_ipu_resets,
2551         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2552         .main_clk       = "ducati_clk_mux_ck",
2553         .prcm = {
2554                 .omap4 = {
2555                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2556                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2557                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2558                         .modulemode   = MODULEMODE_HWCTRL,
2559                 },
2560         },
2561         .dev_attr       = &mmu_ipu_dev_attr,
2562 };
2563
2564 /* mmu dsp */
2565
2566 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2567         .da_start       = 0x0,
2568         .da_end         = 0xfffff000,
2569         .nr_tlb_entries = 32,
2570 };
2571
2572 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2573 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2574         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2575         { .irq = -1 }
2576 };
2577
2578 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2579         { .name = "mmu_cache", .rst_shift = 1 },
2580 };
2581
2582 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2583         {
2584                 .pa_start       = 0x4a066000,
2585                 .pa_end         = 0x4a0660ff,
2586                 .flags          = ADDR_TYPE_RT,
2587         },
2588         { }
2589 };
2590
2591 /* l4_cfg -> dsp */
2592 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2593         .master         = &omap44xx_l4_cfg_hwmod,
2594         .slave          = &omap44xx_mmu_dsp_hwmod,
2595         .clk            = "l4_div_ck",
2596         .addr           = omap44xx_mmu_dsp_addrs,
2597         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2598 };
2599
2600 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2601         .name           = "mmu_dsp",
2602         .class          = &omap44xx_mmu_hwmod_class,
2603         .clkdm_name     = "tesla_clkdm",
2604         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2605         .rst_lines      = omap44xx_mmu_dsp_resets,
2606         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2607         .main_clk       = "dpll_iva_m4x2_ck",
2608         .prcm = {
2609                 .omap4 = {
2610                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2611                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2612                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2613                         .modulemode   = MODULEMODE_HWCTRL,
2614                 },
2615         },
2616         .dev_attr       = &mmu_dsp_dev_attr,
2617 };
2618
2619 /*
2620  * 'mpu' class
2621  * mpu sub-system
2622  */
2623
2624 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2625         .name   = "mpu",
2626 };
2627
2628 /* mpu */
2629 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2630         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2635         { .irq = -1 }
2636 };
2637
2638 static struct omap_hwmod omap44xx_mpu_hwmod = {
2639         .name           = "mpu",
2640         .class          = &omap44xx_mpu_hwmod_class,
2641         .clkdm_name     = "mpuss_clkdm",
2642         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2643         .mpu_irqs       = omap44xx_mpu_irqs,
2644         .main_clk       = "dpll_mpu_m2_ck",
2645         .prcm = {
2646                 .omap4 = {
2647                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2648                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2649                 },
2650         },
2651 };
2652
2653 /*
2654  * 'ocmc_ram' class
2655  * top-level core on-chip ram
2656  */
2657
2658 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2659         .name   = "ocmc_ram",
2660 };
2661
2662 /* ocmc_ram */
2663 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2664         .name           = "ocmc_ram",
2665         .class          = &omap44xx_ocmc_ram_hwmod_class,
2666         .clkdm_name     = "l3_2_clkdm",
2667         .prcm = {
2668                 .omap4 = {
2669                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2670                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2671                 },
2672         },
2673 };
2674
2675 /*
2676  * 'ocp2scp' class
2677  * bridge to transform ocp interface protocol to scp (serial control port)
2678  * protocol
2679  */
2680
2681 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2682         .rev_offs       = 0x0000,
2683         .sysc_offs      = 0x0010,
2684         .syss_offs      = 0x0014,
2685         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2686                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2688         .sysc_fields    = &omap_hwmod_sysc_type1,
2689 };
2690
2691 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2692         .name   = "ocp2scp",
2693         .sysc   = &omap44xx_ocp2scp_sysc,
2694 };
2695
2696 /* ocp2scp dev_attr */
2697 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2698         {
2699                 .name           = "usb_phy",
2700                 .start          = 0x4a0ad080,
2701                 .end            = 0x4a0ae000,
2702                 .flags          = IORESOURCE_MEM,
2703         },
2704         {
2705                 /* XXX: Remove this once control module driver is in place */
2706                 .name           = "ctrl_dev",
2707                 .start          = 0x4a002300,
2708                 .end            = 0x4a002303,
2709                 .flags          = IORESOURCE_MEM,
2710         },
2711         { }
2712 };
2713
2714 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2715         {
2716                 .drv_name       = "omap-usb2",
2717                 .res            = omap44xx_usb_phy_and_pll_addrs,
2718         },
2719         { }
2720 };
2721
2722 /* ocp2scp_usb_phy */
2723 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2724         .name           = "ocp2scp_usb_phy",
2725         .class          = &omap44xx_ocp2scp_hwmod_class,
2726         .clkdm_name     = "l3_init_clkdm",
2727         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2728         .prcm = {
2729                 .omap4 = {
2730                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2731                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2732                         .modulemode   = MODULEMODE_HWCTRL,
2733                 },
2734         },
2735         .dev_attr       = ocp2scp_dev_attr,
2736 };
2737
2738 /*
2739  * 'prcm' class
2740  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2741  * + clock manager 1 (in always on power domain) + local prm in mpu
2742  */
2743
2744 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2745         .name   = "prcm",
2746 };
2747
2748 /* prcm_mpu */
2749 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2750         .name           = "prcm_mpu",
2751         .class          = &omap44xx_prcm_hwmod_class,
2752         .clkdm_name     = "l4_wkup_clkdm",
2753         .flags          = HWMOD_NO_IDLEST,
2754         .prcm = {
2755                 .omap4 = {
2756                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2757                 },
2758         },
2759 };
2760
2761 /* cm_core_aon */
2762 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2763         .name           = "cm_core_aon",
2764         .class          = &omap44xx_prcm_hwmod_class,
2765         .flags          = HWMOD_NO_IDLEST,
2766         .prcm = {
2767                 .omap4 = {
2768                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2769                 },
2770         },
2771 };
2772
2773 /* cm_core */
2774 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2775         .name           = "cm_core",
2776         .class          = &omap44xx_prcm_hwmod_class,
2777         .flags          = HWMOD_NO_IDLEST,
2778         .prcm = {
2779                 .omap4 = {
2780                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2781                 },
2782         },
2783 };
2784
2785 /* prm */
2786 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2787         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2788         { .irq = -1 }
2789 };
2790
2791 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2792         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2793         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2794 };
2795
2796 static struct omap_hwmod omap44xx_prm_hwmod = {
2797         .name           = "prm",
2798         .class          = &omap44xx_prcm_hwmod_class,
2799         .mpu_irqs       = omap44xx_prm_irqs,
2800         .rst_lines      = omap44xx_prm_resets,
2801         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2802 };
2803
2804 /*
2805  * 'scrm' class
2806  * system clock and reset manager
2807  */
2808
2809 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2810         .name   = "scrm",
2811 };
2812
2813 /* scrm */
2814 static struct omap_hwmod omap44xx_scrm_hwmod = {
2815         .name           = "scrm",
2816         .class          = &omap44xx_scrm_hwmod_class,
2817         .clkdm_name     = "l4_wkup_clkdm",
2818         .prcm = {
2819                 .omap4 = {
2820                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2821                 },
2822         },
2823 };
2824
2825 /*
2826  * 'sl2if' class
2827  * shared level 2 memory interface
2828  */
2829
2830 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2831         .name   = "sl2if",
2832 };
2833
2834 /* sl2if */
2835 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2836         .name           = "sl2if",
2837         .class          = &omap44xx_sl2if_hwmod_class,
2838         .clkdm_name     = "ivahd_clkdm",
2839         .prcm = {
2840                 .omap4 = {
2841                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2842                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2843                         .modulemode   = MODULEMODE_HWCTRL,
2844                 },
2845         },
2846 };
2847
2848 /*
2849  * 'slimbus' class
2850  * bidirectional, multi-drop, multi-channel two-line serial interface between
2851  * the device and external components
2852  */
2853
2854 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2855         .rev_offs       = 0x0000,
2856         .sysc_offs      = 0x0010,
2857         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2858                            SYSC_HAS_SOFTRESET),
2859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2860                            SIDLE_SMART_WKUP),
2861         .sysc_fields    = &omap_hwmod_sysc_type2,
2862 };
2863
2864 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2865         .name   = "slimbus",
2866         .sysc   = &omap44xx_slimbus_sysc,
2867 };
2868
2869 /* slimbus1 */
2870 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2871         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2872         { .irq = -1 }
2873 };
2874
2875 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2876         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2877         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2878         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2879         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2882         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2883         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2884         { .dma_req = -1 }
2885 };
2886
2887 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2888         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2889         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2890         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2891         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2892 };
2893
2894 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2895         .name           = "slimbus1",
2896         .class          = &omap44xx_slimbus_hwmod_class,
2897         .clkdm_name     = "abe_clkdm",
2898         .mpu_irqs       = omap44xx_slimbus1_irqs,
2899         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2900         .prcm = {
2901                 .omap4 = {
2902                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2903                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2904                         .modulemode   = MODULEMODE_SWCTRL,
2905                 },
2906         },
2907         .opt_clks       = slimbus1_opt_clks,
2908         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2909 };
2910
2911 /* slimbus2 */
2912 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2913         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2914         { .irq = -1 }
2915 };
2916
2917 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2918         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2919         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2920         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2921         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2924         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2925         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2926         { .dma_req = -1 }
2927 };
2928
2929 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2930         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2931         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2932         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2933 };
2934
2935 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2936         .name           = "slimbus2",
2937         .class          = &omap44xx_slimbus_hwmod_class,
2938         .clkdm_name     = "l4_per_clkdm",
2939         .mpu_irqs       = omap44xx_slimbus2_irqs,
2940         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2941         .prcm = {
2942                 .omap4 = {
2943                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2944                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2945                         .modulemode   = MODULEMODE_SWCTRL,
2946                 },
2947         },
2948         .opt_clks       = slimbus2_opt_clks,
2949         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2950 };
2951
2952 /*
2953  * 'smartreflex' class
2954  * smartreflex module (monitor silicon performance and outputs a measure of
2955  * performance error)
2956  */
2957
2958 /* The IP is not compliant to type1 / type2 scheme */
2959 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2960         .sidle_shift    = 24,
2961         .enwkup_shift   = 26,
2962 };
2963
2964 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2965         .sysc_offs      = 0x0038,
2966         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2967         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2968                            SIDLE_SMART_WKUP),
2969         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2970 };
2971
2972 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2973         .name   = "smartreflex",
2974         .sysc   = &omap44xx_smartreflex_sysc,
2975         .rev    = 2,
2976 };
2977
2978 /* smartreflex_core */
2979 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2980         .sensor_voltdm_name   = "core",
2981 };
2982
2983 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2984         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2985         { .irq = -1 }
2986 };
2987
2988 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2989         .name           = "smartreflex_core",
2990         .class          = &omap44xx_smartreflex_hwmod_class,
2991         .clkdm_name     = "l4_ao_clkdm",
2992         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2993
2994         .main_clk       = "smartreflex_core_fck",
2995         .prcm = {
2996                 .omap4 = {
2997                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2998                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2999                         .modulemode   = MODULEMODE_SWCTRL,
3000                 },
3001         },
3002         .dev_attr       = &smartreflex_core_dev_attr,
3003 };
3004
3005 /* smartreflex_iva */
3006 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3007         .sensor_voltdm_name     = "iva",
3008 };
3009
3010 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3011         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3012         { .irq = -1 }
3013 };
3014
3015 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3016         .name           = "smartreflex_iva",
3017         .class          = &omap44xx_smartreflex_hwmod_class,
3018         .clkdm_name     = "l4_ao_clkdm",
3019         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3020         .main_clk       = "smartreflex_iva_fck",
3021         .prcm = {
3022                 .omap4 = {
3023                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3024                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3025                         .modulemode   = MODULEMODE_SWCTRL,
3026                 },
3027         },
3028         .dev_attr       = &smartreflex_iva_dev_attr,
3029 };
3030
3031 /* smartreflex_mpu */
3032 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3033         .sensor_voltdm_name     = "mpu",
3034 };
3035
3036 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3037         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3038         { .irq = -1 }
3039 };
3040
3041 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3042         .name           = "smartreflex_mpu",
3043         .class          = &omap44xx_smartreflex_hwmod_class,
3044         .clkdm_name     = "l4_ao_clkdm",
3045         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3046         .main_clk       = "smartreflex_mpu_fck",
3047         .prcm = {
3048                 .omap4 = {
3049                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3050                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3051                         .modulemode   = MODULEMODE_SWCTRL,
3052                 },
3053         },
3054         .dev_attr       = &smartreflex_mpu_dev_attr,
3055 };
3056
3057 /*
3058  * 'spinlock' class
3059  * spinlock provides hardware assistance for synchronizing the processes
3060  * running on multiple processors
3061  */
3062
3063 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3064         .rev_offs       = 0x0000,
3065         .sysc_offs      = 0x0010,
3066         .syss_offs      = 0x0014,
3067         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3068                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3069                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3070         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3071                            SIDLE_SMART_WKUP),
3072         .sysc_fields    = &omap_hwmod_sysc_type1,
3073 };
3074
3075 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3076         .name   = "spinlock",
3077         .sysc   = &omap44xx_spinlock_sysc,
3078 };
3079
3080 /* spinlock */
3081 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3082         .name           = "spinlock",
3083         .class          = &omap44xx_spinlock_hwmod_class,
3084         .clkdm_name     = "l4_cfg_clkdm",
3085         .prcm = {
3086                 .omap4 = {
3087                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3088                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3089                 },
3090         },
3091 };
3092
3093 /*
3094  * 'timer' class
3095  * general purpose timer module with accurate 1ms tick
3096  * This class contains several variants: ['timer_1ms', 'timer']
3097  */
3098
3099 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3100         .rev_offs       = 0x0000,
3101         .sysc_offs      = 0x0010,
3102         .syss_offs      = 0x0014,
3103         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3104                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3105                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3106                            SYSS_HAS_RESET_STATUS),
3107         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3108         .sysc_fields    = &omap_hwmod_sysc_type1,
3109 };
3110
3111 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3112         .name   = "timer",
3113         .sysc   = &omap44xx_timer_1ms_sysc,
3114 };
3115
3116 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3117         .rev_offs       = 0x0000,
3118         .sysc_offs      = 0x0010,
3119         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3120                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3122                            SIDLE_SMART_WKUP),
3123         .sysc_fields    = &omap_hwmod_sysc_type2,
3124 };
3125
3126 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3127         .name   = "timer",
3128         .sysc   = &omap44xx_timer_sysc,
3129 };
3130
3131 /* always-on timers dev attribute */
3132 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3133         .timer_capability       = OMAP_TIMER_ALWON,
3134 };
3135
3136 /* pwm timers dev attribute */
3137 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3138         .timer_capability       = OMAP_TIMER_HAS_PWM,
3139 };
3140
3141 /* timers with DSP interrupt dev attribute */
3142 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3143         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3144 };
3145
3146 /* pwm timers with DSP interrupt dev attribute */
3147 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3148         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3149 };
3150
3151 /* timer1 */
3152 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3153         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3154         { .irq = -1 }
3155 };
3156
3157 static struct omap_hwmod omap44xx_timer1_hwmod = {
3158         .name           = "timer1",
3159         .class          = &omap44xx_timer_1ms_hwmod_class,
3160         .clkdm_name     = "l4_wkup_clkdm",
3161         .mpu_irqs       = omap44xx_timer1_irqs,
3162         .main_clk       = "timer1_fck",
3163         .prcm = {
3164                 .omap4 = {
3165                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3166                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3167                         .modulemode   = MODULEMODE_SWCTRL,
3168                 },
3169         },
3170         .dev_attr       = &capability_alwon_dev_attr,
3171 };
3172
3173 /* timer2 */
3174 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3175         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3176         { .irq = -1 }
3177 };
3178
3179 static struct omap_hwmod omap44xx_timer2_hwmod = {
3180         .name           = "timer2",
3181         .class          = &omap44xx_timer_1ms_hwmod_class,
3182         .clkdm_name     = "l4_per_clkdm",
3183         .mpu_irqs       = omap44xx_timer2_irqs,
3184         .main_clk       = "timer2_fck",
3185         .prcm = {
3186                 .omap4 = {
3187                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3188                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3189                         .modulemode   = MODULEMODE_SWCTRL,
3190                 },
3191         },
3192 };
3193
3194 /* timer3 */
3195 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3196         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3197         { .irq = -1 }
3198 };
3199
3200 static struct omap_hwmod omap44xx_timer3_hwmod = {
3201         .name           = "timer3",
3202         .class          = &omap44xx_timer_hwmod_class,
3203         .clkdm_name     = "l4_per_clkdm",
3204         .mpu_irqs       = omap44xx_timer3_irqs,
3205         .main_clk       = "timer3_fck",
3206         .prcm = {
3207                 .omap4 = {
3208                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3209                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3210                         .modulemode   = MODULEMODE_SWCTRL,
3211                 },
3212         },
3213 };
3214
3215 /* timer4 */
3216 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3217         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3218         { .irq = -1 }
3219 };
3220
3221 static struct omap_hwmod omap44xx_timer4_hwmod = {
3222         .name           = "timer4",
3223         .class          = &omap44xx_timer_hwmod_class,
3224         .clkdm_name     = "l4_per_clkdm",
3225         .mpu_irqs       = omap44xx_timer4_irqs,
3226         .main_clk       = "timer4_fck",
3227         .prcm = {
3228                 .omap4 = {
3229                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3230                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3231                         .modulemode   = MODULEMODE_SWCTRL,
3232                 },
3233         },
3234 };
3235
3236 /* timer5 */
3237 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3238         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3239         { .irq = -1 }
3240 };
3241
3242 static struct omap_hwmod omap44xx_timer5_hwmod = {
3243         .name           = "timer5",
3244         .class          = &omap44xx_timer_hwmod_class,
3245         .clkdm_name     = "abe_clkdm",
3246         .mpu_irqs       = omap44xx_timer5_irqs,
3247         .main_clk       = "timer5_fck",
3248         .prcm = {
3249                 .omap4 = {
3250                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3251                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3252                         .modulemode   = MODULEMODE_SWCTRL,
3253                 },
3254         },
3255         .dev_attr       = &capability_dsp_dev_attr,
3256 };
3257
3258 /* timer6 */
3259 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3260         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3261         { .irq = -1 }
3262 };
3263
3264 static struct omap_hwmod omap44xx_timer6_hwmod = {
3265         .name           = "timer6",
3266         .class          = &omap44xx_timer_hwmod_class,
3267         .clkdm_name     = "abe_clkdm",
3268         .mpu_irqs       = omap44xx_timer6_irqs,
3269
3270         .main_clk       = "timer6_fck",
3271         .prcm = {
3272                 .omap4 = {
3273                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3274                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3275                         .modulemode   = MODULEMODE_SWCTRL,
3276                 },
3277         },
3278         .dev_attr       = &capability_dsp_dev_attr,
3279 };
3280
3281 /* timer7 */
3282 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3283         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3284         { .irq = -1 }
3285 };
3286
3287 static struct omap_hwmod omap44xx_timer7_hwmod = {
3288         .name           = "timer7",
3289         .class          = &omap44xx_timer_hwmod_class,
3290         .clkdm_name     = "abe_clkdm",
3291         .mpu_irqs       = omap44xx_timer7_irqs,
3292         .main_clk       = "timer7_fck",
3293         .prcm = {
3294                 .omap4 = {
3295                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3296                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3297                         .modulemode   = MODULEMODE_SWCTRL,
3298                 },
3299         },
3300         .dev_attr       = &capability_dsp_dev_attr,
3301 };
3302
3303 /* timer8 */
3304 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3305         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3306         { .irq = -1 }
3307 };
3308
3309 static struct omap_hwmod omap44xx_timer8_hwmod = {
3310         .name           = "timer8",
3311         .class          = &omap44xx_timer_hwmod_class,
3312         .clkdm_name     = "abe_clkdm",
3313         .mpu_irqs       = omap44xx_timer8_irqs,
3314         .main_clk       = "timer8_fck",
3315         .prcm = {
3316                 .omap4 = {
3317                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3318                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3319                         .modulemode   = MODULEMODE_SWCTRL,
3320                 },
3321         },
3322         .dev_attr       = &capability_dsp_pwm_dev_attr,
3323 };
3324
3325 /* timer9 */
3326 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3327         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3328         { .irq = -1 }
3329 };
3330
3331 static struct omap_hwmod omap44xx_timer9_hwmod = {
3332         .name           = "timer9",
3333         .class          = &omap44xx_timer_hwmod_class,
3334         .clkdm_name     = "l4_per_clkdm",
3335         .mpu_irqs       = omap44xx_timer9_irqs,
3336         .main_clk       = "timer9_fck",
3337         .prcm = {
3338                 .omap4 = {
3339                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3340                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3341                         .modulemode   = MODULEMODE_SWCTRL,
3342                 },
3343         },
3344         .dev_attr       = &capability_pwm_dev_attr,
3345 };
3346
3347 /* timer10 */
3348 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3349         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3350         { .irq = -1 }
3351 };
3352
3353 static struct omap_hwmod omap44xx_timer10_hwmod = {
3354         .name           = "timer10",
3355         .class          = &omap44xx_timer_1ms_hwmod_class,
3356         .clkdm_name     = "l4_per_clkdm",
3357         .mpu_irqs       = omap44xx_timer10_irqs,
3358         .main_clk       = "timer10_fck",
3359         .prcm = {
3360                 .omap4 = {
3361                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3362                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3363                         .modulemode   = MODULEMODE_SWCTRL,
3364                 },
3365         },
3366         .dev_attr       = &capability_pwm_dev_attr,
3367 };
3368
3369 /* timer11 */
3370 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3371         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3372         { .irq = -1 }
3373 };
3374
3375 static struct omap_hwmod omap44xx_timer11_hwmod = {
3376         .name           = "timer11",
3377         .class          = &omap44xx_timer_hwmod_class,
3378         .clkdm_name     = "l4_per_clkdm",
3379         .mpu_irqs       = omap44xx_timer11_irqs,
3380         .main_clk       = "timer11_fck",
3381         .prcm = {
3382                 .omap4 = {
3383                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3384                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3385                         .modulemode   = MODULEMODE_SWCTRL,
3386                 },
3387         },
3388         .dev_attr       = &capability_pwm_dev_attr,
3389 };
3390
3391 /*
3392  * 'uart' class
3393  * universal asynchronous receiver/transmitter (uart)
3394  */
3395
3396 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3397         .rev_offs       = 0x0050,
3398         .sysc_offs      = 0x0054,
3399         .syss_offs      = 0x0058,
3400         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3401                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3402                            SYSS_HAS_RESET_STATUS),
3403         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3404                            SIDLE_SMART_WKUP),
3405         .sysc_fields    = &omap_hwmod_sysc_type1,
3406 };
3407
3408 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3409         .name   = "uart",
3410         .sysc   = &omap44xx_uart_sysc,
3411 };
3412
3413 /* uart1 */
3414 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3415         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3416         { .irq = -1 }
3417 };
3418
3419 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3420         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3421         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3422         { .dma_req = -1 }
3423 };
3424
3425 static struct omap_hwmod omap44xx_uart1_hwmod = {
3426         .name           = "uart1",
3427         .class          = &omap44xx_uart_hwmod_class,
3428         .clkdm_name     = "l4_per_clkdm",
3429         .mpu_irqs       = omap44xx_uart1_irqs,
3430         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3431         .main_clk       = "uart1_fck",
3432         .prcm = {
3433                 .omap4 = {
3434                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3435                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3436                         .modulemode   = MODULEMODE_SWCTRL,
3437                 },
3438         },
3439 };
3440
3441 /* uart2 */
3442 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3443         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3444         { .irq = -1 }
3445 };
3446
3447 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3448         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3449         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3450         { .dma_req = -1 }
3451 };
3452
3453 static struct omap_hwmod omap44xx_uart2_hwmod = {
3454         .name           = "uart2",
3455         .class          = &omap44xx_uart_hwmod_class,
3456         .clkdm_name     = "l4_per_clkdm",
3457         .mpu_irqs       = omap44xx_uart2_irqs,
3458         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3459         .main_clk       = "uart2_fck",
3460         .prcm = {
3461                 .omap4 = {
3462                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3463                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3464                         .modulemode   = MODULEMODE_SWCTRL,
3465                 },
3466         },
3467 };
3468
3469 /* uart3 */
3470 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3471         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3472         { .irq = -1 }
3473 };
3474
3475 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3476         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3477         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3478         { .dma_req = -1 }
3479 };
3480
3481 static struct omap_hwmod omap44xx_uart3_hwmod = {
3482         .name           = "uart3",
3483         .class          = &omap44xx_uart_hwmod_class,
3484         .clkdm_name     = "l4_per_clkdm",
3485         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3486         .mpu_irqs       = omap44xx_uart3_irqs,
3487         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3488         .main_clk       = "uart3_fck",
3489         .prcm = {
3490                 .omap4 = {
3491                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3492                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3493                         .modulemode   = MODULEMODE_SWCTRL,
3494                 },
3495         },
3496 };
3497
3498 /* uart4 */
3499 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3500         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3501         { .irq = -1 }
3502 };
3503
3504 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3505         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3506         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3507         { .dma_req = -1 }
3508 };
3509
3510 static struct omap_hwmod omap44xx_uart4_hwmod = {
3511         .name           = "uart4",
3512         .class          = &omap44xx_uart_hwmod_class,
3513         .clkdm_name     = "l4_per_clkdm",
3514         .mpu_irqs       = omap44xx_uart4_irqs,
3515         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3516         .main_clk       = "uart4_fck",
3517         .prcm = {
3518                 .omap4 = {
3519                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3520                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3521                         .modulemode   = MODULEMODE_SWCTRL,
3522                 },
3523         },
3524 };
3525
3526 /*
3527  * 'usb_host_fs' class
3528  * full-speed usb host controller
3529  */
3530
3531 /* The IP is not compliant to type1 / type2 scheme */
3532 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3533         .midle_shift    = 4,
3534         .sidle_shift    = 2,
3535         .srst_shift     = 1,
3536 };
3537
3538 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3539         .rev_offs       = 0x0000,
3540         .sysc_offs      = 0x0210,
3541         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3542                            SYSC_HAS_SOFTRESET),
3543         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3544                            SIDLE_SMART_WKUP),
3545         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3546 };
3547
3548 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3549         .name   = "usb_host_fs",
3550         .sysc   = &omap44xx_usb_host_fs_sysc,
3551 };
3552
3553 /* usb_host_fs */
3554 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3555         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3556         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3557         { .irq = -1 }
3558 };
3559
3560 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3561         .name           = "usb_host_fs",
3562         .class          = &omap44xx_usb_host_fs_hwmod_class,
3563         .clkdm_name     = "l3_init_clkdm",
3564         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3565         .main_clk       = "usb_host_fs_fck",
3566         .prcm = {
3567                 .omap4 = {
3568                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3569                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3570                         .modulemode   = MODULEMODE_SWCTRL,
3571                 },
3572         },
3573 };
3574
3575 /*
3576  * 'usb_host_hs' class
3577  * high-speed multi-port usb host controller
3578  */
3579
3580 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3581         .rev_offs       = 0x0000,
3582         .sysc_offs      = 0x0010,
3583         .syss_offs      = 0x0014,
3584         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3585                            SYSC_HAS_SOFTRESET),
3586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3587                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3588                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3589         .sysc_fields    = &omap_hwmod_sysc_type2,
3590 };
3591
3592 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3593         .name   = "usb_host_hs",
3594         .sysc   = &omap44xx_usb_host_hs_sysc,
3595 };
3596
3597 /* usb_host_hs */
3598 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3599         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3600         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3601         { .irq = -1 }
3602 };
3603
3604 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3605         .name           = "usb_host_hs",
3606         .class          = &omap44xx_usb_host_hs_hwmod_class,
3607         .clkdm_name     = "l3_init_clkdm",
3608         .main_clk       = "usb_host_hs_fck",
3609         .prcm = {
3610                 .omap4 = {
3611                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3612                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3613                         .modulemode   = MODULEMODE_SWCTRL,
3614                 },
3615         },
3616         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3617
3618         /*
3619          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3620          * id: i660
3621          *
3622          * Description:
3623          * In the following configuration :
3624          * - USBHOST module is set to smart-idle mode
3625          * - PRCM asserts idle_req to the USBHOST module ( This typically
3626          *   happens when the system is going to a low power mode : all ports
3627          *   have been suspended, the master part of the USBHOST module has
3628          *   entered the standby state, and SW has cut the functional clocks)
3629          * - an USBHOST interrupt occurs before the module is able to answer
3630          *   idle_ack, typically a remote wakeup IRQ.
3631          * Then the USB HOST module will enter a deadlock situation where it
3632          * is no more accessible nor functional.
3633          *
3634          * Workaround:
3635          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3636          */
3637
3638         /*
3639          * Errata: USB host EHCI may stall when entering smart-standby mode
3640          * Id: i571
3641          *
3642          * Description:
3643          * When the USBHOST module is set to smart-standby mode, and when it is
3644          * ready to enter the standby state (i.e. all ports are suspended and
3645          * all attached devices are in suspend mode), then it can wrongly assert
3646          * the Mstandby signal too early while there are still some residual OCP
3647          * transactions ongoing. If this condition occurs, the internal state
3648          * machine may go to an undefined state and the USB link may be stuck
3649          * upon the next resume.
3650          *
3651          * Workaround:
3652          * Don't use smart standby; use only force standby,
3653          * hence HWMOD_SWSUP_MSTANDBY
3654          */
3655
3656         /*
3657          * During system boot; If the hwmod framework resets the module
3658          * the module will have smart idle settings; which can lead to deadlock
3659          * (above Errata Id:i660); so, dont reset the module during boot;
3660          * Use HWMOD_INIT_NO_RESET.
3661          */
3662
3663         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3664                           HWMOD_INIT_NO_RESET,
3665 };
3666
3667 /*
3668  * 'usb_otg_hs' class
3669  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3670  */
3671
3672 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3673         .rev_offs       = 0x0400,
3674         .sysc_offs      = 0x0404,
3675         .syss_offs      = 0x0408,
3676         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3677                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3678                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3680                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3681                            MSTANDBY_SMART),
3682         .sysc_fields    = &omap_hwmod_sysc_type1,
3683 };
3684
3685 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3686         .name   = "usb_otg_hs",
3687         .sysc   = &omap44xx_usb_otg_hs_sysc,
3688 };
3689
3690 /* usb_otg_hs */
3691 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3692         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3693         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3694         { .irq = -1 }
3695 };
3696
3697 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3698         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3699 };
3700
3701 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3702         .name           = "usb_otg_hs",
3703         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3704         .clkdm_name     = "l3_init_clkdm",
3705         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3706         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3707         .main_clk       = "usb_otg_hs_ick",
3708         .prcm = {
3709                 .omap4 = {
3710                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3711                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3712                         .modulemode   = MODULEMODE_HWCTRL,
3713                 },
3714         },
3715         .opt_clks       = usb_otg_hs_opt_clks,
3716         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3717 };
3718
3719 /*
3720  * 'usb_tll_hs' class
3721  * usb_tll_hs module is the adapter on the usb_host_hs ports
3722  */
3723
3724 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3725         .rev_offs       = 0x0000,
3726         .sysc_offs      = 0x0010,
3727         .syss_offs      = 0x0014,
3728         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3729                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3730                            SYSC_HAS_AUTOIDLE),
3731         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3732         .sysc_fields    = &omap_hwmod_sysc_type1,
3733 };
3734
3735 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3736         .name   = "usb_tll_hs",
3737         .sysc   = &omap44xx_usb_tll_hs_sysc,
3738 };
3739
3740 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3741         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3742         { .irq = -1 }
3743 };
3744
3745 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3746         .name           = "usb_tll_hs",
3747         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3748         .clkdm_name     = "l3_init_clkdm",
3749         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3750         .main_clk       = "usb_tll_hs_ick",
3751         .prcm = {
3752                 .omap4 = {
3753                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3754                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3755                         .modulemode   = MODULEMODE_HWCTRL,
3756                 },
3757         },
3758 };
3759
3760 /*
3761  * 'wd_timer' class
3762  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3763  * overflow condition
3764  */
3765
3766 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3767         .rev_offs       = 0x0000,
3768         .sysc_offs      = 0x0010,
3769         .syss_offs      = 0x0014,
3770         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3771                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3773                            SIDLE_SMART_WKUP),
3774         .sysc_fields    = &omap_hwmod_sysc_type1,
3775 };
3776
3777 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3778         .name           = "wd_timer",
3779         .sysc           = &omap44xx_wd_timer_sysc,
3780         .pre_shutdown   = &omap2_wd_timer_disable,
3781         .reset          = &omap2_wd_timer_reset,
3782 };
3783
3784 /* wd_timer2 */
3785 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3786         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3787         { .irq = -1 }
3788 };
3789
3790 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3791         .name           = "wd_timer2",
3792         .class          = &omap44xx_wd_timer_hwmod_class,
3793         .clkdm_name     = "l4_wkup_clkdm",
3794         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3795         .main_clk       = "wd_timer2_fck",
3796         .prcm = {
3797                 .omap4 = {
3798                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3799                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3800                         .modulemode   = MODULEMODE_SWCTRL,
3801                 },
3802         },
3803 };
3804
3805 /* wd_timer3 */
3806 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3807         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3808         { .irq = -1 }
3809 };
3810
3811 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3812         .name           = "wd_timer3",
3813         .class          = &omap44xx_wd_timer_hwmod_class,
3814         .clkdm_name     = "abe_clkdm",
3815         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3816         .main_clk       = "wd_timer3_fck",
3817         .prcm = {
3818                 .omap4 = {
3819                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3820                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3821                         .modulemode   = MODULEMODE_SWCTRL,
3822                 },
3823         },
3824 };
3825
3826
3827 /*
3828  * interfaces
3829  */
3830
3831 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3832         {
3833                 .pa_start       = 0x4a204000,
3834                 .pa_end         = 0x4a2040ff,
3835                 .flags          = ADDR_TYPE_RT
3836         },
3837         { }
3838 };
3839
3840 /* c2c -> c2c_target_fw */
3841 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3842         .master         = &omap44xx_c2c_hwmod,
3843         .slave          = &omap44xx_c2c_target_fw_hwmod,
3844         .clk            = "div_core_ck",
3845         .addr           = omap44xx_c2c_target_fw_addrs,
3846         .user           = OCP_USER_MPU,
3847 };
3848
3849 /* l4_cfg -> c2c_target_fw */
3850 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3851         .master         = &omap44xx_l4_cfg_hwmod,
3852         .slave          = &omap44xx_c2c_target_fw_hwmod,
3853         .clk            = "l4_div_ck",
3854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3855 };
3856
3857 /* l3_main_1 -> dmm */
3858 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3859         .master         = &omap44xx_l3_main_1_hwmod,
3860         .slave          = &omap44xx_dmm_hwmod,
3861         .clk            = "l3_div_ck",
3862         .user           = OCP_USER_SDMA,
3863 };
3864
3865 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3866         {
3867                 .pa_start       = 0x4e000000,
3868                 .pa_end         = 0x4e0007ff,
3869                 .flags          = ADDR_TYPE_RT
3870         },
3871         { }
3872 };
3873
3874 /* mpu -> dmm */
3875 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3876         .master         = &omap44xx_mpu_hwmod,
3877         .slave          = &omap44xx_dmm_hwmod,
3878         .clk            = "l3_div_ck",
3879         .addr           = omap44xx_dmm_addrs,
3880         .user           = OCP_USER_MPU,
3881 };
3882
3883 /* c2c -> emif_fw */
3884 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3885         .master         = &omap44xx_c2c_hwmod,
3886         .slave          = &omap44xx_emif_fw_hwmod,
3887         .clk            = "div_core_ck",
3888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3889 };
3890
3891 /* dmm -> emif_fw */
3892 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3893         .master         = &omap44xx_dmm_hwmod,
3894         .slave          = &omap44xx_emif_fw_hwmod,
3895         .clk            = "l3_div_ck",
3896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3897 };
3898
3899 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3900         {
3901                 .pa_start       = 0x4a20c000,
3902                 .pa_end         = 0x4a20c0ff,
3903                 .flags          = ADDR_TYPE_RT
3904         },
3905         { }
3906 };
3907
3908 /* l4_cfg -> emif_fw */
3909 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3910         .master         = &omap44xx_l4_cfg_hwmod,
3911         .slave          = &omap44xx_emif_fw_hwmod,
3912         .clk            = "l4_div_ck",
3913         .addr           = omap44xx_emif_fw_addrs,
3914         .user           = OCP_USER_MPU,
3915 };
3916
3917 /* iva -> l3_instr */
3918 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3919         .master         = &omap44xx_iva_hwmod,
3920         .slave          = &omap44xx_l3_instr_hwmod,
3921         .clk            = "l3_div_ck",
3922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3923 };
3924
3925 /* l3_main_3 -> l3_instr */
3926 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3927         .master         = &omap44xx_l3_main_3_hwmod,
3928         .slave          = &omap44xx_l3_instr_hwmod,
3929         .clk            = "l3_div_ck",
3930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3931 };
3932
3933 /* ocp_wp_noc -> l3_instr */
3934 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3935         .master         = &omap44xx_ocp_wp_noc_hwmod,
3936         .slave          = &omap44xx_l3_instr_hwmod,
3937         .clk            = "l3_div_ck",
3938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3939 };
3940
3941 /* dsp -> l3_main_1 */
3942 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3943         .master         = &omap44xx_dsp_hwmod,
3944         .slave          = &omap44xx_l3_main_1_hwmod,
3945         .clk            = "l3_div_ck",
3946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3947 };
3948
3949 /* dss -> l3_main_1 */
3950 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3951         .master         = &omap44xx_dss_hwmod,
3952         .slave          = &omap44xx_l3_main_1_hwmod,
3953         .clk            = "l3_div_ck",
3954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3955 };
3956
3957 /* l3_main_2 -> l3_main_1 */
3958 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3959         .master         = &omap44xx_l3_main_2_hwmod,
3960         .slave          = &omap44xx_l3_main_1_hwmod,
3961         .clk            = "l3_div_ck",
3962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3963 };
3964
3965 /* l4_cfg -> l3_main_1 */
3966 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3967         .master         = &omap44xx_l4_cfg_hwmod,
3968         .slave          = &omap44xx_l3_main_1_hwmod,
3969         .clk            = "l4_div_ck",
3970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3971 };
3972
3973 /* mmc1 -> l3_main_1 */
3974 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3975         .master         = &omap44xx_mmc1_hwmod,
3976         .slave          = &omap44xx_l3_main_1_hwmod,
3977         .clk            = "l3_div_ck",
3978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3979 };
3980
3981 /* mmc2 -> l3_main_1 */
3982 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3983         .master         = &omap44xx_mmc2_hwmod,
3984         .slave          = &omap44xx_l3_main_1_hwmod,
3985         .clk            = "l3_div_ck",
3986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3990         {
3991                 .pa_start       = 0x44000000,
3992                 .pa_end         = 0x44000fff,
3993                 .flags          = ADDR_TYPE_RT
3994         },
3995         { }
3996 };
3997
3998 /* mpu -> l3_main_1 */
3999 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4000         .master         = &omap44xx_mpu_hwmod,
4001         .slave          = &omap44xx_l3_main_1_hwmod,
4002         .clk            = "l3_div_ck",
4003         .addr           = omap44xx_l3_main_1_addrs,
4004         .user           = OCP_USER_MPU,
4005 };
4006
4007 /* c2c_target_fw -> l3_main_2 */
4008 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4009         .master         = &omap44xx_c2c_target_fw_hwmod,
4010         .slave          = &omap44xx_l3_main_2_hwmod,
4011         .clk            = "l3_div_ck",
4012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4013 };
4014
4015 /* debugss -> l3_main_2 */
4016 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4017         .master         = &omap44xx_debugss_hwmod,
4018         .slave          = &omap44xx_l3_main_2_hwmod,
4019         .clk            = "dbgclk_mux_ck",
4020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4021 };
4022
4023 /* dma_system -> l3_main_2 */
4024 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4025         .master         = &omap44xx_dma_system_hwmod,
4026         .slave          = &omap44xx_l3_main_2_hwmod,
4027         .clk            = "l3_div_ck",
4028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4029 };
4030
4031 /* fdif -> l3_main_2 */
4032 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4033         .master         = &omap44xx_fdif_hwmod,
4034         .slave          = &omap44xx_l3_main_2_hwmod,
4035         .clk            = "l3_div_ck",
4036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4037 };
4038
4039 /* gpu -> l3_main_2 */
4040 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4041         .master         = &omap44xx_gpu_hwmod,
4042         .slave          = &omap44xx_l3_main_2_hwmod,
4043         .clk            = "l3_div_ck",
4044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4045 };
4046
4047 /* hsi -> l3_main_2 */
4048 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4049         .master         = &omap44xx_hsi_hwmod,
4050         .slave          = &omap44xx_l3_main_2_hwmod,
4051         .clk            = "l3_div_ck",
4052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4053 };
4054
4055 /* ipu -> l3_main_2 */
4056 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4057         .master         = &omap44xx_ipu_hwmod,
4058         .slave          = &omap44xx_l3_main_2_hwmod,
4059         .clk            = "l3_div_ck",
4060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4061 };
4062
4063 /* iss -> l3_main_2 */
4064 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4065         .master         = &omap44xx_iss_hwmod,
4066         .slave          = &omap44xx_l3_main_2_hwmod,
4067         .clk            = "l3_div_ck",
4068         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4069 };
4070
4071 /* iva -> l3_main_2 */
4072 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4073         .master         = &omap44xx_iva_hwmod,
4074         .slave          = &omap44xx_l3_main_2_hwmod,
4075         .clk            = "l3_div_ck",
4076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4077 };
4078
4079 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4080         {
4081                 .pa_start       = 0x44800000,
4082                 .pa_end         = 0x44801fff,
4083                 .flags          = ADDR_TYPE_RT
4084         },
4085         { }
4086 };
4087
4088 /* l3_main_1 -> l3_main_2 */
4089 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4090         .master         = &omap44xx_l3_main_1_hwmod,
4091         .slave          = &omap44xx_l3_main_2_hwmod,
4092         .clk            = "l3_div_ck",
4093         .addr           = omap44xx_l3_main_2_addrs,
4094         .user           = OCP_USER_MPU,
4095 };
4096
4097 /* l4_cfg -> l3_main_2 */
4098 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4099         .master         = &omap44xx_l4_cfg_hwmod,
4100         .slave          = &omap44xx_l3_main_2_hwmod,
4101         .clk            = "l4_div_ck",
4102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4103 };
4104
4105 /* usb_host_fs -> l3_main_2 */
4106 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4107         .master         = &omap44xx_usb_host_fs_hwmod,
4108         .slave          = &omap44xx_l3_main_2_hwmod,
4109         .clk            = "l3_div_ck",
4110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4111 };
4112
4113 /* usb_host_hs -> l3_main_2 */
4114 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4115         .master         = &omap44xx_usb_host_hs_hwmod,
4116         .slave          = &omap44xx_l3_main_2_hwmod,
4117         .clk            = "l3_div_ck",
4118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4119 };
4120
4121 /* usb_otg_hs -> l3_main_2 */
4122 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4123         .master         = &omap44xx_usb_otg_hs_hwmod,
4124         .slave          = &omap44xx_l3_main_2_hwmod,
4125         .clk            = "l3_div_ck",
4126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4127 };
4128
4129 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4130         {
4131                 .pa_start       = 0x45000000,
4132                 .pa_end         = 0x45000fff,
4133                 .flags          = ADDR_TYPE_RT
4134         },
4135         { }
4136 };
4137
4138 /* l3_main_1 -> l3_main_3 */
4139 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4140         .master         = &omap44xx_l3_main_1_hwmod,
4141         .slave          = &omap44xx_l3_main_3_hwmod,
4142         .clk            = "l3_div_ck",
4143         .addr           = omap44xx_l3_main_3_addrs,
4144         .user           = OCP_USER_MPU,
4145 };
4146
4147 /* l3_main_2 -> l3_main_3 */
4148 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4149         .master         = &omap44xx_l3_main_2_hwmod,
4150         .slave          = &omap44xx_l3_main_3_hwmod,
4151         .clk            = "l3_div_ck",
4152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4154
4155 /* l4_cfg -> l3_main_3 */
4156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4157         .master         = &omap44xx_l4_cfg_hwmod,
4158         .slave          = &omap44xx_l3_main_3_hwmod,
4159         .clk            = "l4_div_ck",
4160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4161 };
4162
4163 /* aess -> l4_abe */
4164 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4165         .master         = &omap44xx_aess_hwmod,
4166         .slave          = &omap44xx_l4_abe_hwmod,
4167         .clk            = "ocp_abe_iclk",
4168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4169 };
4170
4171 /* dsp -> l4_abe */
4172 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4173         .master         = &omap44xx_dsp_hwmod,
4174         .slave          = &omap44xx_l4_abe_hwmod,
4175         .clk            = "ocp_abe_iclk",
4176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4177 };
4178
4179 /* l3_main_1 -> l4_abe */
4180 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4181         .master         = &omap44xx_l3_main_1_hwmod,
4182         .slave          = &omap44xx_l4_abe_hwmod,
4183         .clk            = "l3_div_ck",
4184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4185 };
4186
4187 /* mpu -> l4_abe */
4188 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4189         .master         = &omap44xx_mpu_hwmod,
4190         .slave          = &omap44xx_l4_abe_hwmod,
4191         .clk            = "ocp_abe_iclk",
4192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4193 };
4194
4195 /* l3_main_1 -> l4_cfg */
4196 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4197         .master         = &omap44xx_l3_main_1_hwmod,
4198         .slave          = &omap44xx_l4_cfg_hwmod,
4199         .clk            = "l3_div_ck",
4200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4201 };
4202
4203 /* l3_main_2 -> l4_per */
4204 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4205         .master         = &omap44xx_l3_main_2_hwmod,
4206         .slave          = &omap44xx_l4_per_hwmod,
4207         .clk            = "l3_div_ck",
4208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4209 };
4210
4211 /* l4_cfg -> l4_wkup */
4212 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4213         .master         = &omap44xx_l4_cfg_hwmod,
4214         .slave          = &omap44xx_l4_wkup_hwmod,
4215         .clk            = "l4_div_ck",
4216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4217 };
4218
4219 /* mpu -> mpu_private */
4220 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4221         .master         = &omap44xx_mpu_hwmod,
4222         .slave          = &omap44xx_mpu_private_hwmod,
4223         .clk            = "l3_div_ck",
4224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4225 };
4226
4227 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4228         {
4229                 .pa_start       = 0x4a102000,
4230                 .pa_end         = 0x4a10207f,
4231                 .flags          = ADDR_TYPE_RT
4232         },
4233         { }
4234 };
4235
4236 /* l4_cfg -> ocp_wp_noc */
4237 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4238         .master         = &omap44xx_l4_cfg_hwmod,
4239         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4240         .clk            = "l4_div_ck",
4241         .addr           = omap44xx_ocp_wp_noc_addrs,
4242         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4244
4245 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4246         {
4247                 .pa_start       = 0x401f1000,
4248                 .pa_end         = 0x401f13ff,
4249                 .flags          = ADDR_TYPE_RT
4250         },
4251         { }
4252 };
4253
4254 /* l4_abe -> aess */
4255 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4256         .master         = &omap44xx_l4_abe_hwmod,
4257         .slave          = &omap44xx_aess_hwmod,
4258         .clk            = "ocp_abe_iclk",
4259         .addr           = omap44xx_aess_addrs,
4260         .user           = OCP_USER_MPU,
4261 };
4262
4263 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4264         {
4265                 .pa_start       = 0x490f1000,
4266                 .pa_end         = 0x490f13ff,
4267                 .flags          = ADDR_TYPE_RT
4268         },
4269         { }
4270 };
4271
4272 /* l4_abe -> aess (dma) */
4273 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4274         .master         = &omap44xx_l4_abe_hwmod,
4275         .slave          = &omap44xx_aess_hwmod,
4276         .clk            = "ocp_abe_iclk",
4277         .addr           = omap44xx_aess_dma_addrs,
4278         .user           = OCP_USER_SDMA,
4279 };
4280
4281 /* l3_main_2 -> c2c */
4282 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4283         .master         = &omap44xx_l3_main_2_hwmod,
4284         .slave          = &omap44xx_c2c_hwmod,
4285         .clk            = "l3_div_ck",
4286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4287 };
4288
4289 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4290         {
4291                 .pa_start       = 0x4a304000,
4292                 .pa_end         = 0x4a30401f,
4293                 .flags          = ADDR_TYPE_RT
4294         },
4295         { }
4296 };
4297
4298 /* l4_wkup -> counter_32k */
4299 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4300         .master         = &omap44xx_l4_wkup_hwmod,
4301         .slave          = &omap44xx_counter_32k_hwmod,
4302         .clk            = "l4_wkup_clk_mux_ck",
4303         .addr           = omap44xx_counter_32k_addrs,
4304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4305 };
4306
4307 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4308         {
4309                 .pa_start       = 0x4a002000,
4310                 .pa_end         = 0x4a0027ff,
4311                 .flags          = ADDR_TYPE_RT
4312         },
4313         { }
4314 };
4315
4316 /* l4_cfg -> ctrl_module_core */
4317 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4318         .master         = &omap44xx_l4_cfg_hwmod,
4319         .slave          = &omap44xx_ctrl_module_core_hwmod,
4320         .clk            = "l4_div_ck",
4321         .addr           = omap44xx_ctrl_module_core_addrs,
4322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4323 };
4324
4325 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4326         {
4327                 .pa_start       = 0x4a100000,
4328                 .pa_end         = 0x4a1007ff,
4329                 .flags          = ADDR_TYPE_RT
4330         },
4331         { }
4332 };
4333
4334 /* l4_cfg -> ctrl_module_pad_core */
4335 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4336         .master         = &omap44xx_l4_cfg_hwmod,
4337         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4338         .clk            = "l4_div_ck",
4339         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4340         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4341 };
4342
4343 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4344         {
4345                 .pa_start       = 0x4a30c000,
4346                 .pa_end         = 0x4a30c7ff,
4347                 .flags          = ADDR_TYPE_RT
4348         },
4349         { }
4350 };
4351
4352 /* l4_wkup -> ctrl_module_wkup */
4353 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4354         .master         = &omap44xx_l4_wkup_hwmod,
4355         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4356         .clk            = "l4_wkup_clk_mux_ck",
4357         .addr           = omap44xx_ctrl_module_wkup_addrs,
4358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4359 };
4360
4361 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4362         {
4363                 .pa_start       = 0x4a31e000,
4364                 .pa_end         = 0x4a31e7ff,
4365                 .flags          = ADDR_TYPE_RT
4366         },
4367         { }
4368 };
4369
4370 /* l4_wkup -> ctrl_module_pad_wkup */
4371 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4372         .master         = &omap44xx_l4_wkup_hwmod,
4373         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4374         .clk            = "l4_wkup_clk_mux_ck",
4375         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4376         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4380         {
4381                 .pa_start       = 0x54160000,
4382                 .pa_end         = 0x54167fff,
4383                 .flags          = ADDR_TYPE_RT
4384         },
4385         { }
4386 };
4387
4388 /* l3_instr -> debugss */
4389 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4390         .master         = &omap44xx_l3_instr_hwmod,
4391         .slave          = &omap44xx_debugss_hwmod,
4392         .clk            = "l3_div_ck",
4393         .addr           = omap44xx_debugss_addrs,
4394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4398         {
4399                 .pa_start       = 0x4a056000,
4400                 .pa_end         = 0x4a056fff,
4401                 .flags          = ADDR_TYPE_RT
4402         },
4403         { }
4404 };
4405
4406 /* l4_cfg -> dma_system */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4408         .master         = &omap44xx_l4_cfg_hwmod,
4409         .slave          = &omap44xx_dma_system_hwmod,
4410         .clk            = "l4_div_ck",
4411         .addr           = omap44xx_dma_system_addrs,
4412         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4416         {
4417                 .name           = "mpu",
4418                 .pa_start       = 0x4012e000,
4419                 .pa_end         = 0x4012e07f,
4420                 .flags          = ADDR_TYPE_RT
4421         },
4422         { }
4423 };
4424
4425 /* l4_abe -> dmic */
4426 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4427         .master         = &omap44xx_l4_abe_hwmod,
4428         .slave          = &omap44xx_dmic_hwmod,
4429         .clk            = "ocp_abe_iclk",
4430         .addr           = omap44xx_dmic_addrs,
4431         .user           = OCP_USER_MPU,
4432 };
4433
4434 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4435         {
4436                 .name           = "dma",
4437                 .pa_start       = 0x4902e000,
4438                 .pa_end         = 0x4902e07f,
4439                 .flags          = ADDR_TYPE_RT
4440         },
4441         { }
4442 };
4443
4444 /* l4_abe -> dmic (dma) */
4445 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4446         .master         = &omap44xx_l4_abe_hwmod,
4447         .slave          = &omap44xx_dmic_hwmod,
4448         .clk            = "ocp_abe_iclk",
4449         .addr           = omap44xx_dmic_dma_addrs,
4450         .user           = OCP_USER_SDMA,
4451 };
4452
4453 /* dsp -> iva */
4454 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4455         .master         = &omap44xx_dsp_hwmod,
4456         .slave          = &omap44xx_iva_hwmod,
4457         .clk            = "dpll_iva_m5x2_ck",
4458         .user           = OCP_USER_DSP,
4459 };
4460
4461 /* dsp -> sl2if */
4462 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4463         .master         = &omap44xx_dsp_hwmod,
4464         .slave          = &omap44xx_sl2if_hwmod,
4465         .clk            = "dpll_iva_m5x2_ck",
4466         .user           = OCP_USER_DSP,
4467 };
4468
4469 /* l4_cfg -> dsp */
4470 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4471         .master         = &omap44xx_l4_cfg_hwmod,
4472         .slave          = &omap44xx_dsp_hwmod,
4473         .clk            = "l4_div_ck",
4474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4475 };
4476
4477 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4478         {
4479                 .pa_start       = 0x58000000,
4480                 .pa_end         = 0x5800007f,
4481                 .flags          = ADDR_TYPE_RT
4482         },
4483         { }
4484 };
4485
4486 /* l3_main_2 -> dss */
4487 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4488         .master         = &omap44xx_l3_main_2_hwmod,
4489         .slave          = &omap44xx_dss_hwmod,
4490         .clk            = "dss_fck",
4491         .addr           = omap44xx_dss_dma_addrs,
4492         .user           = OCP_USER_SDMA,
4493 };
4494
4495 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4496         {
4497                 .pa_start       = 0x48040000,
4498                 .pa_end         = 0x4804007f,
4499                 .flags          = ADDR_TYPE_RT
4500         },
4501         { }
4502 };
4503
4504 /* l4_per -> dss */
4505 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4506         .master         = &omap44xx_l4_per_hwmod,
4507         .slave          = &omap44xx_dss_hwmod,
4508         .clk            = "l4_div_ck",
4509         .addr           = omap44xx_dss_addrs,
4510         .user           = OCP_USER_MPU,
4511 };
4512
4513 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4514         {
4515                 .pa_start       = 0x58001000,
4516                 .pa_end         = 0x58001fff,
4517                 .flags          = ADDR_TYPE_RT
4518         },
4519         { }
4520 };
4521
4522 /* l3_main_2 -> dss_dispc */
4523 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4524         .master         = &omap44xx_l3_main_2_hwmod,
4525         .slave          = &omap44xx_dss_dispc_hwmod,
4526         .clk            = "dss_fck",
4527         .addr           = omap44xx_dss_dispc_dma_addrs,
4528         .user           = OCP_USER_SDMA,
4529 };
4530
4531 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4532         {
4533                 .pa_start       = 0x48041000,
4534                 .pa_end         = 0x48041fff,
4535                 .flags          = ADDR_TYPE_RT
4536         },
4537         { }
4538 };
4539
4540 /* l4_per -> dss_dispc */
4541 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4542         .master         = &omap44xx_l4_per_hwmod,
4543         .slave          = &omap44xx_dss_dispc_hwmod,
4544         .clk            = "l4_div_ck",
4545         .addr           = omap44xx_dss_dispc_addrs,
4546         .user           = OCP_USER_MPU,
4547 };
4548
4549 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4550         {
4551                 .pa_start       = 0x58004000,
4552                 .pa_end         = 0x580041ff,
4553                 .flags          = ADDR_TYPE_RT
4554         },
4555         { }
4556 };
4557
4558 /* l3_main_2 -> dss_dsi1 */
4559 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4560         .master         = &omap44xx_l3_main_2_hwmod,
4561         .slave          = &omap44xx_dss_dsi1_hwmod,
4562         .clk            = "dss_fck",
4563         .addr           = omap44xx_dss_dsi1_dma_addrs,
4564         .user           = OCP_USER_SDMA,
4565 };
4566
4567 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4568         {
4569                 .pa_start       = 0x48044000,
4570                 .pa_end         = 0x480441ff,
4571                 .flags          = ADDR_TYPE_RT
4572         },
4573         { }
4574 };
4575
4576 /* l4_per -> dss_dsi1 */
4577 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4578         .master         = &omap44xx_l4_per_hwmod,
4579         .slave          = &omap44xx_dss_dsi1_hwmod,
4580         .clk            = "l4_div_ck",
4581         .addr           = omap44xx_dss_dsi1_addrs,
4582         .user           = OCP_USER_MPU,
4583 };
4584
4585 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4586         {
4587                 .pa_start       = 0x58005000,
4588                 .pa_end         = 0x580051ff,
4589                 .flags          = ADDR_TYPE_RT
4590         },
4591         { }
4592 };
4593
4594 /* l3_main_2 -> dss_dsi2 */
4595 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4596         .master         = &omap44xx_l3_main_2_hwmod,
4597         .slave          = &omap44xx_dss_dsi2_hwmod,
4598         .clk            = "dss_fck",
4599         .addr           = omap44xx_dss_dsi2_dma_addrs,
4600         .user           = OCP_USER_SDMA,
4601 };
4602
4603 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4604         {
4605                 .pa_start       = 0x48045000,
4606                 .pa_end         = 0x480451ff,
4607                 .flags          = ADDR_TYPE_RT
4608         },
4609         { }
4610 };
4611
4612 /* l4_per -> dss_dsi2 */
4613 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4614         .master         = &omap44xx_l4_per_hwmod,
4615         .slave          = &omap44xx_dss_dsi2_hwmod,
4616         .clk            = "l4_div_ck",
4617         .addr           = omap44xx_dss_dsi2_addrs,
4618         .user           = OCP_USER_MPU,
4619 };
4620
4621 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4622         {
4623                 .pa_start       = 0x58006000,
4624                 .pa_end         = 0x58006fff,
4625                 .flags          = ADDR_TYPE_RT
4626         },
4627         { }
4628 };
4629
4630 /* l3_main_2 -> dss_hdmi */
4631 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4632         .master         = &omap44xx_l3_main_2_hwmod,
4633         .slave          = &omap44xx_dss_hdmi_hwmod,
4634         .clk            = "dss_fck",
4635         .addr           = omap44xx_dss_hdmi_dma_addrs,
4636         .user           = OCP_USER_SDMA,
4637 };
4638
4639 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4640         {
4641                 .pa_start       = 0x48046000,
4642                 .pa_end         = 0x48046fff,
4643                 .flags          = ADDR_TYPE_RT
4644         },
4645         { }
4646 };
4647
4648 /* l4_per -> dss_hdmi */
4649 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4650         .master         = &omap44xx_l4_per_hwmod,
4651         .slave          = &omap44xx_dss_hdmi_hwmod,
4652         .clk            = "l4_div_ck",
4653         .addr           = omap44xx_dss_hdmi_addrs,
4654         .user           = OCP_USER_MPU,
4655 };
4656
4657 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4658         {
4659                 .pa_start       = 0x58002000,
4660                 .pa_end         = 0x580020ff,
4661                 .flags          = ADDR_TYPE_RT
4662         },
4663         { }
4664 };
4665
4666 /* l3_main_2 -> dss_rfbi */
4667 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4668         .master         = &omap44xx_l3_main_2_hwmod,
4669         .slave          = &omap44xx_dss_rfbi_hwmod,
4670         .clk            = "dss_fck",
4671         .addr           = omap44xx_dss_rfbi_dma_addrs,
4672         .user           = OCP_USER_SDMA,
4673 };
4674
4675 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4676         {
4677                 .pa_start       = 0x48042000,
4678                 .pa_end         = 0x480420ff,
4679                 .flags          = ADDR_TYPE_RT
4680         },
4681         { }
4682 };
4683
4684 /* l4_per -> dss_rfbi */
4685 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4686         .master         = &omap44xx_l4_per_hwmod,
4687         .slave          = &omap44xx_dss_rfbi_hwmod,
4688         .clk            = "l4_div_ck",
4689         .addr           = omap44xx_dss_rfbi_addrs,
4690         .user           = OCP_USER_MPU,
4691 };
4692
4693 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4694         {
4695                 .pa_start       = 0x58003000,
4696                 .pa_end         = 0x580030ff,
4697                 .flags          = ADDR_TYPE_RT
4698         },
4699         { }
4700 };
4701
4702 /* l3_main_2 -> dss_venc */
4703 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4704         .master         = &omap44xx_l3_main_2_hwmod,
4705         .slave          = &omap44xx_dss_venc_hwmod,
4706         .clk            = "dss_fck",
4707         .addr           = omap44xx_dss_venc_dma_addrs,
4708         .user           = OCP_USER_SDMA,
4709 };
4710
4711 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4712         {
4713                 .pa_start       = 0x48043000,
4714                 .pa_end         = 0x480430ff,
4715                 .flags          = ADDR_TYPE_RT
4716         },
4717         { }
4718 };
4719
4720 /* l4_per -> dss_venc */
4721 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4722         .master         = &omap44xx_l4_per_hwmod,
4723         .slave          = &omap44xx_dss_venc_hwmod,
4724         .clk            = "l4_div_ck",
4725         .addr           = omap44xx_dss_venc_addrs,
4726         .user           = OCP_USER_MPU,
4727 };
4728
4729 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4730         {
4731                 .pa_start       = 0x48078000,
4732                 .pa_end         = 0x48078fff,
4733                 .flags          = ADDR_TYPE_RT
4734         },
4735         { }
4736 };
4737
4738 /* l4_per -> elm */
4739 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4740         .master         = &omap44xx_l4_per_hwmod,
4741         .slave          = &omap44xx_elm_hwmod,
4742         .clk            = "l4_div_ck",
4743         .addr           = omap44xx_elm_addrs,
4744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4745 };
4746
4747 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4748         {
4749                 .pa_start       = 0x4c000000,
4750                 .pa_end         = 0x4c0000ff,
4751                 .flags          = ADDR_TYPE_RT
4752         },
4753         { }
4754 };
4755
4756 /* emif_fw -> emif1 */
4757 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4758         .master         = &omap44xx_emif_fw_hwmod,
4759         .slave          = &omap44xx_emif1_hwmod,
4760         .clk            = "l3_div_ck",
4761         .addr           = omap44xx_emif1_addrs,
4762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4763 };
4764
4765 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4766         {
4767                 .pa_start       = 0x4d000000,
4768                 .pa_end         = 0x4d0000ff,
4769                 .flags          = ADDR_TYPE_RT
4770         },
4771         { }
4772 };
4773
4774 /* emif_fw -> emif2 */
4775 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4776         .master         = &omap44xx_emif_fw_hwmod,
4777         .slave          = &omap44xx_emif2_hwmod,
4778         .clk            = "l3_div_ck",
4779         .addr           = omap44xx_emif2_addrs,
4780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4781 };
4782
4783 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4784         {
4785                 .pa_start       = 0x4a10a000,
4786                 .pa_end         = 0x4a10a1ff,
4787                 .flags          = ADDR_TYPE_RT
4788         },
4789         { }
4790 };
4791
4792 /* l4_cfg -> fdif */
4793 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4794         .master         = &omap44xx_l4_cfg_hwmod,
4795         .slave          = &omap44xx_fdif_hwmod,
4796         .clk            = "l4_div_ck",
4797         .addr           = omap44xx_fdif_addrs,
4798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4799 };
4800
4801 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4802         {
4803                 .pa_start       = 0x4a310000,
4804                 .pa_end         = 0x4a3101ff,
4805                 .flags          = ADDR_TYPE_RT
4806         },
4807         { }
4808 };
4809
4810 /* l4_wkup -> gpio1 */
4811 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4812         .master         = &omap44xx_l4_wkup_hwmod,
4813         .slave          = &omap44xx_gpio1_hwmod,
4814         .clk            = "l4_wkup_clk_mux_ck",
4815         .addr           = omap44xx_gpio1_addrs,
4816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4817 };
4818
4819 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4820         {
4821                 .pa_start       = 0x48055000,
4822                 .pa_end         = 0x480551ff,
4823                 .flags          = ADDR_TYPE_RT
4824         },
4825         { }
4826 };
4827
4828 /* l4_per -> gpio2 */
4829 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4830         .master         = &omap44xx_l4_per_hwmod,
4831         .slave          = &omap44xx_gpio2_hwmod,
4832         .clk            = "l4_div_ck",
4833         .addr           = omap44xx_gpio2_addrs,
4834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4836
4837 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4838         {
4839                 .pa_start       = 0x48057000,
4840                 .pa_end         = 0x480571ff,
4841                 .flags          = ADDR_TYPE_RT
4842         },
4843         { }
4844 };
4845
4846 /* l4_per -> gpio3 */
4847 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4848         .master         = &omap44xx_l4_per_hwmod,
4849         .slave          = &omap44xx_gpio3_hwmod,
4850         .clk            = "l4_div_ck",
4851         .addr           = omap44xx_gpio3_addrs,
4852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4856         {
4857                 .pa_start       = 0x48059000,
4858                 .pa_end         = 0x480591ff,
4859                 .flags          = ADDR_TYPE_RT
4860         },
4861         { }
4862 };
4863
4864 /* l4_per -> gpio4 */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4866         .master         = &omap44xx_l4_per_hwmod,
4867         .slave          = &omap44xx_gpio4_hwmod,
4868         .clk            = "l4_div_ck",
4869         .addr           = omap44xx_gpio4_addrs,
4870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4874         {
4875                 .pa_start       = 0x4805b000,
4876                 .pa_end         = 0x4805b1ff,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879         { }
4880 };
4881
4882 /* l4_per -> gpio5 */
4883 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4884         .master         = &omap44xx_l4_per_hwmod,
4885         .slave          = &omap44xx_gpio5_hwmod,
4886         .clk            = "l4_div_ck",
4887         .addr           = omap44xx_gpio5_addrs,
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4892         {
4893                 .pa_start       = 0x4805d000,
4894                 .pa_end         = 0x4805d1ff,
4895                 .flags          = ADDR_TYPE_RT
4896         },
4897         { }
4898 };
4899
4900 /* l4_per -> gpio6 */
4901 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4902         .master         = &omap44xx_l4_per_hwmod,
4903         .slave          = &omap44xx_gpio6_hwmod,
4904         .clk            = "l4_div_ck",
4905         .addr           = omap44xx_gpio6_addrs,
4906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4907 };
4908
4909 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4910         {
4911                 .pa_start       = 0x50000000,
4912                 .pa_end         = 0x500003ff,
4913                 .flags          = ADDR_TYPE_RT
4914         },
4915         { }
4916 };
4917
4918 /* l3_main_2 -> gpmc */
4919 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4920         .master         = &omap44xx_l3_main_2_hwmod,
4921         .slave          = &omap44xx_gpmc_hwmod,
4922         .clk            = "l3_div_ck",
4923         .addr           = omap44xx_gpmc_addrs,
4924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4928         {
4929                 .pa_start       = 0x56000000,
4930                 .pa_end         = 0x5600ffff,
4931                 .flags          = ADDR_TYPE_RT
4932         },
4933         { }
4934 };
4935
4936 /* l3_main_2 -> gpu */
4937 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4938         .master         = &omap44xx_l3_main_2_hwmod,
4939         .slave          = &omap44xx_gpu_hwmod,
4940         .clk            = "l3_div_ck",
4941         .addr           = omap44xx_gpu_addrs,
4942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4943 };
4944
4945 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4946         {
4947                 .pa_start       = 0x480b2000,
4948                 .pa_end         = 0x480b201f,
4949                 .flags          = ADDR_TYPE_RT
4950         },
4951         { }
4952 };
4953
4954 /* l4_per -> hdq1w */
4955 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4956         .master         = &omap44xx_l4_per_hwmod,
4957         .slave          = &omap44xx_hdq1w_hwmod,
4958         .clk            = "l4_div_ck",
4959         .addr           = omap44xx_hdq1w_addrs,
4960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4961 };
4962
4963 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4964         {
4965                 .pa_start       = 0x4a058000,
4966                 .pa_end         = 0x4a05bfff,
4967                 .flags          = ADDR_TYPE_RT
4968         },
4969         { }
4970 };
4971
4972 /* l4_cfg -> hsi */
4973 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4974         .master         = &omap44xx_l4_cfg_hwmod,
4975         .slave          = &omap44xx_hsi_hwmod,
4976         .clk            = "l4_div_ck",
4977         .addr           = omap44xx_hsi_addrs,
4978         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4979 };
4980
4981 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4982         {
4983                 .pa_start       = 0x48070000,
4984                 .pa_end         = 0x480700ff,
4985                 .flags          = ADDR_TYPE_RT
4986         },
4987         { }
4988 };
4989
4990 /* l4_per -> i2c1 */
4991 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4992         .master         = &omap44xx_l4_per_hwmod,
4993         .slave          = &omap44xx_i2c1_hwmod,
4994         .clk            = "l4_div_ck",
4995         .addr           = omap44xx_i2c1_addrs,
4996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4997 };
4998
4999 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5000         {
5001                 .pa_start       = 0x48072000,
5002                 .pa_end         = 0x480720ff,
5003                 .flags          = ADDR_TYPE_RT
5004         },
5005         { }
5006 };
5007
5008 /* l4_per -> i2c2 */
5009 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5010         .master         = &omap44xx_l4_per_hwmod,
5011         .slave          = &omap44xx_i2c2_hwmod,
5012         .clk            = "l4_div_ck",
5013         .addr           = omap44xx_i2c2_addrs,
5014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5015 };
5016
5017 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5018         {
5019                 .pa_start       = 0x48060000,
5020                 .pa_end         = 0x480600ff,
5021                 .flags          = ADDR_TYPE_RT
5022         },
5023         { }
5024 };
5025
5026 /* l4_per -> i2c3 */
5027 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5028         .master         = &omap44xx_l4_per_hwmod,
5029         .slave          = &omap44xx_i2c3_hwmod,
5030         .clk            = "l4_div_ck",
5031         .addr           = omap44xx_i2c3_addrs,
5032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5033 };
5034
5035 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5036         {
5037                 .pa_start       = 0x48350000,
5038                 .pa_end         = 0x483500ff,
5039                 .flags          = ADDR_TYPE_RT
5040         },
5041         { }
5042 };
5043
5044 /* l4_per -> i2c4 */
5045 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5046         .master         = &omap44xx_l4_per_hwmod,
5047         .slave          = &omap44xx_i2c4_hwmod,
5048         .clk            = "l4_div_ck",
5049         .addr           = omap44xx_i2c4_addrs,
5050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5051 };
5052
5053 /* l3_main_2 -> ipu */
5054 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5055         .master         = &omap44xx_l3_main_2_hwmod,
5056         .slave          = &omap44xx_ipu_hwmod,
5057         .clk            = "l3_div_ck",
5058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5059 };
5060
5061 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5062         {
5063                 .pa_start       = 0x52000000,
5064                 .pa_end         = 0x520000ff,
5065                 .flags          = ADDR_TYPE_RT
5066         },
5067         { }
5068 };
5069
5070 /* l3_main_2 -> iss */
5071 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5072         .master         = &omap44xx_l3_main_2_hwmod,
5073         .slave          = &omap44xx_iss_hwmod,
5074         .clk            = "l3_div_ck",
5075         .addr           = omap44xx_iss_addrs,
5076         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5077 };
5078
5079 /* iva -> sl2if */
5080 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5081         .master         = &omap44xx_iva_hwmod,
5082         .slave          = &omap44xx_sl2if_hwmod,
5083         .clk            = "dpll_iva_m5x2_ck",
5084         .user           = OCP_USER_IVA,
5085 };
5086
5087 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5088         {
5089                 .pa_start       = 0x5a000000,
5090                 .pa_end         = 0x5a07ffff,
5091                 .flags          = ADDR_TYPE_RT
5092         },
5093         { }
5094 };
5095
5096 /* l3_main_2 -> iva */
5097 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5098         .master         = &omap44xx_l3_main_2_hwmod,
5099         .slave          = &omap44xx_iva_hwmod,
5100         .clk            = "l3_div_ck",
5101         .addr           = omap44xx_iva_addrs,
5102         .user           = OCP_USER_MPU,
5103 };
5104
5105 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5106         {
5107                 .pa_start       = 0x4a31c000,
5108                 .pa_end         = 0x4a31c07f,
5109                 .flags          = ADDR_TYPE_RT
5110         },
5111         { }
5112 };
5113
5114 /* l4_wkup -> kbd */
5115 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5116         .master         = &omap44xx_l4_wkup_hwmod,
5117         .slave          = &omap44xx_kbd_hwmod,
5118         .clk            = "l4_wkup_clk_mux_ck",
5119         .addr           = omap44xx_kbd_addrs,
5120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5121 };
5122
5123 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5124         {
5125                 .pa_start       = 0x4a0f4000,
5126                 .pa_end         = 0x4a0f41ff,
5127                 .flags          = ADDR_TYPE_RT
5128         },
5129         { }
5130 };
5131
5132 /* l4_cfg -> mailbox */
5133 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5134         .master         = &omap44xx_l4_cfg_hwmod,
5135         .slave          = &omap44xx_mailbox_hwmod,
5136         .clk            = "l4_div_ck",
5137         .addr           = omap44xx_mailbox_addrs,
5138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5139 };
5140
5141 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5142         {
5143                 .pa_start       = 0x40128000,
5144                 .pa_end         = 0x401283ff,
5145                 .flags          = ADDR_TYPE_RT
5146         },
5147         { }
5148 };
5149
5150 /* l4_abe -> mcasp */
5151 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5152         .master         = &omap44xx_l4_abe_hwmod,
5153         .slave          = &omap44xx_mcasp_hwmod,
5154         .clk            = "ocp_abe_iclk",
5155         .addr           = omap44xx_mcasp_addrs,
5156         .user           = OCP_USER_MPU,
5157 };
5158
5159 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5160         {
5161                 .pa_start       = 0x49028000,
5162                 .pa_end         = 0x490283ff,
5163                 .flags          = ADDR_TYPE_RT
5164         },
5165         { }
5166 };
5167
5168 /* l4_abe -> mcasp (dma) */
5169 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5170         .master         = &omap44xx_l4_abe_hwmod,
5171         .slave          = &omap44xx_mcasp_hwmod,
5172         .clk            = "ocp_abe_iclk",
5173         .addr           = omap44xx_mcasp_dma_addrs,
5174         .user           = OCP_USER_SDMA,
5175 };
5176
5177 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5178         {
5179                 .name           = "mpu",
5180                 .pa_start       = 0x40122000,
5181                 .pa_end         = 0x401220ff,
5182                 .flags          = ADDR_TYPE_RT
5183         },
5184         { }
5185 };
5186
5187 /* l4_abe -> mcbsp1 */
5188 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5189         .master         = &omap44xx_l4_abe_hwmod,
5190         .slave          = &omap44xx_mcbsp1_hwmod,
5191         .clk            = "ocp_abe_iclk",
5192         .addr           = omap44xx_mcbsp1_addrs,
5193         .user           = OCP_USER_MPU,
5194 };
5195
5196 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5197         {
5198                 .name           = "dma",
5199                 .pa_start       = 0x49022000,
5200                 .pa_end         = 0x490220ff,
5201                 .flags          = ADDR_TYPE_RT
5202         },
5203         { }
5204 };
5205
5206 /* l4_abe -> mcbsp1 (dma) */
5207 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5208         .master         = &omap44xx_l4_abe_hwmod,
5209         .slave          = &omap44xx_mcbsp1_hwmod,
5210         .clk            = "ocp_abe_iclk",
5211         .addr           = omap44xx_mcbsp1_dma_addrs,
5212         .user           = OCP_USER_SDMA,
5213 };
5214
5215 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5216         {
5217                 .name           = "mpu",
5218                 .pa_start       = 0x40124000,
5219                 .pa_end         = 0x401240ff,
5220                 .flags          = ADDR_TYPE_RT
5221         },
5222         { }
5223 };
5224
5225 /* l4_abe -> mcbsp2 */
5226 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5227         .master         = &omap44xx_l4_abe_hwmod,
5228         .slave          = &omap44xx_mcbsp2_hwmod,
5229         .clk            = "ocp_abe_iclk",
5230         .addr           = omap44xx_mcbsp2_addrs,
5231         .user           = OCP_USER_MPU,
5232 };
5233
5234 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5235         {
5236                 .name           = "dma",
5237                 .pa_start       = 0x49024000,
5238                 .pa_end         = 0x490240ff,
5239                 .flags          = ADDR_TYPE_RT
5240         },
5241         { }
5242 };
5243
5244 /* l4_abe -> mcbsp2 (dma) */
5245 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5246         .master         = &omap44xx_l4_abe_hwmod,
5247         .slave          = &omap44xx_mcbsp2_hwmod,
5248         .clk            = "ocp_abe_iclk",
5249         .addr           = omap44xx_mcbsp2_dma_addrs,
5250         .user           = OCP_USER_SDMA,
5251 };
5252
5253 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5254         {
5255                 .name           = "mpu",
5256                 .pa_start       = 0x40126000,
5257                 .pa_end         = 0x401260ff,
5258                 .flags          = ADDR_TYPE_RT
5259         },
5260         { }
5261 };
5262
5263 /* l4_abe -> mcbsp3 */
5264 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5265         .master         = &omap44xx_l4_abe_hwmod,
5266         .slave          = &omap44xx_mcbsp3_hwmod,
5267         .clk            = "ocp_abe_iclk",
5268         .addr           = omap44xx_mcbsp3_addrs,
5269         .user           = OCP_USER_MPU,
5270 };
5271
5272 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5273         {
5274                 .name           = "dma",
5275                 .pa_start       = 0x49026000,
5276                 .pa_end         = 0x490260ff,
5277                 .flags          = ADDR_TYPE_RT
5278         },
5279         { }
5280 };
5281
5282 /* l4_abe -> mcbsp3 (dma) */
5283 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5284         .master         = &omap44xx_l4_abe_hwmod,
5285         .slave          = &omap44xx_mcbsp3_hwmod,
5286         .clk            = "ocp_abe_iclk",
5287         .addr           = omap44xx_mcbsp3_dma_addrs,
5288         .user           = OCP_USER_SDMA,
5289 };
5290
5291 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5292         {
5293                 .pa_start       = 0x48096000,
5294                 .pa_end         = 0x480960ff,
5295                 .flags          = ADDR_TYPE_RT
5296         },
5297         { }
5298 };
5299
5300 /* l4_per -> mcbsp4 */
5301 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5302         .master         = &omap44xx_l4_per_hwmod,
5303         .slave          = &omap44xx_mcbsp4_hwmod,
5304         .clk            = "l4_div_ck",
5305         .addr           = omap44xx_mcbsp4_addrs,
5306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5307 };
5308
5309 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5310         {
5311                 .name           = "mpu",
5312                 .pa_start       = 0x40132000,
5313                 .pa_end         = 0x4013207f,
5314                 .flags          = ADDR_TYPE_RT
5315         },
5316         { }
5317 };
5318
5319 /* l4_abe -> mcpdm */
5320 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5321         .master         = &omap44xx_l4_abe_hwmod,
5322         .slave          = &omap44xx_mcpdm_hwmod,
5323         .clk            = "ocp_abe_iclk",
5324         .addr           = omap44xx_mcpdm_addrs,
5325         .user           = OCP_USER_MPU,
5326 };
5327
5328 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5329         {
5330                 .name           = "dma",
5331                 .pa_start       = 0x49032000,
5332                 .pa_end         = 0x4903207f,
5333                 .flags          = ADDR_TYPE_RT
5334         },
5335         { }
5336 };
5337
5338 /* l4_abe -> mcpdm (dma) */
5339 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5340         .master         = &omap44xx_l4_abe_hwmod,
5341         .slave          = &omap44xx_mcpdm_hwmod,
5342         .clk            = "ocp_abe_iclk",
5343         .addr           = omap44xx_mcpdm_dma_addrs,
5344         .user           = OCP_USER_SDMA,
5345 };
5346
5347 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5348         {
5349                 .pa_start       = 0x48098000,
5350                 .pa_end         = 0x480981ff,
5351                 .flags          = ADDR_TYPE_RT
5352         },
5353         { }
5354 };
5355
5356 /* l4_per -> mcspi1 */
5357 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5358         .master         = &omap44xx_l4_per_hwmod,
5359         .slave          = &omap44xx_mcspi1_hwmod,
5360         .clk            = "l4_div_ck",
5361         .addr           = omap44xx_mcspi1_addrs,
5362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5363 };
5364
5365 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5366         {
5367                 .pa_start       = 0x4809a000,
5368                 .pa_end         = 0x4809a1ff,
5369                 .flags          = ADDR_TYPE_RT
5370         },
5371         { }
5372 };
5373
5374 /* l4_per -> mcspi2 */
5375 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5376         .master         = &omap44xx_l4_per_hwmod,
5377         .slave          = &omap44xx_mcspi2_hwmod,
5378         .clk            = "l4_div_ck",
5379         .addr           = omap44xx_mcspi2_addrs,
5380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5381 };
5382
5383 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5384         {
5385                 .pa_start       = 0x480b8000,
5386                 .pa_end         = 0x480b81ff,
5387                 .flags          = ADDR_TYPE_RT
5388         },
5389         { }
5390 };
5391
5392 /* l4_per -> mcspi3 */
5393 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5394         .master         = &omap44xx_l4_per_hwmod,
5395         .slave          = &omap44xx_mcspi3_hwmod,
5396         .clk            = "l4_div_ck",
5397         .addr           = omap44xx_mcspi3_addrs,
5398         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5399 };
5400
5401 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5402         {
5403                 .pa_start       = 0x480ba000,
5404                 .pa_end         = 0x480ba1ff,
5405                 .flags          = ADDR_TYPE_RT
5406         },
5407         { }
5408 };
5409
5410 /* l4_per -> mcspi4 */
5411 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5412         .master         = &omap44xx_l4_per_hwmod,
5413         .slave          = &omap44xx_mcspi4_hwmod,
5414         .clk            = "l4_div_ck",
5415         .addr           = omap44xx_mcspi4_addrs,
5416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5417 };
5418
5419 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5420         {
5421                 .pa_start       = 0x4809c000,
5422                 .pa_end         = 0x4809c3ff,
5423                 .flags          = ADDR_TYPE_RT
5424         },
5425         { }
5426 };
5427
5428 /* l4_per -> mmc1 */
5429 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5430         .master         = &omap44xx_l4_per_hwmod,
5431         .slave          = &omap44xx_mmc1_hwmod,
5432         .clk            = "l4_div_ck",
5433         .addr           = omap44xx_mmc1_addrs,
5434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5435 };
5436
5437 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5438         {
5439                 .pa_start       = 0x480b4000,
5440                 .pa_end         = 0x480b43ff,
5441                 .flags          = ADDR_TYPE_RT
5442         },
5443         { }
5444 };
5445
5446 /* l4_per -> mmc2 */
5447 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5448         .master         = &omap44xx_l4_per_hwmod,
5449         .slave          = &omap44xx_mmc2_hwmod,
5450         .clk            = "l4_div_ck",
5451         .addr           = omap44xx_mmc2_addrs,
5452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5453 };
5454
5455 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5456         {
5457                 .pa_start       = 0x480ad000,
5458                 .pa_end         = 0x480ad3ff,
5459                 .flags          = ADDR_TYPE_RT
5460         },
5461         { }
5462 };
5463
5464 /* l4_per -> mmc3 */
5465 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5466         .master         = &omap44xx_l4_per_hwmod,
5467         .slave          = &omap44xx_mmc3_hwmod,
5468         .clk            = "l4_div_ck",
5469         .addr           = omap44xx_mmc3_addrs,
5470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5471 };
5472
5473 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5474         {
5475                 .pa_start       = 0x480d1000,
5476                 .pa_end         = 0x480d13ff,
5477                 .flags          = ADDR_TYPE_RT
5478         },
5479         { }
5480 };
5481
5482 /* l4_per -> mmc4 */
5483 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5484         .master         = &omap44xx_l4_per_hwmod,
5485         .slave          = &omap44xx_mmc4_hwmod,
5486         .clk            = "l4_div_ck",
5487         .addr           = omap44xx_mmc4_addrs,
5488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5489 };
5490
5491 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5492         {
5493                 .pa_start       = 0x480d5000,
5494                 .pa_end         = 0x480d53ff,
5495                 .flags          = ADDR_TYPE_RT
5496         },
5497         { }
5498 };
5499
5500 /* l4_per -> mmc5 */
5501 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5502         .master         = &omap44xx_l4_per_hwmod,
5503         .slave          = &omap44xx_mmc5_hwmod,
5504         .clk            = "l4_div_ck",
5505         .addr           = omap44xx_mmc5_addrs,
5506         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5507 };
5508
5509 /* l3_main_2 -> ocmc_ram */
5510 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5511         .master         = &omap44xx_l3_main_2_hwmod,
5512         .slave          = &omap44xx_ocmc_ram_hwmod,
5513         .clk            = "l3_div_ck",
5514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5515 };
5516
5517 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5518         {
5519                 .pa_start       = 0x4a0ad000,
5520                 .pa_end         = 0x4a0ad01f,
5521                 .flags          = ADDR_TYPE_RT
5522         },
5523         { }
5524 };
5525
5526 /* l4_cfg -> ocp2scp_usb_phy */
5527 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5528         .master         = &omap44xx_l4_cfg_hwmod,
5529         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5530         .clk            = "l4_div_ck",
5531         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5533 };
5534
5535 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5536         {
5537                 .pa_start       = 0x48243000,
5538                 .pa_end         = 0x48243fff,
5539                 .flags          = ADDR_TYPE_RT
5540         },
5541         { }
5542 };
5543
5544 /* mpu_private -> prcm_mpu */
5545 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5546         .master         = &omap44xx_mpu_private_hwmod,
5547         .slave          = &omap44xx_prcm_mpu_hwmod,
5548         .clk            = "l3_div_ck",
5549         .addr           = omap44xx_prcm_mpu_addrs,
5550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5551 };
5552
5553 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5554         {
5555                 .pa_start       = 0x4a004000,
5556                 .pa_end         = 0x4a004fff,
5557                 .flags          = ADDR_TYPE_RT
5558         },
5559         { }
5560 };
5561
5562 /* l4_wkup -> cm_core_aon */
5563 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5564         .master         = &omap44xx_l4_wkup_hwmod,
5565         .slave          = &omap44xx_cm_core_aon_hwmod,
5566         .clk            = "l4_wkup_clk_mux_ck",
5567         .addr           = omap44xx_cm_core_aon_addrs,
5568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5569 };
5570
5571 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5572         {
5573                 .pa_start       = 0x4a008000,
5574                 .pa_end         = 0x4a009fff,
5575                 .flags          = ADDR_TYPE_RT
5576         },
5577         { }
5578 };
5579
5580 /* l4_cfg -> cm_core */
5581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5582         .master         = &omap44xx_l4_cfg_hwmod,
5583         .slave          = &omap44xx_cm_core_hwmod,
5584         .clk            = "l4_div_ck",
5585         .addr           = omap44xx_cm_core_addrs,
5586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5587 };
5588
5589 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5590         {
5591                 .pa_start       = 0x4a306000,
5592                 .pa_end         = 0x4a307fff,
5593                 .flags          = ADDR_TYPE_RT
5594         },
5595         { }
5596 };
5597
5598 /* l4_wkup -> prm */
5599 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5600         .master         = &omap44xx_l4_wkup_hwmod,
5601         .slave          = &omap44xx_prm_hwmod,
5602         .clk            = "l4_wkup_clk_mux_ck",
5603         .addr           = omap44xx_prm_addrs,
5604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5605 };
5606
5607 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5608         {
5609                 .pa_start       = 0x4a30a000,
5610                 .pa_end         = 0x4a30a7ff,
5611                 .flags          = ADDR_TYPE_RT
5612         },
5613         { }
5614 };
5615
5616 /* l4_wkup -> scrm */
5617 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5618         .master         = &omap44xx_l4_wkup_hwmod,
5619         .slave          = &omap44xx_scrm_hwmod,
5620         .clk            = "l4_wkup_clk_mux_ck",
5621         .addr           = omap44xx_scrm_addrs,
5622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5623 };
5624
5625 /* l3_main_2 -> sl2if */
5626 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5627         .master         = &omap44xx_l3_main_2_hwmod,
5628         .slave          = &omap44xx_sl2if_hwmod,
5629         .clk            = "l3_div_ck",
5630         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5631 };
5632
5633 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5634         {
5635                 .pa_start       = 0x4012c000,
5636                 .pa_end         = 0x4012c3ff,
5637                 .flags          = ADDR_TYPE_RT
5638         },
5639         { }
5640 };
5641
5642 /* l4_abe -> slimbus1 */
5643 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5644         .master         = &omap44xx_l4_abe_hwmod,
5645         .slave          = &omap44xx_slimbus1_hwmod,
5646         .clk            = "ocp_abe_iclk",
5647         .addr           = omap44xx_slimbus1_addrs,
5648         .user           = OCP_USER_MPU,
5649 };
5650
5651 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5652         {
5653                 .pa_start       = 0x4902c000,
5654                 .pa_end         = 0x4902c3ff,
5655                 .flags          = ADDR_TYPE_RT
5656         },
5657         { }
5658 };
5659
5660 /* l4_abe -> slimbus1 (dma) */
5661 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5662         .master         = &omap44xx_l4_abe_hwmod,
5663         .slave          = &omap44xx_slimbus1_hwmod,
5664         .clk            = "ocp_abe_iclk",
5665         .addr           = omap44xx_slimbus1_dma_addrs,
5666         .user           = OCP_USER_SDMA,
5667 };
5668
5669 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5670         {
5671                 .pa_start       = 0x48076000,
5672                 .pa_end         = 0x480763ff,
5673                 .flags          = ADDR_TYPE_RT
5674         },
5675         { }
5676 };
5677
5678 /* l4_per -> slimbus2 */
5679 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5680         .master         = &omap44xx_l4_per_hwmod,
5681         .slave          = &omap44xx_slimbus2_hwmod,
5682         .clk            = "l4_div_ck",
5683         .addr           = omap44xx_slimbus2_addrs,
5684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5685 };
5686
5687 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5688         {
5689                 .pa_start       = 0x4a0dd000,
5690                 .pa_end         = 0x4a0dd03f,
5691                 .flags          = ADDR_TYPE_RT
5692         },
5693         { }
5694 };
5695
5696 /* l4_cfg -> smartreflex_core */
5697 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5698         .master         = &omap44xx_l4_cfg_hwmod,
5699         .slave          = &omap44xx_smartreflex_core_hwmod,
5700         .clk            = "l4_div_ck",
5701         .addr           = omap44xx_smartreflex_core_addrs,
5702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5703 };
5704
5705 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5706         {
5707                 .pa_start       = 0x4a0db000,
5708                 .pa_end         = 0x4a0db03f,
5709                 .flags          = ADDR_TYPE_RT
5710         },
5711         { }
5712 };
5713
5714 /* l4_cfg -> smartreflex_iva */
5715 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5716         .master         = &omap44xx_l4_cfg_hwmod,
5717         .slave          = &omap44xx_smartreflex_iva_hwmod,
5718         .clk            = "l4_div_ck",
5719         .addr           = omap44xx_smartreflex_iva_addrs,
5720         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5721 };
5722
5723 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5724         {
5725                 .pa_start       = 0x4a0d9000,
5726                 .pa_end         = 0x4a0d903f,
5727                 .flags          = ADDR_TYPE_RT
5728         },
5729         { }
5730 };
5731
5732 /* l4_cfg -> smartreflex_mpu */
5733 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5734         .master         = &omap44xx_l4_cfg_hwmod,
5735         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5736         .clk            = "l4_div_ck",
5737         .addr           = omap44xx_smartreflex_mpu_addrs,
5738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5739 };
5740
5741 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5742         {
5743                 .pa_start       = 0x4a0f6000,
5744                 .pa_end         = 0x4a0f6fff,
5745                 .flags          = ADDR_TYPE_RT
5746         },
5747         { }
5748 };
5749
5750 /* l4_cfg -> spinlock */
5751 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5752         .master         = &omap44xx_l4_cfg_hwmod,
5753         .slave          = &omap44xx_spinlock_hwmod,
5754         .clk            = "l4_div_ck",
5755         .addr           = omap44xx_spinlock_addrs,
5756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5757 };
5758
5759 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5760         {
5761                 .pa_start       = 0x4a318000,
5762                 .pa_end         = 0x4a31807f,
5763                 .flags          = ADDR_TYPE_RT
5764         },
5765         { }
5766 };
5767
5768 /* l4_wkup -> timer1 */
5769 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5770         .master         = &omap44xx_l4_wkup_hwmod,
5771         .slave          = &omap44xx_timer1_hwmod,
5772         .clk            = "l4_wkup_clk_mux_ck",
5773         .addr           = omap44xx_timer1_addrs,
5774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5775 };
5776
5777 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5778         {
5779                 .pa_start       = 0x48032000,
5780                 .pa_end         = 0x4803207f,
5781                 .flags          = ADDR_TYPE_RT
5782         },
5783         { }
5784 };
5785
5786 /* l4_per -> timer2 */
5787 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5788         .master         = &omap44xx_l4_per_hwmod,
5789         .slave          = &omap44xx_timer2_hwmod,
5790         .clk            = "l4_div_ck",
5791         .addr           = omap44xx_timer2_addrs,
5792         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5793 };
5794
5795 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5796         {
5797                 .pa_start       = 0x48034000,
5798                 .pa_end         = 0x4803407f,
5799                 .flags          = ADDR_TYPE_RT
5800         },
5801         { }
5802 };
5803
5804 /* l4_per -> timer3 */
5805 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5806         .master         = &omap44xx_l4_per_hwmod,
5807         .slave          = &omap44xx_timer3_hwmod,
5808         .clk            = "l4_div_ck",
5809         .addr           = omap44xx_timer3_addrs,
5810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5811 };
5812
5813 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5814         {
5815                 .pa_start       = 0x48036000,
5816                 .pa_end         = 0x4803607f,
5817                 .flags          = ADDR_TYPE_RT
5818         },
5819         { }
5820 };
5821
5822 /* l4_per -> timer4 */
5823 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5824         .master         = &omap44xx_l4_per_hwmod,
5825         .slave          = &omap44xx_timer4_hwmod,
5826         .clk            = "l4_div_ck",
5827         .addr           = omap44xx_timer4_addrs,
5828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5829 };
5830
5831 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5832         {
5833                 .pa_start       = 0x40138000,
5834                 .pa_end         = 0x4013807f,
5835                 .flags          = ADDR_TYPE_RT
5836         },
5837         { }
5838 };
5839
5840 /* l4_abe -> timer5 */
5841 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5842         .master         = &omap44xx_l4_abe_hwmod,
5843         .slave          = &omap44xx_timer5_hwmod,
5844         .clk            = "ocp_abe_iclk",
5845         .addr           = omap44xx_timer5_addrs,
5846         .user           = OCP_USER_MPU,
5847 };
5848
5849 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5850         {
5851                 .pa_start       = 0x49038000,
5852                 .pa_end         = 0x4903807f,
5853                 .flags          = ADDR_TYPE_RT
5854         },
5855         { }
5856 };
5857
5858 /* l4_abe -> timer5 (dma) */
5859 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5860         .master         = &omap44xx_l4_abe_hwmod,
5861         .slave          = &omap44xx_timer5_hwmod,
5862         .clk            = "ocp_abe_iclk",
5863         .addr           = omap44xx_timer5_dma_addrs,
5864         .user           = OCP_USER_SDMA,
5865 };
5866
5867 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5868         {
5869                 .pa_start       = 0x4013a000,
5870                 .pa_end         = 0x4013a07f,
5871                 .flags          = ADDR_TYPE_RT
5872         },
5873         { }
5874 };
5875
5876 /* l4_abe -> timer6 */
5877 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5878         .master         = &omap44xx_l4_abe_hwmod,
5879         .slave          = &omap44xx_timer6_hwmod,
5880         .clk            = "ocp_abe_iclk",
5881         .addr           = omap44xx_timer6_addrs,
5882         .user           = OCP_USER_MPU,
5883 };
5884
5885 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5886         {
5887                 .pa_start       = 0x4903a000,
5888                 .pa_end         = 0x4903a07f,
5889                 .flags          = ADDR_TYPE_RT
5890         },
5891         { }
5892 };
5893
5894 /* l4_abe -> timer6 (dma) */
5895 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5896         .master         = &omap44xx_l4_abe_hwmod,
5897         .slave          = &omap44xx_timer6_hwmod,
5898         .clk            = "ocp_abe_iclk",
5899         .addr           = omap44xx_timer6_dma_addrs,
5900         .user           = OCP_USER_SDMA,
5901 };
5902
5903 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5904         {
5905                 .pa_start       = 0x4013c000,
5906                 .pa_end         = 0x4013c07f,
5907                 .flags          = ADDR_TYPE_RT
5908         },
5909         { }
5910 };
5911
5912 /* l4_abe -> timer7 */
5913 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5914         .master         = &omap44xx_l4_abe_hwmod,
5915         .slave          = &omap44xx_timer7_hwmod,
5916         .clk            = "ocp_abe_iclk",
5917         .addr           = omap44xx_timer7_addrs,
5918         .user           = OCP_USER_MPU,
5919 };
5920
5921 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5922         {
5923                 .pa_start       = 0x4903c000,
5924                 .pa_end         = 0x4903c07f,
5925                 .flags          = ADDR_TYPE_RT
5926         },
5927         { }
5928 };
5929
5930 /* l4_abe -> timer7 (dma) */
5931 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5932         .master         = &omap44xx_l4_abe_hwmod,
5933         .slave          = &omap44xx_timer7_hwmod,
5934         .clk            = "ocp_abe_iclk",
5935         .addr           = omap44xx_timer7_dma_addrs,
5936         .user           = OCP_USER_SDMA,
5937 };
5938
5939 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5940         {
5941                 .pa_start       = 0x4013e000,
5942                 .pa_end         = 0x4013e07f,
5943                 .flags          = ADDR_TYPE_RT
5944         },
5945         { }
5946 };
5947
5948 /* l4_abe -> timer8 */
5949 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5950         .master         = &omap44xx_l4_abe_hwmod,
5951         .slave          = &omap44xx_timer8_hwmod,
5952         .clk            = "ocp_abe_iclk",
5953         .addr           = omap44xx_timer8_addrs,
5954         .user           = OCP_USER_MPU,
5955 };
5956
5957 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5958         {
5959                 .pa_start       = 0x4903e000,
5960                 .pa_end         = 0x4903e07f,
5961                 .flags          = ADDR_TYPE_RT
5962         },
5963         { }
5964 };
5965
5966 /* l4_abe -> timer8 (dma) */
5967 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5968         .master         = &omap44xx_l4_abe_hwmod,
5969         .slave          = &omap44xx_timer8_hwmod,
5970         .clk            = "ocp_abe_iclk",
5971         .addr           = omap44xx_timer8_dma_addrs,
5972         .user           = OCP_USER_SDMA,
5973 };
5974
5975 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5976         {
5977                 .pa_start       = 0x4803e000,
5978                 .pa_end         = 0x4803e07f,
5979                 .flags          = ADDR_TYPE_RT
5980         },
5981         { }
5982 };
5983
5984 /* l4_per -> timer9 */
5985 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5986         .master         = &omap44xx_l4_per_hwmod,
5987         .slave          = &omap44xx_timer9_hwmod,
5988         .clk            = "l4_div_ck",
5989         .addr           = omap44xx_timer9_addrs,
5990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5991 };
5992
5993 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5994         {
5995                 .pa_start       = 0x48086000,
5996                 .pa_end         = 0x4808607f,
5997                 .flags          = ADDR_TYPE_RT
5998         },
5999         { }
6000 };
6001
6002 /* l4_per -> timer10 */
6003 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6004         .master         = &omap44xx_l4_per_hwmod,
6005         .slave          = &omap44xx_timer10_hwmod,
6006         .clk            = "l4_div_ck",
6007         .addr           = omap44xx_timer10_addrs,
6008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6009 };
6010
6011 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6012         {
6013                 .pa_start       = 0x48088000,
6014                 .pa_end         = 0x4808807f,
6015                 .flags          = ADDR_TYPE_RT
6016         },
6017         { }
6018 };
6019
6020 /* l4_per -> timer11 */
6021 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6022         .master         = &omap44xx_l4_per_hwmod,
6023         .slave          = &omap44xx_timer11_hwmod,
6024         .clk            = "l4_div_ck",
6025         .addr           = omap44xx_timer11_addrs,
6026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6027 };
6028
6029 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6030         {
6031                 .pa_start       = 0x4806a000,
6032                 .pa_end         = 0x4806a0ff,
6033                 .flags          = ADDR_TYPE_RT
6034         },
6035         { }
6036 };
6037
6038 /* l4_per -> uart1 */
6039 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6040         .master         = &omap44xx_l4_per_hwmod,
6041         .slave          = &omap44xx_uart1_hwmod,
6042         .clk            = "l4_div_ck",
6043         .addr           = omap44xx_uart1_addrs,
6044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6045 };
6046
6047 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6048         {
6049                 .pa_start       = 0x4806c000,
6050                 .pa_end         = 0x4806c0ff,
6051                 .flags          = ADDR_TYPE_RT
6052         },
6053         { }
6054 };
6055
6056 /* l4_per -> uart2 */
6057 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6058         .master         = &omap44xx_l4_per_hwmod,
6059         .slave          = &omap44xx_uart2_hwmod,
6060         .clk            = "l4_div_ck",
6061         .addr           = omap44xx_uart2_addrs,
6062         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6063 };
6064
6065 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6066         {
6067                 .pa_start       = 0x48020000,
6068                 .pa_end         = 0x480200ff,
6069                 .flags          = ADDR_TYPE_RT
6070         },
6071         { }
6072 };
6073
6074 /* l4_per -> uart3 */
6075 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6076         .master         = &omap44xx_l4_per_hwmod,
6077         .slave          = &omap44xx_uart3_hwmod,
6078         .clk            = "l4_div_ck",
6079         .addr           = omap44xx_uart3_addrs,
6080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6081 };
6082
6083 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6084         {
6085                 .pa_start       = 0x4806e000,
6086                 .pa_end         = 0x4806e0ff,
6087                 .flags          = ADDR_TYPE_RT
6088         },
6089         { }
6090 };
6091
6092 /* l4_per -> uart4 */
6093 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6094         .master         = &omap44xx_l4_per_hwmod,
6095         .slave          = &omap44xx_uart4_hwmod,
6096         .clk            = "l4_div_ck",
6097         .addr           = omap44xx_uart4_addrs,
6098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6099 };
6100
6101 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6102         {
6103                 .pa_start       = 0x4a0a9000,
6104                 .pa_end         = 0x4a0a93ff,
6105                 .flags          = ADDR_TYPE_RT
6106         },
6107         { }
6108 };
6109
6110 /* l4_cfg -> usb_host_fs */
6111 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6112         .master         = &omap44xx_l4_cfg_hwmod,
6113         .slave          = &omap44xx_usb_host_fs_hwmod,
6114         .clk            = "l4_div_ck",
6115         .addr           = omap44xx_usb_host_fs_addrs,
6116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6117 };
6118
6119 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6120         {
6121                 .name           = "uhh",
6122                 .pa_start       = 0x4a064000,
6123                 .pa_end         = 0x4a0647ff,
6124                 .flags          = ADDR_TYPE_RT
6125         },
6126         {
6127                 .name           = "ohci",
6128                 .pa_start       = 0x4a064800,
6129                 .pa_end         = 0x4a064bff,
6130         },
6131         {
6132                 .name           = "ehci",
6133                 .pa_start       = 0x4a064c00,
6134                 .pa_end         = 0x4a064fff,
6135         },
6136         {}
6137 };
6138
6139 /* l4_cfg -> usb_host_hs */
6140 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6141         .master         = &omap44xx_l4_cfg_hwmod,
6142         .slave          = &omap44xx_usb_host_hs_hwmod,
6143         .clk            = "l4_div_ck",
6144         .addr           = omap44xx_usb_host_hs_addrs,
6145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6146 };
6147
6148 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6149         {
6150                 .pa_start       = 0x4a0ab000,
6151                 .pa_end         = 0x4a0ab7ff,
6152                 .flags          = ADDR_TYPE_RT
6153         },
6154         {
6155                 /* XXX: Remove this once control module driver is in place */
6156                 .pa_start       = 0x4a00233c,
6157                 .pa_end         = 0x4a00233f,
6158                 .flags          = ADDR_TYPE_RT
6159         },
6160         { }
6161 };
6162
6163 /* l4_cfg -> usb_otg_hs */
6164 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6165         .master         = &omap44xx_l4_cfg_hwmod,
6166         .slave          = &omap44xx_usb_otg_hs_hwmod,
6167         .clk            = "l4_div_ck",
6168         .addr           = omap44xx_usb_otg_hs_addrs,
6169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6170 };
6171
6172 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6173         {
6174                 .name           = "tll",
6175                 .pa_start       = 0x4a062000,
6176                 .pa_end         = 0x4a063fff,
6177                 .flags          = ADDR_TYPE_RT
6178         },
6179         {}
6180 };
6181
6182 /* l4_cfg -> usb_tll_hs */
6183 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6184         .master         = &omap44xx_l4_cfg_hwmod,
6185         .slave          = &omap44xx_usb_tll_hs_hwmod,
6186         .clk            = "l4_div_ck",
6187         .addr           = omap44xx_usb_tll_hs_addrs,
6188         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6189 };
6190
6191 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6192         {
6193                 .pa_start       = 0x4a314000,
6194                 .pa_end         = 0x4a31407f,
6195                 .flags          = ADDR_TYPE_RT
6196         },
6197         { }
6198 };
6199
6200 /* l4_wkup -> wd_timer2 */
6201 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6202         .master         = &omap44xx_l4_wkup_hwmod,
6203         .slave          = &omap44xx_wd_timer2_hwmod,
6204         .clk            = "l4_wkup_clk_mux_ck",
6205         .addr           = omap44xx_wd_timer2_addrs,
6206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6207 };
6208
6209 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6210         {
6211                 .pa_start       = 0x40130000,
6212                 .pa_end         = 0x4013007f,
6213                 .flags          = ADDR_TYPE_RT
6214         },
6215         { }
6216 };
6217
6218 /* l4_abe -> wd_timer3 */
6219 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6220         .master         = &omap44xx_l4_abe_hwmod,
6221         .slave          = &omap44xx_wd_timer3_hwmod,
6222         .clk            = "ocp_abe_iclk",
6223         .addr           = omap44xx_wd_timer3_addrs,
6224         .user           = OCP_USER_MPU,
6225 };
6226
6227 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6228         {
6229                 .pa_start       = 0x49030000,
6230                 .pa_end         = 0x4903007f,
6231                 .flags          = ADDR_TYPE_RT
6232         },
6233         { }
6234 };
6235
6236 /* l4_abe -> wd_timer3 (dma) */
6237 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6238         .master         = &omap44xx_l4_abe_hwmod,
6239         .slave          = &omap44xx_wd_timer3_hwmod,
6240         .clk            = "ocp_abe_iclk",
6241         .addr           = omap44xx_wd_timer3_dma_addrs,
6242         .user           = OCP_USER_SDMA,
6243 };
6244
6245 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6246         &omap44xx_c2c__c2c_target_fw,
6247         &omap44xx_l4_cfg__c2c_target_fw,
6248         &omap44xx_l3_main_1__dmm,
6249         &omap44xx_mpu__dmm,
6250         &omap44xx_c2c__emif_fw,
6251         &omap44xx_dmm__emif_fw,
6252         &omap44xx_l4_cfg__emif_fw,
6253         &omap44xx_iva__l3_instr,
6254         &omap44xx_l3_main_3__l3_instr,
6255         &omap44xx_ocp_wp_noc__l3_instr,
6256         &omap44xx_dsp__l3_main_1,
6257         &omap44xx_dss__l3_main_1,
6258         &omap44xx_l3_main_2__l3_main_1,
6259         &omap44xx_l4_cfg__l3_main_1,
6260         &omap44xx_mmc1__l3_main_1,
6261         &omap44xx_mmc2__l3_main_1,
6262         &omap44xx_mpu__l3_main_1,
6263         &omap44xx_c2c_target_fw__l3_main_2,
6264         &omap44xx_debugss__l3_main_2,
6265         &omap44xx_dma_system__l3_main_2,
6266         &omap44xx_fdif__l3_main_2,
6267         &omap44xx_gpu__l3_main_2,
6268         &omap44xx_hsi__l3_main_2,
6269         &omap44xx_ipu__l3_main_2,
6270         &omap44xx_iss__l3_main_2,
6271         &omap44xx_iva__l3_main_2,
6272         &omap44xx_l3_main_1__l3_main_2,
6273         &omap44xx_l4_cfg__l3_main_2,
6274         /* &omap44xx_usb_host_fs__l3_main_2, */
6275         &omap44xx_usb_host_hs__l3_main_2,
6276         &omap44xx_usb_otg_hs__l3_main_2,
6277         &omap44xx_l3_main_1__l3_main_3,
6278         &omap44xx_l3_main_2__l3_main_3,
6279         &omap44xx_l4_cfg__l3_main_3,
6280         /* &omap44xx_aess__l4_abe, */
6281         &omap44xx_dsp__l4_abe,
6282         &omap44xx_l3_main_1__l4_abe,
6283         &omap44xx_mpu__l4_abe,
6284         &omap44xx_l3_main_1__l4_cfg,
6285         &omap44xx_l3_main_2__l4_per,
6286         &omap44xx_l4_cfg__l4_wkup,
6287         &omap44xx_mpu__mpu_private,
6288         &omap44xx_l4_cfg__ocp_wp_noc,
6289         /* &omap44xx_l4_abe__aess, */
6290         /* &omap44xx_l4_abe__aess_dma, */
6291         &omap44xx_l3_main_2__c2c,
6292         &omap44xx_l4_wkup__counter_32k,
6293         &omap44xx_l4_cfg__ctrl_module_core,
6294         &omap44xx_l4_cfg__ctrl_module_pad_core,
6295         &omap44xx_l4_wkup__ctrl_module_wkup,
6296         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6297         &omap44xx_l3_instr__debugss,
6298         &omap44xx_l4_cfg__dma_system,
6299         &omap44xx_l4_abe__dmic,
6300         &omap44xx_l4_abe__dmic_dma,
6301         &omap44xx_dsp__iva,
6302         /* &omap44xx_dsp__sl2if, */
6303         &omap44xx_l4_cfg__dsp,
6304         &omap44xx_l3_main_2__dss,
6305         &omap44xx_l4_per__dss,
6306         &omap44xx_l3_main_2__dss_dispc,
6307         &omap44xx_l4_per__dss_dispc,
6308         &omap44xx_l3_main_2__dss_dsi1,
6309         &omap44xx_l4_per__dss_dsi1,
6310         &omap44xx_l3_main_2__dss_dsi2,
6311         &omap44xx_l4_per__dss_dsi2,
6312         &omap44xx_l3_main_2__dss_hdmi,
6313         &omap44xx_l4_per__dss_hdmi,
6314         &omap44xx_l3_main_2__dss_rfbi,
6315         &omap44xx_l4_per__dss_rfbi,
6316         &omap44xx_l3_main_2__dss_venc,
6317         &omap44xx_l4_per__dss_venc,
6318         &omap44xx_l4_per__elm,
6319         &omap44xx_emif_fw__emif1,
6320         &omap44xx_emif_fw__emif2,
6321         &omap44xx_l4_cfg__fdif,
6322         &omap44xx_l4_wkup__gpio1,
6323         &omap44xx_l4_per__gpio2,
6324         &omap44xx_l4_per__gpio3,
6325         &omap44xx_l4_per__gpio4,
6326         &omap44xx_l4_per__gpio5,
6327         &omap44xx_l4_per__gpio6,
6328         &omap44xx_l3_main_2__gpmc,
6329         &omap44xx_l3_main_2__gpu,
6330         &omap44xx_l4_per__hdq1w,
6331         &omap44xx_l4_cfg__hsi,
6332         &omap44xx_l4_per__i2c1,
6333         &omap44xx_l4_per__i2c2,
6334         &omap44xx_l4_per__i2c3,
6335         &omap44xx_l4_per__i2c4,
6336         &omap44xx_l3_main_2__ipu,
6337         &omap44xx_l3_main_2__iss,
6338         /* &omap44xx_iva__sl2if, */
6339         &omap44xx_l3_main_2__iva,
6340         &omap44xx_l4_wkup__kbd,
6341         &omap44xx_l4_cfg__mailbox,
6342         &omap44xx_l4_abe__mcasp,
6343         &omap44xx_l4_abe__mcasp_dma,
6344         &omap44xx_l4_abe__mcbsp1,
6345         &omap44xx_l4_abe__mcbsp1_dma,
6346         &omap44xx_l4_abe__mcbsp2,
6347         &omap44xx_l4_abe__mcbsp2_dma,
6348         &omap44xx_l4_abe__mcbsp3,
6349         &omap44xx_l4_abe__mcbsp3_dma,
6350         &omap44xx_l4_per__mcbsp4,
6351         &omap44xx_l4_abe__mcpdm,
6352         &omap44xx_l4_abe__mcpdm_dma,
6353         &omap44xx_l4_per__mcspi1,
6354         &omap44xx_l4_per__mcspi2,
6355         &omap44xx_l4_per__mcspi3,
6356         &omap44xx_l4_per__mcspi4,
6357         &omap44xx_l4_per__mmc1,
6358         &omap44xx_l4_per__mmc2,
6359         &omap44xx_l4_per__mmc3,
6360         &omap44xx_l4_per__mmc4,
6361         &omap44xx_l4_per__mmc5,
6362         &omap44xx_l3_main_2__mmu_ipu,
6363         &omap44xx_l4_cfg__mmu_dsp,
6364         &omap44xx_l3_main_2__ocmc_ram,
6365         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6366         &omap44xx_mpu_private__prcm_mpu,
6367         &omap44xx_l4_wkup__cm_core_aon,
6368         &omap44xx_l4_cfg__cm_core,
6369         &omap44xx_l4_wkup__prm,
6370         &omap44xx_l4_wkup__scrm,
6371         /* &omap44xx_l3_main_2__sl2if, */
6372         &omap44xx_l4_abe__slimbus1,
6373         &omap44xx_l4_abe__slimbus1_dma,
6374         &omap44xx_l4_per__slimbus2,
6375         &omap44xx_l4_cfg__smartreflex_core,
6376         &omap44xx_l4_cfg__smartreflex_iva,
6377         &omap44xx_l4_cfg__smartreflex_mpu,
6378         &omap44xx_l4_cfg__spinlock,
6379         &omap44xx_l4_wkup__timer1,
6380         &omap44xx_l4_per__timer2,
6381         &omap44xx_l4_per__timer3,
6382         &omap44xx_l4_per__timer4,
6383         &omap44xx_l4_abe__timer5,
6384         &omap44xx_l4_abe__timer5_dma,
6385         &omap44xx_l4_abe__timer6,
6386         &omap44xx_l4_abe__timer6_dma,
6387         &omap44xx_l4_abe__timer7,
6388         &omap44xx_l4_abe__timer7_dma,
6389         &omap44xx_l4_abe__timer8,
6390         &omap44xx_l4_abe__timer8_dma,
6391         &omap44xx_l4_per__timer9,
6392         &omap44xx_l4_per__timer10,
6393         &omap44xx_l4_per__timer11,
6394         &omap44xx_l4_per__uart1,
6395         &omap44xx_l4_per__uart2,
6396         &omap44xx_l4_per__uart3,
6397         &omap44xx_l4_per__uart4,
6398         /* &omap44xx_l4_cfg__usb_host_fs, */
6399         &omap44xx_l4_cfg__usb_host_hs,
6400         &omap44xx_l4_cfg__usb_otg_hs,
6401         &omap44xx_l4_cfg__usb_tll_hs,
6402         &omap44xx_l4_wkup__wd_timer2,
6403         &omap44xx_l4_abe__wd_timer3,
6404         &omap44xx_l4_abe__wd_timer3_dma,
6405         NULL,
6406 };
6407
6408 int __init omap44xx_hwmod_init(void)
6409 {
6410         omap_hwmod_init();
6411         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6412 }
6413