arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/dmtimer.h>
  31 #include <plat/iommu.h>
  32
  33 #include "omap_hwmod.h"
  34 #include "omap_hwmod_common_data.h"
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /*
  54  * 'c2c_target_fw' class
  55  * instance(s): c2c_target_fw
  56  */
  57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  58         .name   = "c2c_target_fw",
  59 };
  60
  61 /* c2c_target_fw */
  62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  63         .name           = "c2c_target_fw",
  64         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  65         .clkdm_name     = "d2d_clkdm",
  66         .prcm = {
  67                 .omap4 = {
  68                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  69                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm */
  83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  84         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  85         { .irq = -1 }
  86 };
  87
  88 static struct omap_hwmod omap44xx_dmm_hwmod = {
  89         .name           = "dmm",
  90         .class          = &omap44xx_dmm_hwmod_class,
  91         .clkdm_name     = "l3_emif_clkdm",
  92         .mpu_irqs       = omap44xx_dmm_irqs,
  93         .prcm = {
  94                 .omap4 = {
  95                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  96                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  97                 },
  98         },
  99 };
 100
 101 /*
 102  * 'emif_fw' class
 103  * instance(s): emif_fw
 104  */
 105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 106         .name   = "emif_fw",
 107 };
 108
 109 /* emif_fw */
 110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 111         .name           = "emif_fw",
 112         .class          = &omap44xx_emif_fw_hwmod_class,
 113         .clkdm_name     = "l3_emif_clkdm",
 114         .prcm = {
 115                 .omap4 = {
 116                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 117                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 118                 },
 119         },
 120 };
 121
 122 /*
 123  * 'l3' class
 124  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 125  */
 126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 127         .name   = "l3",
 128 };
 129
 130 /* l3_instr */
 131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 132         .name           = "l3_instr",
 133         .class          = &omap44xx_l3_hwmod_class,
 134         .clkdm_name     = "l3_instr_clkdm",
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 139                         .modulemode   = MODULEMODE_HWCTRL,
 140                 },
 141         },
 142 };
 143
 144 /* l3_main_1 */
 145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 146         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 147         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 148         { .irq = -1 }
 149 };
 150
 151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 152         .name           = "l3_main_1",
 153         .class          = &omap44xx_l3_hwmod_class,
 154         .clkdm_name     = "l3_1_clkdm",
 155         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 156         .prcm = {
 157                 .omap4 = {
 158                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 159                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 160                 },
 161         },
 162 };
 163
 164 /* l3_main_2 */
 165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 166         .name           = "l3_main_2",
 167         .class          = &omap44xx_l3_hwmod_class,
 168         .clkdm_name     = "l3_2_clkdm",
 169         .prcm = {
 170                 .omap4 = {
 171                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 172                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 173                 },
 174         },
 175 };
 176
 177 /* l3_main_3 */
 178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 179         .name           = "l3_main_3",
 180         .class          = &omap44xx_l3_hwmod_class,
 181         .clkdm_name     = "l3_instr_clkdm",
 182         .prcm = {
 183                 .omap4 = {
 184                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 185                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 186                         .modulemode   = MODULEMODE_HWCTRL,
 187                 },
 188         },
 189 };
 190
 191 /*
 192  * 'l4' class
 193  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 194  */
 195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 196         .name   = "l4",
 197 };
 198
 199 /* l4_abe */
 200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 201         .name           = "l4_abe",
 202         .class          = &omap44xx_l4_hwmod_class,
 203         .clkdm_name     = "abe_clkdm",
 204         .prcm = {
 205                 .omap4 = {
 206                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 207                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 208                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 209                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210                 },
 211         },
 212 };
 213
 214 /* l4_cfg */
 215 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 216         .name           = "l4_cfg",
 217         .class          = &omap44xx_l4_hwmod_class,
 218         .clkdm_name     = "l4_cfg_clkdm",
 219         .prcm = {
 220                 .omap4 = {
 221                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 222                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 223                 },
 224         },
 225 };
 226
 227 /* l4_per */
 228 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 229         .name           = "l4_per",
 230         .class          = &omap44xx_l4_hwmod_class,
 231         .clkdm_name     = "l4_per_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 236                 },
 237         },
 238 };
 239
 240 /* l4_wkup */
 241 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 242         .name           = "l4_wkup",
 243         .class          = &omap44xx_l4_hwmod_class,
 244         .clkdm_name     = "l4_wkup_clkdm",
 245         .prcm = {
 246                 .omap4 = {
 247                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 248                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 249                 },
 250         },
 251 };
 252
 253 /*
 254  * 'mpu_bus' class
 255  * instance(s): mpu_private
 256  */
 257 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 258         .name   = "mpu_bus",
 259 };
 260
 261 /* mpu_private */
 262 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 263         .name           = "mpu_private",
 264         .class          = &omap44xx_mpu_bus_hwmod_class,
 265         .clkdm_name     = "mpuss_clkdm",
 266         .prcm = {
 267                 .omap4 = {
 268                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 269                 },
 270         },
 271 };
 272
 273 /*
 274  * 'ocp_wp_noc' class
 275  * instance(s): ocp_wp_noc
 276  */
 277 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 278         .name   = "ocp_wp_noc",
 279 };
 280
 281 /* ocp_wp_noc */
 282 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 283         .name           = "ocp_wp_noc",
 284         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 285         .clkdm_name     = "l3_instr_clkdm",
 286         .prcm = {
 287                 .omap4 = {
 288                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 289                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 290                         .modulemode   = MODULEMODE_HWCTRL,
 291                 },
 292         },
 293 };
 294
 295 /*
 296  * Modules omap_hwmod structures
 297  *
 298  * The following IPs are excluded for the moment because:
 299  * - They do not need an explicit SW control using omap_hwmod API.
 300  * - They still need to be validated with the driver
 301  *   properly adapted to omap_hwmod / omap_device
 302  *
 303  * usim
 304  */
 305
 306 /*
 307  * 'aess' class
 308  * audio engine sub system
 309  */
 310
 311 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 312         .rev_offs       = 0x0000,
 313         .sysc_offs      = 0x0010,
 314         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 316                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 317                            MSTANDBY_SMART_WKUP),
 318         .sysc_fields    = &omap_hwmod_sysc_type2,
 319 };
 320
 321 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 322         .name   = "aess",
 323         .sysc   = &omap44xx_aess_sysc,
 324 };
 325
 326 /* aess */
 327 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 328         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 329         { .irq = -1 }
 330 };
 331
 332 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 333         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 341         { .dma_req = -1 }
 342 };
 343
 344 static struct omap_hwmod omap44xx_aess_hwmod = {
 345         .name           = "aess",
 346         .class          = &omap44xx_aess_hwmod_class,
 347         .clkdm_name     = "abe_clkdm",
 348         .mpu_irqs       = omap44xx_aess_irqs,
 349         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 350         .main_clk       = "aess_fck",
 351         .prcm = {
 352                 .omap4 = {
 353                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 354                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 355                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 356                         .modulemode   = MODULEMODE_SWCTRL,
 357                 },
 358         },
 359 };
 360
 361 /*
 362  * 'c2c' class
 363  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 364  * soc
 365  */
 366
 367 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 368         .name   = "c2c",
 369 };
 370
 371 /* c2c */
 372 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 373         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 374         { .irq = -1 }
 375 };
 376
 377 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 378         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 379         { .dma_req = -1 }
 380 };
 381
 382 static struct omap_hwmod omap44xx_c2c_hwmod = {
 383         .name           = "c2c",
 384         .class          = &omap44xx_c2c_hwmod_class,
 385         .clkdm_name     = "d2d_clkdm",
 386         .mpu_irqs       = omap44xx_c2c_irqs,
 387         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 388         .prcm = {
 389                 .omap4 = {
 390                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 391                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 392                 },
 393         },
 394 };
 395
 396 /*
 397  * 'counter' class
 398  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 399  */
 400
 401 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 402         .rev_offs       = 0x0000,
 403         .sysc_offs      = 0x0004,
 404         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 405         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 406         .sysc_fields    = &omap_hwmod_sysc_type1,
 407 };
 408
 409 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 410         .name   = "counter",
 411         .sysc   = &omap44xx_counter_sysc,
 412 };
 413
 414 /* counter_32k */
 415 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 416         .name           = "counter_32k",
 417         .class          = &omap44xx_counter_hwmod_class,
 418         .clkdm_name     = "l4_wkup_clkdm",
 419         .flags          = HWMOD_SWSUP_SIDLE,
 420         .main_clk       = "sys_32k_ck",
 421         .prcm = {
 422                 .omap4 = {
 423                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 424                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 425                 },
 426         },
 427 };
 428
 429 /*
 430  * 'ctrl_module' class
 431  * attila core control module + core pad control module + wkup pad control
 432  * module + attila wkup control module
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 439         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 440                            SIDLE_SMART_WKUP),
 441         .sysc_fields    = &omap_hwmod_sysc_type2,
 442 };
 443
 444 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 445         .name   = "ctrl_module",
 446         .sysc   = &omap44xx_ctrl_module_sysc,
 447 };
 448
 449 /* ctrl_module_core */
 450 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 451         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 452         { .irq = -1 }
 453 };
 454
 455 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 456         .name           = "ctrl_module_core",
 457         .class          = &omap44xx_ctrl_module_hwmod_class,
 458         .clkdm_name     = "l4_cfg_clkdm",
 459         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 460         .prcm = {
 461                 .omap4 = {
 462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 463                 },
 464         },
 465 };
 466
 467 /* ctrl_module_pad_core */
 468 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 469         .name           = "ctrl_module_pad_core",
 470         .class          = &omap44xx_ctrl_module_hwmod_class,
 471         .clkdm_name     = "l4_cfg_clkdm",
 472         .prcm = {
 473                 .omap4 = {
 474                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 475                 },
 476         },
 477 };
 478
 479 /* ctrl_module_wkup */
 480 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 481         .name           = "ctrl_module_wkup",
 482         .class          = &omap44xx_ctrl_module_hwmod_class,
 483         .clkdm_name     = "l4_wkup_clkdm",
 484         .prcm = {
 485                 .omap4 = {
 486                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 487                 },
 488         },
 489 };
 490
 491 /* ctrl_module_pad_wkup */
 492 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 493         .name           = "ctrl_module_pad_wkup",
 494         .class          = &omap44xx_ctrl_module_hwmod_class,
 495         .clkdm_name     = "l4_wkup_clkdm",
 496         .prcm = {
 497                 .omap4 = {
 498                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 499                 },
 500         },
 501 };
 502
 503 /*
 504  * 'debugss' class
 505  * debug and emulation sub system
 506  */
 507
 508 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 509         .name   = "debugss",
 510 };
 511
 512 /* debugss */
 513 static struct omap_hwmod omap44xx_debugss_hwmod = {
 514         .name           = "debugss",
 515         .class          = &omap44xx_debugss_hwmod_class,
 516         .clkdm_name     = "emu_sys_clkdm",
 517         .main_clk       = "trace_clk_div_ck",
 518         .prcm = {
 519                 .omap4 = {
 520                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 521                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 522                 },
 523         },
 524 };
 525
 526 /*
 527  * 'dma' class
 528  * dma controller for data exchange between memory to memory (i.e. internal or
 529  * external memory) and gp peripherals to memory or memory to gp peripherals
 530  */
 531
 532 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 533         .rev_offs       = 0x0000,
 534         .sysc_offs      = 0x002c,
 535         .syss_offs      = 0x0028,
 536         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 537                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 538                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 539                            SYSS_HAS_RESET_STATUS),
 540         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 541                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 546         .name   = "dma",
 547         .sysc   = &omap44xx_dma_sysc,
 548 };
 549
 550 /* dma dev_attr */
 551 static struct omap_dma_dev_attr dma_dev_attr = {
 552         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 553                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 554         .lch_count      = 32,
 555 };
 556
 557 /* dma_system */
 558 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 559         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 563         { .irq = -1 }
 564 };
 565
 566 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 567         .name           = "dma_system",
 568         .class          = &omap44xx_dma_hwmod_class,
 569         .clkdm_name     = "l3_dma_clkdm",
 570         .mpu_irqs       = omap44xx_dma_system_irqs,
 571         .main_clk       = "l3_div_ck",
 572         .prcm = {
 573                 .omap4 = {
 574                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 575                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 576                 },
 577         },
 578         .dev_attr       = &dma_dev_attr,
 579 };
 580
 581 /*
 582  * 'dmic' class
 583  * digital microphone controller
 584  */
 585
 586 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 587         .rev_offs       = 0x0000,
 588         .sysc_offs      = 0x0010,
 589         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 590                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 592                            SIDLE_SMART_WKUP),
 593         .sysc_fields    = &omap_hwmod_sysc_type2,
 594 };
 595
 596 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 597         .name   = "dmic",
 598         .sysc   = &omap44xx_dmic_sysc,
 599 };
 600
 601 /* dmic */
 602 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 603         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 604         { .irq = -1 }
 605 };
 606
 607 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 608         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 609         { .dma_req = -1 }
 610 };
 611
 612 static struct omap_hwmod omap44xx_dmic_hwmod = {
 613         .name           = "dmic",
 614         .class          = &omap44xx_dmic_hwmod_class,
 615         .clkdm_name     = "abe_clkdm",
 616         .mpu_irqs       = omap44xx_dmic_irqs,
 617         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 618         .main_clk       = "dmic_fck",
 619         .prcm = {
 620                 .omap4 = {
 621                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 622                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 623                         .modulemode   = MODULEMODE_SWCTRL,
 624                 },
 625         },
 626 };
 627
 628 /*
 629  * 'dsp' class
 630  * dsp sub-system
 631  */
 632
 633 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 634         .name   = "dsp",
 635 };
 636
 637 /* dsp */
 638 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 639         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 640         { .irq = -1 }
 641 };
 642
 643 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 644         { .name = "dsp", .rst_shift = 0 },
 645 };
 646
 647 static struct omap_hwmod omap44xx_dsp_hwmod = {
 648         .name           = "dsp",
 649         .class          = &omap44xx_dsp_hwmod_class,
 650         .clkdm_name     = "tesla_clkdm",
 651         .mpu_irqs       = omap44xx_dsp_irqs,
 652         .rst_lines      = omap44xx_dsp_resets,
 653         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 654         .main_clk       = "dsp_fck",
 655         .prcm = {
 656                 .omap4 = {
 657                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 658                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 659                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 660                         .modulemode   = MODULEMODE_HWCTRL,
 661                 },
 662         },
 663 };
 664
 665 /*
 666  * 'dss' class
 667  * display sub-system
 668  */
 669
 670 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 671         .rev_offs       = 0x0000,
 672         .syss_offs      = 0x0014,
 673         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 674 };
 675
 676 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 677         .name   = "dss",
 678         .sysc   = &omap44xx_dss_sysc,
 679         .reset  = omap_dss_reset,
 680 };
 681
 682 /* dss */
 683 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 684         { .role = "sys_clk", .clk = "dss_sys_clk" },
 685         { .role = "tv_clk", .clk = "dss_tv_clk" },
 686         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 687 };
 688
 689 static struct omap_hwmod omap44xx_dss_hwmod = {
 690         .name           = "dss_core",
 691         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 692         .class          = &omap44xx_dss_hwmod_class,
 693         .clkdm_name     = "l3_dss_clkdm",
 694         .main_clk       = "dss_dss_clk",
 695         .prcm = {
 696                 .omap4 = {
 697                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 698                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 699                 },
 700         },
 701         .opt_clks       = dss_opt_clks,
 702         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 703 };
 704
 705 /*
 706  * 'dispc' class
 707  * display controller
 708  */
 709
 710 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 711         .rev_offs       = 0x0000,
 712         .sysc_offs      = 0x0010,
 713         .syss_offs      = 0x0014,
 714         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 715                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 716                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 717                            SYSS_HAS_RESET_STATUS),
 718         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 719                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 720         .sysc_fields    = &omap_hwmod_sysc_type1,
 721 };
 722
 723 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 724         .name   = "dispc",
 725         .sysc   = &omap44xx_dispc_sysc,
 726 };
 727
 728 /* dss_dispc */
 729 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 730         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 731         { .irq = -1 }
 732 };
 733
 734 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 735         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 736         { .dma_req = -1 }
 737 };
 738
 739 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 740         .manager_count          = 3,
 741         .has_framedonetv_irq    = 1
 742 };
 743
 744 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 745         .name           = "dss_dispc",
 746         .class          = &omap44xx_dispc_hwmod_class,
 747         .clkdm_name     = "l3_dss_clkdm",
 748         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 749         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 750         .main_clk       = "dss_dss_clk",
 751         .prcm = {
 752                 .omap4 = {
 753                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 754                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 755                 },
 756         },
 757         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 758 };
 759
 760 /*
 761  * 'dsi' class
 762  * display serial interface controller
 763  */
 764
 765 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 766         .rev_offs       = 0x0000,
 767         .sysc_offs      = 0x0010,
 768         .syss_offs      = 0x0014,
 769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 770                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 771                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 773         .sysc_fields    = &omap_hwmod_sysc_type1,
 774 };
 775
 776 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 777         .name   = "dsi",
 778         .sysc   = &omap44xx_dsi_sysc,
 779 };
 780
 781 /* dss_dsi1 */
 782 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 783         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 784         { .irq = -1 }
 785 };
 786
 787 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 788         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 789         { .dma_req = -1 }
 790 };
 791
 792 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 793         { .role = "sys_clk", .clk = "dss_sys_clk" },
 794 };
 795
 796 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 797         .name           = "dss_dsi1",
 798         .class          = &omap44xx_dsi_hwmod_class,
 799         .clkdm_name     = "l3_dss_clkdm",
 800         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 801         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 802         .main_clk       = "dss_dss_clk",
 803         .prcm = {
 804                 .omap4 = {
 805                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 806                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 807                 },
 808         },
 809         .opt_clks       = dss_dsi1_opt_clks,
 810         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 811 };
 812
 813 /* dss_dsi2 */
 814 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 815         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 816         { .irq = -1 }
 817 };
 818
 819 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 820         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 821         { .dma_req = -1 }
 822 };
 823
 824 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 825         { .role = "sys_clk", .clk = "dss_sys_clk" },
 826 };
 827
 828 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 829         .name           = "dss_dsi2",
 830         .class          = &omap44xx_dsi_hwmod_class,
 831         .clkdm_name     = "l3_dss_clkdm",
 832         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 833         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 834         .main_clk       = "dss_dss_clk",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 838                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 839                 },
 840         },
 841         .opt_clks       = dss_dsi2_opt_clks,
 842         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 843 };
 844
 845 /*
 846  * 'hdmi' class
 847  * hdmi controller
 848  */
 849
 850 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 851         .rev_offs       = 0x0000,
 852         .sysc_offs      = 0x0010,
 853         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 854                            SYSC_HAS_SOFTRESET),
 855         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 856                            SIDLE_SMART_WKUP),
 857         .sysc_fields    = &omap_hwmod_sysc_type2,
 858 };
 859
 860 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 861         .name   = "hdmi",
 862         .sysc   = &omap44xx_hdmi_sysc,
 863 };
 864
 865 /* dss_hdmi */
 866 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 867         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 868         { .irq = -1 }
 869 };
 870
 871 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 872         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 873         { .dma_req = -1 }
 874 };
 875
 876 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 877         { .role = "sys_clk", .clk = "dss_sys_clk" },
 878 };
 879
 880 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 881         .name           = "dss_hdmi",
 882         .class          = &omap44xx_hdmi_hwmod_class,
 883         .clkdm_name     = "l3_dss_clkdm",
 884         /*
 885          * HDMI audio requires to use no-idle mode. Hence,
 886          * set idle mode by software.
 887          */
 888         .flags          = HWMOD_SWSUP_SIDLE,
 889         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 890         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 891         .main_clk       = "dss_48mhz_clk",
 892         .prcm = {
 893                 .omap4 = {
 894                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 895                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 896                 },
 897         },
 898         .opt_clks       = dss_hdmi_opt_clks,
 899         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 900 };
 901
 902 /*
 903  * 'rfbi' class
 904  * remote frame buffer interface
 905  */
 906
 907 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 908         .rev_offs       = 0x0000,
 909         .sysc_offs      = 0x0010,
 910         .syss_offs      = 0x0014,
 911         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 912                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 913         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 914         .sysc_fields    = &omap_hwmod_sysc_type1,
 915 };
 916
 917 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 918         .name   = "rfbi",
 919         .sysc   = &omap44xx_rfbi_sysc,
 920 };
 921
 922 /* dss_rfbi */
 923 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 924         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 925         { .dma_req = -1 }
 926 };
 927
 928 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 929         { .role = "ick", .clk = "dss_fck" },
 930 };
 931
 932 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 933         .name           = "dss_rfbi",
 934         .class          = &omap44xx_rfbi_hwmod_class,
 935         .clkdm_name     = "l3_dss_clkdm",
 936         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 937         .main_clk       = "dss_dss_clk",
 938         .prcm = {
 939                 .omap4 = {
 940                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 941                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 942                 },
 943         },
 944         .opt_clks       = dss_rfbi_opt_clks,
 945         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 946 };
 947
 948 /*
 949  * 'venc' class
 950  * video encoder
 951  */
 952
 953 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 954         .name   = "venc",
 955 };
 956
 957 /* dss_venc */
 958 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 959         .name           = "dss_venc",
 960         .class          = &omap44xx_venc_hwmod_class,
 961         .clkdm_name     = "l3_dss_clkdm",
 962         .main_clk       = "dss_tv_clk",
 963         .prcm = {
 964                 .omap4 = {
 965                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 966                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 967                 },
 968         },
 969 };
 970
 971 /*
 972  * 'elm' class
 973  * bch error location module
 974  */
 975
 976 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 977         .rev_offs       = 0x0000,
 978         .sysc_offs      = 0x0010,
 979         .syss_offs      = 0x0014,
 980         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 981                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 982                            SYSS_HAS_RESET_STATUS),
 983         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 984         .sysc_fields    = &omap_hwmod_sysc_type1,
 985 };
 986
 987 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 988         .name   = "elm",
 989         .sysc   = &omap44xx_elm_sysc,
 990 };
 991
 992 /* elm */
 993 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 994         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 995         { .irq = -1 }
 996 };
 997
 998 static struct omap_hwmod omap44xx_elm_hwmod = {
 999         .name           = "elm",
1000         .class          = &omap44xx_elm_hwmod_class,
1001         .clkdm_name     = "l4_per_clkdm",
1002         .mpu_irqs       = omap44xx_elm_irqs,
1003         .prcm = {
1004                 .omap4 = {
1005                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1006                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1007                 },
1008         },
1009 };
1010
1011 /*
1012  * 'emif' class
1013  * external memory interface no1
1014  */
1015
1016 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1017         .rev_offs       = 0x0000,
1018 };
1019
1020 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1021         .name   = "emif",
1022         .sysc   = &omap44xx_emif_sysc,
1023 };
1024
1025 /* emif1 */
1026 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1027         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1028         { .irq = -1 }
1029 };
1030
1031 static struct omap_hwmod omap44xx_emif1_hwmod = {
1032         .name           = "emif1",
1033         .class          = &omap44xx_emif_hwmod_class,
1034         .clkdm_name     = "l3_emif_clkdm",
1035         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1036         .mpu_irqs       = omap44xx_emif1_irqs,
1037         .main_clk       = "ddrphy_ck",
1038         .prcm = {
1039                 .omap4 = {
1040                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1041                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1042                         .modulemode   = MODULEMODE_HWCTRL,
1043                 },
1044         },
1045 };
1046
1047 /* emif2 */
1048 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1049         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1050         { .irq = -1 }
1051 };
1052
1053 static struct omap_hwmod omap44xx_emif2_hwmod = {
1054         .name           = "emif2",
1055         .class          = &omap44xx_emif_hwmod_class,
1056         .clkdm_name     = "l3_emif_clkdm",
1057         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1058         .mpu_irqs       = omap44xx_emif2_irqs,
1059         .main_clk       = "ddrphy_ck",
1060         .prcm = {
1061                 .omap4 = {
1062                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1063                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1064                         .modulemode   = MODULEMODE_HWCTRL,
1065                 },
1066         },
1067 };
1068
1069 /*
1070  * 'fdif' class
1071  * face detection hw accelerator module
1072  */
1073
1074 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1075         .rev_offs       = 0x0000,
1076         .sysc_offs      = 0x0010,
1077         /*
1078          * FDIF needs 100 OCP clk cycles delay after a softreset before
1079          * accessing sysconfig again.
1080          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1081          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1082          *
1083          * TODO: Indicate errata when available.
1084          */
1085         .srst_udelay    = 2,
1086         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1087                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1088         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090         .sysc_fields    = &omap_hwmod_sysc_type2,
1091 };
1092
1093 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1094         .name   = "fdif",
1095         .sysc   = &omap44xx_fdif_sysc,
1096 };
1097
1098 /* fdif */
1099 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1100         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod omap44xx_fdif_hwmod = {
1105         .name           = "fdif",
1106         .class          = &omap44xx_fdif_hwmod_class,
1107         .clkdm_name     = "iss_clkdm",
1108         .mpu_irqs       = omap44xx_fdif_irqs,
1109         .main_clk       = "fdif_fck",
1110         .prcm = {
1111                 .omap4 = {
1112                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1113                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1114                         .modulemode   = MODULEMODE_SWCTRL,
1115                 },
1116         },
1117 };
1118
1119 /*
1120  * 'gpio' class
1121  * general purpose io module
1122  */
1123
1124 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1125         .rev_offs       = 0x0000,
1126         .sysc_offs      = 0x0010,
1127         .syss_offs      = 0x0114,
1128         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1129                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1130                            SYSS_HAS_RESET_STATUS),
1131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1132                            SIDLE_SMART_WKUP),
1133         .sysc_fields    = &omap_hwmod_sysc_type1,
1134 };
1135
1136 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1137         .name   = "gpio",
1138         .sysc   = &omap44xx_gpio_sysc,
1139         .rev    = 2,
1140 };
1141
1142 /* gpio dev_attr */
1143 static struct omap_gpio_dev_attr gpio_dev_attr = {
1144         .bank_width     = 32,
1145         .dbck_flag      = true,
1146 };
1147
1148 /* gpio1 */
1149 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1150         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1151         { .irq = -1 }
1152 };
1153
1154 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1155         { .role = "dbclk", .clk = "gpio1_dbclk" },
1156 };
1157
1158 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1159         .name           = "gpio1",
1160         .class          = &omap44xx_gpio_hwmod_class,
1161         .clkdm_name     = "l4_wkup_clkdm",
1162         .mpu_irqs       = omap44xx_gpio1_irqs,
1163         .main_clk       = "gpio1_ick",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1167                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1168                         .modulemode   = MODULEMODE_HWCTRL,
1169                 },
1170         },
1171         .opt_clks       = gpio1_opt_clks,
1172         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1173         .dev_attr       = &gpio_dev_attr,
1174 };
1175
1176 /* gpio2 */
1177 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1178         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1179         { .irq = -1 }
1180 };
1181
1182 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1183         { .role = "dbclk", .clk = "gpio2_dbclk" },
1184 };
1185
1186 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1187         .name           = "gpio2",
1188         .class          = &omap44xx_gpio_hwmod_class,
1189         .clkdm_name     = "l4_per_clkdm",
1190         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1191         .mpu_irqs       = omap44xx_gpio2_irqs,
1192         .main_clk       = "gpio2_ick",
1193         .prcm = {
1194                 .omap4 = {
1195                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1196                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1197                         .modulemode   = MODULEMODE_HWCTRL,
1198                 },
1199         },
1200         .opt_clks       = gpio2_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1202         .dev_attr       = &gpio_dev_attr,
1203 };
1204
1205 /* gpio3 */
1206 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1207         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1208         { .irq = -1 }
1209 };
1210
1211 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1212         { .role = "dbclk", .clk = "gpio3_dbclk" },
1213 };
1214
1215 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1216         .name           = "gpio3",
1217         .class          = &omap44xx_gpio_hwmod_class,
1218         .clkdm_name     = "l4_per_clkdm",
1219         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1220         .mpu_irqs       = omap44xx_gpio3_irqs,
1221         .main_clk       = "gpio3_ick",
1222         .prcm = {
1223                 .omap4 = {
1224                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1225                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1226                         .modulemode   = MODULEMODE_HWCTRL,
1227                 },
1228         },
1229         .opt_clks       = gpio3_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1231         .dev_attr       = &gpio_dev_attr,
1232 };
1233
1234 /* gpio4 */
1235 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1236         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1237         { .irq = -1 }
1238 };
1239
1240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1241         { .role = "dbclk", .clk = "gpio4_dbclk" },
1242 };
1243
1244 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1245         .name           = "gpio4",
1246         .class          = &omap44xx_gpio_hwmod_class,
1247         .clkdm_name     = "l4_per_clkdm",
1248         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249         .mpu_irqs       = omap44xx_gpio4_irqs,
1250         .main_clk       = "gpio4_ick",
1251         .prcm = {
1252                 .omap4 = {
1253                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1254                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1255                         .modulemode   = MODULEMODE_HWCTRL,
1256                 },
1257         },
1258         .opt_clks       = gpio4_opt_clks,
1259         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1260         .dev_attr       = &gpio_dev_attr,
1261 };
1262
1263 /* gpio5 */
1264 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1265         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1266         { .irq = -1 }
1267 };
1268
1269 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1270         { .role = "dbclk", .clk = "gpio5_dbclk" },
1271 };
1272
1273 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1274         .name           = "gpio5",
1275         .class          = &omap44xx_gpio_hwmod_class,
1276         .clkdm_name     = "l4_per_clkdm",
1277         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1278         .mpu_irqs       = omap44xx_gpio5_irqs,
1279         .main_clk       = "gpio5_ick",
1280         .prcm = {
1281                 .omap4 = {
1282                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1283                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1284                         .modulemode   = MODULEMODE_HWCTRL,
1285                 },
1286         },
1287         .opt_clks       = gpio5_opt_clks,
1288         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1289         .dev_attr       = &gpio_dev_attr,
1290 };
1291
1292 /* gpio6 */
1293 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1294         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1295         { .irq = -1 }
1296 };
1297
1298 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1299         { .role = "dbclk", .clk = "gpio6_dbclk" },
1300 };
1301
1302 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1303         .name           = "gpio6",
1304         .class          = &omap44xx_gpio_hwmod_class,
1305         .clkdm_name     = "l4_per_clkdm",
1306         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1307         .mpu_irqs       = omap44xx_gpio6_irqs,
1308         .main_clk       = "gpio6_ick",
1309         .prcm = {
1310                 .omap4 = {
1311                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1312                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1313                         .modulemode   = MODULEMODE_HWCTRL,
1314                 },
1315         },
1316         .opt_clks       = gpio6_opt_clks,
1317         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1318         .dev_attr       = &gpio_dev_attr,
1319 };
1320
1321 /*
1322  * 'gpmc' class
1323  * general purpose memory controller
1324  */
1325
1326 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1327         .rev_offs       = 0x0000,
1328         .sysc_offs      = 0x0010,
1329         .syss_offs      = 0x0014,
1330         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1331                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333         .sysc_fields    = &omap_hwmod_sysc_type1,
1334 };
1335
1336 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1337         .name   = "gpmc",
1338         .sysc   = &omap44xx_gpmc_sysc,
1339 };
1340
1341 /* gpmc */
1342 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1343         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1344         { .irq = -1 }
1345 };
1346
1347 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1348         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1349         { .dma_req = -1 }
1350 };
1351
1352 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1353         .name           = "gpmc",
1354         .class          = &omap44xx_gpmc_hwmod_class,
1355         .clkdm_name     = "l3_2_clkdm",
1356         /*
1357          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1358          * block.  It is not being added due to any known bugs with
1359          * resetting the GPMC IP block, but rather because any timings
1360          * set by the bootloader are not being correctly programmed by
1361          * the kernel from the board file or DT data.
1362          * HWMOD_INIT_NO_RESET should be removed ASAP.
1363          */
1364         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1365         .mpu_irqs       = omap44xx_gpmc_irqs,
1366         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1367         .prcm = {
1368                 .omap4 = {
1369                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1370                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1371                         .modulemode   = MODULEMODE_HWCTRL,
1372                 },
1373         },
1374 };
1375
1376 /*
1377  * 'gpu' class
1378  * 2d/3d graphics accelerator
1379  */
1380
1381 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1382         .rev_offs       = 0x1fc00,
1383         .sysc_offs      = 0x1fc10,
1384         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1387                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1388         .sysc_fields    = &omap_hwmod_sysc_type2,
1389 };
1390
1391 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1392         .name   = "gpu",
1393         .sysc   = &omap44xx_gpu_sysc,
1394 };
1395
1396 /* gpu */
1397 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1398         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1399         { .irq = -1 }
1400 };
1401
1402 static struct omap_hwmod omap44xx_gpu_hwmod = {
1403         .name           = "gpu",
1404         .class          = &omap44xx_gpu_hwmod_class,
1405         .clkdm_name     = "l3_gfx_clkdm",
1406         .mpu_irqs       = omap44xx_gpu_irqs,
1407         .main_clk       = "gpu_fck",
1408         .prcm = {
1409                 .omap4 = {
1410                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1411                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1412                         .modulemode   = MODULEMODE_SWCTRL,
1413                 },
1414         },
1415 };
1416
1417 /*
1418  * 'hdq1w' class
1419  * hdq / 1-wire serial interface controller
1420  */
1421
1422 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1423         .rev_offs       = 0x0000,
1424         .sysc_offs      = 0x0014,
1425         .syss_offs      = 0x0018,
1426         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1427                            SYSS_HAS_RESET_STATUS),
1428         .sysc_fields    = &omap_hwmod_sysc_type1,
1429 };
1430
1431 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1432         .name   = "hdq1w",
1433         .sysc   = &omap44xx_hdq1w_sysc,
1434 };
1435
1436 /* hdq1w */
1437 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1438         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1439         { .irq = -1 }
1440 };
1441
1442 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1443         .name           = "hdq1w",
1444         .class          = &omap44xx_hdq1w_hwmod_class,
1445         .clkdm_name     = "l4_per_clkdm",
1446         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1447         .mpu_irqs       = omap44xx_hdq1w_irqs,
1448         .main_clk       = "hdq1w_fck",
1449         .prcm = {
1450                 .omap4 = {
1451                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1452                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1453                         .modulemode   = MODULEMODE_SWCTRL,
1454                 },
1455         },
1456 };
1457
1458 /*
1459  * 'hsi' class
1460  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1461  * serial if)
1462  */
1463
1464 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1465         .rev_offs       = 0x0000,
1466         .sysc_offs      = 0x0010,
1467         .syss_offs      = 0x0014,
1468         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1469                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1470                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1471         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1473                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1474         .sysc_fields    = &omap_hwmod_sysc_type1,
1475 };
1476
1477 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1478         .name   = "hsi",
1479         .sysc   = &omap44xx_hsi_sysc,
1480 };
1481
1482 /* hsi */
1483 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1484         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1485         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1487         { .irq = -1 }
1488 };
1489
1490 static struct omap_hwmod omap44xx_hsi_hwmod = {
1491         .name           = "hsi",
1492         .class          = &omap44xx_hsi_hwmod_class,
1493         .clkdm_name     = "l3_init_clkdm",
1494         .mpu_irqs       = omap44xx_hsi_irqs,
1495         .main_clk       = "hsi_fck",
1496         .prcm = {
1497                 .omap4 = {
1498                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1499                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1500                         .modulemode   = MODULEMODE_HWCTRL,
1501                 },
1502         },
1503 };
1504
1505 /*
1506  * 'i2c' class
1507  * multimaster high-speed i2c controller
1508  */
1509
1510 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1511         .sysc_offs      = 0x0010,
1512         .syss_offs      = 0x0090,
1513         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1514                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1515                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1517                            SIDLE_SMART_WKUP),
1518         .clockact       = CLOCKACT_TEST_ICLK,
1519         .sysc_fields    = &omap_hwmod_sysc_type1,
1520 };
1521
1522 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1523         .name   = "i2c",
1524         .sysc   = &omap44xx_i2c_sysc,
1525         .rev    = OMAP_I2C_IP_VERSION_2,
1526         .reset  = &omap_i2c_reset,
1527 };
1528
1529 static struct omap_i2c_dev_attr i2c_dev_attr = {
1530         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1531                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "i2c1_fck",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "i2c2_fck",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "i2c3_fck",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "i2c4_fck",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ipu_fck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "iss_fck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "iva_fck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "kbd_fck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "mcasp_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "mcbsp1_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "mcbsp2_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "mcbsp3_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "mcbsp4_fck",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         .mpu_irqs       = omap44xx_mcpdm_irqs,
2130         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2131         .main_clk       = "mcpdm_fck",
2132         .prcm = {
2133                 .omap4 = {
2134                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2135                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2136                         .modulemode   = MODULEMODE_SWCTRL,
2137                 },
2138         },
2139 };
2140
2141 /*
2142  * 'mcspi' class
2143  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2144  * bus
2145  */
2146
2147 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2148         .rev_offs       = 0x0000,
2149         .sysc_offs      = 0x0010,
2150         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2151                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2153                            SIDLE_SMART_WKUP),
2154         .sysc_fields    = &omap_hwmod_sysc_type2,
2155 };
2156
2157 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2158         .name   = "mcspi",
2159         .sysc   = &omap44xx_mcspi_sysc,
2160         .rev    = OMAP4_MCSPI_REV,
2161 };
2162
2163 /* mcspi1 */
2164 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2165         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2166         { .irq = -1 }
2167 };
2168
2169 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2170         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2171         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2172         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2173         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2174         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2175         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2176         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2177         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2178         { .dma_req = -1 }
2179 };
2180
2181 /* mcspi1 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2183         .num_chipselect = 4,
2184 };
2185
2186 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2187         .name           = "mcspi1",
2188         .class          = &omap44xx_mcspi_hwmod_class,
2189         .clkdm_name     = "l4_per_clkdm",
2190         .mpu_irqs       = omap44xx_mcspi1_irqs,
2191         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2192         .main_clk       = "mcspi1_fck",
2193         .prcm = {
2194                 .omap4 = {
2195                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2196                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2197                         .modulemode   = MODULEMODE_SWCTRL,
2198                 },
2199         },
2200         .dev_attr       = &mcspi1_dev_attr,
2201 };
2202
2203 /* mcspi2 */
2204 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2205         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2206         { .irq = -1 }
2207 };
2208
2209 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2210         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2211         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2212         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2214         { .dma_req = -1 }
2215 };
2216
2217 /* mcspi2 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2219         .num_chipselect = 2,
2220 };
2221
2222 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2223         .name           = "mcspi2",
2224         .class          = &omap44xx_mcspi_hwmod_class,
2225         .clkdm_name     = "l4_per_clkdm",
2226         .mpu_irqs       = omap44xx_mcspi2_irqs,
2227         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2228         .main_clk       = "mcspi2_fck",
2229         .prcm = {
2230                 .omap4 = {
2231                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2232                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2233                         .modulemode   = MODULEMODE_SWCTRL,
2234                 },
2235         },
2236         .dev_attr       = &mcspi2_dev_attr,
2237 };
2238
2239 /* mcspi3 */
2240 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2241         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2242         { .irq = -1 }
2243 };
2244
2245 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2246         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2247         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2248         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2249         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2250         { .dma_req = -1 }
2251 };
2252
2253 /* mcspi3 dev_attr */
2254 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2255         .num_chipselect = 2,
2256 };
2257
2258 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2259         .name           = "mcspi3",
2260         .class          = &omap44xx_mcspi_hwmod_class,
2261         .clkdm_name     = "l4_per_clkdm",
2262         .mpu_irqs       = omap44xx_mcspi3_irqs,
2263         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2264         .main_clk       = "mcspi3_fck",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2268                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2269                         .modulemode   = MODULEMODE_SWCTRL,
2270                 },
2271         },
2272         .dev_attr       = &mcspi3_dev_attr,
2273 };
2274
2275 /* mcspi4 */
2276 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2277         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2278         { .irq = -1 }
2279 };
2280
2281 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2282         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2283         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2284         { .dma_req = -1 }
2285 };
2286
2287 /* mcspi4 dev_attr */
2288 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2289         .num_chipselect = 1,
2290 };
2291
2292 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2293         .name           = "mcspi4",
2294         .class          = &omap44xx_mcspi_hwmod_class,
2295         .clkdm_name     = "l4_per_clkdm",
2296         .mpu_irqs       = omap44xx_mcspi4_irqs,
2297         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2298         .main_clk       = "mcspi4_fck",
2299         .prcm = {
2300                 .omap4 = {
2301                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2302                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2303                         .modulemode   = MODULEMODE_SWCTRL,
2304                 },
2305         },
2306         .dev_attr       = &mcspi4_dev_attr,
2307 };
2308
2309 /*
2310  * 'mmc' class
2311  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2312  */
2313
2314 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2315         .rev_offs       = 0x0000,
2316         .sysc_offs      = 0x0010,
2317         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2318                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2319                            SYSC_HAS_SOFTRESET),
2320         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2321                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2322                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2323         .sysc_fields    = &omap_hwmod_sysc_type2,
2324 };
2325
2326 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2327         .name   = "mmc",
2328         .sysc   = &omap44xx_mmc_sysc,
2329 };
2330
2331 /* mmc1 */
2332 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2333         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2334         { .irq = -1 }
2335 };
2336
2337 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2338         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2339         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2340         { .dma_req = -1 }
2341 };
2342
2343 /* mmc1 dev_attr */
2344 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2345         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2346 };
2347
2348 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2349         .name           = "mmc1",
2350         .class          = &omap44xx_mmc_hwmod_class,
2351         .clkdm_name     = "l3_init_clkdm",
2352         .mpu_irqs       = omap44xx_mmc1_irqs,
2353         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2354         .main_clk       = "mmc1_fck",
2355         .prcm = {
2356                 .omap4 = {
2357                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2358                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2359                         .modulemode   = MODULEMODE_SWCTRL,
2360                 },
2361         },
2362         .dev_attr       = &mmc1_dev_attr,
2363 };
2364
2365 /* mmc2 */
2366 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2367         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2368         { .irq = -1 }
2369 };
2370
2371 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2372         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2373         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2374         { .dma_req = -1 }
2375 };
2376
2377 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2378         .name           = "mmc2",
2379         .class          = &omap44xx_mmc_hwmod_class,
2380         .clkdm_name     = "l3_init_clkdm",
2381         .mpu_irqs       = omap44xx_mmc2_irqs,
2382         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2383         .main_clk       = "mmc2_fck",
2384         .prcm = {
2385                 .omap4 = {
2386                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2387                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2388                         .modulemode   = MODULEMODE_SWCTRL,
2389                 },
2390         },
2391 };
2392
2393 /* mmc3 */
2394 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2395         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2396         { .irq = -1 }
2397 };
2398
2399 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2400         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2401         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2402         { .dma_req = -1 }
2403 };
2404
2405 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2406         .name           = "mmc3",
2407         .class          = &omap44xx_mmc_hwmod_class,
2408         .clkdm_name     = "l4_per_clkdm",
2409         .mpu_irqs       = omap44xx_mmc3_irqs,
2410         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2411         .main_clk       = "mmc3_fck",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2415                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419 };
2420
2421 /* mmc4 */
2422 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2423         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2424         { .irq = -1 }
2425 };
2426
2427 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2428         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2429         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2430         { .dma_req = -1 }
2431 };
2432
2433 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2434         .name           = "mmc4",
2435         .class          = &omap44xx_mmc_hwmod_class,
2436         .clkdm_name     = "l4_per_clkdm",
2437         .mpu_irqs       = omap44xx_mmc4_irqs,
2438         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2439         .main_clk       = "mmc4_fck",
2440         .prcm = {
2441                 .omap4 = {
2442                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2443                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2444                         .modulemode   = MODULEMODE_SWCTRL,
2445                 },
2446         },
2447 };
2448
2449 /* mmc5 */
2450 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2451         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2452         { .irq = -1 }
2453 };
2454
2455 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2456         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2457         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2458         { .dma_req = -1 }
2459 };
2460
2461 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2462         .name           = "mmc5",
2463         .class          = &omap44xx_mmc_hwmod_class,
2464         .clkdm_name     = "l4_per_clkdm",
2465         .mpu_irqs       = omap44xx_mmc5_irqs,
2466         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2467         .main_clk       = "mmc5_fck",
2468         .prcm = {
2469                 .omap4 = {
2470                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2471                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2472                         .modulemode   = MODULEMODE_SWCTRL,
2473                 },
2474         },
2475 };
2476
2477 /*
2478  * 'mmu' class
2479  * The memory management unit performs virtual to physical address translation
2480  * for its requestors.
2481  */
2482
2483 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2484         .rev_offs       = 0x000,
2485         .sysc_offs      = 0x010,
2486         .syss_offs      = 0x014,
2487         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2488                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2489         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2490         .sysc_fields    = &omap_hwmod_sysc_type1,
2491 };
2492
2493 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2494         .name = "mmu",
2495         .sysc = &mmu_sysc,
2496 };
2497
2498 /* mmu ipu */
2499
2500 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2501         .da_start       = 0x0,
2502         .da_end         = 0xfffff000,
2503         .nr_tlb_entries = 32,
2504 };
2505
2506 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2507 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2508         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2509         { .irq = -1 }
2510 };
2511
2512 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2513         { .name = "mmu_cache", .rst_shift = 2 },
2514 };
2515
2516 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2517         {
2518                 .pa_start       = 0x55082000,
2519                 .pa_end         = 0x550820ff,
2520                 .flags          = ADDR_TYPE_RT,
2521         },
2522         { }
2523 };
2524
2525 /* l3_main_2 -> mmu_ipu */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2527         .master         = &omap44xx_l3_main_2_hwmod,
2528         .slave          = &omap44xx_mmu_ipu_hwmod,
2529         .clk            = "l3_div_ck",
2530         .addr           = omap44xx_mmu_ipu_addrs,
2531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2532 };
2533
2534 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2535         .name           = "mmu_ipu",
2536         .class          = &omap44xx_mmu_hwmod_class,
2537         .clkdm_name     = "ducati_clkdm",
2538         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2539         .rst_lines      = omap44xx_mmu_ipu_resets,
2540         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2541         .main_clk       = "ducati_clk_mux_ck",
2542         .prcm = {
2543                 .omap4 = {
2544                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2545                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2546                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2547                         .modulemode   = MODULEMODE_HWCTRL,
2548                 },
2549         },
2550         .dev_attr       = &mmu_ipu_dev_attr,
2551 };
2552
2553 /* mmu dsp */
2554
2555 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2556         .da_start       = 0x0,
2557         .da_end         = 0xfffff000,
2558         .nr_tlb_entries = 32,
2559 };
2560
2561 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2562 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2563         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2564         { .irq = -1 }
2565 };
2566
2567 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2568         { .name = "mmu_cache", .rst_shift = 1 },
2569 };
2570
2571 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2572         {
2573                 .pa_start       = 0x4a066000,
2574                 .pa_end         = 0x4a0660ff,
2575                 .flags          = ADDR_TYPE_RT,
2576         },
2577         { }
2578 };
2579
2580 /* l4_cfg -> dsp */
2581 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2582         .master         = &omap44xx_l4_cfg_hwmod,
2583         .slave          = &omap44xx_mmu_dsp_hwmod,
2584         .clk            = "l4_div_ck",
2585         .addr           = omap44xx_mmu_dsp_addrs,
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2590         .name           = "mmu_dsp",
2591         .class          = &omap44xx_mmu_hwmod_class,
2592         .clkdm_name     = "tesla_clkdm",
2593         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2594         .rst_lines      = omap44xx_mmu_dsp_resets,
2595         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2596         .main_clk       = "dpll_iva_m4x2_ck",
2597         .prcm = {
2598                 .omap4 = {
2599                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2600                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2601                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2602                         .modulemode   = MODULEMODE_HWCTRL,
2603                 },
2604         },
2605         .dev_attr       = &mmu_dsp_dev_attr,
2606 };
2607
2608 /*
2609  * 'mpu' class
2610  * mpu sub-system
2611  */
2612
2613 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2614         .name   = "mpu",
2615 };
2616
2617 /* mpu */
2618 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2619         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2620         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2621         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2624         { .irq = -1 }
2625 };
2626
2627 static struct omap_hwmod omap44xx_mpu_hwmod = {
2628         .name           = "mpu",
2629         .class          = &omap44xx_mpu_hwmod_class,
2630         .clkdm_name     = "mpuss_clkdm",
2631         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2632         .mpu_irqs       = omap44xx_mpu_irqs,
2633         .main_clk       = "dpll_mpu_m2_ck",
2634         .prcm = {
2635                 .omap4 = {
2636                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2637                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2638                 },
2639         },
2640 };
2641
2642 /*
2643  * 'ocmc_ram' class
2644  * top-level core on-chip ram
2645  */
2646
2647 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2648         .name   = "ocmc_ram",
2649 };
2650
2651 /* ocmc_ram */
2652 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2653         .name           = "ocmc_ram",
2654         .class          = &omap44xx_ocmc_ram_hwmod_class,
2655         .clkdm_name     = "l3_2_clkdm",
2656         .prcm = {
2657                 .omap4 = {
2658                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2659                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2660                 },
2661         },
2662 };
2663
2664 /*
2665  * 'ocp2scp' class
2666  * bridge to transform ocp interface protocol to scp (serial control port)
2667  * protocol
2668  */
2669
2670 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2671         .rev_offs       = 0x0000,
2672         .sysc_offs      = 0x0010,
2673         .syss_offs      = 0x0014,
2674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2675                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2677         .sysc_fields    = &omap_hwmod_sysc_type1,
2678 };
2679
2680 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2681         .name   = "ocp2scp",
2682         .sysc   = &omap44xx_ocp2scp_sysc,
2683 };
2684
2685 /* ocp2scp_usb_phy */
2686 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2687         .name           = "ocp2scp_usb_phy",
2688         .class          = &omap44xx_ocp2scp_hwmod_class,
2689         .clkdm_name     = "l3_init_clkdm",
2690         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2691         .prcm = {
2692                 .omap4 = {
2693                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2694                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2695                         .modulemode   = MODULEMODE_HWCTRL,
2696                 },
2697         },
2698 };
2699
2700 /*
2701  * 'prcm' class
2702  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2703  * + clock manager 1 (in always on power domain) + local prm in mpu
2704  */
2705
2706 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2707         .name   = "prcm",
2708 };
2709
2710 /* prcm_mpu */
2711 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2712         .name           = "prcm_mpu",
2713         .class          = &omap44xx_prcm_hwmod_class,
2714         .clkdm_name     = "l4_wkup_clkdm",
2715         .flags          = HWMOD_NO_IDLEST,
2716         .prcm = {
2717                 .omap4 = {
2718                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2719                 },
2720         },
2721 };
2722
2723 /* cm_core_aon */
2724 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2725         .name           = "cm_core_aon",
2726         .class          = &omap44xx_prcm_hwmod_class,
2727         .flags          = HWMOD_NO_IDLEST,
2728         .prcm = {
2729                 .omap4 = {
2730                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2731                 },
2732         },
2733 };
2734
2735 /* cm_core */
2736 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2737         .name           = "cm_core",
2738         .class          = &omap44xx_prcm_hwmod_class,
2739         .flags          = HWMOD_NO_IDLEST,
2740         .prcm = {
2741                 .omap4 = {
2742                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2743                 },
2744         },
2745 };
2746
2747 /* prm */
2748 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2749         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2750         { .irq = -1 }
2751 };
2752
2753 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2754         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2755         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2756 };
2757
2758 static struct omap_hwmod omap44xx_prm_hwmod = {
2759         .name           = "prm",
2760         .class          = &omap44xx_prcm_hwmod_class,
2761         .mpu_irqs       = omap44xx_prm_irqs,
2762         .rst_lines      = omap44xx_prm_resets,
2763         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2764 };
2765
2766 /*
2767  * 'scrm' class
2768  * system clock and reset manager
2769  */
2770
2771 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2772         .name   = "scrm",
2773 };
2774
2775 /* scrm */
2776 static struct omap_hwmod omap44xx_scrm_hwmod = {
2777         .name           = "scrm",
2778         .class          = &omap44xx_scrm_hwmod_class,
2779         .clkdm_name     = "l4_wkup_clkdm",
2780         .prcm = {
2781                 .omap4 = {
2782                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2783                 },
2784         },
2785 };
2786
2787 /*
2788  * 'sl2if' class
2789  * shared level 2 memory interface
2790  */
2791
2792 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2793         .name   = "sl2if",
2794 };
2795
2796 /* sl2if */
2797 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2798         .name           = "sl2if",
2799         .class          = &omap44xx_sl2if_hwmod_class,
2800         .clkdm_name     = "ivahd_clkdm",
2801         .prcm = {
2802                 .omap4 = {
2803                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2804                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2805                         .modulemode   = MODULEMODE_HWCTRL,
2806                 },
2807         },
2808 };
2809
2810 /*
2811  * 'slimbus' class
2812  * bidirectional, multi-drop, multi-channel two-line serial interface between
2813  * the device and external components
2814  */
2815
2816 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2817         .rev_offs       = 0x0000,
2818         .sysc_offs      = 0x0010,
2819         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2820                            SYSC_HAS_SOFTRESET),
2821         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2822                            SIDLE_SMART_WKUP),
2823         .sysc_fields    = &omap_hwmod_sysc_type2,
2824 };
2825
2826 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2827         .name   = "slimbus",
2828         .sysc   = &omap44xx_slimbus_sysc,
2829 };
2830
2831 /* slimbus1 */
2832 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2833         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2834         { .irq = -1 }
2835 };
2836
2837 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2838         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2839         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2840         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2841         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2842         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2843         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2844         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2845         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2846         { .dma_req = -1 }
2847 };
2848
2849 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2850         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2851         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2852         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2853         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2854 };
2855
2856 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2857         .name           = "slimbus1",
2858         .class          = &omap44xx_slimbus_hwmod_class,
2859         .clkdm_name     = "abe_clkdm",
2860         .mpu_irqs       = omap44xx_slimbus1_irqs,
2861         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2862         .prcm = {
2863                 .omap4 = {
2864                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2865                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2866                         .modulemode   = MODULEMODE_SWCTRL,
2867                 },
2868         },
2869         .opt_clks       = slimbus1_opt_clks,
2870         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2871 };
2872
2873 /* slimbus2 */
2874 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2875         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2876         { .irq = -1 }
2877 };
2878
2879 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2880         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2881         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2883         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2884         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2887         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2888         { .dma_req = -1 }
2889 };
2890
2891 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2892         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2893         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2894         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2895 };
2896
2897 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2898         .name           = "slimbus2",
2899         .class          = &omap44xx_slimbus_hwmod_class,
2900         .clkdm_name     = "l4_per_clkdm",
2901         .mpu_irqs       = omap44xx_slimbus2_irqs,
2902         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2903         .prcm = {
2904                 .omap4 = {
2905                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2906                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2907                         .modulemode   = MODULEMODE_SWCTRL,
2908                 },
2909         },
2910         .opt_clks       = slimbus2_opt_clks,
2911         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2912 };
2913
2914 /*
2915  * 'smartreflex' class
2916  * smartreflex module (monitor silicon performance and outputs a measure of
2917  * performance error)
2918  */
2919
2920 /* The IP is not compliant to type1 / type2 scheme */
2921 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2922         .sidle_shift    = 24,
2923         .enwkup_shift   = 26,
2924 };
2925
2926 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2927         .sysc_offs      = 0x0038,
2928         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2929         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2930                            SIDLE_SMART_WKUP),
2931         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2932 };
2933
2934 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2935         .name   = "smartreflex",
2936         .sysc   = &omap44xx_smartreflex_sysc,
2937         .rev    = 2,
2938 };
2939
2940 /* smartreflex_core */
2941 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2942         .sensor_voltdm_name   = "core",
2943 };
2944
2945 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2946         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2947         { .irq = -1 }
2948 };
2949
2950 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2951         .name           = "smartreflex_core",
2952         .class          = &omap44xx_smartreflex_hwmod_class,
2953         .clkdm_name     = "l4_ao_clkdm",
2954         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2955
2956         .main_clk       = "smartreflex_core_fck",
2957         .prcm = {
2958                 .omap4 = {
2959                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2960                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2961                         .modulemode   = MODULEMODE_SWCTRL,
2962                 },
2963         },
2964         .dev_attr       = &smartreflex_core_dev_attr,
2965 };
2966
2967 /* smartreflex_iva */
2968 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2969         .sensor_voltdm_name     = "iva",
2970 };
2971
2972 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2973         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2974         { .irq = -1 }
2975 };
2976
2977 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2978         .name           = "smartreflex_iva",
2979         .class          = &omap44xx_smartreflex_hwmod_class,
2980         .clkdm_name     = "l4_ao_clkdm",
2981         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2982         .main_clk       = "smartreflex_iva_fck",
2983         .prcm = {
2984                 .omap4 = {
2985                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2986                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2987                         .modulemode   = MODULEMODE_SWCTRL,
2988                 },
2989         },
2990         .dev_attr       = &smartreflex_iva_dev_attr,
2991 };
2992
2993 /* smartreflex_mpu */
2994 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2995         .sensor_voltdm_name     = "mpu",
2996 };
2997
2998 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2999         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3000         { .irq = -1 }
3001 };
3002
3003 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3004         .name           = "smartreflex_mpu",
3005         .class          = &omap44xx_smartreflex_hwmod_class,
3006         .clkdm_name     = "l4_ao_clkdm",
3007         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3008         .main_clk       = "smartreflex_mpu_fck",
3009         .prcm = {
3010                 .omap4 = {
3011                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3012                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3013                         .modulemode   = MODULEMODE_SWCTRL,
3014                 },
3015         },
3016         .dev_attr       = &smartreflex_mpu_dev_attr,
3017 };
3018
3019 /*
3020  * 'spinlock' class
3021  * spinlock provides hardware assistance for synchronizing the processes
3022  * running on multiple processors
3023  */
3024
3025 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3026         .rev_offs       = 0x0000,
3027         .sysc_offs      = 0x0010,
3028         .syss_offs      = 0x0014,
3029         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3030                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3031                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3032         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3033                            SIDLE_SMART_WKUP),
3034         .sysc_fields    = &omap_hwmod_sysc_type1,
3035 };
3036
3037 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3038         .name   = "spinlock",
3039         .sysc   = &omap44xx_spinlock_sysc,
3040 };
3041
3042 /* spinlock */
3043 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3044         .name           = "spinlock",
3045         .class          = &omap44xx_spinlock_hwmod_class,
3046         .clkdm_name     = "l4_cfg_clkdm",
3047         .prcm = {
3048                 .omap4 = {
3049                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3050                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3051                 },
3052         },
3053 };
3054
3055 /*
3056  * 'timer' class
3057  * general purpose timer module with accurate 1ms tick
3058  * This class contains several variants: ['timer_1ms', 'timer']
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .syss_offs      = 0x0014,
3065         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3066                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3067                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3068                            SYSS_HAS_RESET_STATUS),
3069         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3070         .sysc_fields    = &omap_hwmod_sysc_type1,
3071 };
3072
3073 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3074         .name   = "timer",
3075         .sysc   = &omap44xx_timer_1ms_sysc,
3076 };
3077
3078 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3079         .rev_offs       = 0x0000,
3080         .sysc_offs      = 0x0010,
3081         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3082                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3083         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3084                            SIDLE_SMART_WKUP),
3085         .sysc_fields    = &omap_hwmod_sysc_type2,
3086 };
3087
3088 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3089         .name   = "timer",
3090         .sysc   = &omap44xx_timer_sysc,
3091 };
3092
3093 /* always-on timers dev attribute */
3094 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3095         .timer_capability       = OMAP_TIMER_ALWON,
3096 };
3097
3098 /* pwm timers dev attribute */
3099 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3100         .timer_capability       = OMAP_TIMER_HAS_PWM,
3101 };
3102
3103 /* timers with DSP interrupt dev attribute */
3104 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3105         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3106 };
3107
3108 /* pwm timers with DSP interrupt dev attribute */
3109 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3110         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3111 };
3112
3113 /* timer1 */
3114 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3115         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3116         { .irq = -1 }
3117 };
3118
3119 static struct omap_hwmod omap44xx_timer1_hwmod = {
3120         .name           = "timer1",
3121         .class          = &omap44xx_timer_1ms_hwmod_class,
3122         .clkdm_name     = "l4_wkup_clkdm",
3123         .mpu_irqs       = omap44xx_timer1_irqs,
3124         .main_clk       = "timer1_fck",
3125         .prcm = {
3126                 .omap4 = {
3127                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3128                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3129                         .modulemode   = MODULEMODE_SWCTRL,
3130                 },
3131         },
3132         .dev_attr       = &capability_alwon_dev_attr,
3133 };
3134
3135 /* timer2 */
3136 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3137         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3138         { .irq = -1 }
3139 };
3140
3141 static struct omap_hwmod omap44xx_timer2_hwmod = {
3142         .name           = "timer2",
3143         .class          = &omap44xx_timer_1ms_hwmod_class,
3144         .clkdm_name     = "l4_per_clkdm",
3145         .mpu_irqs       = omap44xx_timer2_irqs,
3146         .main_clk       = "timer2_fck",
3147         .prcm = {
3148                 .omap4 = {
3149                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3150                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3151                         .modulemode   = MODULEMODE_SWCTRL,
3152                 },
3153         },
3154 };
3155
3156 /* timer3 */
3157 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3158         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3159         { .irq = -1 }
3160 };
3161
3162 static struct omap_hwmod omap44xx_timer3_hwmod = {
3163         .name           = "timer3",
3164         .class          = &omap44xx_timer_hwmod_class,
3165         .clkdm_name     = "l4_per_clkdm",
3166         .mpu_irqs       = omap44xx_timer3_irqs,
3167         .main_clk       = "timer3_fck",
3168         .prcm = {
3169                 .omap4 = {
3170                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3171                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3172                         .modulemode   = MODULEMODE_SWCTRL,
3173                 },
3174         },
3175 };
3176
3177 /* timer4 */
3178 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3179         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3180         { .irq = -1 }
3181 };
3182
3183 static struct omap_hwmod omap44xx_timer4_hwmod = {
3184         .name           = "timer4",
3185         .class          = &omap44xx_timer_hwmod_class,
3186         .clkdm_name     = "l4_per_clkdm",
3187         .mpu_irqs       = omap44xx_timer4_irqs,
3188         .main_clk       = "timer4_fck",
3189         .prcm = {
3190                 .omap4 = {
3191                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3192                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3193                         .modulemode   = MODULEMODE_SWCTRL,
3194                 },
3195         },
3196 };
3197
3198 /* timer5 */
3199 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3200         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3201         { .irq = -1 }
3202 };
3203
3204 static struct omap_hwmod omap44xx_timer5_hwmod = {
3205         .name           = "timer5",
3206         .class          = &omap44xx_timer_hwmod_class,
3207         .clkdm_name     = "abe_clkdm",
3208         .mpu_irqs       = omap44xx_timer5_irqs,
3209         .main_clk       = "timer5_fck",
3210         .prcm = {
3211                 .omap4 = {
3212                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3213                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3214                         .modulemode   = MODULEMODE_SWCTRL,
3215                 },
3216         },
3217         .dev_attr       = &capability_dsp_dev_attr,
3218 };
3219
3220 /* timer6 */
3221 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3222         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3223         { .irq = -1 }
3224 };
3225
3226 static struct omap_hwmod omap44xx_timer6_hwmod = {
3227         .name           = "timer6",
3228         .class          = &omap44xx_timer_hwmod_class,
3229         .clkdm_name     = "abe_clkdm",
3230         .mpu_irqs       = omap44xx_timer6_irqs,
3231
3232         .main_clk       = "timer6_fck",
3233         .prcm = {
3234                 .omap4 = {
3235                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3236                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3237                         .modulemode   = MODULEMODE_SWCTRL,
3238                 },
3239         },
3240         .dev_attr       = &capability_dsp_dev_attr,
3241 };
3242
3243 /* timer7 */
3244 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3245         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3246         { .irq = -1 }
3247 };
3248
3249 static struct omap_hwmod omap44xx_timer7_hwmod = {
3250         .name           = "timer7",
3251         .class          = &omap44xx_timer_hwmod_class,
3252         .clkdm_name     = "abe_clkdm",
3253         .mpu_irqs       = omap44xx_timer7_irqs,
3254         .main_clk       = "timer7_fck",
3255         .prcm = {
3256                 .omap4 = {
3257                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3258                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3259                         .modulemode   = MODULEMODE_SWCTRL,
3260                 },
3261         },
3262         .dev_attr       = &capability_dsp_dev_attr,
3263 };
3264
3265 /* timer8 */
3266 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3267         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3268         { .irq = -1 }
3269 };
3270
3271 static struct omap_hwmod omap44xx_timer8_hwmod = {
3272         .name           = "timer8",
3273         .class          = &omap44xx_timer_hwmod_class,
3274         .clkdm_name     = "abe_clkdm",
3275         .mpu_irqs       = omap44xx_timer8_irqs,
3276         .main_clk       = "timer8_fck",
3277         .prcm = {
3278                 .omap4 = {
3279                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3280                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3281                         .modulemode   = MODULEMODE_SWCTRL,
3282                 },
3283         },
3284         .dev_attr       = &capability_dsp_pwm_dev_attr,
3285 };
3286
3287 /* timer9 */
3288 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3289         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3290         { .irq = -1 }
3291 };
3292
3293 static struct omap_hwmod omap44xx_timer9_hwmod = {
3294         .name           = "timer9",
3295         .class          = &omap44xx_timer_hwmod_class,
3296         .clkdm_name     = "l4_per_clkdm",
3297         .mpu_irqs       = omap44xx_timer9_irqs,
3298         .main_clk       = "timer9_fck",
3299         .prcm = {
3300                 .omap4 = {
3301                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3302                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3303                         .modulemode   = MODULEMODE_SWCTRL,
3304                 },
3305         },
3306         .dev_attr       = &capability_pwm_dev_attr,
3307 };
3308
3309 /* timer10 */
3310 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3311         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3312         { .irq = -1 }
3313 };
3314
3315 static struct omap_hwmod omap44xx_timer10_hwmod = {
3316         .name           = "timer10",
3317         .class          = &omap44xx_timer_1ms_hwmod_class,
3318         .clkdm_name     = "l4_per_clkdm",
3319         .mpu_irqs       = omap44xx_timer10_irqs,
3320         .main_clk       = "timer10_fck",
3321         .prcm = {
3322                 .omap4 = {
3323                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3324                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3325                         .modulemode   = MODULEMODE_SWCTRL,
3326                 },
3327         },
3328         .dev_attr       = &capability_pwm_dev_attr,
3329 };
3330
3331 /* timer11 */
3332 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3333         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3334         { .irq = -1 }
3335 };
3336
3337 static struct omap_hwmod omap44xx_timer11_hwmod = {
3338         .name           = "timer11",
3339         .class          = &omap44xx_timer_hwmod_class,
3340         .clkdm_name     = "l4_per_clkdm",
3341         .mpu_irqs       = omap44xx_timer11_irqs,
3342         .main_clk       = "timer11_fck",
3343         .prcm = {
3344                 .omap4 = {
3345                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3346                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3347                         .modulemode   = MODULEMODE_SWCTRL,
3348                 },
3349         },
3350         .dev_attr       = &capability_pwm_dev_attr,
3351 };
3352
3353 /*
3354  * 'uart' class
3355  * universal asynchronous receiver/transmitter (uart)
3356  */
3357
3358 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3359         .rev_offs       = 0x0050,
3360         .sysc_offs      = 0x0054,
3361         .syss_offs      = 0x0058,
3362         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3363                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3364                            SYSS_HAS_RESET_STATUS),
3365         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3366                            SIDLE_SMART_WKUP),
3367         .sysc_fields    = &omap_hwmod_sysc_type1,
3368 };
3369
3370 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3371         .name   = "uart",
3372         .sysc   = &omap44xx_uart_sysc,
3373 };
3374
3375 /* uart1 */
3376 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3377         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3378         { .irq = -1 }
3379 };
3380
3381 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3382         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3383         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3384         { .dma_req = -1 }
3385 };
3386
3387 static struct omap_hwmod omap44xx_uart1_hwmod = {
3388         .name           = "uart1",
3389         .class          = &omap44xx_uart_hwmod_class,
3390         .clkdm_name     = "l4_per_clkdm",
3391         .mpu_irqs       = omap44xx_uart1_irqs,
3392         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3393         .main_clk       = "uart1_fck",
3394         .prcm = {
3395                 .omap4 = {
3396                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3397                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3398                         .modulemode   = MODULEMODE_SWCTRL,
3399                 },
3400         },
3401 };
3402
3403 /* uart2 */
3404 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3405         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3406         { .irq = -1 }
3407 };
3408
3409 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3410         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3411         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3412         { .dma_req = -1 }
3413 };
3414
3415 static struct omap_hwmod omap44xx_uart2_hwmod = {
3416         .name           = "uart2",
3417         .class          = &omap44xx_uart_hwmod_class,
3418         .clkdm_name     = "l4_per_clkdm",
3419         .mpu_irqs       = omap44xx_uart2_irqs,
3420         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3421         .main_clk       = "uart2_fck",
3422         .prcm = {
3423                 .omap4 = {
3424                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3425                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3426                         .modulemode   = MODULEMODE_SWCTRL,
3427                 },
3428         },
3429 };
3430
3431 /* uart3 */
3432 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3433         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3434         { .irq = -1 }
3435 };
3436
3437 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3438         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3439         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3440         { .dma_req = -1 }
3441 };
3442
3443 static struct omap_hwmod omap44xx_uart3_hwmod = {
3444         .name           = "uart3",
3445         .class          = &omap44xx_uart_hwmod_class,
3446         .clkdm_name     = "l4_per_clkdm",
3447         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3448         .mpu_irqs       = omap44xx_uart3_irqs,
3449         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3450         .main_clk       = "uart3_fck",
3451         .prcm = {
3452                 .omap4 = {
3453                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3454                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3455                         .modulemode   = MODULEMODE_SWCTRL,
3456                 },
3457         },
3458 };
3459
3460 /* uart4 */
3461 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3462         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3463         { .irq = -1 }
3464 };
3465
3466 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3467         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3468         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3469         { .dma_req = -1 }
3470 };
3471
3472 static struct omap_hwmod omap44xx_uart4_hwmod = {
3473         .name           = "uart4",
3474         .class          = &omap44xx_uart_hwmod_class,
3475         .clkdm_name     = "l4_per_clkdm",
3476         .mpu_irqs       = omap44xx_uart4_irqs,
3477         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3478         .main_clk       = "uart4_fck",
3479         .prcm = {
3480                 .omap4 = {
3481                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3482                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3483                         .modulemode   = MODULEMODE_SWCTRL,
3484                 },
3485         },
3486 };
3487
3488 /*
3489  * 'usb_host_fs' class
3490  * full-speed usb host controller
3491  */
3492
3493 /* The IP is not compliant to type1 / type2 scheme */
3494 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3495         .midle_shift    = 4,
3496         .sidle_shift    = 2,
3497         .srst_shift     = 1,
3498 };
3499
3500 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3501         .rev_offs       = 0x0000,
3502         .sysc_offs      = 0x0210,
3503         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3504                            SYSC_HAS_SOFTRESET),
3505         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3506                            SIDLE_SMART_WKUP),
3507         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3508 };
3509
3510 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3511         .name   = "usb_host_fs",
3512         .sysc   = &omap44xx_usb_host_fs_sysc,
3513 };
3514
3515 /* usb_host_fs */
3516 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3517         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3518         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3519         { .irq = -1 }
3520 };
3521
3522 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3523         .name           = "usb_host_fs",
3524         .class          = &omap44xx_usb_host_fs_hwmod_class,
3525         .clkdm_name     = "l3_init_clkdm",
3526         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3527         .main_clk       = "usb_host_fs_fck",
3528         .prcm = {
3529                 .omap4 = {
3530                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3531                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3532                         .modulemode   = MODULEMODE_SWCTRL,
3533                 },
3534         },
3535 };
3536
3537 /*
3538  * 'usb_host_hs' class
3539  * high-speed multi-port usb host controller
3540  */
3541
3542 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3543         .rev_offs       = 0x0000,
3544         .sysc_offs      = 0x0010,
3545         .syss_offs      = 0x0014,
3546         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3547                            SYSC_HAS_SOFTRESET),
3548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3549                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3550                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3551         .sysc_fields    = &omap_hwmod_sysc_type2,
3552 };
3553
3554 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3555         .name   = "usb_host_hs",
3556         .sysc   = &omap44xx_usb_host_hs_sysc,
3557 };
3558
3559 /* usb_host_hs */
3560 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3561         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3562         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3563         { .irq = -1 }
3564 };
3565
3566 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3567         .name           = "usb_host_hs",
3568         .class          = &omap44xx_usb_host_hs_hwmod_class,
3569         .clkdm_name     = "l3_init_clkdm",
3570         .main_clk       = "usb_host_hs_fck",
3571         .prcm = {
3572                 .omap4 = {
3573                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3574                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3575                         .modulemode   = MODULEMODE_SWCTRL,
3576                 },
3577         },
3578         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3579
3580         /*
3581          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3582          * id: i660
3583          *
3584          * Description:
3585          * In the following configuration :
3586          * - USBHOST module is set to smart-idle mode
3587          * - PRCM asserts idle_req to the USBHOST module ( This typically
3588          *   happens when the system is going to a low power mode : all ports
3589          *   have been suspended, the master part of the USBHOST module has
3590          *   entered the standby state, and SW has cut the functional clocks)
3591          * - an USBHOST interrupt occurs before the module is able to answer
3592          *   idle_ack, typically a remote wakeup IRQ.
3593          * Then the USB HOST module will enter a deadlock situation where it
3594          * is no more accessible nor functional.
3595          *
3596          * Workaround:
3597          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3598          */
3599
3600         /*
3601          * Errata: USB host EHCI may stall when entering smart-standby mode
3602          * Id: i571
3603          *
3604          * Description:
3605          * When the USBHOST module is set to smart-standby mode, and when it is
3606          * ready to enter the standby state (i.e. all ports are suspended and
3607          * all attached devices are in suspend mode), then it can wrongly assert
3608          * the Mstandby signal too early while there are still some residual OCP
3609          * transactions ongoing. If this condition occurs, the internal state
3610          * machine may go to an undefined state and the USB link may be stuck
3611          * upon the next resume.
3612          *
3613          * Workaround:
3614          * Don't use smart standby; use only force standby,
3615          * hence HWMOD_SWSUP_MSTANDBY
3616          */
3617
3618         /*
3619          * During system boot; If the hwmod framework resets the module
3620          * the module will have smart idle settings; which can lead to deadlock
3621          * (above Errata Id:i660); so, dont reset the module during boot;
3622          * Use HWMOD_INIT_NO_RESET.
3623          */
3624
3625         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3626                           HWMOD_INIT_NO_RESET,
3627 };
3628
3629 /*
3630  * 'usb_otg_hs' class
3631  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3632  */
3633
3634 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3635         .rev_offs       = 0x0400,
3636         .sysc_offs      = 0x0404,
3637         .syss_offs      = 0x0408,
3638         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3639                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3640                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3641         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3642                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3643                            MSTANDBY_SMART),
3644         .sysc_fields    = &omap_hwmod_sysc_type1,
3645 };
3646
3647 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3648         .name   = "usb_otg_hs",
3649         .sysc   = &omap44xx_usb_otg_hs_sysc,
3650 };
3651
3652 /* usb_otg_hs */
3653 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3654         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3655         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3656         { .irq = -1 }
3657 };
3658
3659 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3660         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3661 };
3662
3663 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3664         .name           = "usb_otg_hs",
3665         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3666         .clkdm_name     = "l3_init_clkdm",
3667         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3668         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3669         .main_clk       = "usb_otg_hs_ick",
3670         .prcm = {
3671                 .omap4 = {
3672                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3673                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3674                         .modulemode   = MODULEMODE_HWCTRL,
3675                 },
3676         },
3677         .opt_clks       = usb_otg_hs_opt_clks,
3678         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3679 };
3680
3681 /*
3682  * 'usb_tll_hs' class
3683  * usb_tll_hs module is the adapter on the usb_host_hs ports
3684  */
3685
3686 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3687         .rev_offs       = 0x0000,
3688         .sysc_offs      = 0x0010,
3689         .syss_offs      = 0x0014,
3690         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3691                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3692                            SYSC_HAS_AUTOIDLE),
3693         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3694         .sysc_fields    = &omap_hwmod_sysc_type1,
3695 };
3696
3697 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3698         .name   = "usb_tll_hs",
3699         .sysc   = &omap44xx_usb_tll_hs_sysc,
3700 };
3701
3702 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3703         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3704         { .irq = -1 }
3705 };
3706
3707 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3708         .name           = "usb_tll_hs",
3709         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3710         .clkdm_name     = "l3_init_clkdm",
3711         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3712         .main_clk       = "usb_tll_hs_ick",
3713         .prcm = {
3714                 .omap4 = {
3715                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3716                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3717                         .modulemode   = MODULEMODE_HWCTRL,
3718                 },
3719         },
3720 };
3721
3722 /*
3723  * 'wd_timer' class
3724  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3725  * overflow condition
3726  */
3727
3728 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3729         .rev_offs       = 0x0000,
3730         .sysc_offs      = 0x0010,
3731         .syss_offs      = 0x0014,
3732         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3733                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3735                            SIDLE_SMART_WKUP),
3736         .sysc_fields    = &omap_hwmod_sysc_type1,
3737 };
3738
3739 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3740         .name           = "wd_timer",
3741         .sysc           = &omap44xx_wd_timer_sysc,
3742         .pre_shutdown   = &omap2_wd_timer_disable,
3743         .reset          = &omap2_wd_timer_reset,
3744 };
3745
3746 /* wd_timer2 */
3747 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3748         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3749         { .irq = -1 }
3750 };
3751
3752 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3753         .name           = "wd_timer2",
3754         .class          = &omap44xx_wd_timer_hwmod_class,
3755         .clkdm_name     = "l4_wkup_clkdm",
3756         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3757         .main_clk       = "wd_timer2_fck",
3758         .prcm = {
3759                 .omap4 = {
3760                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3761                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3762                         .modulemode   = MODULEMODE_SWCTRL,
3763                 },
3764         },
3765 };
3766
3767 /* wd_timer3 */
3768 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3769         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3770         { .irq = -1 }
3771 };
3772
3773 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3774         .name           = "wd_timer3",
3775         .class          = &omap44xx_wd_timer_hwmod_class,
3776         .clkdm_name     = "abe_clkdm",
3777         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3778         .main_clk       = "wd_timer3_fck",
3779         .prcm = {
3780                 .omap4 = {
3781                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3782                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3783                         .modulemode   = MODULEMODE_SWCTRL,
3784                 },
3785         },
3786 };
3787
3788
3789 /*
3790  * interfaces
3791  */
3792
3793 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3794         {
3795                 .pa_start       = 0x4a204000,
3796                 .pa_end         = 0x4a2040ff,
3797                 .flags          = ADDR_TYPE_RT
3798         },
3799         { }
3800 };
3801
3802 /* c2c -> c2c_target_fw */
3803 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3804         .master         = &omap44xx_c2c_hwmod,
3805         .slave          = &omap44xx_c2c_target_fw_hwmod,
3806         .clk            = "div_core_ck",
3807         .addr           = omap44xx_c2c_target_fw_addrs,
3808         .user           = OCP_USER_MPU,
3809 };
3810
3811 /* l4_cfg -> c2c_target_fw */
3812 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3813         .master         = &omap44xx_l4_cfg_hwmod,
3814         .slave          = &omap44xx_c2c_target_fw_hwmod,
3815         .clk            = "l4_div_ck",
3816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3817 };
3818
3819 /* l3_main_1 -> dmm */
3820 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3821         .master         = &omap44xx_l3_main_1_hwmod,
3822         .slave          = &omap44xx_dmm_hwmod,
3823         .clk            = "l3_div_ck",
3824         .user           = OCP_USER_SDMA,
3825 };
3826
3827 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3828         {
3829                 .pa_start       = 0x4e000000,
3830                 .pa_end         = 0x4e0007ff,
3831                 .flags          = ADDR_TYPE_RT
3832         },
3833         { }
3834 };
3835
3836 /* mpu -> dmm */
3837 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3838         .master         = &omap44xx_mpu_hwmod,
3839         .slave          = &omap44xx_dmm_hwmod,
3840         .clk            = "l3_div_ck",
3841         .addr           = omap44xx_dmm_addrs,
3842         .user           = OCP_USER_MPU,
3843 };
3844
3845 /* c2c -> emif_fw */
3846 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3847         .master         = &omap44xx_c2c_hwmod,
3848         .slave          = &omap44xx_emif_fw_hwmod,
3849         .clk            = "div_core_ck",
3850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3851 };
3852
3853 /* dmm -> emif_fw */
3854 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3855         .master         = &omap44xx_dmm_hwmod,
3856         .slave          = &omap44xx_emif_fw_hwmod,
3857         .clk            = "l3_div_ck",
3858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3859 };
3860
3861 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3862         {
3863                 .pa_start       = 0x4a20c000,
3864                 .pa_end         = 0x4a20c0ff,
3865                 .flags          = ADDR_TYPE_RT
3866         },
3867         { }
3868 };
3869
3870 /* l4_cfg -> emif_fw */
3871 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3872         .master         = &omap44xx_l4_cfg_hwmod,
3873         .slave          = &omap44xx_emif_fw_hwmod,
3874         .clk            = "l4_div_ck",
3875         .addr           = omap44xx_emif_fw_addrs,
3876         .user           = OCP_USER_MPU,
3877 };
3878
3879 /* iva -> l3_instr */
3880 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3881         .master         = &omap44xx_iva_hwmod,
3882         .slave          = &omap44xx_l3_instr_hwmod,
3883         .clk            = "l3_div_ck",
3884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3885 };
3886
3887 /* l3_main_3 -> l3_instr */
3888 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3889         .master         = &omap44xx_l3_main_3_hwmod,
3890         .slave          = &omap44xx_l3_instr_hwmod,
3891         .clk            = "l3_div_ck",
3892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3893 };
3894
3895 /* ocp_wp_noc -> l3_instr */
3896 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3897         .master         = &omap44xx_ocp_wp_noc_hwmod,
3898         .slave          = &omap44xx_l3_instr_hwmod,
3899         .clk            = "l3_div_ck",
3900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3901 };
3902
3903 /* dsp -> l3_main_1 */
3904 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3905         .master         = &omap44xx_dsp_hwmod,
3906         .slave          = &omap44xx_l3_main_1_hwmod,
3907         .clk            = "l3_div_ck",
3908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3909 };
3910
3911 /* dss -> l3_main_1 */
3912 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3913         .master         = &omap44xx_dss_hwmod,
3914         .slave          = &omap44xx_l3_main_1_hwmod,
3915         .clk            = "l3_div_ck",
3916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3917 };
3918
3919 /* l3_main_2 -> l3_main_1 */
3920 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3921         .master         = &omap44xx_l3_main_2_hwmod,
3922         .slave          = &omap44xx_l3_main_1_hwmod,
3923         .clk            = "l3_div_ck",
3924         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3925 };
3926
3927 /* l4_cfg -> l3_main_1 */
3928 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3929         .master         = &omap44xx_l4_cfg_hwmod,
3930         .slave          = &omap44xx_l3_main_1_hwmod,
3931         .clk            = "l4_div_ck",
3932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3933 };
3934
3935 /* mmc1 -> l3_main_1 */
3936 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3937         .master         = &omap44xx_mmc1_hwmod,
3938         .slave          = &omap44xx_l3_main_1_hwmod,
3939         .clk            = "l3_div_ck",
3940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3941 };
3942
3943 /* mmc2 -> l3_main_1 */
3944 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3945         .master         = &omap44xx_mmc2_hwmod,
3946         .slave          = &omap44xx_l3_main_1_hwmod,
3947         .clk            = "l3_div_ck",
3948         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3949 };
3950
3951 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3952         {
3953                 .pa_start       = 0x44000000,
3954                 .pa_end         = 0x44000fff,
3955                 .flags          = ADDR_TYPE_RT
3956         },
3957         { }
3958 };
3959
3960 /* mpu -> l3_main_1 */
3961 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3962         .master         = &omap44xx_mpu_hwmod,
3963         .slave          = &omap44xx_l3_main_1_hwmod,
3964         .clk            = "l3_div_ck",
3965         .addr           = omap44xx_l3_main_1_addrs,
3966         .user           = OCP_USER_MPU,
3967 };
3968
3969 /* c2c_target_fw -> l3_main_2 */
3970 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3971         .master         = &omap44xx_c2c_target_fw_hwmod,
3972         .slave          = &omap44xx_l3_main_2_hwmod,
3973         .clk            = "l3_div_ck",
3974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 /* debugss -> l3_main_2 */
3978 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3979         .master         = &omap44xx_debugss_hwmod,
3980         .slave          = &omap44xx_l3_main_2_hwmod,
3981         .clk            = "dbgclk_mux_ck",
3982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3983 };
3984
3985 /* dma_system -> l3_main_2 */
3986 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3987         .master         = &omap44xx_dma_system_hwmod,
3988         .slave          = &omap44xx_l3_main_2_hwmod,
3989         .clk            = "l3_div_ck",
3990         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3991 };
3992
3993 /* fdif -> l3_main_2 */
3994 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3995         .master         = &omap44xx_fdif_hwmod,
3996         .slave          = &omap44xx_l3_main_2_hwmod,
3997         .clk            = "l3_div_ck",
3998         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3999 };
4000
4001 /* gpu -> l3_main_2 */
4002 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4003         .master         = &omap44xx_gpu_hwmod,
4004         .slave          = &omap44xx_l3_main_2_hwmod,
4005         .clk            = "l3_div_ck",
4006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4007 };
4008
4009 /* hsi -> l3_main_2 */
4010 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4011         .master         = &omap44xx_hsi_hwmod,
4012         .slave          = &omap44xx_l3_main_2_hwmod,
4013         .clk            = "l3_div_ck",
4014         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4015 };
4016
4017 /* ipu -> l3_main_2 */
4018 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4019         .master         = &omap44xx_ipu_hwmod,
4020         .slave          = &omap44xx_l3_main_2_hwmod,
4021         .clk            = "l3_div_ck",
4022         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4023 };
4024
4025 /* iss -> l3_main_2 */
4026 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4027         .master         = &omap44xx_iss_hwmod,
4028         .slave          = &omap44xx_l3_main_2_hwmod,
4029         .clk            = "l3_div_ck",
4030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4031 };
4032
4033 /* iva -> l3_main_2 */
4034 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4035         .master         = &omap44xx_iva_hwmod,
4036         .slave          = &omap44xx_l3_main_2_hwmod,
4037         .clk            = "l3_div_ck",
4038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4039 };
4040
4041 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4042         {
4043                 .pa_start       = 0x44800000,
4044                 .pa_end         = 0x44801fff,
4045                 .flags          = ADDR_TYPE_RT
4046         },
4047         { }
4048 };
4049
4050 /* l3_main_1 -> l3_main_2 */
4051 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4052         .master         = &omap44xx_l3_main_1_hwmod,
4053         .slave          = &omap44xx_l3_main_2_hwmod,
4054         .clk            = "l3_div_ck",
4055         .addr           = omap44xx_l3_main_2_addrs,
4056         .user           = OCP_USER_MPU,
4057 };
4058
4059 /* l4_cfg -> l3_main_2 */
4060 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4061         .master         = &omap44xx_l4_cfg_hwmod,
4062         .slave          = &omap44xx_l3_main_2_hwmod,
4063         .clk            = "l4_div_ck",
4064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4065 };
4066
4067 /* usb_host_fs -> l3_main_2 */
4068 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4069         .master         = &omap44xx_usb_host_fs_hwmod,
4070         .slave          = &omap44xx_l3_main_2_hwmod,
4071         .clk            = "l3_div_ck",
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* usb_host_hs -> l3_main_2 */
4076 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4077         .master         = &omap44xx_usb_host_hs_hwmod,
4078         .slave          = &omap44xx_l3_main_2_hwmod,
4079         .clk            = "l3_div_ck",
4080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* usb_otg_hs -> l3_main_2 */
4084 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4085         .master         = &omap44xx_usb_otg_hs_hwmod,
4086         .slave          = &omap44xx_l3_main_2_hwmod,
4087         .clk            = "l3_div_ck",
4088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4089 };
4090
4091 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4092         {
4093                 .pa_start       = 0x45000000,
4094                 .pa_end         = 0x45000fff,
4095                 .flags          = ADDR_TYPE_RT
4096         },
4097         { }
4098 };
4099
4100 /* l3_main_1 -> l3_main_3 */
4101 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4102         .master         = &omap44xx_l3_main_1_hwmod,
4103         .slave          = &omap44xx_l3_main_3_hwmod,
4104         .clk            = "l3_div_ck",
4105         .addr           = omap44xx_l3_main_3_addrs,
4106         .user           = OCP_USER_MPU,
4107 };
4108
4109 /* l3_main_2 -> l3_main_3 */
4110 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4111         .master         = &omap44xx_l3_main_2_hwmod,
4112         .slave          = &omap44xx_l3_main_3_hwmod,
4113         .clk            = "l3_div_ck",
4114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4115 };
4116
4117 /* l4_cfg -> l3_main_3 */
4118 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4119         .master         = &omap44xx_l4_cfg_hwmod,
4120         .slave          = &omap44xx_l3_main_3_hwmod,
4121         .clk            = "l4_div_ck",
4122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4123 };
4124
4125 /* aess -> l4_abe */
4126 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4127         .master         = &omap44xx_aess_hwmod,
4128         .slave          = &omap44xx_l4_abe_hwmod,
4129         .clk            = "ocp_abe_iclk",
4130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4131 };
4132
4133 /* dsp -> l4_abe */
4134 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4135         .master         = &omap44xx_dsp_hwmod,
4136         .slave          = &omap44xx_l4_abe_hwmod,
4137         .clk            = "ocp_abe_iclk",
4138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4139 };
4140
4141 /* l3_main_1 -> l4_abe */
4142 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4143         .master         = &omap44xx_l3_main_1_hwmod,
4144         .slave          = &omap44xx_l4_abe_hwmod,
4145         .clk            = "l3_div_ck",
4146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4147 };
4148
4149 /* mpu -> l4_abe */
4150 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4151         .master         = &omap44xx_mpu_hwmod,
4152         .slave          = &omap44xx_l4_abe_hwmod,
4153         .clk            = "ocp_abe_iclk",
4154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4155 };
4156
4157 /* l3_main_1 -> l4_cfg */
4158 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4159         .master         = &omap44xx_l3_main_1_hwmod,
4160         .slave          = &omap44xx_l4_cfg_hwmod,
4161         .clk            = "l3_div_ck",
4162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4163 };
4164
4165 /* l3_main_2 -> l4_per */
4166 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4167         .master         = &omap44xx_l3_main_2_hwmod,
4168         .slave          = &omap44xx_l4_per_hwmod,
4169         .clk            = "l3_div_ck",
4170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4172
4173 /* l4_cfg -> l4_wkup */
4174 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4175         .master         = &omap44xx_l4_cfg_hwmod,
4176         .slave          = &omap44xx_l4_wkup_hwmod,
4177         .clk            = "l4_div_ck",
4178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4179 };
4180
4181 /* mpu -> mpu_private */
4182 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4183         .master         = &omap44xx_mpu_hwmod,
4184         .slave          = &omap44xx_mpu_private_hwmod,
4185         .clk            = "l3_div_ck",
4186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4187 };
4188
4189 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4190         {
4191                 .pa_start       = 0x4a102000,
4192                 .pa_end         = 0x4a10207f,
4193                 .flags          = ADDR_TYPE_RT
4194         },
4195         { }
4196 };
4197
4198 /* l4_cfg -> ocp_wp_noc */
4199 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4200         .master         = &omap44xx_l4_cfg_hwmod,
4201         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4202         .clk            = "l4_div_ck",
4203         .addr           = omap44xx_ocp_wp_noc_addrs,
4204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4205 };
4206
4207 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4208         {
4209                 .pa_start       = 0x401f1000,
4210                 .pa_end         = 0x401f13ff,
4211                 .flags          = ADDR_TYPE_RT
4212         },
4213         { }
4214 };
4215
4216 /* l4_abe -> aess */
4217 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4218         .master         = &omap44xx_l4_abe_hwmod,
4219         .slave          = &omap44xx_aess_hwmod,
4220         .clk            = "ocp_abe_iclk",
4221         .addr           = omap44xx_aess_addrs,
4222         .user           = OCP_USER_MPU,
4223 };
4224
4225 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4226         {
4227                 .pa_start       = 0x490f1000,
4228                 .pa_end         = 0x490f13ff,
4229                 .flags          = ADDR_TYPE_RT
4230         },
4231         { }
4232 };
4233
4234 /* l4_abe -> aess (dma) */
4235 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4236         .master         = &omap44xx_l4_abe_hwmod,
4237         .slave          = &omap44xx_aess_hwmod,
4238         .clk            = "ocp_abe_iclk",
4239         .addr           = omap44xx_aess_dma_addrs,
4240         .user           = OCP_USER_SDMA,
4241 };
4242
4243 /* l3_main_2 -> c2c */
4244 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4245         .master         = &omap44xx_l3_main_2_hwmod,
4246         .slave          = &omap44xx_c2c_hwmod,
4247         .clk            = "l3_div_ck",
4248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4249 };
4250
4251 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4252         {
4253                 .pa_start       = 0x4a304000,
4254                 .pa_end         = 0x4a30401f,
4255                 .flags          = ADDR_TYPE_RT
4256         },
4257         { }
4258 };
4259
4260 /* l4_wkup -> counter_32k */
4261 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4262         .master         = &omap44xx_l4_wkup_hwmod,
4263         .slave          = &omap44xx_counter_32k_hwmod,
4264         .clk            = "l4_wkup_clk_mux_ck",
4265         .addr           = omap44xx_counter_32k_addrs,
4266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4267 };
4268
4269 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4270         {
4271                 .pa_start       = 0x4a002000,
4272                 .pa_end         = 0x4a0027ff,
4273                 .flags          = ADDR_TYPE_RT
4274         },
4275         { }
4276 };
4277
4278 /* l4_cfg -> ctrl_module_core */
4279 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4280         .master         = &omap44xx_l4_cfg_hwmod,
4281         .slave          = &omap44xx_ctrl_module_core_hwmod,
4282         .clk            = "l4_div_ck",
4283         .addr           = omap44xx_ctrl_module_core_addrs,
4284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4285 };
4286
4287 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4288         {
4289                 .pa_start       = 0x4a100000,
4290                 .pa_end         = 0x4a1007ff,
4291                 .flags          = ADDR_TYPE_RT
4292         },
4293         { }
4294 };
4295
4296 /* l4_cfg -> ctrl_module_pad_core */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4298         .master         = &omap44xx_l4_cfg_hwmod,
4299         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4300         .clk            = "l4_div_ck",
4301         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4303 };
4304
4305 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4306         {
4307                 .pa_start       = 0x4a30c000,
4308                 .pa_end         = 0x4a30c7ff,
4309                 .flags          = ADDR_TYPE_RT
4310         },
4311         { }
4312 };
4313
4314 /* l4_wkup -> ctrl_module_wkup */
4315 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4316         .master         = &omap44xx_l4_wkup_hwmod,
4317         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4318         .clk            = "l4_wkup_clk_mux_ck",
4319         .addr           = omap44xx_ctrl_module_wkup_addrs,
4320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4324         {
4325                 .pa_start       = 0x4a31e000,
4326                 .pa_end         = 0x4a31e7ff,
4327                 .flags          = ADDR_TYPE_RT
4328         },
4329         { }
4330 };
4331
4332 /* l4_wkup -> ctrl_module_pad_wkup */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4334         .master         = &omap44xx_l4_wkup_hwmod,
4335         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4336         .clk            = "l4_wkup_clk_mux_ck",
4337         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4340
4341 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4342         {
4343                 .pa_start       = 0x54160000,
4344                 .pa_end         = 0x54167fff,
4345                 .flags          = ADDR_TYPE_RT
4346         },
4347         { }
4348 };
4349
4350 /* l3_instr -> debugss */
4351 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4352         .master         = &omap44xx_l3_instr_hwmod,
4353         .slave          = &omap44xx_debugss_hwmod,
4354         .clk            = "l3_div_ck",
4355         .addr           = omap44xx_debugss_addrs,
4356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4357 };
4358
4359 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4360         {
4361                 .pa_start       = 0x4a056000,
4362                 .pa_end         = 0x4a056fff,
4363                 .flags          = ADDR_TYPE_RT
4364         },
4365         { }
4366 };
4367
4368 /* l4_cfg -> dma_system */
4369 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4370         .master         = &omap44xx_l4_cfg_hwmod,
4371         .slave          = &omap44xx_dma_system_hwmod,
4372         .clk            = "l4_div_ck",
4373         .addr           = omap44xx_dma_system_addrs,
4374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4375 };
4376
4377 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4378         {
4379                 .name           = "mpu",
4380                 .pa_start       = 0x4012e000,
4381                 .pa_end         = 0x4012e07f,
4382                 .flags          = ADDR_TYPE_RT
4383         },
4384         { }
4385 };
4386
4387 /* l4_abe -> dmic */
4388 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4389         .master         = &omap44xx_l4_abe_hwmod,
4390         .slave          = &omap44xx_dmic_hwmod,
4391         .clk            = "ocp_abe_iclk",
4392         .addr           = omap44xx_dmic_addrs,
4393         .user           = OCP_USER_MPU,
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4397         {
4398                 .name           = "dma",
4399                 .pa_start       = 0x4902e000,
4400                 .pa_end         = 0x4902e07f,
4401                 .flags          = ADDR_TYPE_RT
4402         },
4403         { }
4404 };
4405
4406 /* l4_abe -> dmic (dma) */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4408         .master         = &omap44xx_l4_abe_hwmod,
4409         .slave          = &omap44xx_dmic_hwmod,
4410         .clk            = "ocp_abe_iclk",
4411         .addr           = omap44xx_dmic_dma_addrs,
4412         .user           = OCP_USER_SDMA,
4413 };
4414
4415 /* dsp -> iva */
4416 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4417         .master         = &omap44xx_dsp_hwmod,
4418         .slave          = &omap44xx_iva_hwmod,
4419         .clk            = "dpll_iva_m5x2_ck",
4420         .user           = OCP_USER_DSP,
4421 };
4422
4423 /* dsp -> sl2if */
4424 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4425         .master         = &omap44xx_dsp_hwmod,
4426         .slave          = &omap44xx_sl2if_hwmod,
4427         .clk            = "dpll_iva_m5x2_ck",
4428         .user           = OCP_USER_DSP,
4429 };
4430
4431 /* l4_cfg -> dsp */
4432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4433         .master         = &omap44xx_l4_cfg_hwmod,
4434         .slave          = &omap44xx_dsp_hwmod,
4435         .clk            = "l4_div_ck",
4436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4438
4439 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4440         {
4441                 .pa_start       = 0x58000000,
4442                 .pa_end         = 0x5800007f,
4443                 .flags          = ADDR_TYPE_RT
4444         },
4445         { }
4446 };
4447
4448 /* l3_main_2 -> dss */
4449 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4450         .master         = &omap44xx_l3_main_2_hwmod,
4451         .slave          = &omap44xx_dss_hwmod,
4452         .clk            = "dss_fck",
4453         .addr           = omap44xx_dss_dma_addrs,
4454         .user           = OCP_USER_SDMA,
4455 };
4456
4457 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4458         {
4459                 .pa_start       = 0x48040000,
4460                 .pa_end         = 0x4804007f,
4461                 .flags          = ADDR_TYPE_RT
4462         },
4463         { }
4464 };
4465
4466 /* l4_per -> dss */
4467 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4468         .master         = &omap44xx_l4_per_hwmod,
4469         .slave          = &omap44xx_dss_hwmod,
4470         .clk            = "l4_div_ck",
4471         .addr           = omap44xx_dss_addrs,
4472         .user           = OCP_USER_MPU,
4473 };
4474
4475 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4476         {
4477                 .pa_start       = 0x58001000,
4478                 .pa_end         = 0x58001fff,
4479                 .flags          = ADDR_TYPE_RT
4480         },
4481         { }
4482 };
4483
4484 /* l3_main_2 -> dss_dispc */
4485 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4486         .master         = &omap44xx_l3_main_2_hwmod,
4487         .slave          = &omap44xx_dss_dispc_hwmod,
4488         .clk            = "dss_fck",
4489         .addr           = omap44xx_dss_dispc_dma_addrs,
4490         .user           = OCP_USER_SDMA,
4491 };
4492
4493 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4494         {
4495                 .pa_start       = 0x48041000,
4496                 .pa_end         = 0x48041fff,
4497                 .flags          = ADDR_TYPE_RT
4498         },
4499         { }
4500 };
4501
4502 /* l4_per -> dss_dispc */
4503 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4504         .master         = &omap44xx_l4_per_hwmod,
4505         .slave          = &omap44xx_dss_dispc_hwmod,
4506         .clk            = "l4_div_ck",
4507         .addr           = omap44xx_dss_dispc_addrs,
4508         .user           = OCP_USER_MPU,
4509 };
4510
4511 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4512         {
4513                 .pa_start       = 0x58004000,
4514                 .pa_end         = 0x580041ff,
4515                 .flags          = ADDR_TYPE_RT
4516         },
4517         { }
4518 };
4519
4520 /* l3_main_2 -> dss_dsi1 */
4521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4522         .master         = &omap44xx_l3_main_2_hwmod,
4523         .slave          = &omap44xx_dss_dsi1_hwmod,
4524         .clk            = "dss_fck",
4525         .addr           = omap44xx_dss_dsi1_dma_addrs,
4526         .user           = OCP_USER_SDMA,
4527 };
4528
4529 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4530         {
4531                 .pa_start       = 0x48044000,
4532                 .pa_end         = 0x480441ff,
4533                 .flags          = ADDR_TYPE_RT
4534         },
4535         { }
4536 };
4537
4538 /* l4_per -> dss_dsi1 */
4539 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4540         .master         = &omap44xx_l4_per_hwmod,
4541         .slave          = &omap44xx_dss_dsi1_hwmod,
4542         .clk            = "l4_div_ck",
4543         .addr           = omap44xx_dss_dsi1_addrs,
4544         .user           = OCP_USER_MPU,
4545 };
4546
4547 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4548         {
4549                 .pa_start       = 0x58005000,
4550                 .pa_end         = 0x580051ff,
4551                 .flags          = ADDR_TYPE_RT
4552         },
4553         { }
4554 };
4555
4556 /* l3_main_2 -> dss_dsi2 */
4557 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4558         .master         = &omap44xx_l3_main_2_hwmod,
4559         .slave          = &omap44xx_dss_dsi2_hwmod,
4560         .clk            = "dss_fck",
4561         .addr           = omap44xx_dss_dsi2_dma_addrs,
4562         .user           = OCP_USER_SDMA,
4563 };
4564
4565 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4566         {
4567                 .pa_start       = 0x48045000,
4568                 .pa_end         = 0x480451ff,
4569                 .flags          = ADDR_TYPE_RT
4570         },
4571         { }
4572 };
4573
4574 /* l4_per -> dss_dsi2 */
4575 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4576         .master         = &omap44xx_l4_per_hwmod,
4577         .slave          = &omap44xx_dss_dsi2_hwmod,
4578         .clk            = "l4_div_ck",
4579         .addr           = omap44xx_dss_dsi2_addrs,
4580         .user           = OCP_USER_MPU,
4581 };
4582
4583 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4584         {
4585                 .pa_start       = 0x58006000,
4586                 .pa_end         = 0x58006fff,
4587                 .flags          = ADDR_TYPE_RT
4588         },
4589         { }
4590 };
4591
4592 /* l3_main_2 -> dss_hdmi */
4593 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4594         .master         = &omap44xx_l3_main_2_hwmod,
4595         .slave          = &omap44xx_dss_hdmi_hwmod,
4596         .clk            = "dss_fck",
4597         .addr           = omap44xx_dss_hdmi_dma_addrs,
4598         .user           = OCP_USER_SDMA,
4599 };
4600
4601 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4602         {
4603                 .pa_start       = 0x48046000,
4604                 .pa_end         = 0x48046fff,
4605                 .flags          = ADDR_TYPE_RT
4606         },
4607         { }
4608 };
4609
4610 /* l4_per -> dss_hdmi */
4611 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4612         .master         = &omap44xx_l4_per_hwmod,
4613         .slave          = &omap44xx_dss_hdmi_hwmod,
4614         .clk            = "l4_div_ck",
4615         .addr           = omap44xx_dss_hdmi_addrs,
4616         .user           = OCP_USER_MPU,
4617 };
4618
4619 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4620         {
4621                 .pa_start       = 0x58002000,
4622                 .pa_end         = 0x580020ff,
4623                 .flags          = ADDR_TYPE_RT
4624         },
4625         { }
4626 };
4627
4628 /* l3_main_2 -> dss_rfbi */
4629 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4630         .master         = &omap44xx_l3_main_2_hwmod,
4631         .slave          = &omap44xx_dss_rfbi_hwmod,
4632         .clk            = "dss_fck",
4633         .addr           = omap44xx_dss_rfbi_dma_addrs,
4634         .user           = OCP_USER_SDMA,
4635 };
4636
4637 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4638         {
4639                 .pa_start       = 0x48042000,
4640                 .pa_end         = 0x480420ff,
4641                 .flags          = ADDR_TYPE_RT
4642         },
4643         { }
4644 };
4645
4646 /* l4_per -> dss_rfbi */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4648         .master         = &omap44xx_l4_per_hwmod,
4649         .slave          = &omap44xx_dss_rfbi_hwmod,
4650         .clk            = "l4_div_ck",
4651         .addr           = omap44xx_dss_rfbi_addrs,
4652         .user           = OCP_USER_MPU,
4653 };
4654
4655 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4656         {
4657                 .pa_start       = 0x58003000,
4658                 .pa_end         = 0x580030ff,
4659                 .flags          = ADDR_TYPE_RT
4660         },
4661         { }
4662 };
4663
4664 /* l3_main_2 -> dss_venc */
4665 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4666         .master         = &omap44xx_l3_main_2_hwmod,
4667         .slave          = &omap44xx_dss_venc_hwmod,
4668         .clk            = "dss_fck",
4669         .addr           = omap44xx_dss_venc_dma_addrs,
4670         .user           = OCP_USER_SDMA,
4671 };
4672
4673 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4674         {
4675                 .pa_start       = 0x48043000,
4676                 .pa_end         = 0x480430ff,
4677                 .flags          = ADDR_TYPE_RT
4678         },
4679         { }
4680 };
4681
4682 /* l4_per -> dss_venc */
4683 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4684         .master         = &omap44xx_l4_per_hwmod,
4685         .slave          = &omap44xx_dss_venc_hwmod,
4686         .clk            = "l4_div_ck",
4687         .addr           = omap44xx_dss_venc_addrs,
4688         .user           = OCP_USER_MPU,
4689 };
4690
4691 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4692         {
4693                 .pa_start       = 0x48078000,
4694                 .pa_end         = 0x48078fff,
4695                 .flags          = ADDR_TYPE_RT
4696         },
4697         { }
4698 };
4699
4700 /* l4_per -> elm */
4701 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4702         .master         = &omap44xx_l4_per_hwmod,
4703         .slave          = &omap44xx_elm_hwmod,
4704         .clk            = "l4_div_ck",
4705         .addr           = omap44xx_elm_addrs,
4706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4707 };
4708
4709 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4710         {
4711                 .pa_start       = 0x4c000000,
4712                 .pa_end         = 0x4c0000ff,
4713                 .flags          = ADDR_TYPE_RT
4714         },
4715         { }
4716 };
4717
4718 /* emif_fw -> emif1 */
4719 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4720         .master         = &omap44xx_emif_fw_hwmod,
4721         .slave          = &omap44xx_emif1_hwmod,
4722         .clk            = "l3_div_ck",
4723         .addr           = omap44xx_emif1_addrs,
4724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4725 };
4726
4727 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4728         {
4729                 .pa_start       = 0x4d000000,
4730                 .pa_end         = 0x4d0000ff,
4731                 .flags          = ADDR_TYPE_RT
4732         },
4733         { }
4734 };
4735
4736 /* emif_fw -> emif2 */
4737 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4738         .master         = &omap44xx_emif_fw_hwmod,
4739         .slave          = &omap44xx_emif2_hwmod,
4740         .clk            = "l3_div_ck",
4741         .addr           = omap44xx_emif2_addrs,
4742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4743 };
4744
4745 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4746         {
4747                 .pa_start       = 0x4a10a000,
4748                 .pa_end         = 0x4a10a1ff,
4749                 .flags          = ADDR_TYPE_RT
4750         },
4751         { }
4752 };
4753
4754 /* l4_cfg -> fdif */
4755 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4756         .master         = &omap44xx_l4_cfg_hwmod,
4757         .slave          = &omap44xx_fdif_hwmod,
4758         .clk            = "l4_div_ck",
4759         .addr           = omap44xx_fdif_addrs,
4760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4761 };
4762
4763 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4764         {
4765                 .pa_start       = 0x4a310000,
4766                 .pa_end         = 0x4a3101ff,
4767                 .flags          = ADDR_TYPE_RT
4768         },
4769         { }
4770 };
4771
4772 /* l4_wkup -> gpio1 */
4773 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4774         .master         = &omap44xx_l4_wkup_hwmod,
4775         .slave          = &omap44xx_gpio1_hwmod,
4776         .clk            = "l4_wkup_clk_mux_ck",
4777         .addr           = omap44xx_gpio1_addrs,
4778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4779 };
4780
4781 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4782         {
4783                 .pa_start       = 0x48055000,
4784                 .pa_end         = 0x480551ff,
4785                 .flags          = ADDR_TYPE_RT
4786         },
4787         { }
4788 };
4789
4790 /* l4_per -> gpio2 */
4791 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4792         .master         = &omap44xx_l4_per_hwmod,
4793         .slave          = &omap44xx_gpio2_hwmod,
4794         .clk            = "l4_div_ck",
4795         .addr           = omap44xx_gpio2_addrs,
4796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4797 };
4798
4799 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4800         {
4801                 .pa_start       = 0x48057000,
4802                 .pa_end         = 0x480571ff,
4803                 .flags          = ADDR_TYPE_RT
4804         },
4805         { }
4806 };
4807
4808 /* l4_per -> gpio3 */
4809 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4810         .master         = &omap44xx_l4_per_hwmod,
4811         .slave          = &omap44xx_gpio3_hwmod,
4812         .clk            = "l4_div_ck",
4813         .addr           = omap44xx_gpio3_addrs,
4814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4815 };
4816
4817 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4818         {
4819                 .pa_start       = 0x48059000,
4820                 .pa_end         = 0x480591ff,
4821                 .flags          = ADDR_TYPE_RT
4822         },
4823         { }
4824 };
4825
4826 /* l4_per -> gpio4 */
4827 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4828         .master         = &omap44xx_l4_per_hwmod,
4829         .slave          = &omap44xx_gpio4_hwmod,
4830         .clk            = "l4_div_ck",
4831         .addr           = omap44xx_gpio4_addrs,
4832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4833 };
4834
4835 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4836         {
4837                 .pa_start       = 0x4805b000,
4838                 .pa_end         = 0x4805b1ff,
4839                 .flags          = ADDR_TYPE_RT
4840         },
4841         { }
4842 };
4843
4844 /* l4_per -> gpio5 */
4845 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4846         .master         = &omap44xx_l4_per_hwmod,
4847         .slave          = &omap44xx_gpio5_hwmod,
4848         .clk            = "l4_div_ck",
4849         .addr           = omap44xx_gpio5_addrs,
4850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4851 };
4852
4853 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4854         {
4855                 .pa_start       = 0x4805d000,
4856                 .pa_end         = 0x4805d1ff,
4857                 .flags          = ADDR_TYPE_RT
4858         },
4859         { }
4860 };
4861
4862 /* l4_per -> gpio6 */
4863 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4864         .master         = &omap44xx_l4_per_hwmod,
4865         .slave          = &omap44xx_gpio6_hwmod,
4866         .clk            = "l4_div_ck",
4867         .addr           = omap44xx_gpio6_addrs,
4868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4869 };
4870
4871 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4872         {
4873                 .pa_start       = 0x50000000,
4874                 .pa_end         = 0x500003ff,
4875                 .flags          = ADDR_TYPE_RT
4876         },
4877         { }
4878 };
4879
4880 /* l3_main_2 -> gpmc */
4881 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4882         .master         = &omap44xx_l3_main_2_hwmod,
4883         .slave          = &omap44xx_gpmc_hwmod,
4884         .clk            = "l3_div_ck",
4885         .addr           = omap44xx_gpmc_addrs,
4886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4887 };
4888
4889 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4890         {
4891                 .pa_start       = 0x56000000,
4892                 .pa_end         = 0x5600ffff,
4893                 .flags          = ADDR_TYPE_RT
4894         },
4895         { }
4896 };
4897
4898 /* l3_main_2 -> gpu */
4899 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4900         .master         = &omap44xx_l3_main_2_hwmod,
4901         .slave          = &omap44xx_gpu_hwmod,
4902         .clk            = "l3_div_ck",
4903         .addr           = omap44xx_gpu_addrs,
4904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4905 };
4906
4907 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4908         {
4909                 .pa_start       = 0x480b2000,
4910                 .pa_end         = 0x480b201f,
4911                 .flags          = ADDR_TYPE_RT
4912         },
4913         { }
4914 };
4915
4916 /* l4_per -> hdq1w */
4917 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4918         .master         = &omap44xx_l4_per_hwmod,
4919         .slave          = &omap44xx_hdq1w_hwmod,
4920         .clk            = "l4_div_ck",
4921         .addr           = omap44xx_hdq1w_addrs,
4922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4923 };
4924
4925 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4926         {
4927                 .pa_start       = 0x4a058000,
4928                 .pa_end         = 0x4a05bfff,
4929                 .flags          = ADDR_TYPE_RT
4930         },
4931         { }
4932 };
4933
4934 /* l4_cfg -> hsi */
4935 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4936         .master         = &omap44xx_l4_cfg_hwmod,
4937         .slave          = &omap44xx_hsi_hwmod,
4938         .clk            = "l4_div_ck",
4939         .addr           = omap44xx_hsi_addrs,
4940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4941 };
4942
4943 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4944         {
4945                 .pa_start       = 0x48070000,
4946                 .pa_end         = 0x480700ff,
4947                 .flags          = ADDR_TYPE_RT
4948         },
4949         { }
4950 };
4951
4952 /* l4_per -> i2c1 */
4953 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4954         .master         = &omap44xx_l4_per_hwmod,
4955         .slave          = &omap44xx_i2c1_hwmod,
4956         .clk            = "l4_div_ck",
4957         .addr           = omap44xx_i2c1_addrs,
4958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4959 };
4960
4961 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4962         {
4963                 .pa_start       = 0x48072000,
4964                 .pa_end         = 0x480720ff,
4965                 .flags          = ADDR_TYPE_RT
4966         },
4967         { }
4968 };
4969
4970 /* l4_per -> i2c2 */
4971 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4972         .master         = &omap44xx_l4_per_hwmod,
4973         .slave          = &omap44xx_i2c2_hwmod,
4974         .clk            = "l4_div_ck",
4975         .addr           = omap44xx_i2c2_addrs,
4976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4977 };
4978
4979 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4980         {
4981                 .pa_start       = 0x48060000,
4982                 .pa_end         = 0x480600ff,
4983                 .flags          = ADDR_TYPE_RT
4984         },
4985         { }
4986 };
4987
4988 /* l4_per -> i2c3 */
4989 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4990         .master         = &omap44xx_l4_per_hwmod,
4991         .slave          = &omap44xx_i2c3_hwmod,
4992         .clk            = "l4_div_ck",
4993         .addr           = omap44xx_i2c3_addrs,
4994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4995 };
4996
4997 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4998         {
4999                 .pa_start       = 0x48350000,
5000                 .pa_end         = 0x483500ff,
5001                 .flags          = ADDR_TYPE_RT
5002         },
5003         { }
5004 };
5005
5006 /* l4_per -> i2c4 */
5007 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5008         .master         = &omap44xx_l4_per_hwmod,
5009         .slave          = &omap44xx_i2c4_hwmod,
5010         .clk            = "l4_div_ck",
5011         .addr           = omap44xx_i2c4_addrs,
5012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5013 };
5014
5015 /* l3_main_2 -> ipu */
5016 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5017         .master         = &omap44xx_l3_main_2_hwmod,
5018         .slave          = &omap44xx_ipu_hwmod,
5019         .clk            = "l3_div_ck",
5020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5021 };
5022
5023 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5024         {
5025                 .pa_start       = 0x52000000,
5026                 .pa_end         = 0x520000ff,
5027                 .flags          = ADDR_TYPE_RT
5028         },
5029         { }
5030 };
5031
5032 /* l3_main_2 -> iss */
5033 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5034         .master         = &omap44xx_l3_main_2_hwmod,
5035         .slave          = &omap44xx_iss_hwmod,
5036         .clk            = "l3_div_ck",
5037         .addr           = omap44xx_iss_addrs,
5038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5039 };
5040
5041 /* iva -> sl2if */
5042 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5043         .master         = &omap44xx_iva_hwmod,
5044         .slave          = &omap44xx_sl2if_hwmod,
5045         .clk            = "dpll_iva_m5x2_ck",
5046         .user           = OCP_USER_IVA,
5047 };
5048
5049 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5050         {
5051                 .pa_start       = 0x5a000000,
5052                 .pa_end         = 0x5a07ffff,
5053                 .flags          = ADDR_TYPE_RT
5054         },
5055         { }
5056 };
5057
5058 /* l3_main_2 -> iva */
5059 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5060         .master         = &omap44xx_l3_main_2_hwmod,
5061         .slave          = &omap44xx_iva_hwmod,
5062         .clk            = "l3_div_ck",
5063         .addr           = omap44xx_iva_addrs,
5064         .user           = OCP_USER_MPU,
5065 };
5066
5067 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5068         {
5069                 .pa_start       = 0x4a31c000,
5070                 .pa_end         = 0x4a31c07f,
5071                 .flags          = ADDR_TYPE_RT
5072         },
5073         { }
5074 };
5075
5076 /* l4_wkup -> kbd */
5077 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5078         .master         = &omap44xx_l4_wkup_hwmod,
5079         .slave          = &omap44xx_kbd_hwmod,
5080         .clk            = "l4_wkup_clk_mux_ck",
5081         .addr           = omap44xx_kbd_addrs,
5082         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5083 };
5084
5085 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5086         {
5087                 .pa_start       = 0x4a0f4000,
5088                 .pa_end         = 0x4a0f41ff,
5089                 .flags          = ADDR_TYPE_RT
5090         },
5091         { }
5092 };
5093
5094 /* l4_cfg -> mailbox */
5095 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5096         .master         = &omap44xx_l4_cfg_hwmod,
5097         .slave          = &omap44xx_mailbox_hwmod,
5098         .clk            = "l4_div_ck",
5099         .addr           = omap44xx_mailbox_addrs,
5100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5101 };
5102
5103 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5104         {
5105                 .pa_start       = 0x40128000,
5106                 .pa_end         = 0x401283ff,
5107                 .flags          = ADDR_TYPE_RT
5108         },
5109         { }
5110 };
5111
5112 /* l4_abe -> mcasp */
5113 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5114         .master         = &omap44xx_l4_abe_hwmod,
5115         .slave          = &omap44xx_mcasp_hwmod,
5116         .clk            = "ocp_abe_iclk",
5117         .addr           = omap44xx_mcasp_addrs,
5118         .user           = OCP_USER_MPU,
5119 };
5120
5121 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5122         {
5123                 .pa_start       = 0x49028000,
5124                 .pa_end         = 0x490283ff,
5125                 .flags          = ADDR_TYPE_RT
5126         },
5127         { }
5128 };
5129
5130 /* l4_abe -> mcasp (dma) */
5131 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5132         .master         = &omap44xx_l4_abe_hwmod,
5133         .slave          = &omap44xx_mcasp_hwmod,
5134         .clk            = "ocp_abe_iclk",
5135         .addr           = omap44xx_mcasp_dma_addrs,
5136         .user           = OCP_USER_SDMA,
5137 };
5138
5139 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5140         {
5141                 .name           = "mpu",
5142                 .pa_start       = 0x40122000,
5143                 .pa_end         = 0x401220ff,
5144                 .flags          = ADDR_TYPE_RT
5145         },
5146         { }
5147 };
5148
5149 /* l4_abe -> mcbsp1 */
5150 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5151         .master         = &omap44xx_l4_abe_hwmod,
5152         .slave          = &omap44xx_mcbsp1_hwmod,
5153         .clk            = "ocp_abe_iclk",
5154         .addr           = omap44xx_mcbsp1_addrs,
5155         .user           = OCP_USER_MPU,
5156 };
5157
5158 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5159         {
5160                 .name           = "dma",
5161                 .pa_start       = 0x49022000,
5162                 .pa_end         = 0x490220ff,
5163                 .flags          = ADDR_TYPE_RT
5164         },
5165         { }
5166 };
5167
5168 /* l4_abe -> mcbsp1 (dma) */
5169 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5170         .master         = &omap44xx_l4_abe_hwmod,
5171         .slave          = &omap44xx_mcbsp1_hwmod,
5172         .clk            = "ocp_abe_iclk",
5173         .addr           = omap44xx_mcbsp1_dma_addrs,
5174         .user           = OCP_USER_SDMA,
5175 };
5176
5177 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5178         {
5179                 .name           = "mpu",
5180                 .pa_start       = 0x40124000,
5181                 .pa_end         = 0x401240ff,
5182                 .flags          = ADDR_TYPE_RT
5183         },
5184         { }
5185 };
5186
5187 /* l4_abe -> mcbsp2 */
5188 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5189         .master         = &omap44xx_l4_abe_hwmod,
5190         .slave          = &omap44xx_mcbsp2_hwmod,
5191         .clk            = "ocp_abe_iclk",
5192         .addr           = omap44xx_mcbsp2_addrs,
5193         .user           = OCP_USER_MPU,
5194 };
5195
5196 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5197         {
5198                 .name           = "dma",
5199                 .pa_start       = 0x49024000,
5200                 .pa_end         = 0x490240ff,
5201                 .flags          = ADDR_TYPE_RT
5202         },
5203         { }
5204 };
5205
5206 /* l4_abe -> mcbsp2 (dma) */
5207 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5208         .master         = &omap44xx_l4_abe_hwmod,
5209         .slave          = &omap44xx_mcbsp2_hwmod,
5210         .clk            = "ocp_abe_iclk",
5211         .addr           = omap44xx_mcbsp2_dma_addrs,
5212         .user           = OCP_USER_SDMA,
5213 };
5214
5215 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5216         {
5217                 .name           = "mpu",
5218                 .pa_start       = 0x40126000,
5219                 .pa_end         = 0x401260ff,
5220                 .flags          = ADDR_TYPE_RT
5221         },
5222         { }
5223 };
5224
5225 /* l4_abe -> mcbsp3 */
5226 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5227         .master         = &omap44xx_l4_abe_hwmod,
5228         .slave          = &omap44xx_mcbsp3_hwmod,
5229         .clk            = "ocp_abe_iclk",
5230         .addr           = omap44xx_mcbsp3_addrs,
5231         .user           = OCP_USER_MPU,
5232 };
5233
5234 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5235         {
5236                 .name           = "dma",
5237                 .pa_start       = 0x49026000,
5238                 .pa_end         = 0x490260ff,
5239                 .flags          = ADDR_TYPE_RT
5240         },
5241         { }
5242 };
5243
5244 /* l4_abe -> mcbsp3 (dma) */
5245 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5246         .master         = &omap44xx_l4_abe_hwmod,
5247         .slave          = &omap44xx_mcbsp3_hwmod,
5248         .clk            = "ocp_abe_iclk",
5249         .addr           = omap44xx_mcbsp3_dma_addrs,
5250         .user           = OCP_USER_SDMA,
5251 };
5252
5253 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5254         {
5255                 .pa_start       = 0x48096000,
5256                 .pa_end         = 0x480960ff,
5257                 .flags          = ADDR_TYPE_RT
5258         },
5259         { }
5260 };
5261
5262 /* l4_per -> mcbsp4 */
5263 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5264         .master         = &omap44xx_l4_per_hwmod,
5265         .slave          = &omap44xx_mcbsp4_hwmod,
5266         .clk            = "l4_div_ck",
5267         .addr           = omap44xx_mcbsp4_addrs,
5268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5269 };
5270
5271 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5272         {
5273                 .name           = "mpu",
5274                 .pa_start       = 0x40132000,
5275                 .pa_end         = 0x4013207f,
5276                 .flags          = ADDR_TYPE_RT
5277         },
5278         { }
5279 };
5280
5281 /* l4_abe -> mcpdm */
5282 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5283         .master         = &omap44xx_l4_abe_hwmod,
5284         .slave          = &omap44xx_mcpdm_hwmod,
5285         .clk            = "ocp_abe_iclk",
5286         .addr           = omap44xx_mcpdm_addrs,
5287         .user           = OCP_USER_MPU,
5288 };
5289
5290 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5291         {
5292                 .name           = "dma",
5293                 .pa_start       = 0x49032000,
5294                 .pa_end         = 0x4903207f,
5295                 .flags          = ADDR_TYPE_RT
5296         },
5297         { }
5298 };
5299
5300 /* l4_abe -> mcpdm (dma) */
5301 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5302         .master         = &omap44xx_l4_abe_hwmod,
5303         .slave          = &omap44xx_mcpdm_hwmod,
5304         .clk            = "ocp_abe_iclk",
5305         .addr           = omap44xx_mcpdm_dma_addrs,
5306         .user           = OCP_USER_SDMA,
5307 };
5308
5309 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5310         {
5311                 .pa_start       = 0x48098000,
5312                 .pa_end         = 0x480981ff,
5313                 .flags          = ADDR_TYPE_RT
5314         },
5315         { }
5316 };
5317
5318 /* l4_per -> mcspi1 */
5319 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5320         .master         = &omap44xx_l4_per_hwmod,
5321         .slave          = &omap44xx_mcspi1_hwmod,
5322         .clk            = "l4_div_ck",
5323         .addr           = omap44xx_mcspi1_addrs,
5324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5325 };
5326
5327 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5328         {
5329                 .pa_start       = 0x4809a000,
5330                 .pa_end         = 0x4809a1ff,
5331                 .flags          = ADDR_TYPE_RT
5332         },
5333         { }
5334 };
5335
5336 /* l4_per -> mcspi2 */
5337 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5338         .master         = &omap44xx_l4_per_hwmod,
5339         .slave          = &omap44xx_mcspi2_hwmod,
5340         .clk            = "l4_div_ck",
5341         .addr           = omap44xx_mcspi2_addrs,
5342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5343 };
5344
5345 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5346         {
5347                 .pa_start       = 0x480b8000,
5348                 .pa_end         = 0x480b81ff,
5349                 .flags          = ADDR_TYPE_RT
5350         },
5351         { }
5352 };
5353
5354 /* l4_per -> mcspi3 */
5355 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5356         .master         = &omap44xx_l4_per_hwmod,
5357         .slave          = &omap44xx_mcspi3_hwmod,
5358         .clk            = "l4_div_ck",
5359         .addr           = omap44xx_mcspi3_addrs,
5360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5361 };
5362
5363 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5364         {
5365                 .pa_start       = 0x480ba000,
5366                 .pa_end         = 0x480ba1ff,
5367                 .flags          = ADDR_TYPE_RT
5368         },
5369         { }
5370 };
5371
5372 /* l4_per -> mcspi4 */
5373 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5374         .master         = &omap44xx_l4_per_hwmod,
5375         .slave          = &omap44xx_mcspi4_hwmod,
5376         .clk            = "l4_div_ck",
5377         .addr           = omap44xx_mcspi4_addrs,
5378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5379 };
5380
5381 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5382         {
5383                 .pa_start       = 0x4809c000,
5384                 .pa_end         = 0x4809c3ff,
5385                 .flags          = ADDR_TYPE_RT
5386         },
5387         { }
5388 };
5389
5390 /* l4_per -> mmc1 */
5391 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5392         .master         = &omap44xx_l4_per_hwmod,
5393         .slave          = &omap44xx_mmc1_hwmod,
5394         .clk            = "l4_div_ck",
5395         .addr           = omap44xx_mmc1_addrs,
5396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5397 };
5398
5399 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5400         {
5401                 .pa_start       = 0x480b4000,
5402                 .pa_end         = 0x480b43ff,
5403                 .flags          = ADDR_TYPE_RT
5404         },
5405         { }
5406 };
5407
5408 /* l4_per -> mmc2 */
5409 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5410         .master         = &omap44xx_l4_per_hwmod,
5411         .slave          = &omap44xx_mmc2_hwmod,
5412         .clk            = "l4_div_ck",
5413         .addr           = omap44xx_mmc2_addrs,
5414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5415 };
5416
5417 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5418         {
5419                 .pa_start       = 0x480ad000,
5420                 .pa_end         = 0x480ad3ff,
5421                 .flags          = ADDR_TYPE_RT
5422         },
5423         { }
5424 };
5425
5426 /* l4_per -> mmc3 */
5427 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5428         .master         = &omap44xx_l4_per_hwmod,
5429         .slave          = &omap44xx_mmc3_hwmod,
5430         .clk            = "l4_div_ck",
5431         .addr           = omap44xx_mmc3_addrs,
5432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5433 };
5434
5435 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5436         {
5437                 .pa_start       = 0x480d1000,
5438                 .pa_end         = 0x480d13ff,
5439                 .flags          = ADDR_TYPE_RT
5440         },
5441         { }
5442 };
5443
5444 /* l4_per -> mmc4 */
5445 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5446         .master         = &omap44xx_l4_per_hwmod,
5447         .slave          = &omap44xx_mmc4_hwmod,
5448         .clk            = "l4_div_ck",
5449         .addr           = omap44xx_mmc4_addrs,
5450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5451 };
5452
5453 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5454         {
5455                 .pa_start       = 0x480d5000,
5456                 .pa_end         = 0x480d53ff,
5457                 .flags          = ADDR_TYPE_RT
5458         },
5459         { }
5460 };
5461
5462 /* l4_per -> mmc5 */
5463 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5464         .master         = &omap44xx_l4_per_hwmod,
5465         .slave          = &omap44xx_mmc5_hwmod,
5466         .clk            = "l4_div_ck",
5467         .addr           = omap44xx_mmc5_addrs,
5468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5469 };
5470
5471 /* l3_main_2 -> ocmc_ram */
5472 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5473         .master         = &omap44xx_l3_main_2_hwmod,
5474         .slave          = &omap44xx_ocmc_ram_hwmod,
5475         .clk            = "l3_div_ck",
5476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5477 };
5478
5479 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5480         {
5481                 .pa_start       = 0x4a0ad000,
5482                 .pa_end         = 0x4a0ad01f,
5483                 .flags          = ADDR_TYPE_RT
5484         },
5485         { }
5486 };
5487
5488 /* l4_cfg -> ocp2scp_usb_phy */
5489 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5490         .master         = &omap44xx_l4_cfg_hwmod,
5491         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5492         .clk            = "l4_div_ck",
5493         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5495 };
5496
5497 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5498         {
5499                 .pa_start       = 0x48243000,
5500                 .pa_end         = 0x48243fff,
5501                 .flags          = ADDR_TYPE_RT
5502         },
5503         { }
5504 };
5505
5506 /* mpu_private -> prcm_mpu */
5507 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5508         .master         = &omap44xx_mpu_private_hwmod,
5509         .slave          = &omap44xx_prcm_mpu_hwmod,
5510         .clk            = "l3_div_ck",
5511         .addr           = omap44xx_prcm_mpu_addrs,
5512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5513 };
5514
5515 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5516         {
5517                 .pa_start       = 0x4a004000,
5518                 .pa_end         = 0x4a004fff,
5519                 .flags          = ADDR_TYPE_RT
5520         },
5521         { }
5522 };
5523
5524 /* l4_wkup -> cm_core_aon */
5525 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5526         .master         = &omap44xx_l4_wkup_hwmod,
5527         .slave          = &omap44xx_cm_core_aon_hwmod,
5528         .clk            = "l4_wkup_clk_mux_ck",
5529         .addr           = omap44xx_cm_core_aon_addrs,
5530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5531 };
5532
5533 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5534         {
5535                 .pa_start       = 0x4a008000,
5536                 .pa_end         = 0x4a009fff,
5537                 .flags          = ADDR_TYPE_RT
5538         },
5539         { }
5540 };
5541
5542 /* l4_cfg -> cm_core */
5543 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5544         .master         = &omap44xx_l4_cfg_hwmod,
5545         .slave          = &omap44xx_cm_core_hwmod,
5546         .clk            = "l4_div_ck",
5547         .addr           = omap44xx_cm_core_addrs,
5548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5549 };
5550
5551 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5552         {
5553                 .pa_start       = 0x4a306000,
5554                 .pa_end         = 0x4a307fff,
5555                 .flags          = ADDR_TYPE_RT
5556         },
5557         { }
5558 };
5559
5560 /* l4_wkup -> prm */
5561 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5562         .master         = &omap44xx_l4_wkup_hwmod,
5563         .slave          = &omap44xx_prm_hwmod,
5564         .clk            = "l4_wkup_clk_mux_ck",
5565         .addr           = omap44xx_prm_addrs,
5566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5567 };
5568
5569 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5570         {
5571                 .pa_start       = 0x4a30a000,
5572                 .pa_end         = 0x4a30a7ff,
5573                 .flags          = ADDR_TYPE_RT
5574         },
5575         { }
5576 };
5577
5578 /* l4_wkup -> scrm */
5579 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5580         .master         = &omap44xx_l4_wkup_hwmod,
5581         .slave          = &omap44xx_scrm_hwmod,
5582         .clk            = "l4_wkup_clk_mux_ck",
5583         .addr           = omap44xx_scrm_addrs,
5584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5585 };
5586
5587 /* l3_main_2 -> sl2if */
5588 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5589         .master         = &omap44xx_l3_main_2_hwmod,
5590         .slave          = &omap44xx_sl2if_hwmod,
5591         .clk            = "l3_div_ck",
5592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5593 };
5594
5595 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5596         {
5597                 .pa_start       = 0x4012c000,
5598                 .pa_end         = 0x4012c3ff,
5599                 .flags          = ADDR_TYPE_RT
5600         },
5601         { }
5602 };
5603
5604 /* l4_abe -> slimbus1 */
5605 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5606         .master         = &omap44xx_l4_abe_hwmod,
5607         .slave          = &omap44xx_slimbus1_hwmod,
5608         .clk            = "ocp_abe_iclk",
5609         .addr           = omap44xx_slimbus1_addrs,
5610         .user           = OCP_USER_MPU,
5611 };
5612
5613 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5614         {
5615                 .pa_start       = 0x4902c000,
5616                 .pa_end         = 0x4902c3ff,
5617                 .flags          = ADDR_TYPE_RT
5618         },
5619         { }
5620 };
5621
5622 /* l4_abe -> slimbus1 (dma) */
5623 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5624         .master         = &omap44xx_l4_abe_hwmod,
5625         .slave          = &omap44xx_slimbus1_hwmod,
5626         .clk            = "ocp_abe_iclk",
5627         .addr           = omap44xx_slimbus1_dma_addrs,
5628         .user           = OCP_USER_SDMA,
5629 };
5630
5631 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5632         {
5633                 .pa_start       = 0x48076000,
5634                 .pa_end         = 0x480763ff,
5635                 .flags          = ADDR_TYPE_RT
5636         },
5637         { }
5638 };
5639
5640 /* l4_per -> slimbus2 */
5641 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5642         .master         = &omap44xx_l4_per_hwmod,
5643         .slave          = &omap44xx_slimbus2_hwmod,
5644         .clk            = "l4_div_ck",
5645         .addr           = omap44xx_slimbus2_addrs,
5646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5647 };
5648
5649 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5650         {
5651                 .pa_start       = 0x4a0dd000,
5652                 .pa_end         = 0x4a0dd03f,
5653                 .flags          = ADDR_TYPE_RT
5654         },
5655         { }
5656 };
5657
5658 /* l4_cfg -> smartreflex_core */
5659 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5660         .master         = &omap44xx_l4_cfg_hwmod,
5661         .slave          = &omap44xx_smartreflex_core_hwmod,
5662         .clk            = "l4_div_ck",
5663         .addr           = omap44xx_smartreflex_core_addrs,
5664         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5665 };
5666
5667 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5668         {
5669                 .pa_start       = 0x4a0db000,
5670                 .pa_end         = 0x4a0db03f,
5671                 .flags          = ADDR_TYPE_RT
5672         },
5673         { }
5674 };
5675
5676 /* l4_cfg -> smartreflex_iva */
5677 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5678         .master         = &omap44xx_l4_cfg_hwmod,
5679         .slave          = &omap44xx_smartreflex_iva_hwmod,
5680         .clk            = "l4_div_ck",
5681         .addr           = omap44xx_smartreflex_iva_addrs,
5682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5683 };
5684
5685 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5686         {
5687                 .pa_start       = 0x4a0d9000,
5688                 .pa_end         = 0x4a0d903f,
5689                 .flags          = ADDR_TYPE_RT
5690         },
5691         { }
5692 };
5693
5694 /* l4_cfg -> smartreflex_mpu */
5695 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5696         .master         = &omap44xx_l4_cfg_hwmod,
5697         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5698         .clk            = "l4_div_ck",
5699         .addr           = omap44xx_smartreflex_mpu_addrs,
5700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5701 };
5702
5703 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5704         {
5705                 .pa_start       = 0x4a0f6000,
5706                 .pa_end         = 0x4a0f6fff,
5707                 .flags          = ADDR_TYPE_RT
5708         },
5709         { }
5710 };
5711
5712 /* l4_cfg -> spinlock */
5713 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5714         .master         = &omap44xx_l4_cfg_hwmod,
5715         .slave          = &omap44xx_spinlock_hwmod,
5716         .clk            = "l4_div_ck",
5717         .addr           = omap44xx_spinlock_addrs,
5718         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5719 };
5720
5721 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5722         {
5723                 .pa_start       = 0x4a318000,
5724                 .pa_end         = 0x4a31807f,
5725                 .flags          = ADDR_TYPE_RT
5726         },
5727         { }
5728 };
5729
5730 /* l4_wkup -> timer1 */
5731 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5732         .master         = &omap44xx_l4_wkup_hwmod,
5733         .slave          = &omap44xx_timer1_hwmod,
5734         .clk            = "l4_wkup_clk_mux_ck",
5735         .addr           = omap44xx_timer1_addrs,
5736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5737 };
5738
5739 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5740         {
5741                 .pa_start       = 0x48032000,
5742                 .pa_end         = 0x4803207f,
5743                 .flags          = ADDR_TYPE_RT
5744         },
5745         { }
5746 };
5747
5748 /* l4_per -> timer2 */
5749 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5750         .master         = &omap44xx_l4_per_hwmod,
5751         .slave          = &omap44xx_timer2_hwmod,
5752         .clk            = "l4_div_ck",
5753         .addr           = omap44xx_timer2_addrs,
5754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5755 };
5756
5757 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5758         {
5759                 .pa_start       = 0x48034000,
5760                 .pa_end         = 0x4803407f,
5761                 .flags          = ADDR_TYPE_RT
5762         },
5763         { }
5764 };
5765
5766 /* l4_per -> timer3 */
5767 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5768         .master         = &omap44xx_l4_per_hwmod,
5769         .slave          = &omap44xx_timer3_hwmod,
5770         .clk            = "l4_div_ck",
5771         .addr           = omap44xx_timer3_addrs,
5772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5773 };
5774
5775 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5776         {
5777                 .pa_start       = 0x48036000,
5778                 .pa_end         = 0x4803607f,
5779                 .flags          = ADDR_TYPE_RT
5780         },
5781         { }
5782 };
5783
5784 /* l4_per -> timer4 */
5785 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5786         .master         = &omap44xx_l4_per_hwmod,
5787         .slave          = &omap44xx_timer4_hwmod,
5788         .clk            = "l4_div_ck",
5789         .addr           = omap44xx_timer4_addrs,
5790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5791 };
5792
5793 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5794         {
5795                 .pa_start       = 0x40138000,
5796                 .pa_end         = 0x4013807f,
5797                 .flags          = ADDR_TYPE_RT
5798         },
5799         { }
5800 };
5801
5802 /* l4_abe -> timer5 */
5803 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5804         .master         = &omap44xx_l4_abe_hwmod,
5805         .slave          = &omap44xx_timer5_hwmod,
5806         .clk            = "ocp_abe_iclk",
5807         .addr           = omap44xx_timer5_addrs,
5808         .user           = OCP_USER_MPU,
5809 };
5810
5811 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5812         {
5813                 .pa_start       = 0x49038000,
5814                 .pa_end         = 0x4903807f,
5815                 .flags          = ADDR_TYPE_RT
5816         },
5817         { }
5818 };
5819
5820 /* l4_abe -> timer5 (dma) */
5821 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5822         .master         = &omap44xx_l4_abe_hwmod,
5823         .slave          = &omap44xx_timer5_hwmod,
5824         .clk            = "ocp_abe_iclk",
5825         .addr           = omap44xx_timer5_dma_addrs,
5826         .user           = OCP_USER_SDMA,
5827 };
5828
5829 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5830         {
5831                 .pa_start       = 0x4013a000,
5832                 .pa_end         = 0x4013a07f,
5833                 .flags          = ADDR_TYPE_RT
5834         },
5835         { }
5836 };
5837
5838 /* l4_abe -> timer6 */
5839 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5840         .master         = &omap44xx_l4_abe_hwmod,
5841         .slave          = &omap44xx_timer6_hwmod,
5842         .clk            = "ocp_abe_iclk",
5843         .addr           = omap44xx_timer6_addrs,
5844         .user           = OCP_USER_MPU,
5845 };
5846
5847 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5848         {
5849                 .pa_start       = 0x4903a000,
5850                 .pa_end         = 0x4903a07f,
5851                 .flags          = ADDR_TYPE_RT
5852         },
5853         { }
5854 };
5855
5856 /* l4_abe -> timer6 (dma) */
5857 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5858         .master         = &omap44xx_l4_abe_hwmod,
5859         .slave          = &omap44xx_timer6_hwmod,
5860         .clk            = "ocp_abe_iclk",
5861         .addr           = omap44xx_timer6_dma_addrs,
5862         .user           = OCP_USER_SDMA,
5863 };
5864
5865 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5866         {
5867                 .pa_start       = 0x4013c000,
5868                 .pa_end         = 0x4013c07f,
5869                 .flags          = ADDR_TYPE_RT
5870         },
5871         { }
5872 };
5873
5874 /* l4_abe -> timer7 */
5875 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5876         .master         = &omap44xx_l4_abe_hwmod,
5877         .slave          = &omap44xx_timer7_hwmod,
5878         .clk            = "ocp_abe_iclk",
5879         .addr           = omap44xx_timer7_addrs,
5880         .user           = OCP_USER_MPU,
5881 };
5882
5883 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5884         {
5885                 .pa_start       = 0x4903c000,
5886                 .pa_end         = 0x4903c07f,
5887                 .flags          = ADDR_TYPE_RT
5888         },
5889         { }
5890 };
5891
5892 /* l4_abe -> timer7 (dma) */
5893 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5894         .master         = &omap44xx_l4_abe_hwmod,
5895         .slave          = &omap44xx_timer7_hwmod,
5896         .clk            = "ocp_abe_iclk",
5897         .addr           = omap44xx_timer7_dma_addrs,
5898         .user           = OCP_USER_SDMA,
5899 };
5900
5901 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5902         {
5903                 .pa_start       = 0x4013e000,
5904                 .pa_end         = 0x4013e07f,
5905                 .flags          = ADDR_TYPE_RT
5906         },
5907         { }
5908 };
5909
5910 /* l4_abe -> timer8 */
5911 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5912         .master         = &omap44xx_l4_abe_hwmod,
5913         .slave          = &omap44xx_timer8_hwmod,
5914         .clk            = "ocp_abe_iclk",
5915         .addr           = omap44xx_timer8_addrs,
5916         .user           = OCP_USER_MPU,
5917 };
5918
5919 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5920         {
5921                 .pa_start       = 0x4903e000,
5922                 .pa_end         = 0x4903e07f,
5923                 .flags          = ADDR_TYPE_RT
5924         },
5925         { }
5926 };
5927
5928 /* l4_abe -> timer8 (dma) */
5929 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5930         .master         = &omap44xx_l4_abe_hwmod,
5931         .slave          = &omap44xx_timer8_hwmod,
5932         .clk            = "ocp_abe_iclk",
5933         .addr           = omap44xx_timer8_dma_addrs,
5934         .user           = OCP_USER_SDMA,
5935 };
5936
5937 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5938         {
5939                 .pa_start       = 0x4803e000,
5940                 .pa_end         = 0x4803e07f,
5941                 .flags          = ADDR_TYPE_RT
5942         },
5943         { }
5944 };
5945
5946 /* l4_per -> timer9 */
5947 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5948         .master         = &omap44xx_l4_per_hwmod,
5949         .slave          = &omap44xx_timer9_hwmod,
5950         .clk            = "l4_div_ck",
5951         .addr           = omap44xx_timer9_addrs,
5952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5953 };
5954
5955 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5956         {
5957                 .pa_start       = 0x48086000,
5958                 .pa_end         = 0x4808607f,
5959                 .flags          = ADDR_TYPE_RT
5960         },
5961         { }
5962 };
5963
5964 /* l4_per -> timer10 */
5965 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5966         .master         = &omap44xx_l4_per_hwmod,
5967         .slave          = &omap44xx_timer10_hwmod,
5968         .clk            = "l4_div_ck",
5969         .addr           = omap44xx_timer10_addrs,
5970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5971 };
5972
5973 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5974         {
5975                 .pa_start       = 0x48088000,
5976                 .pa_end         = 0x4808807f,
5977                 .flags          = ADDR_TYPE_RT
5978         },
5979         { }
5980 };
5981
5982 /* l4_per -> timer11 */
5983 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5984         .master         = &omap44xx_l4_per_hwmod,
5985         .slave          = &omap44xx_timer11_hwmod,
5986         .clk            = "l4_div_ck",
5987         .addr           = omap44xx_timer11_addrs,
5988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5989 };
5990
5991 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5992         {
5993                 .pa_start       = 0x4806a000,
5994                 .pa_end         = 0x4806a0ff,
5995                 .flags          = ADDR_TYPE_RT
5996         },
5997         { }
5998 };
5999
6000 /* l4_per -> uart1 */
6001 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6002         .master         = &omap44xx_l4_per_hwmod,
6003         .slave          = &omap44xx_uart1_hwmod,
6004         .clk            = "l4_div_ck",
6005         .addr           = omap44xx_uart1_addrs,
6006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6007 };
6008
6009 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6010         {
6011                 .pa_start       = 0x4806c000,
6012                 .pa_end         = 0x4806c0ff,
6013                 .flags          = ADDR_TYPE_RT
6014         },
6015         { }
6016 };
6017
6018 /* l4_per -> uart2 */
6019 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6020         .master         = &omap44xx_l4_per_hwmod,
6021         .slave          = &omap44xx_uart2_hwmod,
6022         .clk            = "l4_div_ck",
6023         .addr           = omap44xx_uart2_addrs,
6024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6025 };
6026
6027 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6028         {
6029                 .pa_start       = 0x48020000,
6030                 .pa_end         = 0x480200ff,
6031                 .flags          = ADDR_TYPE_RT
6032         },
6033         { }
6034 };
6035
6036 /* l4_per -> uart3 */
6037 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6038         .master         = &omap44xx_l4_per_hwmod,
6039         .slave          = &omap44xx_uart3_hwmod,
6040         .clk            = "l4_div_ck",
6041         .addr           = omap44xx_uart3_addrs,
6042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6043 };
6044
6045 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6046         {
6047                 .pa_start       = 0x4806e000,
6048                 .pa_end         = 0x4806e0ff,
6049                 .flags          = ADDR_TYPE_RT
6050         },
6051         { }
6052 };
6053
6054 /* l4_per -> uart4 */
6055 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6056         .master         = &omap44xx_l4_per_hwmod,
6057         .slave          = &omap44xx_uart4_hwmod,
6058         .clk            = "l4_div_ck",
6059         .addr           = omap44xx_uart4_addrs,
6060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6061 };
6062
6063 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6064         {
6065                 .pa_start       = 0x4a0a9000,
6066                 .pa_end         = 0x4a0a93ff,
6067                 .flags          = ADDR_TYPE_RT
6068         },
6069         { }
6070 };
6071
6072 /* l4_cfg -> usb_host_fs */
6073 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6074         .master         = &omap44xx_l4_cfg_hwmod,
6075         .slave          = &omap44xx_usb_host_fs_hwmod,
6076         .clk            = "l4_div_ck",
6077         .addr           = omap44xx_usb_host_fs_addrs,
6078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6079 };
6080
6081 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6082         {
6083                 .name           = "uhh",
6084                 .pa_start       = 0x4a064000,
6085                 .pa_end         = 0x4a0647ff,
6086                 .flags          = ADDR_TYPE_RT
6087         },
6088         {
6089                 .name           = "ohci",
6090                 .pa_start       = 0x4a064800,
6091                 .pa_end         = 0x4a064bff,
6092         },
6093         {
6094                 .name           = "ehci",
6095                 .pa_start       = 0x4a064c00,
6096                 .pa_end         = 0x4a064fff,
6097         },
6098         {}
6099 };
6100
6101 /* l4_cfg -> usb_host_hs */
6102 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6103         .master         = &omap44xx_l4_cfg_hwmod,
6104         .slave          = &omap44xx_usb_host_hs_hwmod,
6105         .clk            = "l4_div_ck",
6106         .addr           = omap44xx_usb_host_hs_addrs,
6107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6108 };
6109
6110 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6111         {
6112                 .pa_start       = 0x4a0ab000,
6113                 .pa_end         = 0x4a0ab7ff,
6114                 .flags          = ADDR_TYPE_RT
6115         },
6116         {
6117                 /* XXX: Remove this once control module driver is in place */
6118                 .pa_start       = 0x4a00233c,
6119                 .pa_end         = 0x4a00233f,
6120                 .flags          = ADDR_TYPE_RT
6121         },
6122         { }
6123 };
6124
6125 /* l4_cfg -> usb_otg_hs */
6126 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6127         .master         = &omap44xx_l4_cfg_hwmod,
6128         .slave          = &omap44xx_usb_otg_hs_hwmod,
6129         .clk            = "l4_div_ck",
6130         .addr           = omap44xx_usb_otg_hs_addrs,
6131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6132 };
6133
6134 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6135         {
6136                 .name           = "tll",
6137                 .pa_start       = 0x4a062000,
6138                 .pa_end         = 0x4a063fff,
6139                 .flags          = ADDR_TYPE_RT
6140         },
6141         {}
6142 };
6143
6144 /* l4_cfg -> usb_tll_hs */
6145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6146         .master         = &omap44xx_l4_cfg_hwmod,
6147         .slave          = &omap44xx_usb_tll_hs_hwmod,
6148         .clk            = "l4_div_ck",
6149         .addr           = omap44xx_usb_tll_hs_addrs,
6150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6151 };
6152
6153 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6154         {
6155                 .pa_start       = 0x4a314000,
6156                 .pa_end         = 0x4a31407f,
6157                 .flags          = ADDR_TYPE_RT
6158         },
6159         { }
6160 };
6161
6162 /* l4_wkup -> wd_timer2 */
6163 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6164         .master         = &omap44xx_l4_wkup_hwmod,
6165         .slave          = &omap44xx_wd_timer2_hwmod,
6166         .clk            = "l4_wkup_clk_mux_ck",
6167         .addr           = omap44xx_wd_timer2_addrs,
6168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6169 };
6170
6171 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6172         {
6173                 .pa_start       = 0x40130000,
6174                 .pa_end         = 0x4013007f,
6175                 .flags          = ADDR_TYPE_RT
6176         },
6177         { }
6178 };
6179
6180 /* l4_abe -> wd_timer3 */
6181 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6182         .master         = &omap44xx_l4_abe_hwmod,
6183         .slave          = &omap44xx_wd_timer3_hwmod,
6184         .clk            = "ocp_abe_iclk",
6185         .addr           = omap44xx_wd_timer3_addrs,
6186         .user           = OCP_USER_MPU,
6187 };
6188
6189 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6190         {
6191                 .pa_start       = 0x49030000,
6192                 .pa_end         = 0x4903007f,
6193                 .flags          = ADDR_TYPE_RT
6194         },
6195         { }
6196 };
6197
6198 /* l4_abe -> wd_timer3 (dma) */
6199 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6200         .master         = &omap44xx_l4_abe_hwmod,
6201         .slave          = &omap44xx_wd_timer3_hwmod,
6202         .clk            = "ocp_abe_iclk",
6203         .addr           = omap44xx_wd_timer3_dma_addrs,
6204         .user           = OCP_USER_SDMA,
6205 };
6206
6207 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6208         &omap44xx_c2c__c2c_target_fw,
6209         &omap44xx_l4_cfg__c2c_target_fw,
6210         &omap44xx_l3_main_1__dmm,
6211         &omap44xx_mpu__dmm,
6212         &omap44xx_c2c__emif_fw,
6213         &omap44xx_dmm__emif_fw,
6214         &omap44xx_l4_cfg__emif_fw,
6215         &omap44xx_iva__l3_instr,
6216         &omap44xx_l3_main_3__l3_instr,
6217         &omap44xx_ocp_wp_noc__l3_instr,
6218         &omap44xx_dsp__l3_main_1,
6219         &omap44xx_dss__l3_main_1,
6220         &omap44xx_l3_main_2__l3_main_1,
6221         &omap44xx_l4_cfg__l3_main_1,
6222         &omap44xx_mmc1__l3_main_1,
6223         &omap44xx_mmc2__l3_main_1,
6224         &omap44xx_mpu__l3_main_1,
6225         &omap44xx_c2c_target_fw__l3_main_2,
6226         &omap44xx_debugss__l3_main_2,
6227         &omap44xx_dma_system__l3_main_2,
6228         &omap44xx_fdif__l3_main_2,
6229         &omap44xx_gpu__l3_main_2,
6230         &omap44xx_hsi__l3_main_2,
6231         &omap44xx_ipu__l3_main_2,
6232         &omap44xx_iss__l3_main_2,
6233         &omap44xx_iva__l3_main_2,
6234         &omap44xx_l3_main_1__l3_main_2,
6235         &omap44xx_l4_cfg__l3_main_2,
6236         /* &omap44xx_usb_host_fs__l3_main_2, */
6237         &omap44xx_usb_host_hs__l3_main_2,
6238         &omap44xx_usb_otg_hs__l3_main_2,
6239         &omap44xx_l3_main_1__l3_main_3,
6240         &omap44xx_l3_main_2__l3_main_3,
6241         &omap44xx_l4_cfg__l3_main_3,
6242         /* &omap44xx_aess__l4_abe, */
6243         &omap44xx_dsp__l4_abe,
6244         &omap44xx_l3_main_1__l4_abe,
6245         &omap44xx_mpu__l4_abe,
6246         &omap44xx_l3_main_1__l4_cfg,
6247         &omap44xx_l3_main_2__l4_per,
6248         &omap44xx_l4_cfg__l4_wkup,
6249         &omap44xx_mpu__mpu_private,
6250         &omap44xx_l4_cfg__ocp_wp_noc,
6251         /* &omap44xx_l4_abe__aess, */
6252         /* &omap44xx_l4_abe__aess_dma, */
6253         &omap44xx_l3_main_2__c2c,
6254         &omap44xx_l4_wkup__counter_32k,
6255         &omap44xx_l4_cfg__ctrl_module_core,
6256         &omap44xx_l4_cfg__ctrl_module_pad_core,
6257         &omap44xx_l4_wkup__ctrl_module_wkup,
6258         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6259         &omap44xx_l3_instr__debugss,
6260         &omap44xx_l4_cfg__dma_system,
6261         &omap44xx_l4_abe__dmic,
6262         &omap44xx_l4_abe__dmic_dma,
6263         &omap44xx_dsp__iva,
6264         /* &omap44xx_dsp__sl2if, */
6265         &omap44xx_l4_cfg__dsp,
6266         &omap44xx_l3_main_2__dss,
6267         &omap44xx_l4_per__dss,
6268         &omap44xx_l3_main_2__dss_dispc,
6269         &omap44xx_l4_per__dss_dispc,
6270         &omap44xx_l3_main_2__dss_dsi1,
6271         &omap44xx_l4_per__dss_dsi1,
6272         &omap44xx_l3_main_2__dss_dsi2,
6273         &omap44xx_l4_per__dss_dsi2,
6274         &omap44xx_l3_main_2__dss_hdmi,
6275         &omap44xx_l4_per__dss_hdmi,
6276         &omap44xx_l3_main_2__dss_rfbi,
6277         &omap44xx_l4_per__dss_rfbi,
6278         &omap44xx_l3_main_2__dss_venc,
6279         &omap44xx_l4_per__dss_venc,
6280         &omap44xx_l4_per__elm,
6281         &omap44xx_emif_fw__emif1,
6282         &omap44xx_emif_fw__emif2,
6283         &omap44xx_l4_cfg__fdif,
6284         &omap44xx_l4_wkup__gpio1,
6285         &omap44xx_l4_per__gpio2,
6286         &omap44xx_l4_per__gpio3,
6287         &omap44xx_l4_per__gpio4,
6288         &omap44xx_l4_per__gpio5,
6289         &omap44xx_l4_per__gpio6,
6290         &omap44xx_l3_main_2__gpmc,
6291         &omap44xx_l3_main_2__gpu,
6292         &omap44xx_l4_per__hdq1w,
6293         &omap44xx_l4_cfg__hsi,
6294         &omap44xx_l4_per__i2c1,
6295         &omap44xx_l4_per__i2c2,
6296         &omap44xx_l4_per__i2c3,
6297         &omap44xx_l4_per__i2c4,
6298         &omap44xx_l3_main_2__ipu,
6299         &omap44xx_l3_main_2__iss,
6300         /* &omap44xx_iva__sl2if, */
6301         &omap44xx_l3_main_2__iva,
6302         &omap44xx_l4_wkup__kbd,
6303         &omap44xx_l4_cfg__mailbox,
6304         &omap44xx_l4_abe__mcasp,
6305         &omap44xx_l4_abe__mcasp_dma,
6306         &omap44xx_l4_abe__mcbsp1,
6307         &omap44xx_l4_abe__mcbsp1_dma,
6308         &omap44xx_l4_abe__mcbsp2,
6309         &omap44xx_l4_abe__mcbsp2_dma,
6310         &omap44xx_l4_abe__mcbsp3,
6311         &omap44xx_l4_abe__mcbsp3_dma,
6312         &omap44xx_l4_per__mcbsp4,
6313         &omap44xx_l4_abe__mcpdm,
6314         &omap44xx_l4_abe__mcpdm_dma,
6315         &omap44xx_l4_per__mcspi1,
6316         &omap44xx_l4_per__mcspi2,
6317         &omap44xx_l4_per__mcspi3,
6318         &omap44xx_l4_per__mcspi4,
6319         &omap44xx_l4_per__mmc1,
6320         &omap44xx_l4_per__mmc2,
6321         &omap44xx_l4_per__mmc3,
6322         &omap44xx_l4_per__mmc4,
6323         &omap44xx_l4_per__mmc5,
6324         &omap44xx_l3_main_2__mmu_ipu,
6325         &omap44xx_l4_cfg__mmu_dsp,
6326         &omap44xx_l3_main_2__ocmc_ram,
6327         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6328         &omap44xx_mpu_private__prcm_mpu,
6329         &omap44xx_l4_wkup__cm_core_aon,
6330         &omap44xx_l4_cfg__cm_core,
6331         &omap44xx_l4_wkup__prm,
6332         &omap44xx_l4_wkup__scrm,
6333         /* &omap44xx_l3_main_2__sl2if, */
6334         &omap44xx_l4_abe__slimbus1,
6335         &omap44xx_l4_abe__slimbus1_dma,
6336         &omap44xx_l4_per__slimbus2,
6337         &omap44xx_l4_cfg__smartreflex_core,
6338         &omap44xx_l4_cfg__smartreflex_iva,
6339         &omap44xx_l4_cfg__smartreflex_mpu,
6340         &omap44xx_l4_cfg__spinlock,
6341         &omap44xx_l4_wkup__timer1,
6342         &omap44xx_l4_per__timer2,
6343         &omap44xx_l4_per__timer3,
6344         &omap44xx_l4_per__timer4,
6345         &omap44xx_l4_abe__timer5,
6346         &omap44xx_l4_abe__timer5_dma,
6347         &omap44xx_l4_abe__timer6,
6348         &omap44xx_l4_abe__timer6_dma,
6349         &omap44xx_l4_abe__timer7,
6350         &omap44xx_l4_abe__timer7_dma,
6351         &omap44xx_l4_abe__timer8,
6352         &omap44xx_l4_abe__timer8_dma,
6353         &omap44xx_l4_per__timer9,
6354         &omap44xx_l4_per__timer10,
6355         &omap44xx_l4_per__timer11,
6356         &omap44xx_l4_per__uart1,
6357         &omap44xx_l4_per__uart2,
6358         &omap44xx_l4_per__uart3,
6359         &omap44xx_l4_per__uart4,
6360         /* &omap44xx_l4_cfg__usb_host_fs, */
6361         &omap44xx_l4_cfg__usb_host_hs,
6362         &omap44xx_l4_cfg__usb_otg_hs,
6363         &omap44xx_l4_cfg__usb_tll_hs,
6364         &omap44xx_l4_wkup__wd_timer2,
6365         &omap44xx_l4_abe__wd_timer3,
6366         &omap44xx_l4_abe__wd_timer3_dma,
6367         NULL,
6368 };
6369
6370 int __init omap44xx_hwmod_init(void)
6371 {
6372         omap_hwmod_init();
6373         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6374 }
6375