arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/export.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25
  26 #include <asm/proc-fns.h>
  27 #include <asm/exception.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/hardware/gic.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/cacheflush.h>
  33
  34 #include <mach/regs-irq.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/regs-gpio.h>
  37 #include <mach/pmu.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/sdhci.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/fimc-core.h>
  48 #include <plat/iic-core.h>
  49 #include <plat/tv-core.h>
  50 #include <plat/regs-serial.h>
  51
  52 #include "common.h"
  53 #define L2_AUX_VAL 0x7C470001
  54 #define L2_AUX_MASK 0xC200ffff
  55
  56 static const char name_exynos4210[] = "EXYNOS4210";
  57 static const char name_exynos4212[] = "EXYNOS4212";
  58 static const char name_exynos4412[] = "EXYNOS4412";
  59 static const char name_exynos5250[] = "EXYNOS5250";
  60
  61 static void exynos4_map_io(void);
  62 static void exynos5_map_io(void);
  63 static void exynos4_init_clocks(int xtal);
  64 static void exynos5_init_clocks(int xtal);
  65 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  66 static int exynos_init(void);
  67
  68 static struct cpu_table cpu_ids[] __initdata = {
  69         {
  70                 .idcode         = EXYNOS4210_CPU_ID,
  71                 .idmask         = EXYNOS4_CPU_MASK,
  72                 .map_io         = exynos4_map_io,
  73                 .init_clocks    = exynos4_init_clocks,
  74                 .init_uarts     = exynos_init_uarts,
  75                 .init           = exynos_init,
  76                 .name           = name_exynos4210,
  77         }, {
  78                 .idcode         = EXYNOS4212_CPU_ID,
  79                 .idmask         = EXYNOS4_CPU_MASK,
  80                 .map_io         = exynos4_map_io,
  81                 .init_clocks    = exynos4_init_clocks,
  82                 .init_uarts     = exynos_init_uarts,
  83                 .init           = exynos_init,
  84                 .name           = name_exynos4212,
  85         }, {
  86                 .idcode         = EXYNOS4412_CPU_ID,
  87                 .idmask         = EXYNOS4_CPU_MASK,
  88                 .map_io         = exynos4_map_io,
  89                 .init_clocks    = exynos4_init_clocks,
  90                 .init_uarts     = exynos_init_uarts,
  91                 .init           = exynos_init,
  92                 .name           = name_exynos4412,
  93         }, {
  94                 .idcode         = EXYNOS5250_SOC_ID,
  95                 .idmask         = EXYNOS5_SOC_MASK,
  96                 .map_io         = exynos5_map_io,
  97                 .init_clocks    = exynos5_init_clocks,
  98                 .init_uarts     = exynos_init_uarts,
  99                 .init           = exynos_init,
 100                 .name           = name_exynos5250,
 101         },
 102 };
 103
 104 /* Initial IO mappings */
 105
 106 static struct map_desc exynos_iodesc[] __initdata = {
 107         {
 108                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 109                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE,
 112         },
 113 };
 114
 115 static struct map_desc exynos4_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S3C_VA_SYS,
 118                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 119                 .length         = SZ_64K,
 120                 .type           = MT_DEVICE,
 121         }, {
 122                 .virtual        = (unsigned long)S3C_VA_TIMER,
 123                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 124                 .length         = SZ_16K,
 125                 .type           = MT_DEVICE,
 126         }, {
 127                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 128                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         }, {
 132                 .virtual        = (unsigned long)S5P_VA_SROMC,
 133                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 134                 .length         = SZ_4K,
 135                 .type           = MT_DEVICE,
 136         }, {
 137                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 139                 .length         = SZ_4K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S5P_VA_PMU,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 144                 .length         = SZ_64K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 154                 .length         = SZ_64K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 159                 .length         = SZ_64K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S3C_VA_UART,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 164                 .length         = SZ_512K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_CMU,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 169                 .length         = SZ_128K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 174                 .length         = SZ_8K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_L2CC,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 179                 .length         = SZ_4K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S5P_VA_DMC0,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 184                 .length         = SZ_64K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_DMC1,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 189                 .length         = SZ_64K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 194                 .length         = SZ_4K,
 195                 .type           = MT_DEVICE,
 196         },
 197 };
 198
 199 static struct map_desc exynos4_iodesc0[] __initdata = {
 200         {
 201                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 202                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 203                 .length         = SZ_4K,
 204                 .type           = MT_DEVICE,
 205         },
 206 };
 207
 208 static struct map_desc exynos4_iodesc1[] __initdata = {
 209         {
 210                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 211                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos5_iodesc[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S3C_VA_SYS,
 220                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 221                 .length         = SZ_64K,
 222                 .type           = MT_DEVICE,
 223         }, {
 224                 .virtual        = (unsigned long)S3C_VA_TIMER,
 225                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 226                 .length         = SZ_16K,
 227                 .type           = MT_DEVICE,
 228         }, {
 229                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 230                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 231                 .length         = SZ_4K,
 232                 .type           = MT_DEVICE,
 233         }, {
 234                 .virtual        = (unsigned long)S5P_VA_SROMC,
 235                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 236                 .length         = SZ_4K,
 237                 .type           = MT_DEVICE,
 238         }, {
 239                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 241                 .length         = SZ_4K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 246                 .length         = SZ_4K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S5P_VA_CMU,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 251                 .length         = 144 * SZ_1K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_PMU,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 256                 .length         = SZ_64K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
 261                 .length         = SZ_4K,
 262                 .type           = MT_DEVICE,
 263         }, {
 264                 .virtual        = (unsigned long)S3C_VA_UART,
 265                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 266                 .length         = SZ_512K,
 267                 .type           = MT_DEVICE,
 268         }, {
 269                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 270                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
 271                 .length         = SZ_8K,
 272                 .type           = MT_DEVICE,
 273         }, {
 274                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 275                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
 276                 .length         = SZ_4K,
 277                 .type           = MT_DEVICE,
 278         },
 279 };
 280
 281 void exynos4_restart(char mode, const char *cmd)
 282 {
 283         __raw_writel(0x1, S5P_SWRESET);
 284 }
 285
 286 void exynos5_restart(char mode, const char *cmd)
 287 {
 288         __raw_writel(0x1, EXYNOS_SWRESET);
 289 }
 290
 291 void __init exynos_init_late(void)
 292 {
 293         exynos_pm_late_initcall();
 294 }
 295
 296 /*
 297  * exynos_map_io
 298  *
 299  * register the standard cpu IO areas
 300  */
 301
 302 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 303 {
 304         /* initialize the io descriptors we need for initialization */
 305         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 306         if (mach_desc)
 307                 iotable_init(mach_desc, size);
 308
 309         /* detect cpu id and rev. */
 310         s5p_init_cpu(S5P_VA_CHIPID);
 311
 312         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 313 }
 314
 315 static void __init exynos4_map_io(void)
 316 {
 317         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 318
 319         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 320                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 321         else
 322                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 323
 324         /* initialize device information early */
 325         exynos4_default_sdhci0();
 326         exynos4_default_sdhci1();
 327         exynos4_default_sdhci2();
 328         exynos4_default_sdhci3();
 329
 330         s3c_adc_setname("samsung-adc-v3");
 331
 332         s3c_fimc_setname(0, "exynos4-fimc");
 333         s3c_fimc_setname(1, "exynos4-fimc");
 334         s3c_fimc_setname(2, "exynos4-fimc");
 335         s3c_fimc_setname(3, "exynos4-fimc");
 336
 337         s3c_sdhci_setname(0, "exynos4-sdhci");
 338         s3c_sdhci_setname(1, "exynos4-sdhci");
 339         s3c_sdhci_setname(2, "exynos4-sdhci");
 340         s3c_sdhci_setname(3, "exynos4-sdhci");
 341
 342         /* The I2C bus controllers are directly compatible with s3c2440 */
 343         s3c_i2c0_setname("s3c2440-i2c");
 344         s3c_i2c1_setname("s3c2440-i2c");
 345         s3c_i2c2_setname("s3c2440-i2c");
 346
 347         s5p_fb_setname(0, "exynos4-fb");
 348         s5p_hdmi_setname("exynos4-hdmi");
 349 }
 350
 351 static void __init exynos5_map_io(void)
 352 {
 353         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 354
 355         s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
 356         s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
 357         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
 358         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 359
 360         s3c_sdhci_setname(0, "exynos4-sdhci");
 361         s3c_sdhci_setname(1, "exynos4-sdhci");
 362         s3c_sdhci_setname(2, "exynos4-sdhci");
 363         s3c_sdhci_setname(3, "exynos4-sdhci");
 364
 365         /* The I2C bus controllers are directly compatible with s3c2440 */
 366         s3c_i2c0_setname("s3c2440-i2c");
 367         s3c_i2c1_setname("s3c2440-i2c");
 368         s3c_i2c2_setname("s3c2440-i2c");
 369 }
 370
 371 static void __init exynos4_init_clocks(int xtal)
 372 {
 373         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 374
 375         s3c24xx_register_baseclocks(xtal);
 376         s5p_register_clocks(xtal);
 377
 378         if (soc_is_exynos4210())
 379                 exynos4210_register_clocks();
 380         else if (soc_is_exynos4212() || soc_is_exynos4412())
 381                 exynos4212_register_clocks();
 382
 383         exynos4_register_clocks();
 384         exynos4_setup_clocks();
 385 }
 386
 387 static void __init exynos5_init_clocks(int xtal)
 388 {
 389         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 390
 391         s3c24xx_register_baseclocks(xtal);
 392         s5p_register_clocks(xtal);
 393
 394         exynos5_register_clocks();
 395         exynos5_setup_clocks();
 396 }
 397
 398 #define COMBINER_ENABLE_SET     0x0
 399 #define COMBINER_ENABLE_CLEAR   0x4
 400 #define COMBINER_INT_STATUS     0xC
 401
 402 static DEFINE_SPINLOCK(irq_controller_lock);
 403
 404 struct combiner_chip_data {
 405         unsigned int irq_offset;
 406         unsigned int irq_mask;
 407         void __iomem *base;
 408 };
 409
 410 static struct irq_domain *combiner_irq_domain;
 411 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 412
 413 static inline void __iomem *combiner_base(struct irq_data *data)
 414 {
 415         struct combiner_chip_data *combiner_data =
 416                 irq_data_get_irq_chip_data(data);
 417
 418         return combiner_data->base;
 419 }
 420
 421 static void combiner_mask_irq(struct irq_data *data)
 422 {
 423         u32 mask = 1 << (data->hwirq % 32);
 424
 425         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 426 }
 427
 428 static void combiner_unmask_irq(struct irq_data *data)
 429 {
 430         u32 mask = 1 << (data->hwirq % 32);
 431
 432         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 433 }
 434
 435 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 436 {
 437         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 438         struct irq_chip *chip = irq_get_chip(irq);
 439         unsigned int cascade_irq, combiner_irq;
 440         unsigned long status;
 441
 442         chained_irq_enter(chip, desc);
 443
 444         spin_lock(&irq_controller_lock);
 445         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 446         spin_unlock(&irq_controller_lock);
 447         status &= chip_data->irq_mask;
 448
 449         if (status == 0)
 450                 goto out;
 451
 452         combiner_irq = __ffs(status);
 453
 454         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 455         if (unlikely(cascade_irq >= NR_IRQS))
 456                 do_bad_IRQ(cascade_irq, desc);
 457         else
 458                 generic_handle_irq(cascade_irq);
 459
 460  out:
 461         chained_irq_exit(chip, desc);
 462 }
 463
 464 static struct irq_chip combiner_chip = {
 465         .name           = "COMBINER",
 466         .irq_mask       = combiner_mask_irq,
 467         .irq_unmask     = combiner_unmask_irq,
 468 };
 469
 470 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 471 {
 472         unsigned int max_nr;
 473
 474         if (soc_is_exynos5250())
 475                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 476         else
 477                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 478
 479         if (combiner_nr >= max_nr)
 480                 BUG();
 481         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 482                 BUG();
 483         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 484 }
 485
 486 static void __init combiner_init_one(unsigned int combiner_nr,
 487                                      void __iomem *base)
 488 {
 489         combiner_data[combiner_nr].base = base;
 490         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 491                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 492         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 493
 494         /* Disable all interrupts */
 495         __raw_writel(combiner_data[combiner_nr].irq_mask,
 496                      base + COMBINER_ENABLE_CLEAR);
 497 }
 498
 499 #ifdef CONFIG_OF
 500 static int combiner_irq_domain_xlate(struct irq_domain *d,
 501                                      struct device_node *controller,
 502                                      const u32 *intspec, unsigned int intsize,
 503                                      unsigned long *out_hwirq,
 504                                      unsigned int *out_type)
 505 {
 506         if (d->of_node != controller)
 507                 return -EINVAL;
 508
 509         if (intsize < 2)
 510                 return -EINVAL;
 511
 512         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 513         *out_type = 0;
 514
 515         return 0;
 516 }
 517 #else
 518 static int combiner_irq_domain_xlate(struct irq_domain *d,
 519                                      struct device_node *controller,
 520                                      const u32 *intspec, unsigned int intsize,
 521                                      unsigned long *out_hwirq,
 522                                      unsigned int *out_type)
 523 {
 524         return -EINVAL;
 525 }
 526 #endif
 527
 528 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 529                                    irq_hw_number_t hw)
 530 {
 531         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 532         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 533         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 534
 535         return 0;
 536 }
 537
 538 static struct irq_domain_ops combiner_irq_domain_ops = {
 539         .xlate  = combiner_irq_domain_xlate,
 540         .map    = combiner_irq_domain_map,
 541 };
 542
 543 static void __init combiner_init(void __iomem *combiner_base,
 544                                  struct device_node *np)
 545 {
 546         int i, irq, irq_base;
 547         unsigned int max_nr, nr_irq;
 548
 549         if (np) {
 550                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 551                         pr_warning("%s: number of combiners not specified, "
 552                                 "setting default as %d.\n",
 553                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 554                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 555                 }
 556         } else {
 557                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 558                                                 EXYNOS4_MAX_COMBINER_NR;
 559         }
 560         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 561
 562         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 563         if (IS_ERR_VALUE(irq_base)) {
 564                 irq_base = COMBINER_IRQ(0, 0);
 565                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 566         }
 567
 568         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 569                                 &combiner_irq_domain_ops, &combiner_data);
 570         if (WARN_ON(!combiner_irq_domain)) {
 571                 pr_warning("%s: irq domain init failed\n", __func__);
 572                 return;
 573         }
 574
 575         for (i = 0; i < max_nr; i++) {
 576                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 577                 irq = IRQ_SPI(i);
 578 #ifdef CONFIG_OF
 579                 if (np)
 580                         irq = irq_of_parse_and_map(np, i);
 581 #endif
 582                 combiner_cascade_irq(i, irq);
 583         }
 584 }
 585
 586 #ifdef CONFIG_OF
 587 int __init combiner_of_init(struct device_node *np, struct device_node *parent)
 588 {
 589         void __iomem *combiner_base;
 590
 591         combiner_base = of_iomap(np, 0);
 592         if (!combiner_base) {
 593                 pr_err("%s: failed to map combiner registers\n", __func__);
 594                 return -ENXIO;
 595         }
 596
 597         combiner_init(combiner_base, np);
 598
 599         return 0;
 600 }
 601
 602 static const struct of_device_id exynos4_dt_irq_match[] = {
 603         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 604         { .compatible = "samsung,exynos4210-combiner",
 605                         .data = combiner_of_init, },
 606         {},
 607 };
 608 #endif
 609
 610 void __init exynos4_init_irq(void)
 611 {
 612         unsigned int gic_bank_offset;
 613
 614         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 615
 616         if (!of_have_populated_dt())
 617                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 618 #ifdef CONFIG_OF
 619         else
 620                 of_irq_init(exynos4_dt_irq_match);
 621 #endif
 622
 623         if (!of_have_populated_dt())
 624                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 625
 626         /*
 627          * The parameters of s5p_init_irq() are for VIC init.
 628          * Theses parameters should be NULL and 0 because EXYNOS4
 629          * uses GIC instead of VIC.
 630          */
 631         s5p_init_irq(NULL, 0);
 632 }
 633
 634 void __init exynos5_init_irq(void)
 635 {
 636 #ifdef CONFIG_OF
 637         of_irq_init(exynos4_dt_irq_match);
 638 #endif
 639         /*
 640          * The parameters of s5p_init_irq() are for VIC init.
 641          * Theses parameters should be NULL and 0 because EXYNOS4
 642          * uses GIC instead of VIC.
 643          */
 644         s5p_init_irq(NULL, 0);
 645 }
 646
 647 struct bus_type exynos_subsys = {
 648         .name           = "exynos-core",
 649         .dev_name       = "exynos-core",
 650 };
 651
 652 static struct device exynos4_dev = {
 653         .bus    = &exynos_subsys,
 654 };
 655
 656 static int __init exynos_core_init(void)
 657 {
 658         return subsys_system_register(&exynos_subsys, NULL);
 659 }
 660 core_initcall(exynos_core_init);
 661
 662 #ifdef CONFIG_CACHE_L2X0
 663 static int __init exynos4_l2x0_cache_init(void)
 664 {
 665         int ret;
 666
 667         if (soc_is_exynos5250())
 668                 return 0;
 669
 670         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 671         if (!ret) {
 672                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 673                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 674                 return 0;
 675         }
 676
 677         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 678                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 679                 /* TAG, Data Latency Control: 2 cycles */
 680                 l2x0_saved_regs.tag_latency = 0x110;
 681
 682                 if (soc_is_exynos4212() || soc_is_exynos4412())
 683                         l2x0_saved_regs.data_latency = 0x120;
 684                 else
 685                         l2x0_saved_regs.data_latency = 0x110;
 686
 687                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 688                 l2x0_saved_regs.pwr_ctrl =
 689                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 690
 691                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 692
 693                 __raw_writel(l2x0_saved_regs.tag_latency,
 694                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 695                 __raw_writel(l2x0_saved_regs.data_latency,
 696                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 697
 698                 /* L2X0 Prefetch Control */
 699                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 700                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 701
 702                 /* L2X0 Power Control */
 703                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 704                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 705
 706                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 707                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 708         }
 709
 710         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 711         return 0;
 712 }
 713 early_initcall(exynos4_l2x0_cache_init);
 714 #endif
 715
 716 static int __init exynos_init(void)
 717 {
 718         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 719
 720         return device_register(&exynos4_dev);
 721 }
 722
 723 /* uart registration process */
 724
 725 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 726 {
 727         struct s3c2410_uartcfg *tcfg = cfg;
 728         u32 ucnt;
 729
 730         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 731                 tcfg->has_fracval = 1;
 732
 733         if (soc_is_exynos5250())
 734                 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
 735         else
 736                 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 737 }
 738
 739 static void __iomem *exynos_eint_base;
 740
 741 static DEFINE_SPINLOCK(eint_lock);
 742
 743 static unsigned int eint0_15_data[16];
 744
 745 static inline int exynos4_irq_to_gpio(unsigned int irq)
 746 {
 747         if (irq < IRQ_EINT(0))
 748                 return -EINVAL;
 749
 750         irq -= IRQ_EINT(0);
 751         if (irq < 8)
 752                 return EXYNOS4_GPX0(irq);
 753
 754         irq -= 8;
 755         if (irq < 8)
 756                 return EXYNOS4_GPX1(irq);
 757
 758         irq -= 8;
 759         if (irq < 8)
 760                 return EXYNOS4_GPX2(irq);
 761
 762         irq -= 8;
 763         if (irq < 8)
 764                 return EXYNOS4_GPX3(irq);
 765
 766         return -EINVAL;
 767 }
 768
 769 static inline int exynos5_irq_to_gpio(unsigned int irq)
 770 {
 771         if (irq < IRQ_EINT(0))
 772                 return -EINVAL;
 773
 774         irq -= IRQ_EINT(0);
 775         if (irq < 8)
 776                 return EXYNOS5_GPX0(irq);
 777
 778         irq -= 8;
 779         if (irq < 8)
 780                 return EXYNOS5_GPX1(irq);
 781
 782         irq -= 8;
 783         if (irq < 8)
 784                 return EXYNOS5_GPX2(irq);
 785
 786         irq -= 8;
 787         if (irq < 8)
 788                 return EXYNOS5_GPX3(irq);
 789
 790         return -EINVAL;
 791 }
 792
 793 static unsigned int exynos4_eint0_15_src_int[16] = {
 794         EXYNOS4_IRQ_EINT0,
 795         EXYNOS4_IRQ_EINT1,
 796         EXYNOS4_IRQ_EINT2,
 797         EXYNOS4_IRQ_EINT3,
 798         EXYNOS4_IRQ_EINT4,
 799         EXYNOS4_IRQ_EINT5,
 800         EXYNOS4_IRQ_EINT6,
 801         EXYNOS4_IRQ_EINT7,
 802         EXYNOS4_IRQ_EINT8,
 803         EXYNOS4_IRQ_EINT9,
 804         EXYNOS4_IRQ_EINT10,
 805         EXYNOS4_IRQ_EINT11,
 806         EXYNOS4_IRQ_EINT12,
 807         EXYNOS4_IRQ_EINT13,
 808         EXYNOS4_IRQ_EINT14,
 809         EXYNOS4_IRQ_EINT15,
 810 };
 811
 812 static unsigned int exynos5_eint0_15_src_int[16] = {
 813         EXYNOS5_IRQ_EINT0,
 814         EXYNOS5_IRQ_EINT1,
 815         EXYNOS5_IRQ_EINT2,
 816         EXYNOS5_IRQ_EINT3,
 817         EXYNOS5_IRQ_EINT4,
 818         EXYNOS5_IRQ_EINT5,
 819         EXYNOS5_IRQ_EINT6,
 820         EXYNOS5_IRQ_EINT7,
 821         EXYNOS5_IRQ_EINT8,
 822         EXYNOS5_IRQ_EINT9,
 823         EXYNOS5_IRQ_EINT10,
 824         EXYNOS5_IRQ_EINT11,
 825         EXYNOS5_IRQ_EINT12,
 826         EXYNOS5_IRQ_EINT13,
 827         EXYNOS5_IRQ_EINT14,
 828         EXYNOS5_IRQ_EINT15,
 829 };
 830 static inline void exynos_irq_eint_mask(struct irq_data *data)
 831 {
 832         u32 mask;
 833
 834         spin_lock(&eint_lock);
 835         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 836         mask |= EINT_OFFSET_BIT(data->irq);
 837         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 838         spin_unlock(&eint_lock);
 839 }
 840
 841 static void exynos_irq_eint_unmask(struct irq_data *data)
 842 {
 843         u32 mask;
 844
 845         spin_lock(&eint_lock);
 846         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 847         mask &= ~(EINT_OFFSET_BIT(data->irq));
 848         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 849         spin_unlock(&eint_lock);
 850 }
 851
 852 static inline void exynos_irq_eint_ack(struct irq_data *data)
 853 {
 854         __raw_writel(EINT_OFFSET_BIT(data->irq),
 855                      EINT_PEND(exynos_eint_base, data->irq));
 856 }
 857
 858 static void exynos_irq_eint_maskack(struct irq_data *data)
 859 {
 860         exynos_irq_eint_mask(data);
 861         exynos_irq_eint_ack(data);
 862 }
 863
 864 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 865 {
 866         int offs = EINT_OFFSET(data->irq);
 867         int shift;
 868         u32 ctrl, mask;
 869         u32 newvalue = 0;
 870
 871         switch (type) {
 872         case IRQ_TYPE_EDGE_RISING:
 873                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 874                 break;
 875
 876         case IRQ_TYPE_EDGE_FALLING:
 877                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 878                 break;
 879
 880         case IRQ_TYPE_EDGE_BOTH:
 881                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 882                 break;
 883
 884         case IRQ_TYPE_LEVEL_LOW:
 885                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 886                 break;
 887
 888         case IRQ_TYPE_LEVEL_HIGH:
 889                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 890                 break;
 891
 892         default:
 893                 printk(KERN_ERR "No such irq type %d", type);
 894                 return -EINVAL;
 895         }
 896
 897         shift = (offs & 0x7) * 4;
 898         mask = 0x7 << shift;
 899
 900         spin_lock(&eint_lock);
 901         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 902         ctrl &= ~mask;
 903         ctrl |= newvalue << shift;
 904         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 905         spin_unlock(&eint_lock);
 906
 907         if (soc_is_exynos5250())
 908                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 909         else
 910                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 911
 912         return 0;
 913 }
 914
 915 static struct irq_chip exynos_irq_eint = {
 916         .name           = "exynos-eint",
 917         .irq_mask       = exynos_irq_eint_mask,
 918         .irq_unmask     = exynos_irq_eint_unmask,
 919         .irq_mask_ack   = exynos_irq_eint_maskack,
 920         .irq_ack        = exynos_irq_eint_ack,
 921         .irq_set_type   = exynos_irq_eint_set_type,
 922 #ifdef CONFIG_PM
 923         .irq_set_wake   = s3c_irqext_wake,
 924 #endif
 925 };
 926
 927 /*
 928  * exynos4_irq_demux_eint
 929  *
 930  * This function demuxes the IRQ from from EINTs 16 to 31.
 931  * It is designed to be inlined into the specific handler
 932  * s5p_irq_demux_eintX_Y.
 933  *
 934  * Each EINT pend/mask registers handle eight of them.
 935  */
 936 static inline void exynos_irq_demux_eint(unsigned int start)
 937 {
 938         unsigned int irq;
 939
 940         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 941         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 942
 943         status &= ~mask;
 944         status &= 0xff;
 945
 946         while (status) {
 947                 irq = fls(status) - 1;
 948                 generic_handle_irq(irq + start);
 949                 status &= ~(1 << irq);
 950         }
 951 }
 952
 953 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 954 {
 955         struct irq_chip *chip = irq_get_chip(irq);
 956         chained_irq_enter(chip, desc);
 957         exynos_irq_demux_eint(IRQ_EINT(16));
 958         exynos_irq_demux_eint(IRQ_EINT(24));
 959         chained_irq_exit(chip, desc);
 960 }
 961
 962 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 963 {
 964         u32 *irq_data = irq_get_handler_data(irq);
 965         struct irq_chip *chip = irq_get_chip(irq);
 966
 967         chained_irq_enter(chip, desc);
 968         chip->irq_mask(&desc->irq_data);
 969
 970         if (chip->irq_ack)
 971                 chip->irq_ack(&desc->irq_data);
 972
 973         generic_handle_irq(*irq_data);
 974
 975         chip->irq_unmask(&desc->irq_data);
 976         chained_irq_exit(chip, desc);
 977 }
 978
 979 static int __init exynos_init_irq_eint(void)
 980 {
 981         int irq;
 982
 983 #ifdef CONFIG_PINCTRL_SAMSUNG
 984         /*
 985          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
 986          * functionality along with support for external gpio and wakeup
 987          * interrupts. If the samsung pinctrl driver is enabled and includes
 988          * the wakeup interrupt support, then the setting up external wakeup
 989          * interrupts here can be skipped. This check here is temporary to
 990          * allow exynos4 platforms that do not use Samsung pinctrl driver to
 991          * co-exist with platforms that do. When all of the Samsung Exynos4
 992          * platforms switch over to using the pinctrl driver, the wakeup
 993          * interrupt support code here can be completely removed.
 994          */
 995         struct device_node *pctrl_np, *wkup_np;
 996         const char *pctrl_compat = "samsung,pinctrl-exynos4210";
 997         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
 998
 999         for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
1000                 if (of_device_is_available(pctrl_np)) {
1001                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
1002                                                         wkup_compat);
1003                         if (wkup_np)
1004                                 return -ENODEV;
1005                 }
1006         }
1007 #endif
1008
1009         if (soc_is_exynos5250())
1010                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1011         else
1012                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1013
1014         if (exynos_eint_base == NULL) {
1015                 pr_err("unable to ioremap for EINT base address\n");
1016                 return -ENOMEM;
1017         }
1018
1019         for (irq = 0 ; irq <= 31 ; irq++) {
1020                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
1021                                          handle_level_irq);
1022                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1023         }
1024
1025         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
1026
1027         for (irq = 0 ; irq <= 15 ; irq++) {
1028                 eint0_15_data[irq] = IRQ_EINT(irq);
1029
1030                 if (soc_is_exynos5250()) {
1031                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1032                                              &eint0_15_data[irq]);
1033                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1034                                                 exynos_irq_eint0_15);
1035                 } else {
1036                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1037                                              &eint0_15_data[irq]);
1038                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1039                                                 exynos_irq_eint0_15);
1040                 }
1041         }
1042
1043         return 0;
1044 }
1045 arch_initcall(exynos_init_irq_eint);