arch/arm/mach-imx/clock-imx27.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/clkdev.h>
  25 #include <linux/of.h>
  26
  27 #include <asm/div64.h>
  28
  29 #include <mach/clock.h>
  30 #include <mach/common.h>
  31 #include <mach/hardware.h>
  32
  33 #define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
  34
  35 /* Register offsets */
  36 #define CCM_CSCR                IO_ADDR_CCM(0x0)
  37 #define CCM_MPCTL0              IO_ADDR_CCM(0x4)
  38 #define CCM_MPCTL1              IO_ADDR_CCM(0x8)
  39 #define CCM_SPCTL0              IO_ADDR_CCM(0xc)
  40 #define CCM_SPCTL1              IO_ADDR_CCM(0x10)
  41 #define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
  42 #define CCM_PCDR0               IO_ADDR_CCM(0x18)
  43 #define CCM_PCDR1               IO_ADDR_CCM(0x1c)
  44 #define CCM_PCCR0               IO_ADDR_CCM(0x20)
  45 #define CCM_PCCR1               IO_ADDR_CCM(0x24)
  46 #define CCM_CCSR                IO_ADDR_CCM(0x28)
  47 #define CCM_PMCTL               IO_ADDR_CCM(0x2c)
  48 #define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
  49 #define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
  50
  51 #define CCM_CSCR_UPDATE_DIS     (1 << 31)
  52 #define CCM_CSCR_SSI2           (1 << 23)
  53 #define CCM_CSCR_SSI1           (1 << 22)
  54 #define CCM_CSCR_VPU            (1 << 21)
  55 #define CCM_CSCR_MSHC           (1 << 20)
  56 #define CCM_CSCR_SPLLRES        (1 << 19)
  57 #define CCM_CSCR_MPLLRES        (1 << 18)
  58 #define CCM_CSCR_SP             (1 << 17)
  59 #define CCM_CSCR_MCU            (1 << 16)
  60 #define CCM_CSCR_OSC26MDIV      (1 << 4)
  61 #define CCM_CSCR_OSC26M         (1 << 3)
  62 #define CCM_CSCR_FPM            (1 << 2)
  63 #define CCM_CSCR_SPEN           (1 << 1)
  64 #define CCM_CSCR_MPEN           (1 << 0)
  65
  66 /* i.MX27 TO 2+ */
  67 #define CCM_CSCR_ARM_SRC        (1 << 15)
  68
  69 #define CCM_SPCTL1_LF           (1 << 15)
  70 #define CCM_SPCTL1_BRMO         (1 << 6)
  71
  72 static struct clk mpll_main1_clk, mpll_main2_clk;
  73
  74 static int clk_pccr_enable(struct clk *clk)
  75 {
  76         unsigned long reg;
  77
  78         if (!clk->enable_reg)
  79                 return 0;
  80
  81         reg = __raw_readl(clk->enable_reg);
  82         reg |= 1 << clk->enable_shift;
  83         __raw_writel(reg, clk->enable_reg);
  84
  85         return 0;
  86 }
  87
  88 static void clk_pccr_disable(struct clk *clk)
  89 {
  90         unsigned long reg;
  91
  92         if (!clk->enable_reg)
  93                 return;
  94
  95         reg = __raw_readl(clk->enable_reg);
  96         reg &= ~(1 << clk->enable_shift);
  97         __raw_writel(reg, clk->enable_reg);
  98 }
  99
 100 static int clk_spll_enable(struct clk *clk)
 101 {
 102         unsigned long reg;
 103
 104         reg = __raw_readl(CCM_CSCR);
 105         reg |= CCM_CSCR_SPEN;
 106         __raw_writel(reg, CCM_CSCR);
 107
 108         while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
 109
 110         return 0;
 111 }
 112
 113 static void clk_spll_disable(struct clk *clk)
 114 {
 115         unsigned long reg;
 116
 117         reg = __raw_readl(CCM_CSCR);
 118         reg &= ~CCM_CSCR_SPEN;
 119         __raw_writel(reg, CCM_CSCR);
 120 }
 121
 122 static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
 123 {
 124         int cscr = __raw_readl(CCM_CSCR);
 125
 126         if (clk->parent == parent)
 127                 return 0;
 128
 129         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
 130                 if (parent == &mpll_main1_clk) {
 131                         cscr |= CCM_CSCR_ARM_SRC;
 132                 } else {
 133                         if (parent == &mpll_main2_clk)
 134                                 cscr &= ~CCM_CSCR_ARM_SRC;
 135                         else
 136                                 return -EINVAL;
 137                 }
 138                 __raw_writel(cscr, CCM_CSCR);
 139                 clk->parent = parent;
 140                 return 0;
 141         }
 142         return -ENODEV;
 143 }
 144
 145 static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
 146 {
 147         int div;
 148         unsigned long parent_rate;
 149
 150         parent_rate = clk_get_rate(clk->parent);
 151
 152         div = parent_rate / rate;
 153         if (parent_rate % rate)
 154                 div++;
 155
 156         if (div > 4)
 157                 div = 4;
 158
 159         return parent_rate / div;
 160 }
 161
 162 static int set_rate_cpu(struct clk *clk, unsigned long rate)
 163 {
 164         unsigned int div;
 165         uint32_t reg;
 166         unsigned long parent_rate;
 167
 168         parent_rate = clk_get_rate(clk->parent);
 169
 170         div = parent_rate / rate;
 171
 172         if (div > 4 || div < 1 || ((parent_rate / div) != rate))
 173                 return -EINVAL;
 174
 175         div--;
 176
 177         reg = __raw_readl(CCM_CSCR);
 178         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
 179                 reg &= ~(3 << 12);
 180                 reg |= div << 12;
 181                 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
 182                 __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
 183         } else {
 184                 printk(KERN_ERR "Can't set CPU frequency!\n");
 185         }
 186
 187         return 0;
 188 }
 189
 190 static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
 191 {
 192         u32 div;
 193         unsigned long parent_rate;
 194
 195         parent_rate = clk_get_rate(clk->parent);
 196
 197         div = parent_rate / rate;
 198         if (parent_rate % rate)
 199                 div++;
 200
 201         if (div > 64)
 202                 div = 64;
 203
 204         return parent_rate / div;
 205 }
 206
 207 static int set_rate_per(struct clk *clk, unsigned long rate)
 208 {
 209         u32 reg;
 210         u32 div;
 211         unsigned long parent_rate;
 212
 213         parent_rate = clk_get_rate(clk->parent);
 214
 215         if (clk->id < 0 || clk->id > 3)
 216                 return -EINVAL;
 217
 218         div = parent_rate / rate;
 219         if (div > 64 || div < 1 || ((parent_rate / div) != rate))
 220                 return -EINVAL;
 221         div--;
 222
 223         reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
 224         reg |= div << (clk->id << 3);
 225         __raw_writel(reg, CCM_PCDR1);
 226
 227         return 0;
 228 }
 229
 230 static unsigned long get_rate_usb(struct clk *clk)
 231 {
 232         unsigned long usb_pdf;
 233         unsigned long parent_rate;
 234
 235         parent_rate = clk_get_rate(clk->parent);
 236
 237         usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
 238
 239         return parent_rate / (usb_pdf + 1U);
 240 }
 241
 242 static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
 243 {
 244         unsigned long parent_rate;
 245
 246         parent_rate = clk_get_rate(clk->parent);
 247
 248         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 249                 pdf += 4;  /* MX27 TO2+ */
 250         else
 251                 pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
 252
 253         return 2UL * parent_rate / pdf;
 254 }
 255
 256 static unsigned long get_rate_ssi1(struct clk *clk)
 257 {
 258         return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
 259 }
 260
 261 static unsigned long get_rate_ssi2(struct clk *clk)
 262 {
 263         return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
 264 }
 265
 266 static unsigned long get_rate_nfc(struct clk *clk)
 267 {
 268         unsigned long nfc_pdf;
 269         unsigned long parent_rate;
 270
 271         parent_rate = clk_get_rate(clk->parent);
 272
 273         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 274                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
 275         else
 276                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
 277
 278         return parent_rate / (nfc_pdf + 1);
 279 }
 280
 281 static unsigned long get_rate_vpu(struct clk *clk)
 282 {
 283         unsigned long vpu_pdf;
 284         unsigned long parent_rate;
 285
 286         parent_rate = clk_get_rate(clk->parent);
 287
 288         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
 289                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
 290                 vpu_pdf += 4;
 291         } else {
 292                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
 293                 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
 294         }
 295
 296         return 2UL * parent_rate / vpu_pdf;
 297 }
 298
 299 static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
 300 {
 301         return clk->parent->round_rate(clk->parent, rate);
 302 }
 303
 304 static unsigned long get_rate_parent(struct clk *clk)
 305 {
 306         return clk_get_rate(clk->parent);
 307 }
 308
 309 static int set_rate_parent(struct clk *clk, unsigned long rate)
 310 {
 311         return clk->parent->set_rate(clk->parent, rate);
 312 }
 313
 314 /* in Hz */
 315 static unsigned long external_high_reference = 26000000;
 316
 317 static unsigned long get_rate_high_reference(struct clk *clk)
 318 {
 319         return external_high_reference;
 320 }
 321
 322 /* in Hz */
 323 static unsigned long external_low_reference = 32768;
 324
 325 static unsigned long get_rate_low_reference(struct clk *clk)
 326 {
 327         return external_low_reference;
 328 }
 329
 330 static unsigned long get_rate_fpm(struct clk *clk)
 331 {
 332         return clk_get_rate(clk->parent) * 1024;
 333 }
 334
 335 static unsigned long get_rate_mpll(struct clk *clk)
 336 {
 337         return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
 338                         clk_get_rate(clk->parent));
 339 }
 340
 341 static unsigned long get_rate_mpll_main(struct clk *clk)
 342 {
 343         unsigned long parent_rate;
 344
 345         parent_rate = clk_get_rate(clk->parent);
 346
 347         /* i.MX27 TO2:
 348          * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
 349          * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
 350          */
 351         if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
 352                 return 2UL * parent_rate / 3UL;
 353
 354         return parent_rate;
 355 }
 356
 357 static unsigned long get_rate_spll(struct clk *clk)
 358 {
 359         uint32_t reg;
 360         unsigned long rate;
 361
 362         rate = clk_get_rate(clk->parent);
 363
 364         reg = __raw_readl(CCM_SPCTL0);
 365
 366         /* On TO2 we have to write the value back. Otherwise we
 367          * read 0 from this register the next time.
 368          */
 369         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 370                 __raw_writel(reg, CCM_SPCTL0);
 371
 372         return mxc_decode_pll(reg, rate);
 373 }
 374
 375 static unsigned long get_rate_cpu(struct clk *clk)
 376 {
 377         u32 div;
 378         unsigned long rate;
 379
 380         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 381                 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
 382         else
 383                 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
 384
 385         rate = clk_get_rate(clk->parent);
 386         return rate / (div + 1);
 387 }
 388
 389 static unsigned long get_rate_ahb(struct clk *clk)
 390 {
 391         unsigned long rate, bclk_pdf;
 392
 393         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 394                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
 395         else
 396                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
 397
 398         rate = clk_get_rate(clk->parent);
 399         return rate / (bclk_pdf + 1);
 400 }
 401
 402 static unsigned long get_rate_ipg(struct clk *clk)
 403 {
 404         unsigned long rate, ipg_pdf;
 405
 406         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
 407                 return clk_get_rate(clk->parent);
 408         else
 409                 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
 410
 411         rate = clk_get_rate(clk->parent);
 412         return rate / (ipg_pdf + 1);
 413 }
 414
 415 static unsigned long get_rate_per(struct clk *clk)
 416 {
 417         unsigned long perclk_pdf, parent_rate;
 418
 419         parent_rate = clk_get_rate(clk->parent);
 420
 421         if (clk->id < 0 || clk->id > 3)
 422                 return 0;
 423
 424         perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
 425
 426         return parent_rate / (perclk_pdf + 1);
 427 }
 428
 429 /*
 430  * the high frequency external clock reference
 431  * Default case is 26MHz. Could be changed at runtime
 432  * with a call to change_external_high_reference()
 433  */
 434 static struct clk ckih_clk = {
 435         .get_rate       = get_rate_high_reference,
 436 };
 437
 438 static struct clk mpll_clk = {
 439         .parent         = &ckih_clk,
 440         .get_rate       = get_rate_mpll,
 441 };
 442
 443 /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
 444  * It provides the clock source whose rate is same as MPLL
 445  */
 446 static struct clk mpll_main1_clk = {
 447         .id             = 0,
 448         .parent         = &mpll_clk,
 449         .get_rate       = get_rate_mpll_main,
 450 };
 451
 452 /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
 453  * It provides the clock source whose rate is same MPLL * 2 / 3
 454  */
 455 static struct clk mpll_main2_clk = {
 456         .id             = 1,
 457         .parent         = &mpll_clk,
 458         .get_rate       = get_rate_mpll_main,
 459 };
 460
 461 static struct clk ahb_clk = {
 462         .parent         = &mpll_main2_clk,
 463         .get_rate       = get_rate_ahb,
 464 };
 465
 466 static struct clk ipg_clk = {
 467         .parent         = &ahb_clk,
 468         .get_rate       = get_rate_ipg,
 469 };
 470
 471 static struct clk cpu_clk = {
 472         .parent = &mpll_main2_clk,
 473         .set_parent = clk_cpu_set_parent,
 474         .round_rate = round_rate_cpu,
 475         .get_rate = get_rate_cpu,
 476         .set_rate = set_rate_cpu,
 477 };
 478
 479 static struct clk spll_clk = {
 480         .parent = &ckih_clk,
 481         .get_rate = get_rate_spll,
 482         .enable = clk_spll_enable,
 483         .disable = clk_spll_disable,
 484 };
 485
 486 /*
 487  * the low frequency external clock reference
 488  * Default case is 32.768kHz.
 489  */
 490 static struct clk ckil_clk = {
 491         .get_rate = get_rate_low_reference,
 492 };
 493
 494 /* Output of frequency pre multiplier */
 495 static struct clk fpm_clk = {
 496         .parent = &ckil_clk,
 497         .get_rate = get_rate_fpm,
 498 };
 499
 500 #define PCCR0 CCM_PCCR0
 501 #define PCCR1 CCM_PCCR1
 502
 503 #define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
 504         static struct clk name = {                      \
 505                 .id             = i,                    \
 506                 .enable_reg     = er,                   \
 507                 .enable_shift   = es,                   \
 508                 .get_rate       = gr,                   \
 509                 .enable         = clk_pccr_enable,      \
 510                 .disable        = clk_pccr_disable,     \
 511                 .secondary      = s,                    \
 512                 .parent         = p,                    \
 513         }
 514
 515 #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
 516         static struct clk name = {                              \
 517                 .id             = i,                            \
 518                 .enable_reg     = er,                           \
 519                 .enable_shift   = es,                           \
 520                 .get_rate       = get_rate_##getsetround,       \
 521                 .set_rate       = set_rate_##getsetround,       \
 522                 .round_rate     = round_rate_##getsetround,     \
 523                 .enable         = clk_pccr_enable,              \
 524                 .disable        = clk_pccr_disable,             \
 525                 .secondary      = s,                            \
 526                 .parent         = p,                            \
 527         }
 528
 529 /* Forward declaration to keep the following list in order */
 530 static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
 531                   dma_clk1, lcdc_clk2, vpu_clk1;
 532
 533 /* All clocks we can gate through PCCRx in the order of PCCRx bits */
 534 DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
 535 DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
 536 DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
 537 DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
 538 DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
 539 DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
 540 DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
 541 DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
 542 DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
 543 DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
 544 DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
 545 DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
 546 DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
 547 DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
 548 DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
 549 DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
 550 DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
 551 DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
 552 DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
 553 DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
 554 DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
 555 DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
 556 DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
 557 DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
 558 DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
 559 DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
 560 DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
 561 DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
 562 DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
 563 DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
 564 DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
 565
 566 DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
 567 DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
 568 DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
 569 DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
 570 DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
 571 DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
 572 DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
 573 DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
 574 DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
 575 DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
 576 DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
 577 DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
 578 DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
 579 DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
 580 DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
 581 DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
 582 DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
 583 DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
 584 DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
 585 DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
 586 DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
 587 DEFINE_CLOCK(pata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
 588 DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
 589 DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
 590 DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
 591 DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
 592 DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
 593 DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
 594 DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
 595 DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
 596
 597 /* Clocks we cannot directly gate, but drivers need their rates */
 598 DEFINE_CLOCK(cspi1_clk,    0, NULL,   0, NULL, &cspi1_clk1, &per2_clk);
 599 DEFINE_CLOCK(cspi2_clk,    1, NULL,   0, NULL, &cspi2_clk1, &per2_clk);
 600 DEFINE_CLOCK(cspi3_clk,    2, NULL,   0, NULL, &cspi13_clk1, &per2_clk);
 601 DEFINE_CLOCK(sdhc1_clk,    0, NULL,   0, NULL, &sdhc1_clk1, &per2_clk);
 602 DEFINE_CLOCK(sdhc2_clk,    1, NULL,   0, NULL, &sdhc2_clk1, &per2_clk);
 603 DEFINE_CLOCK(sdhc3_clk,    2, NULL,   0, NULL, &sdhc3_clk1, &per2_clk);
 604 DEFINE_CLOCK(pwm_clk,      0, NULL,   0, NULL, &pwm_clk1, &per1_clk);
 605 DEFINE_CLOCK(gpt1_clk,     0, NULL,   0, NULL, &gpt1_clk1, &per1_clk);
 606 DEFINE_CLOCK(gpt2_clk,     1, NULL,   0, NULL, &gpt2_clk1, &per1_clk);
 607 DEFINE_CLOCK(gpt3_clk,     2, NULL,   0, NULL, &gpt3_clk1, &per1_clk);
 608 DEFINE_CLOCK(gpt4_clk,     3, NULL,   0, NULL, &gpt4_clk1, &per1_clk);
 609 DEFINE_CLOCK(gpt5_clk,     4, NULL,   0, NULL, &gpt5_clk1, &per1_clk);
 610 DEFINE_CLOCK(gpt6_clk,     5, NULL,   0, NULL, &gpt6_clk1, &per1_clk);
 611 DEFINE_CLOCK(uart1_clk,    0, NULL,   0, NULL, &uart1_clk1, &per1_clk);
 612 DEFINE_CLOCK(uart2_clk,    1, NULL,   0, NULL, &uart2_clk1, &per1_clk);
 613 DEFINE_CLOCK(uart3_clk,    2, NULL,   0, NULL, &uart3_clk1, &per1_clk);
 614 DEFINE_CLOCK(uart4_clk,    3, NULL,   0, NULL, &uart4_clk1, &per1_clk);
 615 DEFINE_CLOCK(uart5_clk,    4, NULL,   0, NULL, &uart5_clk1, &per1_clk);
 616 DEFINE_CLOCK(uart6_clk,    5, NULL,   0, NULL, &uart6_clk1, &per1_clk);
 617 DEFINE_CLOCK1(lcdc_clk,    0, NULL,   0, parent, &lcdc_clk1, &per3_clk);
 618 DEFINE_CLOCK1(csi_clk,     0, NULL,   0, parent, &csi_clk1, &per4_clk);
 619
 620 #define _REGISTER_CLOCK(d, n, c) \
 621         { \
 622                 .dev_id = d, \
 623                 .con_id = n, \
 624                 .clk = &c, \
 625         },
 626
 627 static struct clk_lookup lookups[] = {
 628         /* i.mx27 has the i.mx21 type uart */
 629         _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
 630         _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
 631         _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
 632         _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
 633         _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
 634         _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
 635         _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
 636         _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
 637         _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
 638         _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
 639         _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
 640         _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
 641         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
 642         _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
 643         _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
 644         _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
 645         _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
 646         _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
 647         _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
 648         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
 649         _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
 650         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
 651         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
 652         _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
 653         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
 654         _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
 655         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
 656         _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
 657         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
 658         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
 659         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
 660         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 661         _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
 662         _REGISTER_CLOCK(NULL, "dma", dma_clk)
 663         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
 664         _REGISTER_CLOCK(NULL, "brom", brom_clk)
 665         _REGISTER_CLOCK(NULL, "emma", emma_clk)
 666         _REGISTER_CLOCK("m2m-emmaprp.0", NULL, emma_clk)
 667         _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
 668         _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
 669         _REGISTER_CLOCK(NULL, "emi", emi_clk)
 670         _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
 671         _REGISTER_CLOCK("pata_imx", NULL, pata_clk)
 672         _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
 673         _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
 674         _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
 675         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
 676         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
 677         _REGISTER_CLOCK(NULL, "iim", iim_clk)
 678         _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
 679         _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
 680         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
 681         _REGISTER_CLOCK(NULL, "scc", scc_clk)
 682 };
 683
 684 /* Adjust the clock path for TO2 and later */
 685 static void __init to2_adjust_clocks(void)
 686 {
 687         unsigned long cscr = __raw_readl(CCM_CSCR);
 688
 689         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
 690                 if (cscr & CCM_CSCR_ARM_SRC)
 691                         cpu_clk.parent = &mpll_main1_clk;
 692
 693                 if (!(cscr & CCM_CSCR_SSI2))
 694                         ssi1_clk.parent = &spll_clk;
 695
 696                 if (!(cscr & CCM_CSCR_SSI1))
 697                         ssi1_clk.parent = &spll_clk;
 698
 699                 if (!(cscr & CCM_CSCR_VPU))
 700                         vpu_clk.parent = &spll_clk;
 701         } else {
 702                 cpu_clk.parent = &mpll_clk;
 703                 cpu_clk.set_parent = NULL;
 704                 cpu_clk.round_rate = NULL;
 705                 cpu_clk.set_rate = NULL;
 706                 ahb_clk.parent = &mpll_clk;
 707
 708                 per1_clk.parent = &mpll_clk;
 709                 per2_clk.parent = &mpll_clk;
 710                 per3_clk.parent = &mpll_clk;
 711                 per4_clk.parent = &mpll_clk;
 712
 713                 ssi1_clk.parent = &mpll_clk;
 714                 ssi2_clk.parent = &mpll_clk;
 715
 716                 vpu_clk.parent = &mpll_clk;
 717         }
 718 }
 719
 720 /*
 721  * must be called very early to get information about the
 722  * available clock rate when the timer framework starts
 723  */
 724 int __init mx27_clocks_init(unsigned long fref)
 725 {
 726         u32 cscr = __raw_readl(CCM_CSCR);
 727
 728         external_high_reference = fref;
 729
 730         /* detect clock reference for both system PLLs */
 731         if (cscr & CCM_CSCR_MCU)
 732                 mpll_clk.parent = &ckih_clk;
 733         else
 734                 mpll_clk.parent = &fpm_clk;
 735
 736         if (cscr & CCM_CSCR_SP)
 737                 spll_clk.parent = &ckih_clk;
 738         else
 739                 spll_clk.parent = &fpm_clk;
 740
 741         to2_adjust_clocks();
 742
 743         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 744
 745         /* Turn off all clocks we do not need */
 746         __raw_writel(0, CCM_PCCR0);
 747         __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
 748
 749         spll_clk.disable(&spll_clk);
 750
 751         /* enable basic clocks */
 752         clk_enable(&per1_clk);
 753         clk_enable(&gpio_clk);
 754         clk_enable(&emi_clk);
 755         clk_enable(&iim_clk);
 756         imx_print_silicon_rev("i.MX27", mx27_revision());
 757         clk_disable(&iim_clk);
 758
 759 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
 760         clk_enable(&uart1_clk);
 761 #endif
 762
 763         mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
 764                         MX27_INT_GPT1);
 765
 766         return 0;
 767 }
 768
 769 #ifdef CONFIG_OF
 770 int __init mx27_clocks_init_dt(void)
 771 {
 772         struct device_node *np;
 773         u32 fref = 26000000; /* default */
 774
 775         for_each_compatible_node(np, NULL, "fixed-clock") {
 776                 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
 777                         continue;
 778
 779                 if (!of_property_read_u32(np, "clock-frequency", &fref))
 780                         break;
 781         }
 782
 783         return mx27_clocks_init(fref);
 784 }
 785 #endif