drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/init.h>
  74 #include <linux/delay.h>
  75 #include <linux/netdevice.h>
  76 #include <linux/etherdevice.h>
  77 #include <linux/skbuff.h>
  78 #include <linux/if_vlan.h>
  79 #include <linux/spinlock.h>
  80 #include <linux/mm.h>
  81 #include <linux/of_mdio.h>
  82 #include <linux/of_platform.h>
  83 #include <linux/ip.h>
  84 #include <linux/tcp.h>
  85 #include <linux/udp.h>
  86 #include <linux/in.h>
  87 #include <linux/net_tstamp.h>
  88
  89 #include <asm/io.h>
  90 #include <asm/reg.h>
  91 #include <asm/irq.h>
  92 #include <asm/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (1*HZ)
 105
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                            struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct platform_device *ofdev);
 125 static int gfar_remove(struct platform_device *ofdev);
 126 static void free_skb_resources(struct gfar_private *priv);
 127 static void gfar_set_multi(struct net_device *dev);
 128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 129 static void gfar_configure_serdes(struct net_device *dev);
 130 static int gfar_poll(struct napi_struct *napi, int budget);
 131 #ifdef CONFIG_NET_POLL_CONTROLLER
 132 static void gfar_netpoll(struct net_device *dev);
 133 #endif
 134 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 135 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 136 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 137                               int amount_pull, struct napi_struct *napi);
 138 void gfar_halt(struct net_device *dev);
 139 static void gfar_halt_nodisable(struct net_device *dev);
 140 void gfar_start(struct net_device *dev);
 141 static void gfar_clear_exact_match(struct net_device *dev);
 142 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 143                                   const u8 *addr);
 144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 145
 146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 148 MODULE_LICENSE("GPL");
 149
 150 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 151                             dma_addr_t buf)
 152 {
 153         u32 lstatus;
 154
 155         bdp->bufPtr = buf;
 156
 157         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 158         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 159                 lstatus |= BD_LFLAG(RXBD_WRAP);
 160
 161         eieio();
 162
 163         bdp->lstatus = lstatus;
 164 }
 165
 166 static int gfar_init_bds(struct net_device *ndev)
 167 {
 168         struct gfar_private *priv = netdev_priv(ndev);
 169         struct gfar_priv_tx_q *tx_queue = NULL;
 170         struct gfar_priv_rx_q *rx_queue = NULL;
 171         struct txbd8 *txbdp;
 172         struct rxbd8 *rxbdp;
 173         int i, j;
 174
 175         for (i = 0; i < priv->num_tx_queues; i++) {
 176                 tx_queue = priv->tx_queue[i];
 177                 /* Initialize some variables in our dev structure */
 178                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 179                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 180                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 181                 tx_queue->skb_curtx = 0;
 182                 tx_queue->skb_dirtytx = 0;
 183
 184                 /* Initialize Transmit Descriptor Ring */
 185                 txbdp = tx_queue->tx_bd_base;
 186                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 187                         txbdp->lstatus = 0;
 188                         txbdp->bufPtr = 0;
 189                         txbdp++;
 190                 }
 191
 192                 /* Set the last descriptor in the ring to indicate wrap */
 193                 txbdp--;
 194                 txbdp->status |= TXBD_WRAP;
 195         }
 196
 197         for (i = 0; i < priv->num_rx_queues; i++) {
 198                 rx_queue = priv->rx_queue[i];
 199                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 200                 rx_queue->skb_currx = 0;
 201                 rxbdp = rx_queue->rx_bd_base;
 202
 203                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 204                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 205
 206                         if (skb) {
 207                                 gfar_init_rxbdp(rx_queue, rxbdp,
 208                                                 rxbdp->bufPtr);
 209                         } else {
 210                                 skb = gfar_new_skb(ndev);
 211                                 if (!skb) {
 212                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 213                                         goto err_rxalloc_fail;
 214                                 }
 215                                 rx_queue->rx_skbuff[j] = skb;
 216
 217                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 218                         }
 219
 220                         rxbdp++;
 221                 }
 222
 223         }
 224
 225         return 0;
 226
 227 err_rxalloc_fail:
 228         free_skb_resources(priv);
 229         return -ENOMEM;
 230 }
 231
 232 static int gfar_alloc_skb_resources(struct net_device *ndev)
 233 {
 234         void *vaddr;
 235         dma_addr_t addr;
 236         int i, j, k;
 237         struct gfar_private *priv = netdev_priv(ndev);
 238         struct device *dev = &priv->ofdev->dev;
 239         struct gfar_priv_tx_q *tx_queue = NULL;
 240         struct gfar_priv_rx_q *rx_queue = NULL;
 241
 242         priv->total_tx_ring_size = 0;
 243         for (i = 0; i < priv->num_tx_queues; i++)
 244                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 245
 246         priv->total_rx_ring_size = 0;
 247         for (i = 0; i < priv->num_rx_queues; i++)
 248                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 249
 250         /* Allocate memory for the buffer descriptors */
 251         vaddr = dma_alloc_coherent(dev,
 252                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 253                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 254                         &addr, GFP_KERNEL);
 255         if (!vaddr) {
 256                 netif_err(priv, ifup, ndev,
 257                           "Could not allocate buffer descriptors!\n");
 258                 return -ENOMEM;
 259         }
 260
 261         for (i = 0; i < priv->num_tx_queues; i++) {
 262                 tx_queue = priv->tx_queue[i];
 263                 tx_queue->tx_bd_base = vaddr;
 264                 tx_queue->tx_bd_dma_base = addr;
 265                 tx_queue->dev = ndev;
 266                 /* enet DMA only understands physical addresses */
 267                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 268                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 269         }
 270
 271         /* Start the rx descriptor ring where the tx ring leaves off */
 272         for (i = 0; i < priv->num_rx_queues; i++) {
 273                 rx_queue = priv->rx_queue[i];
 274                 rx_queue->rx_bd_base = vaddr;
 275                 rx_queue->rx_bd_dma_base = addr;
 276                 rx_queue->dev = ndev;
 277                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 278                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 279         }
 280
 281         /* Setup the skbuff rings */
 282         for (i = 0; i < priv->num_tx_queues; i++) {
 283                 tx_queue = priv->tx_queue[i];
 284                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 285                                               tx_queue->tx_ring_size,
 286                                               GFP_KERNEL);
 287                 if (!tx_queue->tx_skbuff) {
 288                         netif_err(priv, ifup, ndev,
 289                                   "Could not allocate tx_skbuff\n");
 290                         goto cleanup;
 291                 }
 292
 293                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 294                         tx_queue->tx_skbuff[k] = NULL;
 295         }
 296
 297         for (i = 0; i < priv->num_rx_queues; i++) {
 298                 rx_queue = priv->rx_queue[i];
 299                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 300                                               rx_queue->rx_ring_size,
 301                                               GFP_KERNEL);
 302
 303                 if (!rx_queue->rx_skbuff) {
 304                         netif_err(priv, ifup, ndev,
 305                                   "Could not allocate rx_skbuff\n");
 306                         goto cleanup;
 307                 }
 308
 309                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 310                         rx_queue->rx_skbuff[j] = NULL;
 311         }
 312
 313         if (gfar_init_bds(ndev))
 314                 goto cleanup;
 315
 316         return 0;
 317
 318 cleanup:
 319         free_skb_resources(priv);
 320         return -ENOMEM;
 321 }
 322
 323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 324 {
 325         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 326         u32 __iomem *baddr;
 327         int i;
 328
 329         baddr = &regs->tbase0;
 330         for (i = 0; i < priv->num_tx_queues; i++) {
 331                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 332                 baddr += 2;
 333         }
 334
 335         baddr = &regs->rbase0;
 336         for (i = 0; i < priv->num_rx_queues; i++) {
 337                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 338                 baddr += 2;
 339         }
 340 }
 341
 342 static void gfar_init_mac(struct net_device *ndev)
 343 {
 344         struct gfar_private *priv = netdev_priv(ndev);
 345         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 346         u32 rctrl = 0;
 347         u32 tctrl = 0;
 348         u32 attrs = 0;
 349
 350         /* write the tx/rx base registers */
 351         gfar_init_tx_rx_base(priv);
 352
 353         /* Configure the coalescing support */
 354         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 355
 356         if (priv->rx_filer_enable) {
 357                 rctrl |= RCTRL_FILREN;
 358                 /* Program the RIR0 reg with the required distribution */
 359                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 360         }
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         if (priv->prio_sched_en)
 398                 tctrl |= TCTRL_TXSCHED_PRIO;
 399         else {
 400                 tctrl |= TCTRL_TXSCHED_WRRS;
 401                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 402                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 403         }
 404
 405         gfar_write(&regs->tctrl, tctrl);
 406
 407         /* Set the extraction length and index */
 408         attrs = ATTRELI_EL(priv->rx_stash_size) |
 409                 ATTRELI_EI(priv->rx_stash_index);
 410
 411         gfar_write(&regs->attreli, attrs);
 412
 413         /* Start with defaults, and add stashing or locking
 414          * depending on the approprate variables
 415          */
 416         attrs = ATTR_INIT_SETTINGS;
 417
 418         if (priv->bd_stash_en)
 419                 attrs |= ATTR_BDSTASH;
 420
 421         if (priv->rx_stash_size != 0)
 422                 attrs |= ATTR_BUFSTASH;
 423
 424         gfar_write(&regs->attr, attrs);
 425
 426         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 427         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 428         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 429 }
 430
 431 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 432 {
 433         struct gfar_private *priv = netdev_priv(dev);
 434         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 435         unsigned long tx_packets = 0, tx_bytes = 0;
 436         int i;
 437
 438         for (i = 0; i < priv->num_rx_queues; i++) {
 439                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 440                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 441                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 442         }
 443
 444         dev->stats.rx_packets = rx_packets;
 445         dev->stats.rx_bytes   = rx_bytes;
 446         dev->stats.rx_dropped = rx_dropped;
 447
 448         for (i = 0; i < priv->num_tx_queues; i++) {
 449                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 450                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 451         }
 452
 453         dev->stats.tx_bytes   = tx_bytes;
 454         dev->stats.tx_packets = tx_packets;
 455
 456         return &dev->stats;
 457 }
 458
 459 static const struct net_device_ops gfar_netdev_ops = {
 460         .ndo_open = gfar_enet_open,
 461         .ndo_start_xmit = gfar_start_xmit,
 462         .ndo_stop = gfar_close,
 463         .ndo_change_mtu = gfar_change_mtu,
 464         .ndo_set_features = gfar_set_features,
 465         .ndo_set_rx_mode = gfar_set_multi,
 466         .ndo_tx_timeout = gfar_timeout,
 467         .ndo_do_ioctl = gfar_ioctl,
 468         .ndo_get_stats = gfar_get_stats,
 469         .ndo_set_mac_address = eth_mac_addr,
 470         .ndo_validate_addr = eth_validate_addr,
 471 #ifdef CONFIG_NET_POLL_CONTROLLER
 472         .ndo_poll_controller = gfar_netpoll,
 473 #endif
 474 };
 475
 476 void lock_rx_qs(struct gfar_private *priv)
 477 {
 478         int i;
 479
 480         for (i = 0; i < priv->num_rx_queues; i++)
 481                 spin_lock(&priv->rx_queue[i]->rxlock);
 482 }
 483
 484 void lock_tx_qs(struct gfar_private *priv)
 485 {
 486         int i;
 487
 488         for (i = 0; i < priv->num_tx_queues; i++)
 489                 spin_lock(&priv->tx_queue[i]->txlock);
 490 }
 491
 492 void unlock_rx_qs(struct gfar_private *priv)
 493 {
 494         int i;
 495
 496         for (i = 0; i < priv->num_rx_queues; i++)
 497                 spin_unlock(&priv->rx_queue[i]->rxlock);
 498 }
 499
 500 void unlock_tx_qs(struct gfar_private *priv)
 501 {
 502         int i;
 503
 504         for (i = 0; i < priv->num_tx_queues; i++)
 505                 spin_unlock(&priv->tx_queue[i]->txlock);
 506 }
 507
 508 static bool gfar_is_vlan_on(struct gfar_private *priv)
 509 {
 510         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 511                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 512 }
 513
 514 /* Returns 1 if incoming frames use an FCB */
 515 static inline int gfar_uses_fcb(struct gfar_private *priv)
 516 {
 517         return gfar_is_vlan_on(priv) ||
 518                (priv->ndev->features & NETIF_F_RXCSUM) ||
 519                (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 520 }
 521
 522 static void free_tx_pointers(struct gfar_private *priv)
 523 {
 524         int i;
 525
 526         for (i = 0; i < priv->num_tx_queues; i++)
 527                 kfree(priv->tx_queue[i]);
 528 }
 529
 530 static void free_rx_pointers(struct gfar_private *priv)
 531 {
 532         int i;
 533
 534         for (i = 0; i < priv->num_rx_queues; i++)
 535                 kfree(priv->rx_queue[i]);
 536 }
 537
 538 static void unmap_group_regs(struct gfar_private *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < MAXGROUPS; i++)
 543                 if (priv->gfargrp[i].regs)
 544                         iounmap(priv->gfargrp[i].regs);
 545 }
 546
 547 static void disable_napi(struct gfar_private *priv)
 548 {
 549         int i;
 550
 551         for (i = 0; i < priv->num_grps; i++)
 552                 napi_disable(&priv->gfargrp[i].napi);
 553 }
 554
 555 static void enable_napi(struct gfar_private *priv)
 556 {
 557         int i;
 558
 559         for (i = 0; i < priv->num_grps; i++)
 560                 napi_enable(&priv->gfargrp[i].napi);
 561 }
 562
 563 static int gfar_parse_group(struct device_node *np,
 564                             struct gfar_private *priv, const char *model)
 565 {
 566         u32 *queue_mask;
 567
 568         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 569         if (!priv->gfargrp[priv->num_grps].regs)
 570                 return -ENOMEM;
 571
 572         priv->gfargrp[priv->num_grps].interruptTransmit =
 573                         irq_of_parse_and_map(np, 0);
 574
 575         /* If we aren't the FEC we have multiple interrupts */
 576         if (model && strcasecmp(model, "FEC")) {
 577                 priv->gfargrp[priv->num_grps].interruptReceive =
 578                         irq_of_parse_and_map(np, 1);
 579                 priv->gfargrp[priv->num_grps].interruptError =
 580                         irq_of_parse_and_map(np,2);
 581                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 582                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 583                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 584                         return -EINVAL;
 585         }
 586
 587         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 588         priv->gfargrp[priv->num_grps].priv = priv;
 589         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 590         if (priv->mode == MQ_MG_MODE) {
 591                 queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL);
 592                 priv->gfargrp[priv->num_grps].rx_bit_map = queue_mask ?
 593                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 594                 queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL);
 595                 priv->gfargrp[priv->num_grps].tx_bit_map = queue_mask ?
 596                         *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 597         } else {
 598                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 599                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 600         }
 601         priv->num_grps++;
 602
 603         return 0;
 604 }
 605
 606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 607 {
 608         const char *model;
 609         const char *ctype;
 610         const void *mac_addr;
 611         int err = 0, i;
 612         struct net_device *dev = NULL;
 613         struct gfar_private *priv = NULL;
 614         struct device_node *np = ofdev->dev.of_node;
 615         struct device_node *child = NULL;
 616         const u32 *stash;
 617         const u32 *stash_len;
 618         const u32 *stash_idx;
 619         unsigned int num_tx_qs, num_rx_qs;
 620         u32 *tx_queues, *rx_queues;
 621
 622         if (!np || !of_device_is_available(np))
 623                 return -ENODEV;
 624
 625         /* parse the num of tx and rx queues */
 626         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 627         num_tx_qs = tx_queues ? *tx_queues : 1;
 628
 629         if (num_tx_qs > MAX_TX_QS) {
 630                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 631                        num_tx_qs, MAX_TX_QS);
 632                 pr_err("Cannot do alloc_etherdev, aborting\n");
 633                 return -EINVAL;
 634         }
 635
 636         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 637         num_rx_qs = rx_queues ? *rx_queues : 1;
 638
 639         if (num_rx_qs > MAX_RX_QS) {
 640                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 641                        num_rx_qs, MAX_RX_QS);
 642                 pr_err("Cannot do alloc_etherdev, aborting\n");
 643                 return -EINVAL;
 644         }
 645
 646         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 647         dev = *pdev;
 648         if (NULL == dev)
 649                 return -ENOMEM;
 650
 651         priv = netdev_priv(dev);
 652         priv->node = ofdev->dev.of_node;
 653         priv->ndev = dev;
 654
 655         priv->num_tx_queues = num_tx_qs;
 656         netif_set_real_num_rx_queues(dev, num_rx_qs);
 657         priv->num_rx_queues = num_rx_qs;
 658         priv->num_grps = 0x0;
 659
 660         /* Init Rx queue filer rule set linked list */
 661         INIT_LIST_HEAD(&priv->rx_list.list);
 662         priv->rx_list.count = 0;
 663         mutex_init(&priv->rx_queue_access);
 664
 665         model = of_get_property(np, "model", NULL);
 666
 667         for (i = 0; i < MAXGROUPS; i++)
 668                 priv->gfargrp[i].regs = NULL;
 669
 670         /* Parse and initialize group specific information */
 671         if (of_device_is_compatible(np, "fsl,etsec2")) {
 672                 priv->mode = MQ_MG_MODE;
 673                 for_each_child_of_node(np, child) {
 674                         err = gfar_parse_group(child, priv, model);
 675                         if (err)
 676                                 goto err_grp_init;
 677                 }
 678         } else {
 679                 priv->mode = SQ_SG_MODE;
 680                 err = gfar_parse_group(np, priv, model);
 681                 if (err)
 682                         goto err_grp_init;
 683         }
 684
 685         for (i = 0; i < priv->num_tx_queues; i++)
 686                priv->tx_queue[i] = NULL;
 687         for (i = 0; i < priv->num_rx_queues; i++)
 688                 priv->rx_queue[i] = NULL;
 689
 690         for (i = 0; i < priv->num_tx_queues; i++) {
 691                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 692                                             GFP_KERNEL);
 693                 if (!priv->tx_queue[i]) {
 694                         err = -ENOMEM;
 695                         goto tx_alloc_failed;
 696                 }
 697                 priv->tx_queue[i]->tx_skbuff = NULL;
 698                 priv->tx_queue[i]->qindex = i;
 699                 priv->tx_queue[i]->dev = dev;
 700                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 701         }
 702
 703         for (i = 0; i < priv->num_rx_queues; i++) {
 704                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 705                                             GFP_KERNEL);
 706                 if (!priv->rx_queue[i]) {
 707                         err = -ENOMEM;
 708                         goto rx_alloc_failed;
 709                 }
 710                 priv->rx_queue[i]->rx_skbuff = NULL;
 711                 priv->rx_queue[i]->qindex = i;
 712                 priv->rx_queue[i]->dev = dev;
 713                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 714         }
 715
 716
 717         stash = of_get_property(np, "bd-stash", NULL);
 718
 719         if (stash) {
 720                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 721                 priv->bd_stash_en = 1;
 722         }
 723
 724         stash_len = of_get_property(np, "rx-stash-len", NULL);
 725
 726         if (stash_len)
 727                 priv->rx_stash_size = *stash_len;
 728
 729         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 730
 731         if (stash_idx)
 732                 priv->rx_stash_index = *stash_idx;
 733
 734         if (stash_len || stash_idx)
 735                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 736
 737         mac_addr = of_get_mac_address(np);
 738
 739         if (mac_addr)
 740                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 741
 742         if (model && !strcasecmp(model, "TSEC"))
 743                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 744                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 745                                      FSL_GIANFAR_DEV_HAS_RMON |
 746                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 747
 748         if (model && !strcasecmp(model, "eTSEC"))
 749                 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
 750                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 751                                      FSL_GIANFAR_DEV_HAS_RMON |
 752                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 753                                      FSL_GIANFAR_DEV_HAS_PADDING |
 754                                      FSL_GIANFAR_DEV_HAS_CSUM |
 755                                      FSL_GIANFAR_DEV_HAS_VLAN |
 756                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 757                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 758                                      FSL_GIANFAR_DEV_HAS_TIMER;
 759
 760         ctype = of_get_property(np, "phy-connection-type", NULL);
 761
 762         /* We only care about rgmii-id.  The rest are autodetected */
 763         if (ctype && !strcmp(ctype, "rgmii-id"))
 764                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 765         else
 766                 priv->interface = PHY_INTERFACE_MODE_MII;
 767
 768         if (of_get_property(np, "fsl,magic-packet", NULL))
 769                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 770
 771         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 772
 773         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 774         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 775
 776         return 0;
 777
 778 rx_alloc_failed:
 779         free_rx_pointers(priv);
 780 tx_alloc_failed:
 781         free_tx_pointers(priv);
 782 err_grp_init:
 783         unmap_group_regs(priv);
 784         free_netdev(dev);
 785         return err;
 786 }
 787
 788 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 789                                struct ifreq *ifr, int cmd)
 790 {
 791         struct hwtstamp_config config;
 792         struct gfar_private *priv = netdev_priv(netdev);
 793
 794         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 795                 return -EFAULT;
 796
 797         /* reserved for future extensions */
 798         if (config.flags)
 799                 return -EINVAL;
 800
 801         switch (config.tx_type) {
 802         case HWTSTAMP_TX_OFF:
 803                 priv->hwts_tx_en = 0;
 804                 break;
 805         case HWTSTAMP_TX_ON:
 806                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 807                         return -ERANGE;
 808                 priv->hwts_tx_en = 1;
 809                 break;
 810         default:
 811                 return -ERANGE;
 812         }
 813
 814         switch (config.rx_filter) {
 815         case HWTSTAMP_FILTER_NONE:
 816                 if (priv->hwts_rx_en) {
 817                         stop_gfar(netdev);
 818                         priv->hwts_rx_en = 0;
 819                         startup_gfar(netdev);
 820                 }
 821                 break;
 822         default:
 823                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 824                         return -ERANGE;
 825                 if (!priv->hwts_rx_en) {
 826                         stop_gfar(netdev);
 827                         priv->hwts_rx_en = 1;
 828                         startup_gfar(netdev);
 829                 }
 830                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 831                 break;
 832         }
 833
 834         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 835                 -EFAULT : 0;
 836 }
 837
 838 /* Ioctl MII Interface */
 839 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 840 {
 841         struct gfar_private *priv = netdev_priv(dev);
 842
 843         if (!netif_running(dev))
 844                 return -EINVAL;
 845
 846         if (cmd == SIOCSHWTSTAMP)
 847                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 848
 849         if (!priv->phydev)
 850                 return -ENODEV;
 851
 852         return phy_mii_ioctl(priv->phydev, rq, cmd);
 853 }
 854
 855 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 856 {
 857         unsigned int new_bit_map = 0x0;
 858         int mask = 0x1 << (max_qs - 1), i;
 859
 860         for (i = 0; i < max_qs; i++) {
 861                 if (bit_map & mask)
 862                         new_bit_map = new_bit_map + (1 << i);
 863                 mask = mask >> 0x1;
 864         }
 865         return new_bit_map;
 866 }
 867
 868 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 869                                    u32 class)
 870 {
 871         u32 rqfpr = FPR_FILER_MASK;
 872         u32 rqfcr = 0x0;
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 876         priv->ftp_rqfpr[rqfar] = rqfpr;
 877         priv->ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_NOMATCH;
 882         priv->ftp_rqfpr[rqfar] = rqfpr;
 883         priv->ftp_rqfcr[rqfar] = rqfcr;
 884         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 885
 886         rqfar--;
 887         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 888         rqfpr = class;
 889         priv->ftp_rqfcr[rqfar] = rqfcr;
 890         priv->ftp_rqfpr[rqfar] = rqfpr;
 891         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 892
 893         rqfar--;
 894         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 895         rqfpr = class;
 896         priv->ftp_rqfcr[rqfar] = rqfcr;
 897         priv->ftp_rqfpr[rqfar] = rqfpr;
 898         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 899
 900         return rqfar;
 901 }
 902
 903 static void gfar_init_filer_table(struct gfar_private *priv)
 904 {
 905         int i = 0x0;
 906         u32 rqfar = MAX_FILER_IDX;
 907         u32 rqfcr = 0x0;
 908         u32 rqfpr = FPR_FILER_MASK;
 909
 910         /* Default rule */
 911         rqfcr = RQFCR_CMP_MATCH;
 912         priv->ftp_rqfcr[rqfar] = rqfcr;
 913         priv->ftp_rqfpr[rqfar] = rqfpr;
 914         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 915
 916         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 917         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 918         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 919         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 920         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 921         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 922
 923         /* cur_filer_idx indicated the first non-masked rule */
 924         priv->cur_filer_idx = rqfar;
 925
 926         /* Rest are masked rules */
 927         rqfcr = RQFCR_CMP_NOMATCH;
 928         for (i = 0; i < rqfar; i++) {
 929                 priv->ftp_rqfcr[i] = rqfcr;
 930                 priv->ftp_rqfpr[i] = rqfpr;
 931                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 932         }
 933 }
 934
 935 static void gfar_detect_errata(struct gfar_private *priv)
 936 {
 937         struct device *dev = &priv->ofdev->dev;
 938         unsigned int pvr = mfspr(SPRN_PVR);
 939         unsigned int svr = mfspr(SPRN_SVR);
 940         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 941         unsigned int rev = svr & 0xffff;
 942
 943         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 944         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 945             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 946                 priv->errata |= GFAR_ERRATA_74;
 947
 948         /* MPC8313 and MPC837x all rev */
 949         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 950             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 951                 priv->errata |= GFAR_ERRATA_76;
 952
 953         /* MPC8313 and MPC837x all rev */
 954         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 955             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 956                 priv->errata |= GFAR_ERRATA_A002;
 957
 958         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 959         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 960             (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 961                 priv->errata |= GFAR_ERRATA_12;
 962
 963         if (priv->errata)
 964                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 965                          priv->errata);
 966 }
 967
 968 /* Set up the ethernet device structure, private data,
 969  * and anything else we need before we start
 970  */
 971 static int gfar_probe(struct platform_device *ofdev)
 972 {
 973         u32 tempval;
 974         struct net_device *dev = NULL;
 975         struct gfar_private *priv = NULL;
 976         struct gfar __iomem *regs = NULL;
 977         int err = 0, i, grp_idx = 0;
 978         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 979         u32 isrg = 0;
 980         u32 __iomem *baddr;
 981
 982         err = gfar_of_init(ofdev, &dev);
 983
 984         if (err)
 985                 return err;
 986
 987         priv = netdev_priv(dev);
 988         priv->ndev = dev;
 989         priv->ofdev = ofdev;
 990         priv->node = ofdev->dev.of_node;
 991         SET_NETDEV_DEV(dev, &ofdev->dev);
 992
 993         spin_lock_init(&priv->bflock);
 994         INIT_WORK(&priv->reset_task, gfar_reset_task);
 995
 996         dev_set_drvdata(&ofdev->dev, priv);
 997         regs = priv->gfargrp[0].regs;
 998
 999         gfar_detect_errata(priv);
1000
1001         /* Stop the DMA engine now, in case it was running before
1002          * (The firmware could have used it, and left it running).
1003          */
1004         gfar_halt(dev);
1005
1006         /* Reset MAC layer */
1007         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1008
1009         /* We need to delay at least 3 TX clocks */
1010         udelay(2);
1011
1012         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1013         gfar_write(&regs->maccfg1, tempval);
1014
1015         /* Initialize MACCFG2. */
1016         tempval = MACCFG2_INIT_SETTINGS;
1017         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1018                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1019         gfar_write(&regs->maccfg2, tempval);
1020
1021         /* Initialize ECNTRL */
1022         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1023
1024         /* Set the dev->base_addr to the gfar reg region */
1025         dev->base_addr = (unsigned long) regs;
1026
1027         SET_NETDEV_DEV(dev, &ofdev->dev);
1028
1029         /* Fill in the dev structure */
1030         dev->watchdog_timeo = TX_TIMEOUT;
1031         dev->mtu = 1500;
1032         dev->netdev_ops = &gfar_netdev_ops;
1033         dev->ethtool_ops = &gfar_ethtool_ops;
1034
1035         /* Register for napi ...We are registering NAPI for each grp */
1036         for (i = 0; i < priv->num_grps; i++)
1037                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1038                                GFAR_DEV_WEIGHT);
1039
1040         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1041                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1042                                    NETIF_F_RXCSUM;
1043                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1044                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1045         }
1046
1047         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1048                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1049                 dev->features |= NETIF_F_HW_VLAN_RX;
1050         }
1051
1052         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1053                 priv->extended_hash = 1;
1054                 priv->hash_width = 9;
1055
1056                 priv->hash_regs[0] = &regs->igaddr0;
1057                 priv->hash_regs[1] = &regs->igaddr1;
1058                 priv->hash_regs[2] = &regs->igaddr2;
1059                 priv->hash_regs[3] = &regs->igaddr3;
1060                 priv->hash_regs[4] = &regs->igaddr4;
1061                 priv->hash_regs[5] = &regs->igaddr5;
1062                 priv->hash_regs[6] = &regs->igaddr6;
1063                 priv->hash_regs[7] = &regs->igaddr7;
1064                 priv->hash_regs[8] = &regs->gaddr0;
1065                 priv->hash_regs[9] = &regs->gaddr1;
1066                 priv->hash_regs[10] = &regs->gaddr2;
1067                 priv->hash_regs[11] = &regs->gaddr3;
1068                 priv->hash_regs[12] = &regs->gaddr4;
1069                 priv->hash_regs[13] = &regs->gaddr5;
1070                 priv->hash_regs[14] = &regs->gaddr6;
1071                 priv->hash_regs[15] = &regs->gaddr7;
1072
1073         } else {
1074                 priv->extended_hash = 0;
1075                 priv->hash_width = 8;
1076
1077                 priv->hash_regs[0] = &regs->gaddr0;
1078                 priv->hash_regs[1] = &regs->gaddr1;
1079                 priv->hash_regs[2] = &regs->gaddr2;
1080                 priv->hash_regs[3] = &regs->gaddr3;
1081                 priv->hash_regs[4] = &regs->gaddr4;
1082                 priv->hash_regs[5] = &regs->gaddr5;
1083                 priv->hash_regs[6] = &regs->gaddr6;
1084                 priv->hash_regs[7] = &regs->gaddr7;
1085         }
1086
1087         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1088                 priv->padding = DEFAULT_PADDING;
1089         else
1090                 priv->padding = 0;
1091
1092         if (dev->features & NETIF_F_IP_CSUM ||
1093             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1094                 dev->needed_headroom = GMAC_FCB_LEN;
1095
1096         /* Program the isrg regs only if number of grps > 1 */
1097         if (priv->num_grps > 1) {
1098                 baddr = &regs->isrg0;
1099                 for (i = 0; i < priv->num_grps; i++) {
1100                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1101                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1102                         gfar_write(baddr, isrg);
1103                         baddr++;
1104                         isrg = 0x0;
1105                 }
1106         }
1107
1108         /* Need to reverse the bit maps as  bit_map's MSB is q0
1109          * but, for_each_set_bit parses from right to left, which
1110          * basically reverses the queue numbers
1111          */
1112         for (i = 0; i< priv->num_grps; i++) {
1113                 priv->gfargrp[i].tx_bit_map =
1114                         reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1115                 priv->gfargrp[i].rx_bit_map =
1116                         reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1117         }
1118
1119         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1120          * also assign queues to groups
1121          */
1122         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1123                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1124
1125                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1126                                  priv->num_rx_queues) {
1127                         priv->gfargrp[grp_idx].num_rx_queues++;
1128                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1129                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1130                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1131                 }
1132                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1133
1134                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1135                                  priv->num_tx_queues) {
1136                         priv->gfargrp[grp_idx].num_tx_queues++;
1137                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1138                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1139                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1140                 }
1141                 priv->gfargrp[grp_idx].rstat = rstat;
1142                 priv->gfargrp[grp_idx].tstat = tstat;
1143                 rstat = tstat =0;
1144         }
1145
1146         gfar_write(&regs->rqueue, rqueue);
1147         gfar_write(&regs->tqueue, tqueue);
1148
1149         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1150
1151         /* Initializing some of the rx/tx queue level parameters */
1152         for (i = 0; i < priv->num_tx_queues; i++) {
1153                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1154                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1155                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1156                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1157         }
1158
1159         for (i = 0; i < priv->num_rx_queues; i++) {
1160                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1161                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1162                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1163         }
1164
1165         /* always enable rx filer */
1166         priv->rx_filer_enable = 1;
1167         /* Enable most messages by default */
1168         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1169         /* use pritority h/w tx queue scheduling for single queue devices */
1170         if (priv->num_tx_queues == 1)
1171                 priv->prio_sched_en = 1;
1172
1173         /* Carrier starts down, phylib will bring it up */
1174         netif_carrier_off(dev);
1175
1176         err = register_netdev(dev);
1177
1178         if (err) {
1179                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1180                 goto register_fail;
1181         }
1182
1183         device_init_wakeup(&dev->dev,
1184                            priv->device_flags &
1185                            FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1186
1187         /* fill out IRQ number and name fields */
1188         for (i = 0; i < priv->num_grps; i++) {
1189                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1190                         sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1191                                 dev->name, "_g", '0' + i, "_tx");
1192                         sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1193                                 dev->name, "_g", '0' + i, "_rx");
1194                         sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1195                                 dev->name, "_g", '0' + i, "_er");
1196                 } else
1197                         strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1198         }
1199
1200         /* Initialize the filer table */
1201         gfar_init_filer_table(priv);
1202
1203         /* Create all the sysfs files */
1204         gfar_init_sysfs(dev);
1205
1206         /* Print out the device info */
1207         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1208
1209         /* Even more device info helps when determining which kernel
1210          * provided which set of benchmarks.
1211          */
1212         netdev_info(dev, "Running with NAPI enabled\n");
1213         for (i = 0; i < priv->num_rx_queues; i++)
1214                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1215                             i, priv->rx_queue[i]->rx_ring_size);
1216         for (i = 0; i < priv->num_tx_queues; i++)
1217                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1218                             i, priv->tx_queue[i]->tx_ring_size);
1219
1220         return 0;
1221
1222 register_fail:
1223         unmap_group_regs(priv);
1224         free_tx_pointers(priv);
1225         free_rx_pointers(priv);
1226         if (priv->phy_node)
1227                 of_node_put(priv->phy_node);
1228         if (priv->tbi_node)
1229                 of_node_put(priv->tbi_node);
1230         free_netdev(dev);
1231         return err;
1232 }
1233
1234 static int gfar_remove(struct platform_device *ofdev)
1235 {
1236         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1237
1238         if (priv->phy_node)
1239                 of_node_put(priv->phy_node);
1240         if (priv->tbi_node)
1241                 of_node_put(priv->tbi_node);
1242
1243         dev_set_drvdata(&ofdev->dev, NULL);
1244
1245         unregister_netdev(priv->ndev);
1246         unmap_group_regs(priv);
1247         free_netdev(priv->ndev);
1248
1249         return 0;
1250 }
1251
1252 #ifdef CONFIG_PM
1253
1254 static int gfar_suspend(struct device *dev)
1255 {
1256         struct gfar_private *priv = dev_get_drvdata(dev);
1257         struct net_device *ndev = priv->ndev;
1258         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1259         unsigned long flags;
1260         u32 tempval;
1261
1262         int magic_packet = priv->wol_en &&
1263                            (priv->device_flags &
1264                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1265
1266         netif_device_detach(ndev);
1267
1268         if (netif_running(ndev)) {
1269
1270                 local_irq_save(flags);
1271                 lock_tx_qs(priv);
1272                 lock_rx_qs(priv);
1273
1274                 gfar_halt_nodisable(ndev);
1275
1276                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1277                 tempval = gfar_read(&regs->maccfg1);
1278
1279                 tempval &= ~MACCFG1_TX_EN;
1280
1281                 if (!magic_packet)
1282                         tempval &= ~MACCFG1_RX_EN;
1283
1284                 gfar_write(&regs->maccfg1, tempval);
1285
1286                 unlock_rx_qs(priv);
1287                 unlock_tx_qs(priv);
1288                 local_irq_restore(flags);
1289
1290                 disable_napi(priv);
1291
1292                 if (magic_packet) {
1293                         /* Enable interrupt on Magic Packet */
1294                         gfar_write(&regs->imask, IMASK_MAG);
1295
1296                         /* Enable Magic Packet mode */
1297                         tempval = gfar_read(&regs->maccfg2);
1298                         tempval |= MACCFG2_MPEN;
1299                         gfar_write(&regs->maccfg2, tempval);
1300                 } else {
1301                         phy_stop(priv->phydev);
1302                 }
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int gfar_resume(struct device *dev)
1309 {
1310         struct gfar_private *priv = dev_get_drvdata(dev);
1311         struct net_device *ndev = priv->ndev;
1312         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1313         unsigned long flags;
1314         u32 tempval;
1315         int magic_packet = priv->wol_en &&
1316                            (priv->device_flags &
1317                             FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1318
1319         if (!netif_running(ndev)) {
1320                 netif_device_attach(ndev);
1321                 return 0;
1322         }
1323
1324         if (!magic_packet && priv->phydev)
1325                 phy_start(priv->phydev);
1326
1327         /* Disable Magic Packet mode, in case something
1328          * else woke us up.
1329          */
1330         local_irq_save(flags);
1331         lock_tx_qs(priv);
1332         lock_rx_qs(priv);
1333
1334         tempval = gfar_read(&regs->maccfg2);
1335         tempval &= ~MACCFG2_MPEN;
1336         gfar_write(&regs->maccfg2, tempval);
1337
1338         gfar_start(ndev);
1339
1340         unlock_rx_qs(priv);
1341         unlock_tx_qs(priv);
1342         local_irq_restore(flags);
1343
1344         netif_device_attach(ndev);
1345
1346         enable_napi(priv);
1347
1348         return 0;
1349 }
1350
1351 static int gfar_restore(struct device *dev)
1352 {
1353         struct gfar_private *priv = dev_get_drvdata(dev);
1354         struct net_device *ndev = priv->ndev;
1355
1356         if (!netif_running(ndev))
1357                 return 0;
1358
1359         gfar_init_bds(ndev);
1360         init_registers(ndev);
1361         gfar_set_mac_address(ndev);
1362         gfar_init_mac(ndev);
1363         gfar_start(ndev);
1364
1365         priv->oldlink = 0;
1366         priv->oldspeed = 0;
1367         priv->oldduplex = -1;
1368
1369         if (priv->phydev)
1370                 phy_start(priv->phydev);
1371
1372         netif_device_attach(ndev);
1373         enable_napi(priv);
1374
1375         return 0;
1376 }
1377
1378 static struct dev_pm_ops gfar_pm_ops = {
1379         .suspend = gfar_suspend,
1380         .resume = gfar_resume,
1381         .freeze = gfar_suspend,
1382         .thaw = gfar_resume,
1383         .restore = gfar_restore,
1384 };
1385
1386 #define GFAR_PM_OPS (&gfar_pm_ops)
1387
1388 #else
1389
1390 #define GFAR_PM_OPS NULL
1391
1392 #endif
1393
1394 /* Reads the controller's registers to determine what interface
1395  * connects it to the PHY.
1396  */
1397 static phy_interface_t gfar_get_interface(struct net_device *dev)
1398 {
1399         struct gfar_private *priv = netdev_priv(dev);
1400         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1401         u32 ecntrl;
1402
1403         ecntrl = gfar_read(&regs->ecntrl);
1404
1405         if (ecntrl & ECNTRL_SGMII_MODE)
1406                 return PHY_INTERFACE_MODE_SGMII;
1407
1408         if (ecntrl & ECNTRL_TBI_MODE) {
1409                 if (ecntrl & ECNTRL_REDUCED_MODE)
1410                         return PHY_INTERFACE_MODE_RTBI;
1411                 else
1412                         return PHY_INTERFACE_MODE_TBI;
1413         }
1414
1415         if (ecntrl & ECNTRL_REDUCED_MODE) {
1416                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1417                         return PHY_INTERFACE_MODE_RMII;
1418                 }
1419                 else {
1420                         phy_interface_t interface = priv->interface;
1421
1422                         /* This isn't autodetected right now, so it must
1423                          * be set by the device tree or platform code.
1424                          */
1425                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1426                                 return PHY_INTERFACE_MODE_RGMII_ID;
1427
1428                         return PHY_INTERFACE_MODE_RGMII;
1429                 }
1430         }
1431
1432         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1433                 return PHY_INTERFACE_MODE_GMII;
1434
1435         return PHY_INTERFACE_MODE_MII;
1436 }
1437
1438
1439 /* Initializes driver's PHY state, and attaches to the PHY.
1440  * Returns 0 on success.
1441  */
1442 static int init_phy(struct net_device *dev)
1443 {
1444         struct gfar_private *priv = netdev_priv(dev);
1445         uint gigabit_support =
1446                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1447                 SUPPORTED_1000baseT_Full : 0;
1448         phy_interface_t interface;
1449
1450         priv->oldlink = 0;
1451         priv->oldspeed = 0;
1452         priv->oldduplex = -1;
1453
1454         interface = gfar_get_interface(dev);
1455
1456         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1457                                       interface);
1458         if (!priv->phydev)
1459                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1460                                                          interface);
1461         if (!priv->phydev) {
1462                 dev_err(&dev->dev, "could not attach to PHY\n");
1463                 return -ENODEV;
1464         }
1465
1466         if (interface == PHY_INTERFACE_MODE_SGMII)
1467                 gfar_configure_serdes(dev);
1468
1469         /* Remove any features not supported by the controller */
1470         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1471         priv->phydev->advertising = priv->phydev->supported;
1472
1473         return 0;
1474 }
1475
1476 /* Initialize TBI PHY interface for communicating with the
1477  * SERDES lynx PHY on the chip.  We communicate with this PHY
1478  * through the MDIO bus on each controller, treating it as a
1479  * "normal" PHY at the address found in the TBIPA register.  We assume
1480  * that the TBIPA register is valid.  Either the MDIO bus code will set
1481  * it to a value that doesn't conflict with other PHYs on the bus, or the
1482  * value doesn't matter, as there are no other PHYs on the bus.
1483  */
1484 static void gfar_configure_serdes(struct net_device *dev)
1485 {
1486         struct gfar_private *priv = netdev_priv(dev);
1487         struct phy_device *tbiphy;
1488
1489         if (!priv->tbi_node) {
1490                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1491                                     "device tree specify a tbi-handle\n");
1492                 return;
1493         }
1494
1495         tbiphy = of_phy_find_device(priv->tbi_node);
1496         if (!tbiphy) {
1497                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1498                 return;
1499         }
1500
1501         /* If the link is already up, we must already be ok, and don't need to
1502          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1503          * everything for us?  Resetting it takes the link down and requires
1504          * several seconds for it to come back.
1505          */
1506         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1507                 return;
1508
1509         /* Single clk mode, mii mode off(for serdes communication) */
1510         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1511
1512         phy_write(tbiphy, MII_ADVERTISE,
1513                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1514                   ADVERTISE_1000XPSE_ASYM);
1515
1516         phy_write(tbiphy, MII_BMCR,
1517                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1518                   BMCR_SPEED1000);
1519 }
1520
1521 static void init_registers(struct net_device *dev)
1522 {
1523         struct gfar_private *priv = netdev_priv(dev);
1524         struct gfar __iomem *regs = NULL;
1525         int i;
1526
1527         for (i = 0; i < priv->num_grps; i++) {
1528                 regs = priv->gfargrp[i].regs;
1529                 /* Clear IEVENT */
1530                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1531
1532                 /* Initialize IMASK */
1533                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1534         }
1535
1536         regs = priv->gfargrp[0].regs;
1537         /* Init hash registers to zero */
1538         gfar_write(&regs->igaddr0, 0);
1539         gfar_write(&regs->igaddr1, 0);
1540         gfar_write(&regs->igaddr2, 0);
1541         gfar_write(&regs->igaddr3, 0);
1542         gfar_write(&regs->igaddr4, 0);
1543         gfar_write(&regs->igaddr5, 0);
1544         gfar_write(&regs->igaddr6, 0);
1545         gfar_write(&regs->igaddr7, 0);
1546
1547         gfar_write(&regs->gaddr0, 0);
1548         gfar_write(&regs->gaddr1, 0);
1549         gfar_write(&regs->gaddr2, 0);
1550         gfar_write(&regs->gaddr3, 0);
1551         gfar_write(&regs->gaddr4, 0);
1552         gfar_write(&regs->gaddr5, 0);
1553         gfar_write(&regs->gaddr6, 0);
1554         gfar_write(&regs->gaddr7, 0);
1555
1556         /* Zero out the rmon mib registers if it has them */
1557         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1558                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1559
1560                 /* Mask off the CAM interrupts */
1561                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1562                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1563         }
1564
1565         /* Initialize the max receive buffer length */
1566         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1567
1568         /* Initialize the Minimum Frame Length Register */
1569         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1570 }
1571
1572 static int __gfar_is_rx_idle(struct gfar_private *priv)
1573 {
1574         u32 res;
1575
1576         /* Normaly TSEC should not hang on GRS commands, so we should
1577          * actually wait for IEVENT_GRSC flag.
1578          */
1579         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1580                 return 0;
1581
1582         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1583          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1584          * and the Rx can be safely reset.
1585          */
1586         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1587         res &= 0x7f807f80;
1588         if ((res & 0xffff) == (res >> 16))
1589                 return 1;
1590
1591         return 0;
1592 }
1593
1594 /* Halt the receive and transmit queues */
1595 static void gfar_halt_nodisable(struct net_device *dev)
1596 {
1597         struct gfar_private *priv = netdev_priv(dev);
1598         struct gfar __iomem *regs = NULL;
1599         u32 tempval;
1600         int i;
1601
1602         for (i = 0; i < priv->num_grps; i++) {
1603                 regs = priv->gfargrp[i].regs;
1604                 /* Mask all interrupts */
1605                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1606
1607                 /* Clear all interrupts */
1608                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1609         }
1610
1611         regs = priv->gfargrp[0].regs;
1612         /* Stop the DMA, and wait for it to stop */
1613         tempval = gfar_read(&regs->dmactrl);
1614         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
1615             (DMACTRL_GRS | DMACTRL_GTS)) {
1616                 int ret;
1617
1618                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1619                 gfar_write(&regs->dmactrl, tempval);
1620
1621                 do {
1622                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1623                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1624                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1625                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1626                                 ret = __gfar_is_rx_idle(priv);
1627                 } while (!ret);
1628         }
1629 }
1630
1631 /* Halt the receive and transmit queues */
1632 void gfar_halt(struct net_device *dev)
1633 {
1634         struct gfar_private *priv = netdev_priv(dev);
1635         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1636         u32 tempval;
1637
1638         gfar_halt_nodisable(dev);
1639
1640         /* Disable Rx and Tx */
1641         tempval = gfar_read(&regs->maccfg1);
1642         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1643         gfar_write(&regs->maccfg1, tempval);
1644 }
1645
1646 static void free_grp_irqs(struct gfar_priv_grp *grp)
1647 {
1648         free_irq(grp->interruptError, grp);
1649         free_irq(grp->interruptTransmit, grp);
1650         free_irq(grp->interruptReceive, grp);
1651 }
1652
1653 void stop_gfar(struct net_device *dev)
1654 {
1655         struct gfar_private *priv = netdev_priv(dev);
1656         unsigned long flags;
1657         int i;
1658
1659         phy_stop(priv->phydev);
1660
1661
1662         /* Lock it down */
1663         local_irq_save(flags);
1664         lock_tx_qs(priv);
1665         lock_rx_qs(priv);
1666
1667         gfar_halt(dev);
1668
1669         unlock_rx_qs(priv);
1670         unlock_tx_qs(priv);
1671         local_irq_restore(flags);
1672
1673         /* Free the IRQs */
1674         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1675                 for (i = 0; i < priv->num_grps; i++)
1676                         free_grp_irqs(&priv->gfargrp[i]);
1677         } else {
1678                 for (i = 0; i < priv->num_grps; i++)
1679                         free_irq(priv->gfargrp[i].interruptTransmit,
1680                                  &priv->gfargrp[i]);
1681         }
1682
1683         free_skb_resources(priv);
1684 }
1685
1686 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1687 {
1688         struct txbd8 *txbdp;
1689         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1690         int i, j;
1691
1692         txbdp = tx_queue->tx_bd_base;
1693
1694         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1695                 if (!tx_queue->tx_skbuff[i])
1696                         continue;
1697
1698                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1699                                  txbdp->length, DMA_TO_DEVICE);
1700                 txbdp->lstatus = 0;
1701                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1702                      j++) {
1703                         txbdp++;
1704                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1705                                        txbdp->length, DMA_TO_DEVICE);
1706                 }
1707                 txbdp++;
1708                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1709                 tx_queue->tx_skbuff[i] = NULL;
1710         }
1711         kfree(tx_queue->tx_skbuff);
1712 }
1713
1714 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1715 {
1716         struct rxbd8 *rxbdp;
1717         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1718         int i;
1719
1720         rxbdp = rx_queue->rx_bd_base;
1721
1722         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1723                 if (rx_queue->rx_skbuff[i]) {
1724                         dma_unmap_single(&priv->ofdev->dev,
1725                                          rxbdp->bufPtr, priv->rx_buffer_size,
1726                                          DMA_FROM_DEVICE);
1727                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1728                         rx_queue->rx_skbuff[i] = NULL;
1729                 }
1730                 rxbdp->lstatus = 0;
1731                 rxbdp->bufPtr = 0;
1732                 rxbdp++;
1733         }
1734         kfree(rx_queue->rx_skbuff);
1735 }
1736
1737 /* If there are any tx skbs or rx skbs still around, free them.
1738  * Then free tx_skbuff and rx_skbuff
1739  */
1740 static void free_skb_resources(struct gfar_private *priv)
1741 {
1742         struct gfar_priv_tx_q *tx_queue = NULL;
1743         struct gfar_priv_rx_q *rx_queue = NULL;
1744         int i;
1745
1746         /* Go through all the buffer descriptors and free their data buffers */
1747         for (i = 0; i < priv->num_tx_queues; i++) {
1748                 struct netdev_queue *txq;
1749
1750                 tx_queue = priv->tx_queue[i];
1751                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1752                 if (tx_queue->tx_skbuff)
1753                         free_skb_tx_queue(tx_queue);
1754                 netdev_tx_reset_queue(txq);
1755         }
1756
1757         for (i = 0; i < priv->num_rx_queues; i++) {
1758                 rx_queue = priv->rx_queue[i];
1759                 if (rx_queue->rx_skbuff)
1760                         free_skb_rx_queue(rx_queue);
1761         }
1762
1763         dma_free_coherent(&priv->ofdev->dev,
1764                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1765                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1766                           priv->tx_queue[0]->tx_bd_base,
1767                           priv->tx_queue[0]->tx_bd_dma_base);
1768 }
1769
1770 void gfar_start(struct net_device *dev)
1771 {
1772         struct gfar_private *priv = netdev_priv(dev);
1773         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1774         u32 tempval;
1775         int i = 0;
1776
1777         /* Enable Rx and Tx in MACCFG1 */
1778         tempval = gfar_read(&regs->maccfg1);
1779         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1780         gfar_write(&regs->maccfg1, tempval);
1781
1782         /* Initialize DMACTRL to have WWR and WOP */
1783         tempval = gfar_read(&regs->dmactrl);
1784         tempval |= DMACTRL_INIT_SETTINGS;
1785         gfar_write(&regs->dmactrl, tempval);
1786
1787         /* Make sure we aren't stopped */
1788         tempval = gfar_read(&regs->dmactrl);
1789         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1790         gfar_write(&regs->dmactrl, tempval);
1791
1792         for (i = 0; i < priv->num_grps; i++) {
1793                 regs = priv->gfargrp[i].regs;
1794                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1795                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1796                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1797                 /* Unmask the interrupts we look for */
1798                 gfar_write(&regs->imask, IMASK_DEFAULT);
1799         }
1800
1801         dev->trans_start = jiffies; /* prevent tx timeout */
1802 }
1803
1804 void gfar_configure_coalescing(struct gfar_private *priv,
1805                                unsigned long tx_mask, unsigned long rx_mask)
1806 {
1807         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1808         u32 __iomem *baddr;
1809         int i = 0;
1810
1811         /* Backward compatible case ---- even if we enable
1812          * multiple queues, there's only single reg to program
1813          */
1814         gfar_write(&regs->txic, 0);
1815         if (likely(priv->tx_queue[0]->txcoalescing))
1816                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1817
1818         gfar_write(&regs->rxic, 0);
1819         if (unlikely(priv->rx_queue[0]->rxcoalescing))
1820                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1821
1822         if (priv->mode == MQ_MG_MODE) {
1823                 baddr = &regs->txic0;
1824                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1825                         gfar_write(baddr + i, 0);
1826                         if (likely(priv->tx_queue[i]->txcoalescing))
1827                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1828                 }
1829
1830                 baddr = &regs->rxic0;
1831                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1832                         gfar_write(baddr + i, 0);
1833                         if (likely(priv->rx_queue[i]->rxcoalescing))
1834                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1835                 }
1836         }
1837 }
1838
1839 static int register_grp_irqs(struct gfar_priv_grp *grp)
1840 {
1841         struct gfar_private *priv = grp->priv;
1842         struct net_device *dev = priv->ndev;
1843         int err;
1844
1845         /* If the device has multiple interrupts, register for
1846          * them.  Otherwise, only register for the one
1847          */
1848         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1849                 /* Install our interrupt handlers for Error,
1850                  * Transmit, and Receive
1851                  */
1852                 if ((err = request_irq(grp->interruptError, gfar_error,
1853                                        0, grp->int_name_er, grp)) < 0) {
1854                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1855                                   grp->interruptError);
1856
1857                         goto err_irq_fail;
1858                 }
1859
1860                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1861                                        0, grp->int_name_tx, grp)) < 0) {
1862                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1863                                   grp->interruptTransmit);
1864                         goto tx_irq_fail;
1865                 }
1866
1867                 if ((err = request_irq(grp->interruptReceive, gfar_receive,
1868                                        0, grp->int_name_rx, grp)) < 0) {
1869                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1870                                   grp->interruptReceive);
1871                         goto rx_irq_fail;
1872                 }
1873         } else {
1874                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt,
1875                                        0, grp->int_name_tx, grp)) < 0) {
1876                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1877                                   grp->interruptTransmit);
1878                         goto err_irq_fail;
1879                 }
1880         }
1881
1882         return 0;
1883
1884 rx_irq_fail:
1885         free_irq(grp->interruptTransmit, grp);
1886 tx_irq_fail:
1887         free_irq(grp->interruptError, grp);
1888 err_irq_fail:
1889         return err;
1890
1891 }
1892
1893 /* Bring the controller up and running */
1894 int startup_gfar(struct net_device *ndev)
1895 {
1896         struct gfar_private *priv = netdev_priv(ndev);
1897         struct gfar __iomem *regs = NULL;
1898         int err, i, j;
1899
1900         for (i = 0; i < priv->num_grps; i++) {
1901                 regs= priv->gfargrp[i].regs;
1902                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1903         }
1904
1905         regs= priv->gfargrp[0].regs;
1906         err = gfar_alloc_skb_resources(ndev);
1907         if (err)
1908                 return err;
1909
1910         gfar_init_mac(ndev);
1911
1912         for (i = 0; i < priv->num_grps; i++) {
1913                 err = register_grp_irqs(&priv->gfargrp[i]);
1914                 if (err) {
1915                         for (j = 0; j < i; j++)
1916                                 free_grp_irqs(&priv->gfargrp[j]);
1917                         goto irq_fail;
1918                 }
1919         }
1920
1921         /* Start the controller */
1922         gfar_start(ndev);
1923
1924         phy_start(priv->phydev);
1925
1926         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1927
1928         return 0;
1929
1930 irq_fail:
1931         free_skb_resources(priv);
1932         return err;
1933 }
1934
1935 /* Called when something needs to use the ethernet device
1936  * Returns 0 for success.
1937  */
1938 static int gfar_enet_open(struct net_device *dev)
1939 {
1940         struct gfar_private *priv = netdev_priv(dev);
1941         int err;
1942
1943         enable_napi(priv);
1944
1945         /* Initialize a bunch of registers */
1946         init_registers(dev);
1947
1948         gfar_set_mac_address(dev);
1949
1950         err = init_phy(dev);
1951
1952         if (err) {
1953                 disable_napi(priv);
1954                 return err;
1955         }
1956
1957         err = startup_gfar(dev);
1958         if (err) {
1959                 disable_napi(priv);
1960                 return err;
1961         }
1962
1963         netif_tx_start_all_queues(dev);
1964
1965         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1966
1967         return err;
1968 }
1969
1970 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1971 {
1972         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1973
1974         memset(fcb, 0, GMAC_FCB_LEN);
1975
1976         return fcb;
1977 }
1978
1979 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1980                                     int fcb_length)
1981 {
1982         /* If we're here, it's a IP packet with a TCP or UDP
1983          * payload.  We set it to checksum, using a pseudo-header
1984          * we provide
1985          */
1986         u8 flags = TXFCB_DEFAULT;
1987
1988         /* Tell the controller what the protocol is
1989          * And provide the already calculated phcs
1990          */
1991         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1992                 flags |= TXFCB_UDP;
1993                 fcb->phcs = udp_hdr(skb)->check;
1994         } else
1995                 fcb->phcs = tcp_hdr(skb)->check;
1996
1997         /* l3os is the distance between the start of the
1998          * frame (skb->data) and the start of the IP hdr.
1999          * l4os is the distance between the start of the
2000          * l3 hdr and the l4 hdr
2001          */
2002         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
2003         fcb->l4os = skb_network_header_len(skb);
2004
2005         fcb->flags = flags;
2006 }
2007
2008 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2009 {
2010         fcb->flags |= TXFCB_VLN;
2011         fcb->vlctl = vlan_tx_tag_get(skb);
2012 }
2013
2014 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2015                                       struct txbd8 *base, int ring_size)
2016 {
2017         struct txbd8 *new_bd = bdp + stride;
2018
2019         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2020 }
2021
2022 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2023                                       int ring_size)
2024 {
2025         return skip_txbd(bdp, 1, base, ring_size);
2026 }
2027
2028 /* This is called by the kernel when a frame is ready for transmission.
2029  * It is pointed to by the dev->hard_start_xmit function pointer
2030  */
2031 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2032 {
2033         struct gfar_private *priv = netdev_priv(dev);
2034         struct gfar_priv_tx_q *tx_queue = NULL;
2035         struct netdev_queue *txq;
2036         struct gfar __iomem *regs = NULL;
2037         struct txfcb *fcb = NULL;
2038         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2039         u32 lstatus;
2040         int i, rq = 0, do_tstamp = 0;
2041         u32 bufaddr;
2042         unsigned long flags;
2043         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2044
2045         /* TOE=1 frames larger than 2500 bytes may see excess delays
2046          * before start of transmission.
2047          */
2048         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2049                      skb->ip_summed == CHECKSUM_PARTIAL &&
2050                      skb->len > 2500)) {
2051                 int ret;
2052
2053                 ret = skb_checksum_help(skb);
2054                 if (ret)
2055                         return ret;
2056         }
2057
2058         rq = skb->queue_mapping;
2059         tx_queue = priv->tx_queue[rq];
2060         txq = netdev_get_tx_queue(dev, rq);
2061         base = tx_queue->tx_bd_base;
2062         regs = tx_queue->grp->regs;
2063
2064         /* check if time stamp should be generated */
2065         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2066                      priv->hwts_tx_en)) {
2067                 do_tstamp = 1;
2068                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2069         }
2070
2071         /* make space for additional header when fcb is needed */
2072         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2073              vlan_tx_tag_present(skb) ||
2074              unlikely(do_tstamp)) &&
2075             (skb_headroom(skb) < fcb_length)) {
2076                 struct sk_buff *skb_new;
2077
2078                 skb_new = skb_realloc_headroom(skb, fcb_length);
2079                 if (!skb_new) {
2080                         dev->stats.tx_errors++;
2081                         kfree_skb(skb);
2082                         return NETDEV_TX_OK;
2083                 }
2084
2085                 if (skb->sk)
2086                         skb_set_owner_w(skb_new, skb->sk);
2087                 consume_skb(skb);
2088                 skb = skb_new;
2089         }
2090
2091         /* total number of fragments in the SKB */
2092         nr_frags = skb_shinfo(skb)->nr_frags;
2093
2094         /* calculate the required number of TxBDs for this skb */
2095         if (unlikely(do_tstamp))
2096                 nr_txbds = nr_frags + 2;
2097         else
2098                 nr_txbds = nr_frags + 1;
2099
2100         /* check if there is space to queue this packet */
2101         if (nr_txbds > tx_queue->num_txbdfree) {
2102                 /* no space, stop the queue */
2103                 netif_tx_stop_queue(txq);
2104                 dev->stats.tx_fifo_errors++;
2105                 return NETDEV_TX_BUSY;
2106         }
2107
2108         /* Update transmit stats */
2109         tx_queue->stats.tx_bytes += skb->len;
2110         tx_queue->stats.tx_packets++;
2111
2112         txbdp = txbdp_start = tx_queue->cur_tx;
2113         lstatus = txbdp->lstatus;
2114
2115         /* Time stamp insertion requires one additional TxBD */
2116         if (unlikely(do_tstamp))
2117                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2118                                                  tx_queue->tx_ring_size);
2119
2120         if (nr_frags == 0) {
2121                 if (unlikely(do_tstamp))
2122                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2123                                                           TXBD_INTERRUPT);
2124                 else
2125                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2126         } else {
2127                 /* Place the fragment addresses and lengths into the TxBDs */
2128                 for (i = 0; i < nr_frags; i++) {
2129                         /* Point at the next BD, wrapping as needed */
2130                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2131
2132                         length = skb_shinfo(skb)->frags[i].size;
2133
2134                         lstatus = txbdp->lstatus | length |
2135                                   BD_LFLAG(TXBD_READY);
2136
2137                         /* Handle the last BD specially */
2138                         if (i == nr_frags - 1)
2139                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2140
2141                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2142                                                    &skb_shinfo(skb)->frags[i],
2143                                                    0,
2144                                                    length,
2145                                                    DMA_TO_DEVICE);
2146
2147                         /* set the TxBD length and buffer pointer */
2148                         txbdp->bufPtr = bufaddr;
2149                         txbdp->lstatus = lstatus;
2150                 }
2151
2152                 lstatus = txbdp_start->lstatus;
2153         }
2154
2155         /* Add TxPAL between FCB and frame if required */
2156         if (unlikely(do_tstamp)) {
2157                 skb_push(skb, GMAC_TXPAL_LEN);
2158                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2159         }
2160
2161         /* Set up checksumming */
2162         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2163                 fcb = gfar_add_fcb(skb);
2164                 /* as specified by errata */
2165                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
2166                              ((unsigned long)fcb % 0x20) > 0x18)) {
2167                         __skb_pull(skb, GMAC_FCB_LEN);
2168                         skb_checksum_help(skb);
2169                 } else {
2170                         lstatus |= BD_LFLAG(TXBD_TOE);
2171                         gfar_tx_checksum(skb, fcb, fcb_length);
2172                 }
2173         }
2174
2175         if (vlan_tx_tag_present(skb)) {
2176                 if (unlikely(NULL == fcb)) {
2177                         fcb = gfar_add_fcb(skb);
2178                         lstatus |= BD_LFLAG(TXBD_TOE);
2179                 }
2180
2181                 gfar_tx_vlan(skb, fcb);
2182         }
2183
2184         /* Setup tx hardware time stamping if requested */
2185         if (unlikely(do_tstamp)) {
2186                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2187                 if (fcb == NULL)
2188                         fcb = gfar_add_fcb(skb);
2189                 fcb->ptp = 1;
2190                 lstatus |= BD_LFLAG(TXBD_TOE);
2191         }
2192
2193         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2194                                              skb_headlen(skb), DMA_TO_DEVICE);
2195
2196         /* If time stamping is requested one additional TxBD must be set up. The
2197          * first TxBD points to the FCB and must have a data length of
2198          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2199          * the full frame length.
2200          */
2201         if (unlikely(do_tstamp)) {
2202                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2203                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2204                                          (skb_headlen(skb) - fcb_length);
2205                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2206         } else {
2207                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2208         }
2209
2210         netdev_tx_sent_queue(txq, skb->len);
2211
2212         /* We can work in parallel with gfar_clean_tx_ring(), except
2213          * when modifying num_txbdfree. Note that we didn't grab the lock
2214          * when we were reading the num_txbdfree and checking for available
2215          * space, that's because outside of this function it can only grow,
2216          * and once we've got needed space, it cannot suddenly disappear.
2217          *
2218          * The lock also protects us from gfar_error(), which can modify
2219          * regs->tstat and thus retrigger the transfers, which is why we
2220          * also must grab the lock before setting ready bit for the first
2221          * to be transmitted BD.
2222          */
2223         spin_lock_irqsave(&tx_queue->txlock, flags);
2224
2225         /* The powerpc-specific eieio() is used, as wmb() has too strong
2226          * semantics (it requires synchronization between cacheable and
2227          * uncacheable mappings, which eieio doesn't provide and which we
2228          * don't need), thus requiring a more expensive sync instruction.  At
2229          * some point, the set of architecture-independent barrier functions
2230          * should be expanded to include weaker barriers.
2231          */
2232         eieio();
2233
2234         txbdp_start->lstatus = lstatus;
2235
2236         eieio(); /* force lstatus write before tx_skbuff */
2237
2238         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2239
2240         /* Update the current skb pointer to the next entry we will use
2241          * (wrapping if necessary)
2242          */
2243         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2244                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2245
2246         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2247
2248         /* reduce TxBD free count */
2249         tx_queue->num_txbdfree -= (nr_txbds);
2250
2251         /* If the next BD still needs to be cleaned up, then the bds
2252          * are full.  We need to tell the kernel to stop sending us stuff.
2253          */
2254         if (!tx_queue->num_txbdfree) {
2255                 netif_tx_stop_queue(txq);
2256
2257                 dev->stats.tx_fifo_errors++;
2258         }
2259
2260         /* Tell the DMA to go go go */
2261         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2262
2263         /* Unlock priv */
2264         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2265
2266         return NETDEV_TX_OK;
2267 }
2268
2269 /* Stops the kernel queue, and halts the controller */
2270 static int gfar_close(struct net_device *dev)
2271 {
2272         struct gfar_private *priv = netdev_priv(dev);
2273
2274         disable_napi(priv);
2275
2276         cancel_work_sync(&priv->reset_task);
2277         stop_gfar(dev);
2278
2279         /* Disconnect from the PHY */
2280         phy_disconnect(priv->phydev);
2281         priv->phydev = NULL;
2282
2283         netif_tx_stop_all_queues(dev);
2284
2285         return 0;
2286 }
2287
2288 /* Changes the mac address if the controller is not running. */
2289 static int gfar_set_mac_address(struct net_device *dev)
2290 {
2291         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2292
2293         return 0;
2294 }
2295
2296 /* Check if rx parser should be activated */
2297 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2298 {
2299         struct gfar __iomem *regs;
2300         u32 tempval;
2301
2302         regs = priv->gfargrp[0].regs;
2303
2304         tempval = gfar_read(&regs->rctrl);
2305         /* If parse is no longer required, then disable parser */
2306         if (tempval & RCTRL_REQ_PARSER)
2307                 tempval |= RCTRL_PRSDEP_INIT;
2308         else
2309                 tempval &= ~RCTRL_PRSDEP_INIT;
2310         gfar_write(&regs->rctrl, tempval);
2311 }
2312
2313 /* Enables and disables VLAN insertion/extraction */
2314 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2315 {
2316         struct gfar_private *priv = netdev_priv(dev);
2317         struct gfar __iomem *regs = NULL;
2318         unsigned long flags;
2319         u32 tempval;
2320
2321         regs = priv->gfargrp[0].regs;
2322         local_irq_save(flags);
2323         lock_rx_qs(priv);
2324
2325         if (features & NETIF_F_HW_VLAN_TX) {
2326                 /* Enable VLAN tag insertion */
2327                 tempval = gfar_read(&regs->tctrl);
2328                 tempval |= TCTRL_VLINS;
2329                 gfar_write(&regs->tctrl, tempval);
2330         } else {
2331                 /* Disable VLAN tag insertion */
2332                 tempval = gfar_read(&regs->tctrl);
2333                 tempval &= ~TCTRL_VLINS;
2334                 gfar_write(&regs->tctrl, tempval);
2335         }
2336
2337         if (features & NETIF_F_HW_VLAN_RX) {
2338                 /* Enable VLAN tag extraction */
2339                 tempval = gfar_read(&regs->rctrl);
2340                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2341                 gfar_write(&regs->rctrl, tempval);
2342         } else {
2343                 /* Disable VLAN tag extraction */
2344                 tempval = gfar_read(&regs->rctrl);
2345                 tempval &= ~RCTRL_VLEX;
2346                 gfar_write(&regs->rctrl, tempval);
2347
2348                 gfar_check_rx_parser_mode(priv);
2349         }
2350
2351         gfar_change_mtu(dev, dev->mtu);
2352
2353         unlock_rx_qs(priv);
2354         local_irq_restore(flags);
2355 }
2356
2357 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2358 {
2359         int tempsize, tempval;
2360         struct gfar_private *priv = netdev_priv(dev);
2361         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2362         int oldsize = priv->rx_buffer_size;
2363         int frame_size = new_mtu + ETH_HLEN;
2364
2365         if (gfar_is_vlan_on(priv))
2366                 frame_size += VLAN_HLEN;
2367
2368         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2369                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2370                 return -EINVAL;
2371         }
2372
2373         if (gfar_uses_fcb(priv))
2374                 frame_size += GMAC_FCB_LEN;
2375
2376         frame_size += priv->padding;
2377
2378         tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2379                    INCREMENTAL_BUFFER_SIZE;
2380
2381         /* Only stop and start the controller if it isn't already
2382          * stopped, and we changed something
2383          */
2384         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2385                 stop_gfar(dev);
2386
2387         priv->rx_buffer_size = tempsize;
2388
2389         dev->mtu = new_mtu;
2390
2391         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2392         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2393
2394         /* If the mtu is larger than the max size for standard
2395          * ethernet frames (ie, a jumbo frame), then set maccfg2
2396          * to allow huge frames, and to check the length
2397          */
2398         tempval = gfar_read(&regs->maccfg2);
2399
2400         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2401             gfar_has_errata(priv, GFAR_ERRATA_74))
2402                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2403         else
2404                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2405
2406         gfar_write(&regs->maccfg2, tempval);
2407
2408         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2409                 startup_gfar(dev);
2410
2411         return 0;
2412 }
2413
2414 /* gfar_reset_task gets scheduled when a packet has not been
2415  * transmitted after a set amount of time.
2416  * For now, assume that clearing out all the structures, and
2417  * starting over will fix the problem.
2418  */
2419 static void gfar_reset_task(struct work_struct *work)
2420 {
2421         struct gfar_private *priv = container_of(work, struct gfar_private,
2422                                                  reset_task);
2423         struct net_device *dev = priv->ndev;
2424
2425         if (dev->flags & IFF_UP) {
2426                 netif_tx_stop_all_queues(dev);
2427                 stop_gfar(dev);
2428                 startup_gfar(dev);
2429                 netif_tx_start_all_queues(dev);
2430         }
2431
2432         netif_tx_schedule_all(dev);
2433 }
2434
2435 static void gfar_timeout(struct net_device *dev)
2436 {
2437         struct gfar_private *priv = netdev_priv(dev);
2438
2439         dev->stats.tx_errors++;
2440         schedule_work(&priv->reset_task);
2441 }
2442
2443 static void gfar_align_skb(struct sk_buff *skb)
2444 {
2445         /* We need the data buffer to be aligned properly.  We will reserve
2446          * as many bytes as needed to align the data properly
2447          */
2448         skb_reserve(skb, RXBUF_ALIGNMENT -
2449                     (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2450 }
2451
2452 /* Interrupt Handler for Transmit complete */
2453 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2454 {
2455         struct net_device *dev = tx_queue->dev;
2456         struct netdev_queue *txq;
2457         struct gfar_private *priv = netdev_priv(dev);
2458         struct gfar_priv_rx_q *rx_queue = NULL;
2459         struct txbd8 *bdp, *next = NULL;
2460         struct txbd8 *lbdp = NULL;
2461         struct txbd8 *base = tx_queue->tx_bd_base;
2462         struct sk_buff *skb;
2463         int skb_dirtytx;
2464         int tx_ring_size = tx_queue->tx_ring_size;
2465         int frags = 0, nr_txbds = 0;
2466         int i;
2467         int howmany = 0;
2468         int tqi = tx_queue->qindex;
2469         unsigned int bytes_sent = 0;
2470         u32 lstatus;
2471         size_t buflen;
2472
2473         rx_queue = priv->rx_queue[tqi];
2474         txq = netdev_get_tx_queue(dev, tqi);
2475         bdp = tx_queue->dirty_tx;
2476         skb_dirtytx = tx_queue->skb_dirtytx;
2477
2478         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2479                 unsigned long flags;
2480
2481                 frags = skb_shinfo(skb)->nr_frags;
2482
2483                 /* When time stamping, one additional TxBD must be freed.
2484                  * Also, we need to dma_unmap_single() the TxPAL.
2485                  */
2486                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2487                         nr_txbds = frags + 2;
2488                 else
2489                         nr_txbds = frags + 1;
2490
2491                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2492
2493                 lstatus = lbdp->lstatus;
2494
2495                 /* Only clean completed frames */
2496                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2497                     (lstatus & BD_LENGTH_MASK))
2498                         break;
2499
2500                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2501                         next = next_txbd(bdp, base, tx_ring_size);
2502                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2503                 } else
2504                         buflen = bdp->length;
2505
2506                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2507                                  buflen, DMA_TO_DEVICE);
2508
2509                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2510                         struct skb_shared_hwtstamps shhwtstamps;
2511                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2512
2513                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2514                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2515                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2516                         skb_tstamp_tx(skb, &shhwtstamps);
2517                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2518                         bdp = next;
2519                 }
2520
2521                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2522                 bdp = next_txbd(bdp, base, tx_ring_size);
2523
2524                 for (i = 0; i < frags; i++) {
2525                         dma_unmap_page(&priv->ofdev->dev, bdp->bufPtr,
2526                                        bdp->length, DMA_TO_DEVICE);
2527                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2528                         bdp = next_txbd(bdp, base, tx_ring_size);
2529                 }
2530
2531                 bytes_sent += skb->len;
2532
2533                 dev_kfree_skb_any(skb);
2534
2535                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2536
2537                 skb_dirtytx = (skb_dirtytx + 1) &
2538                               TX_RING_MOD_MASK(tx_ring_size);
2539
2540                 howmany++;
2541                 spin_lock_irqsave(&tx_queue->txlock, flags);
2542                 tx_queue->num_txbdfree += nr_txbds;
2543                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2544         }
2545
2546         /* If we freed a buffer, we can restart transmission, if necessary */
2547         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2548                 netif_wake_subqueue(dev, tqi);
2549
2550         /* Update dirty indicators */
2551         tx_queue->skb_dirtytx = skb_dirtytx;
2552         tx_queue->dirty_tx = bdp;
2553
2554         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2555
2556         return howmany;
2557 }
2558
2559 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2560 {
2561         unsigned long flags;
2562
2563         spin_lock_irqsave(&gfargrp->grplock, flags);
2564         if (napi_schedule_prep(&gfargrp->napi)) {
2565                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2566                 __napi_schedule(&gfargrp->napi);
2567         } else {
2568                 /* Clear IEVENT, so interrupts aren't called again
2569                  * because of the packets that have already arrived.
2570                  */
2571                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2572         }
2573         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2574
2575 }
2576
2577 /* Interrupt Handler for Transmit complete */
2578 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2579 {
2580         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2581         return IRQ_HANDLED;
2582 }
2583
2584 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2585                            struct sk_buff *skb)
2586 {
2587         struct net_device *dev = rx_queue->dev;
2588         struct gfar_private *priv = netdev_priv(dev);
2589         dma_addr_t buf;
2590
2591         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2592                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2593         gfar_init_rxbdp(rx_queue, bdp, buf);
2594 }
2595
2596 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2597 {
2598         struct gfar_private *priv = netdev_priv(dev);
2599         struct sk_buff *skb;
2600
2601         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2602         if (!skb)
2603                 return NULL;
2604
2605         gfar_align_skb(skb);
2606
2607         return skb;
2608 }
2609
2610 struct sk_buff *gfar_new_skb(struct net_device *dev)
2611 {
2612         return gfar_alloc_skb(dev);
2613 }
2614
2615 static inline void count_errors(unsigned short status, struct net_device *dev)
2616 {
2617         struct gfar_private *priv = netdev_priv(dev);
2618         struct net_device_stats *stats = &dev->stats;
2619         struct gfar_extra_stats *estats = &priv->extra_stats;
2620
2621         /* If the packet was truncated, none of the other errors matter */
2622         if (status & RXBD_TRUNCATED) {
2623                 stats->rx_length_errors++;
2624
2625                 estats->rx_trunc++;
2626
2627                 return;
2628         }
2629         /* Count the errors, if there were any */
2630         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2631                 stats->rx_length_errors++;
2632
2633                 if (status & RXBD_LARGE)
2634                         estats->rx_large++;
2635                 else
2636                         estats->rx_short++;
2637         }
2638         if (status & RXBD_NONOCTET) {
2639                 stats->rx_frame_errors++;
2640                 estats->rx_nonoctet++;
2641         }
2642         if (status & RXBD_CRCERR) {
2643                 estats->rx_crcerr++;
2644                 stats->rx_crc_errors++;
2645         }
2646         if (status & RXBD_OVERRUN) {
2647                 estats->rx_overrun++;
2648                 stats->rx_crc_errors++;
2649         }
2650 }
2651
2652 irqreturn_t gfar_receive(int irq, void *grp_id)
2653 {
2654         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2655         return IRQ_HANDLED;
2656 }
2657
2658 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2659 {
2660         /* If valid headers were found, and valid sums
2661          * were verified, then we tell the kernel that no
2662          * checksumming is necessary.  Otherwise, it is [FIXME]
2663          */
2664         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2665                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2666         else
2667                 skb_checksum_none_assert(skb);
2668 }
2669
2670
2671 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2672 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2673                               int amount_pull, struct napi_struct *napi)
2674 {
2675         struct gfar_private *priv = netdev_priv(dev);
2676         struct rxfcb *fcb = NULL;
2677
2678         gro_result_t ret;
2679
2680         /* fcb is at the beginning if exists */
2681         fcb = (struct rxfcb *)skb->data;
2682
2683         /* Remove the FCB from the skb
2684          * Remove the padded bytes, if there are any
2685          */
2686         if (amount_pull) {
2687                 skb_record_rx_queue(skb, fcb->rq);
2688                 skb_pull(skb, amount_pull);
2689         }
2690
2691         /* Get receive timestamp from the skb */
2692         if (priv->hwts_rx_en) {
2693                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2694                 u64 *ns = (u64 *) skb->data;
2695
2696                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2697                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2698         }
2699
2700         if (priv->padding)
2701                 skb_pull(skb, priv->padding);
2702
2703         if (dev->features & NETIF_F_RXCSUM)
2704                 gfar_rx_checksum(skb, fcb);
2705
2706         /* Tell the skb what kind of packet this is */
2707         skb->protocol = eth_type_trans(skb, dev);
2708
2709         /* There's need to check for NETIF_F_HW_VLAN_RX here.
2710          * Even if vlan rx accel is disabled, on some chips
2711          * RXFCB_VLN is pseudo randomly set.
2712          */
2713         if (dev->features & NETIF_F_HW_VLAN_RX &&
2714             fcb->flags & RXFCB_VLN)
2715                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2716
2717         /* Send the packet up the stack */
2718         ret = napi_gro_receive(napi, skb);
2719
2720         if (GRO_DROP == ret)
2721                 priv->extra_stats.kernel_dropped++;
2722
2723         return 0;
2724 }
2725
2726 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2727  * until the budget/quota has been reached. Returns the number
2728  * of frames handled
2729  */
2730 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2731 {
2732         struct net_device *dev = rx_queue->dev;
2733         struct rxbd8 *bdp, *base;
2734         struct sk_buff *skb;
2735         int pkt_len;
2736         int amount_pull;
2737         int howmany = 0;
2738         struct gfar_private *priv = netdev_priv(dev);
2739
2740         /* Get the first full descriptor */
2741         bdp = rx_queue->cur_rx;
2742         base = rx_queue->rx_bd_base;
2743
2744         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2745
2746         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2747                 struct sk_buff *newskb;
2748
2749                 rmb();
2750
2751                 /* Add another skb for the future */
2752                 newskb = gfar_new_skb(dev);
2753
2754                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2755
2756                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2757                                  priv->rx_buffer_size, DMA_FROM_DEVICE);
2758
2759                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2760                              bdp->length > priv->rx_buffer_size))
2761                         bdp->status = RXBD_LARGE;
2762
2763                 /* We drop the frame if we failed to allocate a new buffer */
2764                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2765                              bdp->status & RXBD_ERR)) {
2766                         count_errors(bdp->status, dev);
2767
2768                         if (unlikely(!newskb))
2769                                 newskb = skb;
2770                         else if (skb)
2771                                 dev_kfree_skb(skb);
2772                 } else {
2773                         /* Increment the number of packets */
2774                         rx_queue->stats.rx_packets++;
2775                         howmany++;
2776
2777                         if (likely(skb)) {
2778                                 pkt_len = bdp->length - ETH_FCS_LEN;
2779                                 /* Remove the FCS from the packet length */
2780                                 skb_put(skb, pkt_len);
2781                                 rx_queue->stats.rx_bytes += pkt_len;
2782                                 skb_record_rx_queue(skb, rx_queue->qindex);
2783                                 gfar_process_frame(dev, skb, amount_pull,
2784                                                    &rx_queue->grp->napi);
2785
2786                         } else {
2787                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2788                                 rx_queue->stats.rx_dropped++;
2789                                 priv->extra_stats.rx_skbmissing++;
2790                         }
2791
2792                 }
2793
2794                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2795
2796                 /* Setup the new bdp */
2797                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2798
2799                 /* Update to the next pointer */
2800                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2801
2802                 /* update to point at the next skb */
2803                 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2804                                       RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2805         }
2806
2807         /* Update the current rxbd pointer to be the next one */
2808         rx_queue->cur_rx = bdp;
2809
2810         return howmany;
2811 }
2812
2813 static int gfar_poll(struct napi_struct *napi, int budget)
2814 {
2815         struct gfar_priv_grp *gfargrp =
2816                 container_of(napi, struct gfar_priv_grp, napi);
2817         struct gfar_private *priv = gfargrp->priv;
2818         struct gfar __iomem *regs = gfargrp->regs;
2819         struct gfar_priv_tx_q *tx_queue = NULL;
2820         struct gfar_priv_rx_q *rx_queue = NULL;
2821         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2822         int tx_cleaned = 0, i, left_over_budget = budget;
2823         unsigned long serviced_queues = 0;
2824         int num_queues = 0;
2825
2826         num_queues = gfargrp->num_rx_queues;
2827         budget_per_queue = budget/num_queues;
2828
2829         /* Clear IEVENT, so interrupts aren't called again
2830          * because of the packets that have already arrived
2831          */
2832         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2833
2834         while (num_queues && left_over_budget) {
2835                 budget_per_queue = left_over_budget/num_queues;
2836                 left_over_budget = 0;
2837
2838                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2839                         if (test_bit(i, &serviced_queues))
2840                                 continue;
2841                         rx_queue = priv->rx_queue[i];
2842                         tx_queue = priv->tx_queue[rx_queue->qindex];
2843
2844                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2845                         rx_cleaned_per_queue =
2846                                 gfar_clean_rx_ring(rx_queue, budget_per_queue);
2847                         rx_cleaned += rx_cleaned_per_queue;
2848                         if (rx_cleaned_per_queue < budget_per_queue) {
2849                                 left_over_budget = left_over_budget +
2850                                         (budget_per_queue -
2851                                          rx_cleaned_per_queue);
2852                                 set_bit(i, &serviced_queues);
2853                                 num_queues--;
2854                         }
2855                 }
2856         }
2857
2858         if (tx_cleaned)
2859                 return budget;
2860
2861         if (rx_cleaned < budget) {
2862                 napi_complete(napi);
2863
2864                 /* Clear the halt bit in RSTAT */
2865                 gfar_write(&regs->rstat, gfargrp->rstat);
2866
2867                 gfar_write(&regs->imask, IMASK_DEFAULT);
2868
2869                 /* If we are coalescing interrupts, update the timer
2870                  * Otherwise, clear it
2871                  */
2872                 gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
2873                                           gfargrp->tx_bit_map);
2874         }
2875
2876         return rx_cleaned;
2877 }
2878
2879 #ifdef CONFIG_NET_POLL_CONTROLLER
2880 /* Polling 'interrupt' - used by things like netconsole to send skbs
2881  * without having to re-enable interrupts. It's not called while
2882  * the interrupt routine is executing.
2883  */
2884 static void gfar_netpoll(struct net_device *dev)
2885 {
2886         struct gfar_private *priv = netdev_priv(dev);
2887         int i;
2888
2889         /* If the device has multiple interrupts, run tx/rx */
2890         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2891                 for (i = 0; i < priv->num_grps; i++) {
2892                         disable_irq(priv->gfargrp[i].interruptTransmit);
2893                         disable_irq(priv->gfargrp[i].interruptReceive);
2894                         disable_irq(priv->gfargrp[i].interruptError);
2895                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2896                                        &priv->gfargrp[i]);
2897                         enable_irq(priv->gfargrp[i].interruptError);
2898                         enable_irq(priv->gfargrp[i].interruptReceive);
2899                         enable_irq(priv->gfargrp[i].interruptTransmit);
2900                 }
2901         } else {
2902                 for (i = 0; i < priv->num_grps; i++) {
2903                         disable_irq(priv->gfargrp[i].interruptTransmit);
2904                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2905                                        &priv->gfargrp[i]);
2906                         enable_irq(priv->gfargrp[i].interruptTransmit);
2907                 }
2908         }
2909 }
2910 #endif
2911
2912 /* The interrupt handler for devices with one interrupt */
2913 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2914 {
2915         struct gfar_priv_grp *gfargrp = grp_id;
2916
2917         /* Save ievent for future reference */
2918         u32 events = gfar_read(&gfargrp->regs->ievent);
2919
2920         /* Check for reception */
2921         if (events & IEVENT_RX_MASK)
2922                 gfar_receive(irq, grp_id);
2923
2924         /* Check for transmit completion */
2925         if (events & IEVENT_TX_MASK)
2926                 gfar_transmit(irq, grp_id);
2927
2928         /* Check for errors */
2929         if (events & IEVENT_ERR_MASK)
2930                 gfar_error(irq, grp_id);
2931
2932         return IRQ_HANDLED;
2933 }
2934
2935 /* Called every time the controller might need to be made
2936  * aware of new link state.  The PHY code conveys this
2937  * information through variables in the phydev structure, and this
2938  * function converts those variables into the appropriate
2939  * register values, and can bring down the device if needed.
2940  */
2941 static void adjust_link(struct net_device *dev)
2942 {
2943         struct gfar_private *priv = netdev_priv(dev);
2944         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2945         unsigned long flags;
2946         struct phy_device *phydev = priv->phydev;
2947         int new_state = 0;
2948
2949         local_irq_save(flags);
2950         lock_tx_qs(priv);
2951
2952         if (phydev->link) {
2953                 u32 tempval = gfar_read(&regs->maccfg2);
2954                 u32 ecntrl = gfar_read(&regs->ecntrl);
2955
2956                 /* Now we make sure that we can be in full duplex mode.
2957                  * If not, we operate in half-duplex mode.
2958                  */
2959                 if (phydev->duplex != priv->oldduplex) {
2960                         new_state = 1;
2961                         if (!(phydev->duplex))
2962                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2963                         else
2964                                 tempval |= MACCFG2_FULL_DUPLEX;
2965
2966                         priv->oldduplex = phydev->duplex;
2967                 }
2968
2969                 if (phydev->speed != priv->oldspeed) {
2970                         new_state = 1;
2971                         switch (phydev->speed) {
2972                         case 1000:
2973                                 tempval =
2974                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2975
2976                                 ecntrl &= ~(ECNTRL_R100);
2977                                 break;
2978                         case 100:
2979                         case 10:
2980                                 tempval =
2981                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2982
2983                                 /* Reduced mode distinguishes
2984                                  * between 10 and 100
2985                                  */
2986                                 if (phydev->speed == SPEED_100)
2987                                         ecntrl |= ECNTRL_R100;
2988                                 else
2989                                         ecntrl &= ~(ECNTRL_R100);
2990                                 break;
2991                         default:
2992                                 netif_warn(priv, link, dev,
2993                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2994                                            phydev->speed);
2995                                 break;
2996                         }
2997
2998                         priv->oldspeed = phydev->speed;
2999                 }
3000
3001                 gfar_write(&regs->maccfg2, tempval);
3002                 gfar_write(&regs->ecntrl, ecntrl);
3003
3004                 if (!priv->oldlink) {
3005                         new_state = 1;
3006                         priv->oldlink = 1;
3007                 }
3008         } else if (priv->oldlink) {
3009                 new_state = 1;
3010                 priv->oldlink = 0;
3011                 priv->oldspeed = 0;
3012                 priv->oldduplex = -1;
3013         }
3014
3015         if (new_state && netif_msg_link(priv))
3016                 phy_print_status(phydev);
3017         unlock_tx_qs(priv);
3018         local_irq_restore(flags);
3019 }
3020
3021 /* Update the hash table based on the current list of multicast
3022  * addresses we subscribe to.  Also, change the promiscuity of
3023  * the device based on the flags (this function is called
3024  * whenever dev->flags is changed
3025  */
3026 static void gfar_set_multi(struct net_device *dev)
3027 {
3028         struct netdev_hw_addr *ha;
3029         struct gfar_private *priv = netdev_priv(dev);
3030         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3031         u32 tempval;
3032
3033         if (dev->flags & IFF_PROMISC) {
3034                 /* Set RCTRL to PROM */
3035                 tempval = gfar_read(&regs->rctrl);
3036                 tempval |= RCTRL_PROM;
3037                 gfar_write(&regs->rctrl, tempval);
3038         } else {
3039                 /* Set RCTRL to not PROM */
3040                 tempval = gfar_read(&regs->rctrl);
3041                 tempval &= ~(RCTRL_PROM);
3042                 gfar_write(&regs->rctrl, tempval);
3043         }
3044
3045         if (dev->flags & IFF_ALLMULTI) {
3046                 /* Set the hash to rx all multicast frames */
3047                 gfar_write(&regs->igaddr0, 0xffffffff);
3048                 gfar_write(&regs->igaddr1, 0xffffffff);
3049                 gfar_write(&regs->igaddr2, 0xffffffff);
3050                 gfar_write(&regs->igaddr3, 0xffffffff);
3051                 gfar_write(&regs->igaddr4, 0xffffffff);
3052                 gfar_write(&regs->igaddr5, 0xffffffff);
3053                 gfar_write(&regs->igaddr6, 0xffffffff);
3054                 gfar_write(&regs->igaddr7, 0xffffffff);
3055                 gfar_write(&regs->gaddr0, 0xffffffff);
3056                 gfar_write(&regs->gaddr1, 0xffffffff);
3057                 gfar_write(&regs->gaddr2, 0xffffffff);
3058                 gfar_write(&regs->gaddr3, 0xffffffff);
3059                 gfar_write(&regs->gaddr4, 0xffffffff);
3060                 gfar_write(&regs->gaddr5, 0xffffffff);
3061                 gfar_write(&regs->gaddr6, 0xffffffff);
3062                 gfar_write(&regs->gaddr7, 0xffffffff);
3063         } else {
3064                 int em_num;
3065                 int idx;
3066
3067                 /* zero out the hash */
3068                 gfar_write(&regs->igaddr0, 0x0);
3069                 gfar_write(&regs->igaddr1, 0x0);
3070                 gfar_write(&regs->igaddr2, 0x0);
3071                 gfar_write(&regs->igaddr3, 0x0);
3072                 gfar_write(&regs->igaddr4, 0x0);
3073                 gfar_write(&regs->igaddr5, 0x0);
3074                 gfar_write(&regs->igaddr6, 0x0);
3075                 gfar_write(&regs->igaddr7, 0x0);
3076                 gfar_write(&regs->gaddr0, 0x0);
3077                 gfar_write(&regs->gaddr1, 0x0);
3078                 gfar_write(&regs->gaddr2, 0x0);
3079                 gfar_write(&regs->gaddr3, 0x0);
3080                 gfar_write(&regs->gaddr4, 0x0);
3081                 gfar_write(&regs->gaddr5, 0x0);
3082                 gfar_write(&regs->gaddr6, 0x0);
3083                 gfar_write(&regs->gaddr7, 0x0);
3084
3085                 /* If we have extended hash tables, we need to
3086                  * clear the exact match registers to prepare for
3087                  * setting them
3088                  */
3089                 if (priv->extended_hash) {
3090                         em_num = GFAR_EM_NUM + 1;
3091                         gfar_clear_exact_match(dev);
3092                         idx = 1;
3093                 } else {
3094                         idx = 0;
3095                         em_num = 0;
3096                 }
3097
3098                 if (netdev_mc_empty(dev))
3099                         return;
3100
3101                 /* Parse the list, and set the appropriate bits */
3102                 netdev_for_each_mc_addr(ha, dev) {
3103                         if (idx < em_num) {
3104                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3105                                 idx++;
3106                         } else
3107                                 gfar_set_hash_for_addr(dev, ha->addr);
3108                 }
3109         }
3110 }
3111
3112
3113 /* Clears each of the exact match registers to zero, so they
3114  * don't interfere with normal reception
3115  */
3116 static void gfar_clear_exact_match(struct net_device *dev)
3117 {
3118         int idx;
3119         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3120
3121         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3122                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3123 }
3124
3125 /* Set the appropriate hash bit for the given addr */
3126 /* The algorithm works like so:
3127  * 1) Take the Destination Address (ie the multicast address), and
3128  * do a CRC on it (little endian), and reverse the bits of the
3129  * result.
3130  * 2) Use the 8 most significant bits as a hash into a 256-entry
3131  * table.  The table is controlled through 8 32-bit registers:
3132  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3133  * gaddr7.  This means that the 3 most significant bits in the
3134  * hash index which gaddr register to use, and the 5 other bits
3135  * indicate which bit (assuming an IBM numbering scheme, which
3136  * for PowerPC (tm) is usually the case) in the register holds
3137  * the entry.
3138  */
3139 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3140 {
3141         u32 tempval;
3142         struct gfar_private *priv = netdev_priv(dev);
3143         u32 result = ether_crc(ETH_ALEN, addr);
3144         int width = priv->hash_width;
3145         u8 whichbit = (result >> (32 - width)) & 0x1f;
3146         u8 whichreg = result >> (32 - width + 5);
3147         u32 value = (1 << (31-whichbit));
3148
3149         tempval = gfar_read(priv->hash_regs[whichreg]);
3150         tempval |= value;
3151         gfar_write(priv->hash_regs[whichreg], tempval);
3152 }
3153
3154
3155 /* There are multiple MAC Address register pairs on some controllers
3156  * This function sets the numth pair to a given address
3157  */
3158 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3159                                   const u8 *addr)
3160 {
3161         struct gfar_private *priv = netdev_priv(dev);
3162         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3163         int idx;
3164         char tmpbuf[ETH_ALEN];
3165         u32 tempval;
3166         u32 __iomem *macptr = &regs->macstnaddr1;
3167
3168         macptr += num*2;
3169
3170         /* Now copy it into the mac registers backwards, cuz
3171          * little endian is silly
3172          */
3173         for (idx = 0; idx < ETH_ALEN; idx++)
3174                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3175
3176         gfar_write(macptr, *((u32 *) (tmpbuf)));
3177
3178         tempval = *((u32 *) (tmpbuf + 4));
3179
3180         gfar_write(macptr+1, tempval);
3181 }
3182
3183 /* GFAR error interrupt handler */
3184 static irqreturn_t gfar_error(int irq, void *grp_id)
3185 {
3186         struct gfar_priv_grp *gfargrp = grp_id;
3187         struct gfar __iomem *regs = gfargrp->regs;
3188         struct gfar_private *priv= gfargrp->priv;
3189         struct net_device *dev = priv->ndev;
3190
3191         /* Save ievent for future reference */
3192         u32 events = gfar_read(&regs->ievent);
3193
3194         /* Clear IEVENT */
3195         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3196
3197         /* Magic Packet is not an error. */
3198         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3199             (events & IEVENT_MAG))
3200                 events &= ~IEVENT_MAG;
3201
3202         /* Hmm... */
3203         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3204                 netdev_dbg(dev,
3205                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3206                            events, gfar_read(&regs->imask));
3207
3208         /* Update the error counters */
3209         if (events & IEVENT_TXE) {
3210                 dev->stats.tx_errors++;
3211
3212                 if (events & IEVENT_LC)
3213                         dev->stats.tx_window_errors++;
3214                 if (events & IEVENT_CRL)
3215                         dev->stats.tx_aborted_errors++;
3216                 if (events & IEVENT_XFUN) {
3217                         unsigned long flags;
3218
3219                         netif_dbg(priv, tx_err, dev,
3220                                   "TX FIFO underrun, packet dropped\n");
3221                         dev->stats.tx_dropped++;
3222                         priv->extra_stats.tx_underrun++;
3223
3224                         local_irq_save(flags);
3225                         lock_tx_qs(priv);
3226
3227                         /* Reactivate the Tx Queues */
3228                         gfar_write(&regs->tstat, gfargrp->tstat);
3229
3230                         unlock_tx_qs(priv);
3231                         local_irq_restore(flags);
3232                 }
3233                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3234         }
3235         if (events & IEVENT_BSY) {
3236                 dev->stats.rx_errors++;
3237                 priv->extra_stats.rx_bsy++;
3238
3239                 gfar_receive(irq, grp_id);
3240
3241                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3242                           gfar_read(&regs->rstat));
3243         }
3244         if (events & IEVENT_BABR) {
3245                 dev->stats.rx_errors++;
3246                 priv->extra_stats.rx_babr++;
3247
3248                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3249         }
3250         if (events & IEVENT_EBERR) {
3251                 priv->extra_stats.eberr++;
3252                 netif_dbg(priv, rx_err, dev, "bus error\n");
3253         }
3254         if (events & IEVENT_RXC)
3255                 netif_dbg(priv, rx_status, dev, "control frame\n");
3256
3257         if (events & IEVENT_BABT) {
3258                 priv->extra_stats.tx_babt++;
3259                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3260         }
3261         return IRQ_HANDLED;
3262 }
3263
3264 static struct of_device_id gfar_match[] =
3265 {
3266         {
3267                 .type = "network",
3268                 .compatible = "gianfar",
3269         },
3270         {
3271                 .compatible = "fsl,etsec2",
3272         },
3273         {},
3274 };
3275 MODULE_DEVICE_TABLE(of, gfar_match);
3276
3277 /* Structure for a device driver */
3278 static struct platform_driver gfar_driver = {
3279         .driver = {
3280                 .name = "fsl-gianfar",
3281                 .owner = THIS_MODULE,
3282                 .pm = GFAR_PM_OPS,
3283                 .of_match_table = gfar_match,
3284         },
3285         .probe = gfar_probe,
3286         .remove = gfar_remove,
3287 };
3288
3289 module_platform_driver(gfar_driver);