drivers/scsi/qla2xxx/qla_nx.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2011 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8 #include <linux/delay.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include <linux/vmalloc.h>
  12 #include <scsi/scsi_tcq.h>
  13
  14 #define MASK(n)                 ((1ULL<<(n))-1)
  15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
  16         ((addr >> 25) & 0x3ff))
  17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
  18         ((addr >> 25) & 0x3ff))
  19 #define MS_WIN(addr) (addr & 0x0ffc0000)
  20 #define QLA82XX_PCI_MN_2M   (0)
  21 #define QLA82XX_PCI_MS_2M   (0x80000)
  22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
  23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
  24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  25 #define BLOCK_PROTECT_BITS 0x0F
  26
  27 /* CRB window related */
  28 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  30 #define CRB_WINDOW_2M   (0x130060)
  31 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  32 #define CRB_HI(off)     ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  33                         ((off) & 0xf0000))
  34 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  35 #define CRB_INDIRECT_2M (0x1e0000UL)
  36
  37 #define MAX_CRB_XFORM 60
  38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  39 int qla82xx_crb_table_initialized;
  40
  41 #define qla82xx_crb_addr_transform(name) \
  42         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  43         QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  44
  45 static void qla82xx_crb_addr_transform_setup(void)
  46 {
  47         qla82xx_crb_addr_transform(XDMA);
  48         qla82xx_crb_addr_transform(TIMR);
  49         qla82xx_crb_addr_transform(SRE);
  50         qla82xx_crb_addr_transform(SQN3);
  51         qla82xx_crb_addr_transform(SQN2);
  52         qla82xx_crb_addr_transform(SQN1);
  53         qla82xx_crb_addr_transform(SQN0);
  54         qla82xx_crb_addr_transform(SQS3);
  55         qla82xx_crb_addr_transform(SQS2);
  56         qla82xx_crb_addr_transform(SQS1);
  57         qla82xx_crb_addr_transform(SQS0);
  58         qla82xx_crb_addr_transform(RPMX7);
  59         qla82xx_crb_addr_transform(RPMX6);
  60         qla82xx_crb_addr_transform(RPMX5);
  61         qla82xx_crb_addr_transform(RPMX4);
  62         qla82xx_crb_addr_transform(RPMX3);
  63         qla82xx_crb_addr_transform(RPMX2);
  64         qla82xx_crb_addr_transform(RPMX1);
  65         qla82xx_crb_addr_transform(RPMX0);
  66         qla82xx_crb_addr_transform(ROMUSB);
  67         qla82xx_crb_addr_transform(SN);
  68         qla82xx_crb_addr_transform(QMN);
  69         qla82xx_crb_addr_transform(QMS);
  70         qla82xx_crb_addr_transform(PGNI);
  71         qla82xx_crb_addr_transform(PGND);
  72         qla82xx_crb_addr_transform(PGN3);
  73         qla82xx_crb_addr_transform(PGN2);
  74         qla82xx_crb_addr_transform(PGN1);
  75         qla82xx_crb_addr_transform(PGN0);
  76         qla82xx_crb_addr_transform(PGSI);
  77         qla82xx_crb_addr_transform(PGSD);
  78         qla82xx_crb_addr_transform(PGS3);
  79         qla82xx_crb_addr_transform(PGS2);
  80         qla82xx_crb_addr_transform(PGS1);
  81         qla82xx_crb_addr_transform(PGS0);
  82         qla82xx_crb_addr_transform(PS);
  83         qla82xx_crb_addr_transform(PH);
  84         qla82xx_crb_addr_transform(NIU);
  85         qla82xx_crb_addr_transform(I2Q);
  86         qla82xx_crb_addr_transform(EG);
  87         qla82xx_crb_addr_transform(MN);
  88         qla82xx_crb_addr_transform(MS);
  89         qla82xx_crb_addr_transform(CAS2);
  90         qla82xx_crb_addr_transform(CAS1);
  91         qla82xx_crb_addr_transform(CAS0);
  92         qla82xx_crb_addr_transform(CAM);
  93         qla82xx_crb_addr_transform(C2C1);
  94         qla82xx_crb_addr_transform(C2C0);
  95         qla82xx_crb_addr_transform(SMB);
  96         qla82xx_crb_addr_transform(OCM0);
  97         /*
  98          * Used only in P3 just define it for P2 also.
  99          */
 100         qla82xx_crb_addr_transform(I2C0);
 101
 102         qla82xx_crb_table_initialized = 1;
 103 }
 104
 105 struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 106         {{{0, 0,         0,         0} } },
 107         {{{1, 0x0100000, 0x0102000, 0x120000},
 108         {1, 0x0110000, 0x0120000, 0x130000},
 109         {1, 0x0120000, 0x0122000, 0x124000},
 110         {1, 0x0130000, 0x0132000, 0x126000},
 111         {1, 0x0140000, 0x0142000, 0x128000},
 112         {1, 0x0150000, 0x0152000, 0x12a000},
 113         {1, 0x0160000, 0x0170000, 0x110000},
 114         {1, 0x0170000, 0x0172000, 0x12e000},
 115         {0, 0x0000000, 0x0000000, 0x000000},
 116         {0, 0x0000000, 0x0000000, 0x000000},
 117         {0, 0x0000000, 0x0000000, 0x000000},
 118         {0, 0x0000000, 0x0000000, 0x000000},
 119         {0, 0x0000000, 0x0000000, 0x000000},
 120         {0, 0x0000000, 0x0000000, 0x000000},
 121         {1, 0x01e0000, 0x01e0800, 0x122000},
 122         {0, 0x0000000, 0x0000000, 0x000000} } } ,
 123         {{{1, 0x0200000, 0x0210000, 0x180000} } },
 124         {{{0, 0,         0,         0} } },
 125         {{{1, 0x0400000, 0x0401000, 0x169000} } },
 126         {{{1, 0x0500000, 0x0510000, 0x140000} } },
 127         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
 128         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
 129         {{{1, 0x0800000, 0x0802000, 0x170000},
 130         {0, 0x0000000, 0x0000000, 0x000000},
 131         {0, 0x0000000, 0x0000000, 0x000000},
 132         {0, 0x0000000, 0x0000000, 0x000000},
 133         {0, 0x0000000, 0x0000000, 0x000000},
 134         {0, 0x0000000, 0x0000000, 0x000000},
 135         {0, 0x0000000, 0x0000000, 0x000000},
 136         {0, 0x0000000, 0x0000000, 0x000000},
 137         {0, 0x0000000, 0x0000000, 0x000000},
 138         {0, 0x0000000, 0x0000000, 0x000000},
 139         {0, 0x0000000, 0x0000000, 0x000000},
 140         {0, 0x0000000, 0x0000000, 0x000000},
 141         {0, 0x0000000, 0x0000000, 0x000000},
 142         {0, 0x0000000, 0x0000000, 0x000000},
 143         {0, 0x0000000, 0x0000000, 0x000000},
 144         {1, 0x08f0000, 0x08f2000, 0x172000} } },
 145         {{{1, 0x0900000, 0x0902000, 0x174000},
 146         {0, 0x0000000, 0x0000000, 0x000000},
 147         {0, 0x0000000, 0x0000000, 0x000000},
 148         {0, 0x0000000, 0x0000000, 0x000000},
 149         {0, 0x0000000, 0x0000000, 0x000000},
 150         {0, 0x0000000, 0x0000000, 0x000000},
 151         {0, 0x0000000, 0x0000000, 0x000000},
 152         {0, 0x0000000, 0x0000000, 0x000000},
 153         {0, 0x0000000, 0x0000000, 0x000000},
 154         {0, 0x0000000, 0x0000000, 0x000000},
 155         {0, 0x0000000, 0x0000000, 0x000000},
 156         {0, 0x0000000, 0x0000000, 0x000000},
 157         {0, 0x0000000, 0x0000000, 0x000000},
 158         {0, 0x0000000, 0x0000000, 0x000000},
 159         {0, 0x0000000, 0x0000000, 0x000000},
 160         {1, 0x09f0000, 0x09f2000, 0x176000} } },
 161         {{{0, 0x0a00000, 0x0a02000, 0x178000},
 162         {0, 0x0000000, 0x0000000, 0x000000},
 163         {0, 0x0000000, 0x0000000, 0x000000},
 164         {0, 0x0000000, 0x0000000, 0x000000},
 165         {0, 0x0000000, 0x0000000, 0x000000},
 166         {0, 0x0000000, 0x0000000, 0x000000},
 167         {0, 0x0000000, 0x0000000, 0x000000},
 168         {0, 0x0000000, 0x0000000, 0x000000},
 169         {0, 0x0000000, 0x0000000, 0x000000},
 170         {0, 0x0000000, 0x0000000, 0x000000},
 171         {0, 0x0000000, 0x0000000, 0x000000},
 172         {0, 0x0000000, 0x0000000, 0x000000},
 173         {0, 0x0000000, 0x0000000, 0x000000},
 174         {0, 0x0000000, 0x0000000, 0x000000},
 175         {0, 0x0000000, 0x0000000, 0x000000},
 176         {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 177         {{{0, 0x0b00000, 0x0b02000, 0x17c000},
 178         {0, 0x0000000, 0x0000000, 0x000000},
 179         {0, 0x0000000, 0x0000000, 0x000000},
 180         {0, 0x0000000, 0x0000000, 0x000000},
 181         {0, 0x0000000, 0x0000000, 0x000000},
 182         {0, 0x0000000, 0x0000000, 0x000000},
 183         {0, 0x0000000, 0x0000000, 0x000000},
 184         {0, 0x0000000, 0x0000000, 0x000000},
 185         {0, 0x0000000, 0x0000000, 0x000000},
 186         {0, 0x0000000, 0x0000000, 0x000000},
 187         {0, 0x0000000, 0x0000000, 0x000000},
 188         {0, 0x0000000, 0x0000000, 0x000000},
 189         {0, 0x0000000, 0x0000000, 0x000000},
 190         {0, 0x0000000, 0x0000000, 0x000000},
 191         {0, 0x0000000, 0x0000000, 0x000000},
 192         {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 193         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
 194         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
 195         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
 196         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
 197         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
 198         {{{1, 0x1100000, 0x1101000, 0x160000} } },
 199         {{{1, 0x1200000, 0x1201000, 0x161000} } },
 200         {{{1, 0x1300000, 0x1301000, 0x162000} } },
 201         {{{1, 0x1400000, 0x1401000, 0x163000} } },
 202         {{{1, 0x1500000, 0x1501000, 0x165000} } },
 203         {{{1, 0x1600000, 0x1601000, 0x166000} } },
 204         {{{0, 0,         0,         0} } },
 205         {{{0, 0,         0,         0} } },
 206         {{{0, 0,         0,         0} } },
 207         {{{0, 0,         0,         0} } },
 208         {{{0, 0,         0,         0} } },
 209         {{{0, 0,         0,         0} } },
 210         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
 211         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
 212         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
 213         {{{0} } },
 214         {{{1, 0x2100000, 0x2102000, 0x120000},
 215         {1, 0x2110000, 0x2120000, 0x130000},
 216         {1, 0x2120000, 0x2122000, 0x124000},
 217         {1, 0x2130000, 0x2132000, 0x126000},
 218         {1, 0x2140000, 0x2142000, 0x128000},
 219         {1, 0x2150000, 0x2152000, 0x12a000},
 220         {1, 0x2160000, 0x2170000, 0x110000},
 221         {1, 0x2170000, 0x2172000, 0x12e000},
 222         {0, 0x0000000, 0x0000000, 0x000000},
 223         {0, 0x0000000, 0x0000000, 0x000000},
 224         {0, 0x0000000, 0x0000000, 0x000000},
 225         {0, 0x0000000, 0x0000000, 0x000000},
 226         {0, 0x0000000, 0x0000000, 0x000000},
 227         {0, 0x0000000, 0x0000000, 0x000000},
 228         {0, 0x0000000, 0x0000000, 0x000000},
 229         {0, 0x0000000, 0x0000000, 0x000000} } },
 230         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
 231         {{{0} } },
 232         {{{0} } },
 233         {{{0} } },
 234         {{{0} } },
 235         {{{0} } },
 236         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
 237         {{{1, 0x2900000, 0x2901000, 0x16b000} } },
 238         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
 239         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
 240         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
 241         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
 242         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
 243         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
 244         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
 245         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
 246         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
 247         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
 248         {{{0} } },
 249         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
 250         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
 251         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
 252         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
 253         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
 254         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
 255         {{{0} } },
 256         {{{0} } },
 257         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
 258         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
 259         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
 260 };
 261
 262 /*
 263  * top 12 bits of crb internal address (hub, agent)
 264  */
 265 unsigned qla82xx_crb_hub_agt[64] = {
 266         0,
 267         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 268         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 269         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 270         0,
 271         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 272         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 276         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 293         0,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 296         0,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 298         0,
 299         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 301         0,
 302         0,
 303         0,
 304         0,
 305         0,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 307         0,
 308         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 309         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 310         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 311         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 313         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 318         0,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 323         0,
 324         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 327         0,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 329         0,
 330 };
 331
 332 /* Device states */
 333 char *q_dev_state[] = {
 334          "Unknown",
 335         "Cold",
 336         "Initializing",
 337         "Ready",
 338         "Need Reset",
 339         "Need Quiescent",
 340         "Failed",
 341         "Quiescent",
 342 };
 343
 344 char *qdev_state(uint32_t dev_state)
 345 {
 346         return q_dev_state[dev_state];
 347 }
 348
 349 /*
 350  * In: 'off' is offset from CRB space in 128M pci map
 351  * Out: 'off' is 2M pci map addr
 352  * side effect: lock crb window
 353  */
 354 static void
 355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
 356 {
 357         u32 win_read;
 358         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 359
 360         ha->crb_win = CRB_HI(*off);
 361         writel(ha->crb_win,
 362                 (void *)(CRB_WINDOW_2M + ha->nx_pcibase));
 363
 364         /* Read back value to make sure write has gone through before trying
 365          * to use it.
 366          */
 367         win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
 368         if (win_read != ha->crb_win) {
 369                 ql_dbg(ql_dbg_p3p, vha, 0xb000,
 370                     "%s: Written crbwin (0x%x) "
 371                     "!= Read crbwin (0x%x), off=0x%lx.\n",
 372                     __func__, ha->crb_win, win_read, *off);
 373         }
 374         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 375 }
 376
 377 static inline unsigned long
 378 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
 379 {
 380         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 381         /* See if we are currently pointing to the region we want to use next */
 382         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
 383                 /* No need to change window. PCIX and PCIEregs are in both
 384                  * regs are in both windows.
 385                  */
 386                 return off;
 387         }
 388
 389         if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
 390                 /* We are in first CRB window */
 391                 if (ha->curr_window != 0)
 392                         WARN_ON(1);
 393                 return off;
 394         }
 395
 396         if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
 397                 /* We are in second CRB window */
 398                 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
 399
 400                 if (ha->curr_window != 1)
 401                         return off;
 402
 403                 /* We are in the QM or direct access
 404                  * register region - do nothing
 405                  */
 406                 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
 407                         (off < QLA82XX_PCI_CAMQM_MAX))
 408                         return off;
 409         }
 410         /* strange address given */
 411         ql_dbg(ql_dbg_p3p, vha, 0xb001,
 412             "%s: Warning: unm_nic_pci_set_crbwindow "
 413             "called with an unknown address(%llx).\n",
 414             QLA2XXX_DRIVER_NAME, off);
 415         return off;
 416 }
 417
 418 static int
 419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
 420 {
 421         struct crb_128M_2M_sub_block_map *m;
 422
 423         if (*off >= QLA82XX_CRB_MAX)
 424                 return -1;
 425
 426         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 427                 *off = (*off - QLA82XX_PCI_CAMQM) +
 428                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 429                 return 0;
 430         }
 431
 432         if (*off < QLA82XX_PCI_CRBSPACE)
 433                 return -1;
 434
 435         *off -= QLA82XX_PCI_CRBSPACE;
 436
 437         /* Try direct map */
 438         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 439
 440         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 441                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 442                 return 0;
 443         }
 444         /* Not in direct map, use crb window */
 445         return 1;
 446 }
 447
 448 #define CRB_WIN_LOCK_TIMEOUT 100000000
 449 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
 450 {
 451         int done = 0, timeout = 0;
 452
 453         while (!done) {
 454                 /* acquire semaphore3 from PCI HW block */
 455                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 456                 if (done == 1)
 457                         break;
 458                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 459                         return -1;
 460                 timeout++;
 461         }
 462         qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
 463         return 0;
 464 }
 465
 466 int
 467 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
 468 {
 469         unsigned long flags = 0;
 470         int rv;
 471
 472         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 473
 474         BUG_ON(rv == -1);
 475
 476         if (rv == 1) {
 477                 write_lock_irqsave(&ha->hw_lock, flags);
 478                 qla82xx_crb_win_lock(ha);
 479                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 480         }
 481
 482         writel(data, (void __iomem *)off);
 483
 484         if (rv == 1) {
 485                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 486                 write_unlock_irqrestore(&ha->hw_lock, flags);
 487         }
 488         return 0;
 489 }
 490
 491 int
 492 qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
 493 {
 494         unsigned long flags = 0;
 495         int rv;
 496         u32 data;
 497
 498         rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
 499
 500         BUG_ON(rv == -1);
 501
 502         if (rv == 1) {
 503                 write_lock_irqsave(&ha->hw_lock, flags);
 504                 qla82xx_crb_win_lock(ha);
 505                 qla82xx_pci_set_crbwindow_2M(ha, &off);
 506         }
 507         data = RD_REG_DWORD((void __iomem *)off);
 508
 509         if (rv == 1) {
 510                 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 511                 write_unlock_irqrestore(&ha->hw_lock, flags);
 512         }
 513         return data;
 514 }
 515
 516 #define IDC_LOCK_TIMEOUT 100000000
 517 int qla82xx_idc_lock(struct qla_hw_data *ha)
 518 {
 519         int i;
 520         int done = 0, timeout = 0;
 521
 522         while (!done) {
 523                 /* acquire semaphore5 from PCI HW block */
 524                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 525                 if (done == 1)
 526                         break;
 527                 if (timeout >= IDC_LOCK_TIMEOUT)
 528                         return -1;
 529
 530                 timeout++;
 531
 532                 /* Yield CPU */
 533                 if (!in_interrupt())
 534                         schedule();
 535                 else {
 536                         for (i = 0; i < 20; i++)
 537                                 cpu_relax();
 538                 }
 539         }
 540
 541         return 0;
 542 }
 543
 544 void qla82xx_idc_unlock(struct qla_hw_data *ha)
 545 {
 546         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 547 }
 548
 549 /*  PCI Windowing for DDR regions.  */
 550 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
 551         (((addr) <= (high)) && ((addr) >= (low)))
 552 /*
 553  * check memory access boundary.
 554  * used by test agent. support ddr access only for now
 555  */
 556 static unsigned long
 557 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
 558         unsigned long long addr, int size)
 559 {
 560         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 561                 QLA82XX_ADDR_DDR_NET_MAX) ||
 562                 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
 563                 QLA82XX_ADDR_DDR_NET_MAX) ||
 564                 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
 565                         return 0;
 566         else
 567                 return 1;
 568 }
 569
 570 int qla82xx_pci_set_window_warning_count;
 571
 572 static unsigned long
 573 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
 574 {
 575         int window;
 576         u32 win_read;
 577         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 578
 579         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 580                 QLA82XX_ADDR_DDR_NET_MAX)) {
 581                 /* DDR network side */
 582                 window = MN_WIN(addr);
 583                 ha->ddr_mn_window = window;
 584                 qla82xx_wr_32(ha,
 585                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 586                 win_read = qla82xx_rd_32(ha,
 587                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 588                 if ((win_read << 17) != window) {
 589                         ql_dbg(ql_dbg_p3p, vha, 0xb003,
 590                             "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
 591                             __func__, window, win_read);
 592                 }
 593                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 594         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 595                 QLA82XX_ADDR_OCM0_MAX)) {
 596                 unsigned int temp1;
 597                 if ((addr & 0x00ff800) == 0xff800) {
 598                         ql_log(ql_log_warn, vha, 0xb004,
 599                             "%s: QM access not handled.\n", __func__);
 600                         addr = -1UL;
 601                 }
 602                 window = OCM_WIN(addr);
 603                 ha->ddr_mn_window = window;
 604                 qla82xx_wr_32(ha,
 605                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
 606                 win_read = qla82xx_rd_32(ha,
 607                         ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
 608                 temp1 = ((window & 0x1FF) << 7) |
 609                     ((window & 0x0FFFE0000) >> 17);
 610                 if (win_read != temp1) {
 611                         ql_log(ql_log_warn, vha, 0xb005,
 612                             "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
 613                             __func__, temp1, win_read);
 614                 }
 615                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 616
 617         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 618                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 619                 /* QDR network side */
 620                 window = MS_WIN(addr);
 621                 ha->qdr_sn_window = window;
 622                 qla82xx_wr_32(ha,
 623                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
 624                 win_read = qla82xx_rd_32(ha,
 625                         ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 626                 if (win_read != window) {
 627                         ql_log(ql_log_warn, vha, 0xb006,
 628                             "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
 629                             __func__, window, win_read);
 630                 }
 631                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 632         } else {
 633                 /*
 634                  * peg gdb frequently accesses memory that doesn't exist,
 635                  * this limits the chit chat so debugging isn't slowed down.
 636                  */
 637                 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
 638                     (qla82xx_pci_set_window_warning_count%64 == 0)) {
 639                         ql_log(ql_log_warn, vha, 0xb007,
 640                             "%s: Warning:%s Unknown address range!.\n",
 641                             __func__, QLA2XXX_DRIVER_NAME);
 642                 }
 643                 addr = -1UL;
 644         }
 645         return addr;
 646 }
 647
 648 /* check if address is in the same windows as the previous access */
 649 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
 650         unsigned long long addr)
 651 {
 652         int                     window;
 653         unsigned long long      qdr_max;
 654
 655         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 656
 657         /* DDR network side */
 658         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 659                 QLA82XX_ADDR_DDR_NET_MAX))
 660                 BUG();
 661         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 662                 QLA82XX_ADDR_OCM0_MAX))
 663                 return 1;
 664         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 665                 QLA82XX_ADDR_OCM1_MAX))
 666                 return 1;
 667         else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
 668                 /* QDR network side */
 669                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 670                 if (ha->qdr_sn_window == window)
 671                         return 1;
 672         }
 673         return 0;
 674 }
 675
 676 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
 677         u64 off, void *data, int size)
 678 {
 679         unsigned long   flags;
 680         void           *addr = NULL;
 681         int             ret = 0;
 682         u64             start;
 683         uint8_t         *mem_ptr = NULL;
 684         unsigned long   mem_base;
 685         unsigned long   mem_page;
 686         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 687
 688         write_lock_irqsave(&ha->hw_lock, flags);
 689
 690         /*
 691          * If attempting to access unknown address or straddle hw windows,
 692          * do not access.
 693          */
 694         start = qla82xx_pci_set_window(ha, off);
 695         if ((start == -1UL) ||
 696                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 697                 write_unlock_irqrestore(&ha->hw_lock, flags);
 698                 ql_log(ql_log_fatal, vha, 0xb008,
 699                     "%s out of bound pci memory "
 700                     "access, offset is 0x%llx.\n",
 701                     QLA2XXX_DRIVER_NAME, off);
 702                 return -1;
 703         }
 704
 705         write_unlock_irqrestore(&ha->hw_lock, flags);
 706         mem_base = pci_resource_start(ha->pdev, 0);
 707         mem_page = start & PAGE_MASK;
 708         /* Map two pages whenever user tries to access addresses in two
 709         * consecutive pages.
 710         */
 711         if (mem_page != ((start + size - 1) & PAGE_MASK))
 712                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 713         else
 714                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 715         if (mem_ptr == 0UL) {
 716                 *(u8  *)data = 0;
 717                 return -1;
 718         }
 719         addr = mem_ptr;
 720         addr += start & (PAGE_SIZE - 1);
 721         write_lock_irqsave(&ha->hw_lock, flags);
 722
 723         switch (size) {
 724         case 1:
 725                 *(u8  *)data = readb(addr);
 726                 break;
 727         case 2:
 728                 *(u16 *)data = readw(addr);
 729                 break;
 730         case 4:
 731                 *(u32 *)data = readl(addr);
 732                 break;
 733         case 8:
 734                 *(u64 *)data = readq(addr);
 735                 break;
 736         default:
 737                 ret = -1;
 738                 break;
 739         }
 740         write_unlock_irqrestore(&ha->hw_lock, flags);
 741
 742         if (mem_ptr)
 743                 iounmap(mem_ptr);
 744         return ret;
 745 }
 746
 747 static int
 748 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
 749         u64 off, void *data, int size)
 750 {
 751         unsigned long   flags;
 752         void           *addr = NULL;
 753         int             ret = 0;
 754         u64             start;
 755         uint8_t         *mem_ptr = NULL;
 756         unsigned long   mem_base;
 757         unsigned long   mem_page;
 758         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 759
 760         write_lock_irqsave(&ha->hw_lock, flags);
 761
 762         /*
 763          * If attempting to access unknown address or straddle hw windows,
 764          * do not access.
 765          */
 766         start = qla82xx_pci_set_window(ha, off);
 767         if ((start == -1UL) ||
 768                 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 769                 write_unlock_irqrestore(&ha->hw_lock, flags);
 770                 ql_log(ql_log_fatal, vha, 0xb009,
 771                     "%s out of bount memory "
 772                     "access, offset is 0x%llx.\n",
 773                     QLA2XXX_DRIVER_NAME, off);
 774                 return -1;
 775         }
 776
 777         write_unlock_irqrestore(&ha->hw_lock, flags);
 778         mem_base = pci_resource_start(ha->pdev, 0);
 779         mem_page = start & PAGE_MASK;
 780         /* Map two pages whenever user tries to access addresses in two
 781          * consecutive pages.
 782          */
 783         if (mem_page != ((start + size - 1) & PAGE_MASK))
 784                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 785         else
 786                 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 787         if (mem_ptr == 0UL)
 788                 return -1;
 789
 790         addr = mem_ptr;
 791         addr += start & (PAGE_SIZE - 1);
 792         write_lock_irqsave(&ha->hw_lock, flags);
 793
 794         switch (size) {
 795         case 1:
 796                 writeb(*(u8  *)data, addr);
 797                 break;
 798         case 2:
 799                 writew(*(u16 *)data, addr);
 800                 break;
 801         case 4:
 802                 writel(*(u32 *)data, addr);
 803                 break;
 804         case 8:
 805                 writeq(*(u64 *)data, addr);
 806                 break;
 807         default:
 808                 ret = -1;
 809                 break;
 810         }
 811         write_unlock_irqrestore(&ha->hw_lock, flags);
 812         if (mem_ptr)
 813                 iounmap(mem_ptr);
 814         return ret;
 815 }
 816
 817 #define MTU_FUDGE_FACTOR 100
 818 static unsigned long
 819 qla82xx_decode_crb_addr(unsigned long addr)
 820 {
 821         int i;
 822         unsigned long base_addr, offset, pci_base;
 823
 824         if (!qla82xx_crb_table_initialized)
 825                 qla82xx_crb_addr_transform_setup();
 826
 827         pci_base = ADDR_ERROR;
 828         base_addr = addr & 0xfff00000;
 829         offset = addr & 0x000fffff;
 830
 831         for (i = 0; i < MAX_CRB_XFORM; i++) {
 832                 if (crb_addr_xform[i] == base_addr) {
 833                         pci_base = i << 20;
 834                         break;
 835                 }
 836         }
 837         if (pci_base == ADDR_ERROR)
 838                 return pci_base;
 839         return pci_base + offset;
 840 }
 841
 842 static long rom_max_timeout = 100;
 843 static long qla82xx_rom_lock_timeout = 100;
 844
 845 static int
 846 qla82xx_rom_lock(struct qla_hw_data *ha)
 847 {
 848         int done = 0, timeout = 0;
 849
 850         while (!done) {
 851                 /* acquire semaphore2 from PCI HW block */
 852                 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 853                 if (done == 1)
 854                         break;
 855                 if (timeout >= qla82xx_rom_lock_timeout)
 856                         return -1;
 857                 timeout++;
 858         }
 859         qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 860         return 0;
 861 }
 862
 863 static void
 864 qla82xx_rom_unlock(struct qla_hw_data *ha)
 865 {
 866         qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 867 }
 868
 869 static int
 870 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
 871 {
 872         long timeout = 0;
 873         long done = 0 ;
 874         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 875
 876         while (done == 0) {
 877                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 878                 done &= 4;
 879                 timeout++;
 880                 if (timeout >= rom_max_timeout) {
 881                         ql_dbg(ql_dbg_p3p, vha, 0xb00a,
 882                             "%s: Timeout reached waiting for rom busy.\n",
 883                             QLA2XXX_DRIVER_NAME);
 884                         return -1;
 885                 }
 886         }
 887         return 0;
 888 }
 889
 890 static int
 891 qla82xx_wait_rom_done(struct qla_hw_data *ha)
 892 {
 893         long timeout = 0;
 894         long done = 0 ;
 895         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 896
 897         while (done == 0) {
 898                 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 899                 done &= 2;
 900                 timeout++;
 901                 if (timeout >= rom_max_timeout) {
 902                         ql_dbg(ql_dbg_p3p, vha, 0xb00b,
 903                             "%s: Timeout reached waiting for rom done.\n",
 904                             QLA2XXX_DRIVER_NAME);
 905                         return -1;
 906                 }
 907         }
 908         return 0;
 909 }
 910
 911 int
 912 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
 913 {
 914         uint32_t  off_value, rval = 0;
 915
 916         WRT_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase),
 917             (off & 0xFFFF0000));
 918
 919         /* Read back value to make sure write has gone through */
 920         RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
 921         off_value  = (off & 0x0000FFFF);
 922
 923         if (flag)
 924                 WRT_REG_DWORD((void *)
 925                     (off_value + CRB_INDIRECT_2M + ha->nx_pcibase),
 926                     data);
 927         else
 928                 rval = RD_REG_DWORD((void *)
 929                     (off_value + CRB_INDIRECT_2M + ha->nx_pcibase));
 930
 931         return rval;
 932 }
 933
 934 static int
 935 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 936 {
 937         /* Dword reads to flash. */
 938         qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
 939         *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
 940             (addr & 0x0000FFFF), 0, 0);
 941
 942         return 0;
 943 }
 944
 945 static int
 946 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
 947 {
 948         int ret, loops = 0;
 949         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 950
 951         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 952                 udelay(100);
 953                 schedule();
 954                 loops++;
 955         }
 956         if (loops >= 50000) {
 957                 ql_log(ql_log_fatal, vha, 0x00b9,
 958                     "Failed to aquire SEM2 lock.\n");
 959                 return -1;
 960         }
 961         ret = qla82xx_do_rom_fast_read(ha, addr, valp);
 962         qla82xx_rom_unlock(ha);
 963         return ret;
 964 }
 965
 966 static int
 967 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
 968 {
 969         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 970         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
 971         qla82xx_wait_rom_busy(ha);
 972         if (qla82xx_wait_rom_done(ha)) {
 973                 ql_log(ql_log_warn, vha, 0xb00c,
 974                     "Error waiting for rom done.\n");
 975                 return -1;
 976         }
 977         *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 978         return 0;
 979 }
 980
 981 static int
 982 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
 983 {
 984         long timeout = 0;
 985         uint32_t done = 1 ;
 986         uint32_t val;
 987         int ret = 0;
 988         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 989
 990         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 991         while ((done != 0) && (ret == 0)) {
 992                 ret = qla82xx_read_status_reg(ha, &val);
 993                 done = val & 1;
 994                 timeout++;
 995                 udelay(10);
 996                 cond_resched();
 997                 if (timeout >= 50000) {
 998                         ql_log(ql_log_warn, vha, 0xb00d,
 999                             "Timeout reached waiting for write finish.\n");
1000                         return -1;
1001                 }
1002         }
1003         return ret;
1004 }
1005
1006 static int
1007 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1008 {
1009         uint32_t val;
1010         qla82xx_wait_rom_busy(ha);
1011         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1012         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1013         qla82xx_wait_rom_busy(ha);
1014         if (qla82xx_wait_rom_done(ha))
1015                 return -1;
1016         if (qla82xx_read_status_reg(ha, &val) != 0)
1017                 return -1;
1018         if ((val & 2) != 2)
1019                 return -1;
1020         return 0;
1021 }
1022
1023 static int
1024 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1025 {
1026         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1027         if (qla82xx_flash_set_write_enable(ha))
1028                 return -1;
1029         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1030         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1031         if (qla82xx_wait_rom_done(ha)) {
1032                 ql_log(ql_log_warn, vha, 0xb00e,
1033                     "Error waiting for rom done.\n");
1034                 return -1;
1035         }
1036         return qla82xx_flash_wait_write_finish(ha);
1037 }
1038
1039 static int
1040 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1041 {
1042         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1043         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1044         if (qla82xx_wait_rom_done(ha)) {
1045                 ql_log(ql_log_warn, vha, 0xb00f,
1046                     "Error waiting for rom done.\n");
1047                 return -1;
1048         }
1049         return 0;
1050 }
1051
1052 static int
1053 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1054 {
1055         int loops = 0;
1056         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1057
1058         while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1059                 udelay(100);
1060                 cond_resched();
1061                 loops++;
1062         }
1063         if (loops >= 50000) {
1064                 ql_log(ql_log_warn, vha, 0xb010,
1065                     "ROM lock failed.\n");
1066                 return -1;
1067         }
1068         return 0;
1069 }
1070
1071 static int
1072 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1073         uint32_t data)
1074 {
1075         int ret = 0;
1076         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1077
1078         ret = ql82xx_rom_lock_d(ha);
1079         if (ret < 0) {
1080                 ql_log(ql_log_warn, vha, 0xb011,
1081                     "ROM lock failed.\n");
1082                 return ret;
1083         }
1084
1085         if (qla82xx_flash_set_write_enable(ha))
1086                 goto done_write;
1087
1088         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1089         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1090         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1091         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1092         qla82xx_wait_rom_busy(ha);
1093         if (qla82xx_wait_rom_done(ha)) {
1094                 ql_log(ql_log_warn, vha, 0xb012,
1095                     "Error waiting for rom done.\n");
1096                 ret = -1;
1097                 goto done_write;
1098         }
1099
1100         ret = qla82xx_flash_wait_write_finish(ha);
1101
1102 done_write:
1103         qla82xx_rom_unlock(ha);
1104         return ret;
1105 }
1106
1107 /* This routine does CRB initialize sequence
1108  *  to put the ISP into operational state
1109  */
1110 static int
1111 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1112 {
1113         int addr, val;
1114         int i ;
1115         struct crb_addr_pair *buf;
1116         unsigned long off;
1117         unsigned offset, n;
1118         struct qla_hw_data *ha = vha->hw;
1119
1120         struct crb_addr_pair {
1121                 long addr;
1122                 long data;
1123         };
1124
1125         /* Halt all the indiviual PEGs and other blocks of the ISP */
1126         qla82xx_rom_lock(ha);
1127
1128         /* disable all I2Q */
1129         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1130         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1131         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1132         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1133         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1134         qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1135
1136         /* disable all niu interrupts */
1137         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1138         /* disable xge rx/tx */
1139         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1140         /* disable xg1 rx/tx */
1141         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1142         /* disable sideband mac */
1143         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1144         /* disable ap0 mac */
1145         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1146         /* disable ap1 mac */
1147         qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1148
1149         /* halt sre */
1150         val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1151         qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1152
1153         /* halt epg */
1154         qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1155
1156         /* halt timers */
1157         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1158         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1159         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1160         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1161         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1162         qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1163
1164         /* halt pegs */
1165         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1166         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1167         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1168         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1169         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1170         msleep(20);
1171
1172         /* big hammer */
1173         if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1174                 /* don't reset CAM block on reset */
1175                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1176         else
1177                 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1178         qla82xx_rom_unlock(ha);
1179
1180         /* Read the signature value from the flash.
1181          * Offset 0: Contain signature (0xcafecafe)
1182          * Offset 4: Offset and number of addr/value pairs
1183          * that present in CRB initialize sequence
1184          */
1185         if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1186             qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1187                 ql_log(ql_log_fatal, vha, 0x006e,
1188                     "Error Reading crb_init area: n: %08x.\n", n);
1189                 return -1;
1190         }
1191
1192         /* Offset in flash = lower 16 bits
1193          * Number of entries = upper 16 bits
1194          */
1195         offset = n & 0xffffU;
1196         n = (n >> 16) & 0xffffU;
1197
1198         /* number of addr/value pair should not exceed 1024 entries */
1199         if (n  >= 1024) {
1200                 ql_log(ql_log_fatal, vha, 0x0071,
1201                     "Card flash not initialized:n=0x%x.\n", n);
1202                 return -1;
1203         }
1204
1205         ql_log(ql_log_info, vha, 0x0072,
1206             "%d CRB init values found in ROM.\n", n);
1207
1208         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1209         if (buf == NULL) {
1210                 ql_log(ql_log_fatal, vha, 0x010c,
1211                     "Unable to allocate memory.\n");
1212                 return -1;
1213         }
1214
1215         for (i = 0; i < n; i++) {
1216                 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1217                     qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1218                         kfree(buf);
1219                         return -1;
1220                 }
1221
1222                 buf[i].addr = addr;
1223                 buf[i].data = val;
1224         }
1225
1226         for (i = 0; i < n; i++) {
1227                 /* Translate internal CRB initialization
1228                  * address to PCI bus address
1229                  */
1230                 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1231                     QLA82XX_PCI_CRBSPACE;
1232                 /* Not all CRB  addr/value pair to be written,
1233                  * some of them are skipped
1234                  */
1235
1236                 /* skipping cold reboot MAGIC */
1237                 if (off == QLA82XX_CAM_RAM(0x1fc))
1238                         continue;
1239
1240                 /* do not reset PCI */
1241                 if (off == (ROMUSB_GLB + 0xbc))
1242                         continue;
1243
1244                 /* skip core clock, so that firmware can increase the clock */
1245                 if (off == (ROMUSB_GLB + 0xc8))
1246                         continue;
1247
1248                 /* skip the function enable register */
1249                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1250                         continue;
1251
1252                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1253                         continue;
1254
1255                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1256                         continue;
1257
1258                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1259                         continue;
1260
1261                 if (off == ADDR_ERROR) {
1262                         ql_log(ql_log_fatal, vha, 0x0116,
1263                             "Unknow addr: 0x%08lx.\n", buf[i].addr);
1264                         continue;
1265                 }
1266
1267                 qla82xx_wr_32(ha, off, buf[i].data);
1268
1269                 /* ISP requires much bigger delay to settle down,
1270                  * else crb_window returns 0xffffffff
1271                  */
1272                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1273                         msleep(1000);
1274
1275                 /* ISP requires millisec delay between
1276                  * successive CRB register updation
1277                  */
1278                 msleep(1);
1279         }
1280
1281         kfree(buf);
1282
1283         /* Resetting the data and instruction cache */
1284         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1285         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1286         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1287
1288         /* Clear all protocol processing engines */
1289         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1290         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1291         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1292         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1293         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1294         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1295         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1296         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1297         return 0;
1298 }
1299
1300 static int
1301 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1302                 u64 off, void *data, int size)
1303 {
1304         int i, j, ret = 0, loop, sz[2], off0;
1305         int scale, shift_amount, startword;
1306         uint32_t temp;
1307         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1308
1309         /*
1310          * If not MN, go check for MS or invalid.
1311          */
1312         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1313                 mem_crb = QLA82XX_CRB_QDR_NET;
1314         else {
1315                 mem_crb = QLA82XX_CRB_DDR_NET;
1316                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1317                         return qla82xx_pci_mem_write_direct(ha,
1318                             off, data, size);
1319         }
1320
1321         off0 = off & 0x7;
1322         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1323         sz[1] = size - sz[0];
1324
1325         off8 = off & 0xfffffff0;
1326         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1327         shift_amount = 4;
1328         scale = 2;
1329         startword = (off & 0xf)/8;
1330
1331         for (i = 0; i < loop; i++) {
1332                 if (qla82xx_pci_mem_read_2M(ha, off8 +
1333                     (i << shift_amount), &word[i * scale], 8))
1334                         return -1;
1335         }
1336
1337         switch (size) {
1338         case 1:
1339                 tmpw = *((uint8_t *)data);
1340                 break;
1341         case 2:
1342                 tmpw = *((uint16_t *)data);
1343                 break;
1344         case 4:
1345                 tmpw = *((uint32_t *)data);
1346                 break;
1347         case 8:
1348         default:
1349                 tmpw = *((uint64_t *)data);
1350                 break;
1351         }
1352
1353         if (sz[0] == 8) {
1354                 word[startword] = tmpw;
1355         } else {
1356                 word[startword] &=
1357                         ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1358                 word[startword] |= tmpw << (off0 * 8);
1359         }
1360         if (sz[1] != 0) {
1361                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1362                 word[startword+1] |= tmpw >> (sz[0] * 8);
1363         }
1364
1365         for (i = 0; i < loop; i++) {
1366                 temp = off8 + (i << shift_amount);
1367                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1368                 temp = 0;
1369                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1370                 temp = word[i * scale] & 0xffffffff;
1371                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1372                 temp = (word[i * scale] >> 32) & 0xffffffff;
1373                 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1374                 temp = word[i*scale + 1] & 0xffffffff;
1375                 qla82xx_wr_32(ha, mem_crb +
1376                     MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1377                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1378                 qla82xx_wr_32(ha, mem_crb +
1379                     MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1380
1381                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1382                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1383                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1384                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1385
1386                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1387                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1388                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1389                                 break;
1390                 }
1391
1392                 if (j >= MAX_CTL_CHECK) {
1393                         if (printk_ratelimit())
1394                                 dev_err(&ha->pdev->dev,
1395                                     "failed to write through agent.\n");
1396                         ret = -1;
1397                         break;
1398                 }
1399         }
1400
1401         return ret;
1402 }
1403
1404 static int
1405 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1406 {
1407         int  i;
1408         long size = 0;
1409         long flashaddr = ha->flt_region_bootload << 2;
1410         long memaddr = BOOTLD_START;
1411         u64 data;
1412         u32 high, low;
1413         size = (IMAGE_START - BOOTLD_START) / 8;
1414
1415         for (i = 0; i < size; i++) {
1416                 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1417                     (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1418                         return -1;
1419                 }
1420                 data = ((u64)high << 32) | low ;
1421                 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1422                 flashaddr += 8;
1423                 memaddr += 8;
1424
1425                 if (i % 0x1000 == 0)
1426                         msleep(1);
1427         }
1428         udelay(100);
1429         read_lock(&ha->hw_lock);
1430         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1431         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1432         read_unlock(&ha->hw_lock);
1433         return 0;
1434 }
1435
1436 int
1437 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1438                 u64 off, void *data, int size)
1439 {
1440         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1441         int           shift_amount;
1442         uint32_t      temp;
1443         uint64_t      off8, val, mem_crb, word[2] = {0, 0};
1444
1445         /*
1446          * If not MN, go check for MS or invalid.
1447          */
1448
1449         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1450                 mem_crb = QLA82XX_CRB_QDR_NET;
1451         else {
1452                 mem_crb = QLA82XX_CRB_DDR_NET;
1453                 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1454                         return qla82xx_pci_mem_read_direct(ha,
1455                             off, data, size);
1456         }
1457
1458         off8 = off & 0xfffffff0;
1459         off0[0] = off & 0xf;
1460         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1461         shift_amount = 4;
1462         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1463         off0[1] = 0;
1464         sz[1] = size - sz[0];
1465
1466         for (i = 0; i < loop; i++) {
1467                 temp = off8 + (i << shift_amount);
1468                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1469                 temp = 0;
1470                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1471                 temp = MIU_TA_CTL_ENABLE;
1472                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1473                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1474                 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1475
1476                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1477                         temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1478                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1479                                 break;
1480                 }
1481
1482                 if (j >= MAX_CTL_CHECK) {
1483                         if (printk_ratelimit())
1484                                 dev_err(&ha->pdev->dev,
1485                                     "failed to read through agent.\n");
1486                         break;
1487                 }
1488
1489                 start = off0[i] >> 2;
1490                 end   = (off0[i] + sz[i] - 1) >> 2;
1491                 for (k = start; k <= end; k++) {
1492                         temp = qla82xx_rd_32(ha,
1493                                         mem_crb + MIU_TEST_AGT_RDDATA(k));
1494                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1495                 }
1496         }
1497
1498         if (j >= MAX_CTL_CHECK)
1499                 return -1;
1500
1501         if ((off0[0] & 7) == 0) {
1502                 val = word[0];
1503         } else {
1504                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1505                         ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1506         }
1507
1508         switch (size) {
1509         case 1:
1510                 *(uint8_t  *)data = val;
1511                 break;
1512         case 2:
1513                 *(uint16_t *)data = val;
1514                 break;
1515         case 4:
1516                 *(uint32_t *)data = val;
1517                 break;
1518         case 8:
1519                 *(uint64_t *)data = val;
1520                 break;
1521         }
1522         return 0;
1523 }
1524
1525
1526 static struct qla82xx_uri_table_desc *
1527 qla82xx_get_table_desc(const u8 *unirom, int section)
1528 {
1529         uint32_t i;
1530         struct qla82xx_uri_table_desc *directory =
1531                 (struct qla82xx_uri_table_desc *)&unirom[0];
1532         __le32 offset;
1533         __le32 tab_type;
1534         __le32 entries = cpu_to_le32(directory->num_entries);
1535
1536         for (i = 0; i < entries; i++) {
1537                 offset = cpu_to_le32(directory->findex) +
1538                     (i * cpu_to_le32(directory->entry_size));
1539                 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1540
1541                 if (tab_type == section)
1542                         return (struct qla82xx_uri_table_desc *)&unirom[offset];
1543         }
1544
1545         return NULL;
1546 }
1547
1548 static struct qla82xx_uri_data_desc *
1549 qla82xx_get_data_desc(struct qla_hw_data *ha,
1550         u32 section, u32 idx_offset)
1551 {
1552         const u8 *unirom = ha->hablob->fw->data;
1553         int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1554         struct qla82xx_uri_table_desc *tab_desc = NULL;
1555         __le32 offset;
1556
1557         tab_desc = qla82xx_get_table_desc(unirom, section);
1558         if (!tab_desc)
1559                 return NULL;
1560
1561         offset = cpu_to_le32(tab_desc->findex) +
1562             (cpu_to_le32(tab_desc->entry_size) * idx);
1563
1564         return (struct qla82xx_uri_data_desc *)&unirom[offset];
1565 }
1566
1567 static u8 *
1568 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1569 {
1570         u32 offset = BOOTLD_START;
1571         struct qla82xx_uri_data_desc *uri_desc = NULL;
1572
1573         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1574                 uri_desc = qla82xx_get_data_desc(ha,
1575                     QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1576                 if (uri_desc)
1577                         offset = cpu_to_le32(uri_desc->findex);
1578         }
1579
1580         return (u8 *)&ha->hablob->fw->data[offset];
1581 }
1582
1583 static __le32
1584 qla82xx_get_fw_size(struct qla_hw_data *ha)
1585 {
1586         struct qla82xx_uri_data_desc *uri_desc = NULL;
1587
1588         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1589                 uri_desc =  qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1590                     QLA82XX_URI_FIRMWARE_IDX_OFF);
1591                 if (uri_desc)
1592                         return cpu_to_le32(uri_desc->size);
1593         }
1594
1595         return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1596 }
1597
1598 static u8 *
1599 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1600 {
1601         u32 offset = IMAGE_START;
1602         struct qla82xx_uri_data_desc *uri_desc = NULL;
1603
1604         if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1605                 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1606                         QLA82XX_URI_FIRMWARE_IDX_OFF);
1607                 if (uri_desc)
1608                         offset = cpu_to_le32(uri_desc->findex);
1609         }
1610
1611         return (u8 *)&ha->hablob->fw->data[offset];
1612 }
1613
1614 /* PCI related functions */
1615 char *
1616 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
1617 {
1618         struct qla_hw_data *ha = vha->hw;
1619         char lwstr[6];
1620         uint16_t lnk;
1621
1622         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1623         ha->link_width = (lnk >> 4) & 0x3f;
1624
1625         strcpy(str, "PCIe (");
1626         strcat(str, "2.5Gb/s ");
1627         snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width);
1628         strcat(str, lwstr);
1629         return str;
1630 }
1631
1632 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1633 {
1634         unsigned long val = 0;
1635         u32 control;
1636
1637         switch (region) {
1638         case 0:
1639                 val = 0;
1640                 break;
1641         case 1:
1642                 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1643                 val = control + QLA82XX_MSIX_TBL_SPACE;
1644                 break;
1645         }
1646         return val;
1647 }
1648
1649
1650 int
1651 qla82xx_iospace_config(struct qla_hw_data *ha)
1652 {
1653         uint32_t len = 0;
1654
1655         if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1656                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1657                     "Failed to reserver selected regions.\n");
1658                 goto iospace_error_exit;
1659         }
1660
1661         /* Use MMIO operations for all accesses. */
1662         if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1663                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1664                     "Region #0 not an MMIO resource, aborting.\n");
1665                 goto iospace_error_exit;
1666         }
1667
1668         len = pci_resource_len(ha->pdev, 0);
1669         ha->nx_pcibase =
1670             (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1671         if (!ha->nx_pcibase) {
1672                 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1673                     "Cannot remap pcibase MMIO, aborting.\n");
1674                 pci_release_regions(ha->pdev);
1675                 goto iospace_error_exit;
1676         }
1677
1678         /* Mapping of IO base pointer */
1679         ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1680             0xbc000 + (ha->pdev->devfn << 11));
1681
1682         if (!ql2xdbwr) {
1683                 ha->nxdb_wr_ptr =
1684                     (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1685                     (ha->pdev->devfn << 12)), 4);
1686                 if (!ha->nxdb_wr_ptr) {
1687                         ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1688                             "Cannot remap MMIO, aborting.\n");
1689                         pci_release_regions(ha->pdev);
1690                         goto iospace_error_exit;
1691                 }
1692
1693                 /* Mapping of IO base pointer,
1694                  * door bell read and write pointer
1695                  */
1696                 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1697                     (ha->pdev->devfn * 8);
1698         } else {
1699                 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1700                         QLA82XX_CAMRAM_DB1 :
1701                         QLA82XX_CAMRAM_DB2);
1702         }
1703
1704         ha->max_req_queues = ha->max_rsp_queues = 1;
1705         ha->msix_count = ha->max_rsp_queues + 1;
1706         ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1707             "nx_pci_base=%p iobase=%p "
1708             "max_req_queues=%d msix_count=%d.\n",
1709             (void *)ha->nx_pcibase, ha->iobase,
1710             ha->max_req_queues, ha->msix_count);
1711         ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1712             "nx_pci_base=%p iobase=%p "
1713             "max_req_queues=%d msix_count=%d.\n",
1714             (void *)ha->nx_pcibase, ha->iobase,
1715             ha->max_req_queues, ha->msix_count);
1716         return 0;
1717
1718 iospace_error_exit:
1719         return -ENOMEM;
1720 }
1721
1722 /* GS related functions */
1723
1724 /* Initialization related functions */
1725
1726 /**
1727  * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1728  * @ha: HA context
1729  *
1730  * Returns 0 on success.
1731 */
1732 int
1733 qla82xx_pci_config(scsi_qla_host_t *vha)
1734 {
1735         struct qla_hw_data *ha = vha->hw;
1736         int ret;
1737
1738         pci_set_master(ha->pdev);
1739         ret = pci_set_mwi(ha->pdev);
1740         ha->chip_revision = ha->pdev->revision;
1741         ql_dbg(ql_dbg_init, vha, 0x0043,
1742             "Chip revision:%d.\n",
1743             ha->chip_revision);
1744         return 0;
1745 }
1746
1747 /**
1748  * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1749  * @ha: HA context
1750  *
1751  * Returns 0 on success.
1752  */
1753 void
1754 qla82xx_reset_chip(scsi_qla_host_t *vha)
1755 {
1756         struct qla_hw_data *ha = vha->hw;
1757         ha->isp_ops->disable_intrs(ha);
1758 }
1759
1760 void qla82xx_config_rings(struct scsi_qla_host *vha)
1761 {
1762         struct qla_hw_data *ha = vha->hw;
1763         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1764         struct init_cb_81xx *icb;
1765         struct req_que *req = ha->req_q_map[0];
1766         struct rsp_que *rsp = ha->rsp_q_map[0];
1767
1768         /* Setup ring parameters in initialization control block. */
1769         icb = (struct init_cb_81xx *)ha->init_cb;
1770         icb->request_q_outpointer = __constant_cpu_to_le16(0);
1771         icb->response_q_inpointer = __constant_cpu_to_le16(0);
1772         icb->request_q_length = cpu_to_le16(req->length);
1773         icb->response_q_length = cpu_to_le16(rsp->length);
1774         icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1775         icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1776         icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1777         icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1778
1779         WRT_REG_DWORD((unsigned long  __iomem *)&reg->req_q_out[0], 0);
1780         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_in[0], 0);
1781         WRT_REG_DWORD((unsigned long  __iomem *)&reg->rsp_q_out[0], 0);
1782 }
1783
1784 void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1785 {
1786         struct qla_hw_data *ha = vha->hw;
1787         vha->flags.online = 0;
1788         qla2x00_try_to_stop_firmware(vha);
1789         ha->isp_ops->disable_intrs(ha);
1790 }
1791
1792 static int
1793 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1794 {
1795         u64 *ptr64;
1796         u32 i, flashaddr, size;
1797         __le64 data;
1798
1799         size = (IMAGE_START - BOOTLD_START) / 8;
1800
1801         ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1802         flashaddr = BOOTLD_START;
1803
1804         for (i = 0; i < size; i++) {
1805                 data = cpu_to_le64(ptr64[i]);
1806                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1807                         return -EIO;
1808                 flashaddr += 8;
1809         }
1810
1811         flashaddr = FLASH_ADDR_START;
1812         size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1813         ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1814
1815         for (i = 0; i < size; i++) {
1816                 data = cpu_to_le64(ptr64[i]);
1817
1818                 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1819                         return -EIO;
1820                 flashaddr += 8;
1821         }
1822         udelay(100);
1823
1824         /* Write a magic value to CAMRAM register
1825          * at a specified offset to indicate
1826          * that all data is written and
1827          * ready for firmware to initialize.
1828          */
1829         qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1830
1831         read_lock(&ha->hw_lock);
1832         qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1833         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1834         read_unlock(&ha->hw_lock);
1835         return 0;
1836 }
1837
1838 static int
1839 qla82xx_set_product_offset(struct qla_hw_data *ha)
1840 {
1841         struct qla82xx_uri_table_desc *ptab_desc = NULL;
1842         const uint8_t *unirom = ha->hablob->fw->data;
1843         uint32_t i;
1844         __le32 entries;
1845         __le32 flags, file_chiprev, offset;
1846         uint8_t chiprev = ha->chip_revision;
1847         /* Hardcoding mn_present flag for P3P */
1848         int mn_present = 0;
1849         uint32_t flagbit;
1850
1851         ptab_desc = qla82xx_get_table_desc(unirom,
1852                  QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1853        if (!ptab_desc)
1854                 return -1;
1855
1856         entries = cpu_to_le32(ptab_desc->num_entries);
1857
1858         for (i = 0; i < entries; i++) {
1859                 offset = cpu_to_le32(ptab_desc->findex) +
1860                         (i * cpu_to_le32(ptab_desc->entry_size));
1861                 flags = cpu_to_le32(*((int *)&unirom[offset] +
1862                         QLA82XX_URI_FLAGS_OFF));
1863                 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1864                         QLA82XX_URI_CHIP_REV_OFF));
1865
1866                 flagbit = mn_present ? 1 : 2;
1867
1868                 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1869                         ha->file_prd_off = offset;
1870                         return 0;
1871                 }
1872         }
1873         return -1;
1874 }
1875
1876 int
1877 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1878 {
1879         __le32 val;
1880         uint32_t min_size;
1881         struct qla_hw_data *ha = vha->hw;
1882         const struct firmware *fw = ha->hablob->fw;
1883
1884         ha->fw_type = fw_type;
1885
1886         if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1887                 if (qla82xx_set_product_offset(ha))
1888                         return -EINVAL;
1889
1890                 min_size = QLA82XX_URI_FW_MIN_SIZE;
1891         } else {
1892                 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1893                 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1894                         return -EINVAL;
1895
1896                 min_size = QLA82XX_FW_MIN_SIZE;
1897         }
1898
1899         if (fw->size < min_size)
1900                 return -EINVAL;
1901         return 0;
1902 }
1903
1904 static int
1905 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1906 {
1907         u32 val = 0;
1908         int retries = 60;
1909         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1910
1911         do {
1912                 read_lock(&ha->hw_lock);
1913                 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1914                 read_unlock(&ha->hw_lock);
1915
1916                 switch (val) {
1917                 case PHAN_INITIALIZE_COMPLETE:
1918                 case PHAN_INITIALIZE_ACK:
1919                         return QLA_SUCCESS;
1920                 case PHAN_INITIALIZE_FAILED:
1921                         break;
1922                 default:
1923                         break;
1924                 }
1925                 ql_log(ql_log_info, vha, 0x00a8,
1926                     "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1927                     val, retries);
1928
1929                 msleep(500);
1930
1931         } while (--retries);
1932
1933         ql_log(ql_log_fatal, vha, 0x00a9,
1934             "Cmd Peg initialization failed: 0x%x.\n", val);
1935
1936         val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1937         read_lock(&ha->hw_lock);
1938         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1939         read_unlock(&ha->hw_lock);
1940         return QLA_FUNCTION_FAILED;
1941 }
1942
1943 static int
1944 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1945 {
1946         u32 val = 0;
1947         int retries = 60;
1948         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1949
1950         do {
1951                 read_lock(&ha->hw_lock);
1952                 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1953                 read_unlock(&ha->hw_lock);
1954
1955                 switch (val) {
1956                 case PHAN_INITIALIZE_COMPLETE:
1957                 case PHAN_INITIALIZE_ACK:
1958                         return QLA_SUCCESS;
1959                 case PHAN_INITIALIZE_FAILED:
1960                         break;
1961                 default:
1962                         break;
1963                 }
1964                 ql_log(ql_log_info, vha, 0x00ab,
1965                     "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1966                     val, retries);
1967
1968                 msleep(500);
1969
1970         } while (--retries);
1971
1972         ql_log(ql_log_fatal, vha, 0x00ac,
1973             "Rcv Peg initializatin failed: 0x%x.\n", val);
1974         read_lock(&ha->hw_lock);
1975         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1976         read_unlock(&ha->hw_lock);
1977         return QLA_FUNCTION_FAILED;
1978 }
1979
1980 /* ISR related functions */
1981 uint32_t qla82xx_isr_int_target_mask_enable[8] = {
1982         ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
1983         ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
1984         ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
1985         ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
1986 };
1987
1988 uint32_t qla82xx_isr_int_target_status[8] = {
1989         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
1990         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
1991         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
1992         ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
1993 };
1994
1995 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1996         QLA82XX_LEGACY_INTR_CONFIG;
1997
1998 /*
1999  * qla82xx_mbx_completion() - Process mailbox command completions.
2000  * @ha: SCSI driver HA context
2001  * @mb0: Mailbox0 register
2002  */
2003 static void
2004 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
2005 {
2006         uint16_t        cnt;
2007         uint16_t __iomem *wptr;
2008         struct qla_hw_data *ha = vha->hw;
2009         struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
2010         wptr = (uint16_t __iomem *)&reg->mailbox_out[1];
2011
2012         /* Load return mailbox registers. */
2013         ha->flags.mbox_int = 1;
2014         ha->mailbox_out[0] = mb0;
2015
2016         for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2017                 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2018                 wptr++;
2019         }
2020
2021         if (!ha->mcp)
2022                 ql_dbg(ql_dbg_async, vha, 0x5053,
2023                     "MBX pointer ERROR.\n");
2024 }
2025
2026 /*
2027  * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2028  * @irq:
2029  * @dev_id: SCSI driver HA context
2030  * @regs:
2031  *
2032  * Called by system whenever the host adapter generates an interrupt.
2033  *
2034  * Returns handled flag.
2035  */
2036 irqreturn_t
2037 qla82xx_intr_handler(int irq, void *dev_id)
2038 {
2039         scsi_qla_host_t *vha;
2040         struct qla_hw_data *ha;
2041         struct rsp_que *rsp;
2042         struct device_reg_82xx __iomem *reg;
2043         int status = 0, status1 = 0;
2044         unsigned long   flags;
2045         unsigned long   iter;
2046         uint32_t        stat = 0;
2047         uint16_t        mb[4];
2048
2049         rsp = (struct rsp_que *) dev_id;
2050         if (!rsp) {
2051                 ql_log(ql_log_info, NULL, 0xb053,
2052                     "%s: NULL response queue pointer.\n", __func__);
2053                 return IRQ_NONE;
2054         }
2055         ha = rsp->hw;
2056
2057         if (!ha->flags.msi_enabled) {
2058                 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2059                 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2060                         return IRQ_NONE;
2061
2062                 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2063                 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2064                         return IRQ_NONE;
2065         }
2066
2067         /* clear the interrupt */
2068         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2069
2070         /* read twice to ensure write is flushed */
2071         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2072         qla82xx_rd_32(ha, ISR_INT_VECTOR);
2073
2074         reg = &ha->iobase->isp82;
2075
2076         spin_lock_irqsave(&ha->hardware_lock, flags);
2077         vha = pci_get_drvdata(ha->pdev);
2078         for (iter = 1; iter--; ) {
2079
2080                 if (RD_REG_DWORD(&reg->host_int)) {
2081                         stat = RD_REG_DWORD(&reg->host_status);
2082
2083                         switch (stat & 0xff) {
2084                         case 0x1:
2085                         case 0x2:
2086                         case 0x10:
2087                         case 0x11:
2088                                 qla82xx_mbx_completion(vha, MSW(stat));
2089                                 status |= MBX_INTERRUPT;
2090                                 break;
2091                         case 0x12:
2092                                 mb[0] = MSW(stat);
2093                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2094                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2095                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2096                                 qla2x00_async_event(vha, rsp, mb);
2097                                 break;
2098                         case 0x13:
2099                                 qla24xx_process_response_queue(vha, rsp);
2100                                 break;
2101                         default:
2102                                 ql_dbg(ql_dbg_async, vha, 0x5054,
2103                                     "Unrecognized interrupt type (%d).\n",
2104                                     stat & 0xff);
2105                                 break;
2106                         }
2107                 }
2108                 WRT_REG_DWORD(&reg->host_int, 0);
2109         }
2110         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2111         if (!ha->flags.msi_enabled)
2112                 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2113
2114 #ifdef QL_DEBUG_LEVEL_17
2115         if (!irq && ha->flags.eeh_busy)
2116                 ql_log(ql_log_warn, vha, 0x503d,
2117                     "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2118                     status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2119 #endif
2120
2121         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2122             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2123                 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2124                 complete(&ha->mbx_intr_comp);
2125         }
2126         return IRQ_HANDLED;
2127 }
2128
2129 irqreturn_t
2130 qla82xx_msix_default(int irq, void *dev_id)
2131 {
2132         scsi_qla_host_t *vha;
2133         struct qla_hw_data *ha;
2134         struct rsp_que *rsp;
2135         struct device_reg_82xx __iomem *reg;
2136         int status = 0;
2137         unsigned long flags;
2138         uint32_t stat = 0;
2139         uint16_t mb[4];
2140
2141         rsp = (struct rsp_que *) dev_id;
2142         if (!rsp) {
2143                 printk(KERN_INFO
2144                         "%s(): NULL response queue pointer.\n", __func__);
2145                 return IRQ_NONE;
2146         }
2147         ha = rsp->hw;
2148
2149         reg = &ha->iobase->isp82;
2150
2151         spin_lock_irqsave(&ha->hardware_lock, flags);
2152         vha = pci_get_drvdata(ha->pdev);
2153         do {
2154                 if (RD_REG_DWORD(&reg->host_int)) {
2155                         stat = RD_REG_DWORD(&reg->host_status);
2156
2157                         switch (stat & 0xff) {
2158                         case 0x1:
2159                         case 0x2:
2160                         case 0x10:
2161                         case 0x11:
2162                                 qla82xx_mbx_completion(vha, MSW(stat));
2163                                 status |= MBX_INTERRUPT;
2164                                 break;
2165                         case 0x12:
2166                                 mb[0] = MSW(stat);
2167                                 mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2168                                 mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2169                                 mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2170                                 qla2x00_async_event(vha, rsp, mb);
2171                                 break;
2172                         case 0x13:
2173                                 qla24xx_process_response_queue(vha, rsp);
2174                                 break;
2175                         default:
2176                                 ql_dbg(ql_dbg_async, vha, 0x5041,
2177                                     "Unrecognized interrupt type (%d).\n",
2178                                     stat & 0xff);
2179                                 break;
2180                         }
2181                 }
2182                 WRT_REG_DWORD(&reg->host_int, 0);
2183         } while (0);
2184
2185         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2186
2187 #ifdef QL_DEBUG_LEVEL_17
2188         if (!irq && ha->flags.eeh_busy)
2189                 ql_log(ql_log_warn, vha, 0x5044,
2190                     "isr:status %x, cmd_flags %lx, mbox_int %x, stat %x.\n",
2191                     status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2192 #endif
2193
2194         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2195                 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2196                         set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2197                         complete(&ha->mbx_intr_comp);
2198         }
2199         return IRQ_HANDLED;
2200 }
2201
2202 irqreturn_t
2203 qla82xx_msix_rsp_q(int irq, void *dev_id)
2204 {
2205         scsi_qla_host_t *vha;
2206         struct qla_hw_data *ha;
2207         struct rsp_que *rsp;
2208         struct device_reg_82xx __iomem *reg;
2209         unsigned long flags;
2210
2211         rsp = (struct rsp_que *) dev_id;
2212         if (!rsp) {
2213                 printk(KERN_INFO
2214                         "%s(): NULL response queue pointer.\n", __func__);
2215                 return IRQ_NONE;
2216         }
2217
2218         ha = rsp->hw;
2219         reg = &ha->iobase->isp82;
2220         spin_lock_irqsave(&ha->hardware_lock, flags);
2221         vha = pci_get_drvdata(ha->pdev);
2222         qla24xx_process_response_queue(vha, rsp);
2223         WRT_REG_DWORD(&reg->host_int, 0);
2224         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2225         return IRQ_HANDLED;
2226 }
2227
2228 void
2229 qla82xx_poll(int irq, void *dev_id)
2230 {
2231         scsi_qla_host_t *vha;
2232         struct qla_hw_data *ha;
2233         struct rsp_que *rsp;
2234         struct device_reg_82xx __iomem *reg;
2235         int status = 0;
2236         uint32_t stat;
2237         uint16_t mb[4];
2238         unsigned long flags;
2239
2240         rsp = (struct rsp_que *) dev_id;
2241         if (!rsp) {
2242                 printk(KERN_INFO
2243                         "%s(): NULL response queue pointer.\n", __func__);
2244                 return;
2245         }
2246         ha = rsp->hw;
2247
2248         reg = &ha->iobase->isp82;
2249         spin_lock_irqsave(&ha->hardware_lock, flags);
2250         vha = pci_get_drvdata(ha->pdev);
2251
2252         if (RD_REG_DWORD(&reg->host_int)) {
2253                 stat = RD_REG_DWORD(&reg->host_status);
2254                 switch (stat & 0xff) {
2255                 case 0x1:
2256                 case 0x2:
2257                 case 0x10:
2258                 case 0x11:
2259                         qla82xx_mbx_completion(vha, MSW(stat));
2260                         status |= MBX_INTERRUPT;
2261                         break;
2262                 case 0x12:
2263                         mb[0] = MSW(stat);
2264                         mb[1] = RD_REG_WORD(&reg->mailbox_out[1]);
2265                         mb[2] = RD_REG_WORD(&reg->mailbox_out[2]);
2266                         mb[3] = RD_REG_WORD(&reg->mailbox_out[3]);
2267                         qla2x00_async_event(vha, rsp, mb);
2268                         break;
2269                 case 0x13:
2270                         qla24xx_process_response_queue(vha, rsp);
2271                         break;
2272                 default:
2273                         ql_dbg(ql_dbg_p3p, vha, 0xb013,
2274                             "Unrecognized interrupt type (%d).\n",
2275                             stat * 0xff);
2276                         break;
2277                 }
2278         }
2279         WRT_REG_DWORD(&reg->host_int, 0);
2280         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2281 }
2282
2283 void
2284 qla82xx_enable_intrs(struct qla_hw_data *ha)
2285 {
2286         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2287         qla82xx_mbx_intr_enable(vha);
2288         spin_lock_irq(&ha->hardware_lock);
2289         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2290         spin_unlock_irq(&ha->hardware_lock);
2291         ha->interrupts_on = 1;
2292 }
2293
2294 void
2295 qla82xx_disable_intrs(struct qla_hw_data *ha)
2296 {
2297         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2298         qla82xx_mbx_intr_disable(vha);
2299         spin_lock_irq(&ha->hardware_lock);
2300         qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2301         spin_unlock_irq(&ha->hardware_lock);
2302         ha->interrupts_on = 0;
2303 }
2304
2305 void qla82xx_init_flags(struct qla_hw_data *ha)
2306 {
2307         struct qla82xx_legacy_intr_set *nx_legacy_intr;
2308
2309         /* ISP 8021 initializations */
2310         rwlock_init(&ha->hw_lock);
2311         ha->qdr_sn_window = -1;
2312         ha->ddr_mn_window = -1;
2313         ha->curr_window = 255;
2314         ha->portnum = PCI_FUNC(ha->pdev->devfn);
2315         nx_legacy_intr = &legacy_intr[ha->portnum];
2316         ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2317         ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2318         ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2319         ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2320 }
2321
2322 inline void
2323 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2324 {
2325         uint32_t drv_active;
2326         struct qla_hw_data *ha = vha->hw;
2327
2328         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2329
2330         /* If reset value is all FF's, initialize DRV_ACTIVE */
2331         if (drv_active == 0xffffffff) {
2332                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2333                         QLA82XX_DRV_NOT_ACTIVE);
2334                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2335         }
2336         drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2337         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2338 }
2339
2340 inline void
2341 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2342 {
2343         uint32_t drv_active;
2344
2345         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2346         drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2347         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2348 }
2349
2350 static inline int
2351 qla82xx_need_reset(struct qla_hw_data *ha)
2352 {
2353         uint32_t drv_state;
2354         int rval;
2355
2356         if (ha->flags.isp82xx_reset_owner)
2357                 return 1;
2358         else {
2359                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2360                 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2361                 return rval;
2362         }
2363 }
2364
2365 static inline void
2366 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2367 {
2368         uint32_t drv_state;
2369         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2370
2371         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2372
2373         /* If reset value is all FF's, initialize DRV_STATE */
2374         if (drv_state == 0xffffffff) {
2375                 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2376                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2377         }
2378         drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2379         ql_dbg(ql_dbg_init, vha, 0x00bb,
2380             "drv_state = 0x%08x.\n", drv_state);
2381         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2382 }
2383
2384 static inline void
2385 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2386 {
2387         uint32_t drv_state;
2388
2389         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2390         drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2391         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2392 }
2393
2394 static inline void
2395 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2396 {
2397         uint32_t qsnt_state;
2398
2399         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2400         qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2401         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2402 }
2403
2404 void
2405 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2406 {
2407         struct qla_hw_data *ha = vha->hw;
2408         uint32_t qsnt_state;
2409
2410         qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2411         qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2412         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2413 }
2414
2415 static int
2416 qla82xx_load_fw(scsi_qla_host_t *vha)
2417 {
2418         int rst;
2419         struct fw_blob *blob;
2420         struct qla_hw_data *ha = vha->hw;
2421
2422         if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2423                 ql_log(ql_log_fatal, vha, 0x009f,
2424                     "Error during CRB initialization.\n");
2425                 return QLA_FUNCTION_FAILED;
2426         }
2427         udelay(500);
2428
2429         /* Bring QM and CAMRAM out of reset */
2430         rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2431         rst &= ~((1 << 28) | (1 << 24));
2432         qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2433
2434         /*
2435          * FW Load priority:
2436          * 1) Operational firmware residing in flash.
2437          * 2) Firmware via request-firmware interface (.bin file).
2438          */
2439         if (ql2xfwloadbin == 2)
2440                 goto try_blob_fw;
2441
2442         ql_log(ql_log_info, vha, 0x00a0,
2443             "Attempting to load firmware from flash.\n");
2444
2445         if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2446                 ql_log(ql_log_info, vha, 0x00a1,
2447                     "Firmware loaded successfully from flash.\n");
2448                 return QLA_SUCCESS;
2449         } else {
2450                 ql_log(ql_log_warn, vha, 0x0108,
2451                     "Firmware load from flash failed.\n");
2452         }
2453
2454 try_blob_fw:
2455         ql_log(ql_log_info, vha, 0x00a2,
2456             "Attempting to load firmware from blob.\n");
2457
2458         /* Load firmware blob. */
2459         blob = ha->hablob = qla2x00_request_firmware(vha);
2460         if (!blob) {
2461                 ql_log(ql_log_fatal, vha, 0x00a3,
2462                     "Firmware image not present.\n");
2463                 goto fw_load_failed;
2464         }
2465
2466         /* Validating firmware blob */
2467         if (qla82xx_validate_firmware_blob(vha,
2468                 QLA82XX_FLASH_ROMIMAGE)) {
2469                 /* Fallback to URI format */
2470                 if (qla82xx_validate_firmware_blob(vha,
2471                         QLA82XX_UNIFIED_ROMIMAGE)) {
2472                         ql_log(ql_log_fatal, vha, 0x00a4,
2473                             "No valid firmware image found.\n");
2474                         return QLA_FUNCTION_FAILED;
2475                 }
2476         }
2477
2478         if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2479                 ql_log(ql_log_info, vha, 0x00a5,
2480                     "Firmware loaded successfully from binary blob.\n");
2481                 return QLA_SUCCESS;
2482         } else {
2483                 ql_log(ql_log_fatal, vha, 0x00a6,
2484                     "Firmware load failed for binary blob.\n");
2485                 blob->fw = NULL;
2486                 blob = NULL;
2487                 goto fw_load_failed;
2488         }
2489         return QLA_SUCCESS;
2490
2491 fw_load_failed:
2492         return QLA_FUNCTION_FAILED;
2493 }
2494
2495 int
2496 qla82xx_start_firmware(scsi_qla_host_t *vha)
2497 {
2498         uint16_t      lnk;
2499         struct qla_hw_data *ha = vha->hw;
2500
2501         /* scrub dma mask expansion register */
2502         qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2503
2504         /* Put both the PEG CMD and RCV PEG to default state
2505          * of 0 before resetting the hardware
2506          */
2507         qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2508         qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2509
2510         /* Overwrite stale initialization register values */
2511         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2512         qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2513
2514         if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2515                 ql_log(ql_log_fatal, vha, 0x00a7,
2516                     "Error trying to start fw.\n");
2517                 return QLA_FUNCTION_FAILED;
2518         }
2519
2520         /* Handshake with the card before we register the devices. */
2521         if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2522                 ql_log(ql_log_fatal, vha, 0x00aa,
2523                     "Error during card handshake.\n");
2524                 return QLA_FUNCTION_FAILED;
2525         }
2526
2527         /* Negotiated Link width */
2528         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2529         ha->link_width = (lnk >> 4) & 0x3f;
2530
2531         /* Synchronize with Receive peg */
2532         return qla82xx_check_rcvpeg_state(ha);
2533 }
2534
2535 static uint32_t *
2536 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2537         uint32_t length)
2538 {
2539         uint32_t i;
2540         uint32_t val;
2541         struct qla_hw_data *ha = vha->hw;
2542
2543         /* Dword reads to flash. */
2544         for (i = 0; i < length/4; i++, faddr += 4) {
2545                 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2546                         ql_log(ql_log_warn, vha, 0x0106,
2547                             "Do ROM fast read failed.\n");
2548                         goto done_read;
2549                 }
2550                 dwptr[i] = __constant_cpu_to_le32(val);
2551         }
2552 done_read:
2553         return dwptr;
2554 }
2555
2556 static int
2557 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2558 {
2559         int ret;
2560         uint32_t val;
2561         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2562
2563         ret = ql82xx_rom_lock_d(ha);
2564         if (ret < 0) {
2565                 ql_log(ql_log_warn, vha, 0xb014,
2566                     "ROM Lock failed.\n");
2567                 return ret;
2568         }
2569
2570         ret = qla82xx_read_status_reg(ha, &val);
2571         if (ret < 0)
2572                 goto done_unprotect;
2573
2574         val &= ~(BLOCK_PROTECT_BITS << 2);
2575         ret = qla82xx_write_status_reg(ha, val);
2576         if (ret < 0) {
2577                 val |= (BLOCK_PROTECT_BITS << 2);
2578                 qla82xx_write_status_reg(ha, val);
2579         }
2580
2581         if (qla82xx_write_disable_flash(ha) != 0)
2582                 ql_log(ql_log_warn, vha, 0xb015,
2583                     "Write disable failed.\n");
2584
2585 done_unprotect:
2586         qla82xx_rom_unlock(ha);
2587         return ret;
2588 }
2589
2590 static int
2591 qla82xx_protect_flash(struct qla_hw_data *ha)
2592 {
2593         int ret;
2594         uint32_t val;
2595         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2596
2597         ret = ql82xx_rom_lock_d(ha);
2598         if (ret < 0) {
2599                 ql_log(ql_log_warn, vha, 0xb016,
2600                     "ROM Lock failed.\n");
2601                 return ret;
2602         }
2603
2604         ret = qla82xx_read_status_reg(ha, &val);
2605         if (ret < 0)
2606                 goto done_protect;
2607
2608         val |= (BLOCK_PROTECT_BITS << 2);
2609         /* LOCK all sectors */
2610         ret = qla82xx_write_status_reg(ha, val);
2611         if (ret < 0)
2612                 ql_log(ql_log_warn, vha, 0xb017,
2613                     "Write status register failed.\n");
2614
2615         if (qla82xx_write_disable_flash(ha) != 0)
2616                 ql_log(ql_log_warn, vha, 0xb018,
2617                     "Write disable failed.\n");
2618 done_protect:
2619         qla82xx_rom_unlock(ha);
2620         return ret;
2621 }
2622
2623 static int
2624 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2625 {
2626         int ret = 0;
2627         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2628
2629         ret = ql82xx_rom_lock_d(ha);
2630         if (ret < 0) {
2631                 ql_log(ql_log_warn, vha, 0xb019,
2632                     "ROM Lock failed.\n");
2633                 return ret;
2634         }
2635
2636         qla82xx_flash_set_write_enable(ha);
2637         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2638         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2639         qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2640
2641         if (qla82xx_wait_rom_done(ha)) {
2642                 ql_log(ql_log_warn, vha, 0xb01a,
2643                     "Error waiting for rom done.\n");
2644                 ret = -1;
2645                 goto done;
2646         }
2647         ret = qla82xx_flash_wait_write_finish(ha);
2648 done:
2649         qla82xx_rom_unlock(ha);
2650         return ret;
2651 }
2652
2653 /*
2654  * Address and length are byte address
2655  */
2656 uint8_t *
2657 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2658         uint32_t offset, uint32_t length)
2659 {
2660         scsi_block_requests(vha->host);
2661         qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2662         scsi_unblock_requests(vha->host);
2663         return buf;
2664 }
2665
2666 static int
2667 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2668         uint32_t faddr, uint32_t dwords)
2669 {
2670         int ret;
2671         uint32_t liter;
2672         uint32_t sec_mask, rest_addr;
2673         dma_addr_t optrom_dma;
2674         void *optrom = NULL;
2675         int page_mode = 0;
2676         struct qla_hw_data *ha = vha->hw;
2677
2678         ret = -1;
2679
2680         /* Prepare burst-capable write on supported ISPs. */
2681         if (page_mode && !(faddr & 0xfff) &&
2682             dwords > OPTROM_BURST_DWORDS) {
2683                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2684                     &optrom_dma, GFP_KERNEL);
2685                 if (!optrom) {
2686                         ql_log(ql_log_warn, vha, 0xb01b,
2687                             "Unable to allocate memory "
2688                             "for optrom burst write (%x KB).\n",
2689                             OPTROM_BURST_SIZE / 1024);
2690                 }
2691         }
2692
2693         rest_addr = ha->fdt_block_size - 1;
2694         sec_mask = ~rest_addr;
2695
2696         ret = qla82xx_unprotect_flash(ha);
2697         if (ret) {
2698                 ql_log(ql_log_warn, vha, 0xb01c,
2699                     "Unable to unprotect flash for update.\n");
2700                 goto write_done;
2701         }
2702
2703         for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2704                 /* Are we at the beginning of a sector? */
2705                 if ((faddr & rest_addr) == 0) {
2706
2707                         ret = qla82xx_erase_sector(ha, faddr);
2708                         if (ret) {
2709                                 ql_log(ql_log_warn, vha, 0xb01d,
2710                                     "Unable to erase sector: address=%x.\n",
2711                                     faddr);
2712                                 break;
2713                         }
2714                 }
2715
2716                 /* Go with burst-write. */
2717                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2718                         /* Copy data to DMA'ble buffer. */
2719                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2720
2721                         ret = qla2x00_load_ram(vha, optrom_dma,
2722                             (ha->flash_data_off | faddr),
2723                             OPTROM_BURST_DWORDS);
2724                         if (ret != QLA_SUCCESS) {
2725                                 ql_log(ql_log_warn, vha, 0xb01e,
2726                                     "Unable to burst-write optrom segment "
2727                                     "(%x/%x/%llx).\n", ret,
2728                                     (ha->flash_data_off | faddr),
2729                                     (unsigned long long)optrom_dma);
2730                                 ql_log(ql_log_warn, vha, 0xb01f,
2731                                     "Reverting to slow-write.\n");
2732
2733                                 dma_free_coherent(&ha->pdev->dev,
2734                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2735                                 optrom = NULL;
2736                         } else {
2737                                 liter += OPTROM_BURST_DWORDS - 1;
2738                                 faddr += OPTROM_BURST_DWORDS - 1;
2739                                 dwptr += OPTROM_BURST_DWORDS - 1;
2740                                 continue;
2741                         }
2742                 }
2743
2744                 ret = qla82xx_write_flash_dword(ha, faddr,
2745                     cpu_to_le32(*dwptr));
2746                 if (ret) {
2747                         ql_dbg(ql_dbg_p3p, vha, 0xb020,
2748                             "Unable to program flash address=%x data=%x.\n",
2749                             faddr, *dwptr);
2750                         break;
2751                 }
2752         }
2753
2754         ret = qla82xx_protect_flash(ha);
2755         if (ret)
2756                 ql_log(ql_log_warn, vha, 0xb021,
2757                     "Unable to protect flash after update.\n");
2758 write_done:
2759         if (optrom)
2760                 dma_free_coherent(&ha->pdev->dev,
2761                     OPTROM_BURST_SIZE, optrom, optrom_dma);
2762         return ret;
2763 }
2764
2765 int
2766 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2767         uint32_t offset, uint32_t length)
2768 {
2769         int rval;
2770
2771         /* Suspend HBA. */
2772         scsi_block_requests(vha->host);
2773         rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2774                 length >> 2);
2775         scsi_unblock_requests(vha->host);
2776
2777         /* Convert return ISP82xx to generic */
2778         if (rval)
2779                 rval = QLA_FUNCTION_FAILED;
2780         else
2781                 rval = QLA_SUCCESS;
2782         return rval;
2783 }
2784
2785 void
2786 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2787 {
2788         struct qla_hw_data *ha = vha->hw;
2789         struct req_que *req = ha->req_q_map[0];
2790         struct device_reg_82xx __iomem *reg;
2791         uint32_t dbval;
2792
2793         /* Adjust ring index. */
2794         req->ring_index++;
2795         if (req->ring_index == req->length) {
2796                 req->ring_index = 0;
2797                 req->ring_ptr = req->ring;
2798         } else
2799                 req->ring_ptr++;
2800
2801         reg = &ha->iobase->isp82;
2802         dbval = 0x04 | (ha->portnum << 5);
2803
2804         dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2805         if (ql2xdbwr)
2806                 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2807         else {
2808                 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
2809                 wmb();
2810                 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2811                         WRT_REG_DWORD((unsigned long  __iomem *)ha->nxdb_wr_ptr,
2812                                 dbval);
2813                         wmb();
2814                 }
2815         }
2816 }
2817
2818 void qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2819 {
2820         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2821
2822         if (qla82xx_rom_lock(ha))
2823                 /* Someone else is holding the lock. */
2824                 ql_log(ql_log_info, vha, 0xb022,
2825                     "Resetting rom_lock.\n");
2826
2827         /*
2828          * Either we got the lock, or someone
2829          * else died while holding it.
2830          * In either case, unlock.
2831          */
2832         qla82xx_rom_unlock(ha);
2833 }
2834
2835 /*
2836  * qla82xx_device_bootstrap
2837  *    Initialize device, set DEV_READY, start fw
2838  *
2839  * Note:
2840  *      IDC lock must be held upon entry
2841  *
2842  * Return:
2843  *    Success : 0
2844  *    Failed  : 1
2845  */
2846 static int
2847 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2848 {
2849         int rval = QLA_SUCCESS;
2850         int i, timeout;
2851         uint32_t old_count, count;
2852         struct qla_hw_data *ha = vha->hw;
2853         int need_reset = 0, peg_stuck = 1;
2854
2855         need_reset = qla82xx_need_reset(ha);
2856
2857         old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2858
2859         for (i = 0; i < 10; i++) {
2860                 timeout = msleep_interruptible(200);
2861                 if (timeout) {
2862                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2863                                 QLA82XX_DEV_FAILED);
2864                         return QLA_FUNCTION_FAILED;
2865                 }
2866
2867                 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2868                 if (count != old_count)
2869                         peg_stuck = 0;
2870         }
2871
2872         if (need_reset) {
2873                 /* We are trying to perform a recovery here. */
2874                 if (peg_stuck)
2875                         qla82xx_rom_lock_recovery(ha);
2876                 goto dev_initialize;
2877         } else  {
2878                 /* Start of day for this ha context. */
2879                 if (peg_stuck) {
2880                         /* Either we are the first or recovery in progress. */
2881                         qla82xx_rom_lock_recovery(ha);
2882                         goto dev_initialize;
2883                 } else
2884                         /* Firmware already running. */
2885                         goto dev_ready;
2886         }
2887
2888         return rval;
2889
2890 dev_initialize:
2891         /* set to DEV_INITIALIZING */
2892         ql_log(ql_log_info, vha, 0x009e,
2893             "HW State: INITIALIZING.\n");
2894         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
2895
2896         /* Driver that sets device state to initializating sets IDC version */
2897         qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2898
2899         qla82xx_idc_unlock(ha);
2900         rval = qla82xx_start_firmware(vha);
2901         qla82xx_idc_lock(ha);
2902
2903         if (rval != QLA_SUCCESS) {
2904                 ql_log(ql_log_fatal, vha, 0x00ad,
2905                     "HW State: FAILED.\n");
2906                 qla82xx_clear_drv_active(ha);
2907                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
2908                 return rval;
2909         }
2910
2911 dev_ready:
2912         ql_log(ql_log_info, vha, 0x00ae,
2913             "HW State: READY.\n");
2914         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
2915
2916         return QLA_SUCCESS;
2917 }
2918
2919 /*
2920 * qla82xx_need_qsnt_handler
2921 *    Code to start quiescence sequence
2922 *
2923 * Note:
2924 *      IDC lock must be held upon entry
2925 *
2926 * Return: void
2927 */
2928
2929 static void
2930 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2931 {
2932         struct qla_hw_data *ha = vha->hw;
2933         uint32_t dev_state, drv_state, drv_active;
2934         unsigned long reset_timeout;
2935
2936         if (vha->flags.online) {
2937                 /*Block any further I/O and wait for pending cmnds to complete*/
2938                 qla82xx_quiescent_state_cleanup(vha);
2939         }
2940
2941         /* Set the quiescence ready bit */
2942         qla82xx_set_qsnt_ready(ha);
2943
2944         /*wait for 30 secs for other functions to ack */
2945         reset_timeout = jiffies + (30 * HZ);
2946
2947         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2948         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2949         /* Its 2 that is written when qsnt is acked, moving one bit */
2950         drv_active = drv_active << 0x01;
2951
2952         while (drv_state != drv_active) {
2953
2954                 if (time_after_eq(jiffies, reset_timeout)) {
2955                         /* quiescence timeout, other functions didn't ack
2956                          * changing the state to DEV_READY
2957                          */
2958                         ql_log(ql_log_info, vha, 0xb023,
2959                             "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2960                             "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2961                             drv_active, drv_state);
2962                         qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2963                             QLA82XX_DEV_READY);
2964                         ql_log(ql_log_info, vha, 0xb025,
2965                             "HW State: DEV_READY.\n");
2966                         qla82xx_idc_unlock(ha);
2967                         qla2x00_perform_loop_resync(vha);
2968                         qla82xx_idc_lock(ha);
2969
2970                         qla82xx_clear_qsnt_ready(vha);
2971                         return;
2972                 }
2973
2974                 qla82xx_idc_unlock(ha);
2975                 msleep(1000);
2976                 qla82xx_idc_lock(ha);
2977
2978                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2979                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2980                 drv_active = drv_active << 0x01;
2981         }
2982         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2983         /* everyone acked so set the state to DEV_QUIESCENCE */
2984         if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) {
2985                 ql_log(ql_log_info, vha, 0xb026,
2986                     "HW State: DEV_QUIESCENT.\n");
2987                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT);
2988         }
2989 }
2990
2991 /*
2992 * qla82xx_wait_for_state_change
2993 *    Wait for device state to change from given current state
2994 *
2995 * Note:
2996 *     IDC lock must not be held upon entry
2997 *
2998 * Return:
2999 *    Changed device state.
3000 */
3001 uint32_t
3002 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
3003 {
3004         struct qla_hw_data *ha = vha->hw;
3005         uint32_t dev_state;
3006
3007         do {
3008                 msleep(1000);
3009                 qla82xx_idc_lock(ha);
3010                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3011                 qla82xx_idc_unlock(ha);
3012         } while (dev_state == curr_state);
3013
3014         return dev_state;
3015 }
3016
3017 static void
3018 qla82xx_dev_failed_handler(scsi_qla_host_t *vha)
3019 {
3020         struct qla_hw_data *ha = vha->hw;
3021
3022         /* Disable the board */
3023         ql_log(ql_log_fatal, vha, 0x00b8,
3024             "Disabling the board.\n");
3025
3026         qla82xx_idc_lock(ha);
3027         qla82xx_clear_drv_active(ha);
3028         qla82xx_idc_unlock(ha);
3029
3030         /* Set DEV_FAILED flag to disable timer */
3031         vha->device_flags |= DFLG_DEV_FAILED;
3032         qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3033         qla2x00_mark_all_devices_lost(vha, 0);
3034         vha->flags.online = 0;
3035         vha->flags.init_done = 0;
3036 }
3037
3038 /*
3039  * qla82xx_need_reset_handler
3040  *    Code to start reset sequence
3041  *
3042  * Note:
3043  *      IDC lock must be held upon entry
3044  *
3045  * Return:
3046  *    Success : 0
3047  *    Failed  : 1
3048  */
3049 static void
3050 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3051 {
3052         uint32_t dev_state, drv_state, drv_active;
3053         uint32_t active_mask = 0;
3054         unsigned long reset_timeout;
3055         struct qla_hw_data *ha = vha->hw;
3056         struct req_que *req = ha->req_q_map[0];
3057
3058         if (vha->flags.online) {
3059                 qla82xx_idc_unlock(ha);
3060                 qla2x00_abort_isp_cleanup(vha);
3061                 ha->isp_ops->get_flash_version(vha, req->ring);
3062                 ha->isp_ops->nvram_config(vha);
3063                 qla82xx_idc_lock(ha);
3064         }
3065
3066         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3067         if (!ha->flags.isp82xx_reset_owner) {
3068                 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3069                     "reset_acknowledged by 0x%x\n", ha->portnum);
3070                 qla82xx_set_rst_ready(ha);
3071         } else {
3072                 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3073                 drv_active &= active_mask;
3074                 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3075                     "active_mask: 0x%08x\n", active_mask);
3076         }
3077
3078         /* wait for 10 seconds for reset ack from all functions */
3079         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3080
3081         drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3082         drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3083         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3084
3085         ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3086             "drv_state: 0x%08x, drv_active: 0x%08x, "
3087             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3088             drv_state, drv_active, dev_state, active_mask);
3089
3090         while (drv_state != drv_active &&
3091             dev_state != QLA82XX_DEV_INITIALIZING) {
3092                 if (time_after_eq(jiffies, reset_timeout)) {
3093                         ql_log(ql_log_warn, vha, 0x00b5,
3094                             "Reset timeout.\n");
3095                         break;
3096                 }
3097                 qla82xx_idc_unlock(ha);
3098                 msleep(1000);
3099                 qla82xx_idc_lock(ha);
3100                 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3101                 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3102                 if (ha->flags.isp82xx_reset_owner)
3103                         drv_active &= active_mask;
3104                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3105         }
3106
3107         ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3108             "drv_state: 0x%08x, drv_active: 0x%08x, "
3109             "dev_state: 0x%08x, active_mask: 0x%08x\n",
3110             drv_state, drv_active, dev_state, active_mask);
3111
3112         ql_log(ql_log_info, vha, 0x00b6,
3113             "Device state is 0x%x = %s.\n",
3114             dev_state,
3115             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3116
3117         /* Force to DEV_COLD unless someone else is starting a reset */
3118         if (dev_state != QLA82XX_DEV_INITIALIZING &&
3119             dev_state != QLA82XX_DEV_COLD) {
3120                 ql_log(ql_log_info, vha, 0x00b7,
3121                     "HW State: COLD/RE-INIT.\n");
3122                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
3123                 qla82xx_set_rst_ready(ha);
3124                 if (ql2xmdenable) {
3125                         if (qla82xx_md_collect(vha))
3126                                 ql_log(ql_log_warn, vha, 0xb02c,
3127                                     "Minidump not collected.\n");
3128                 } else
3129                         ql_log(ql_log_warn, vha, 0xb04f,
3130                             "Minidump disabled.\n");
3131         }
3132 }
3133
3134 int
3135 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3136 {
3137         struct qla_hw_data *ha = vha->hw;
3138         uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3139         int rval = QLA_SUCCESS;
3140
3141         fw_major_version = ha->fw_major_version;
3142         fw_minor_version = ha->fw_minor_version;
3143         fw_subminor_version = ha->fw_subminor_version;
3144
3145         rval = qla2x00_get_fw_version(vha);
3146         if (rval != QLA_SUCCESS)
3147                 return rval;
3148
3149         if (ql2xmdenable) {
3150                 if (!ha->fw_dumped) {
3151                         if (fw_major_version != ha->fw_major_version ||
3152                             fw_minor_version != ha->fw_minor_version ||
3153                             fw_subminor_version != ha->fw_subminor_version) {
3154                                 ql_log(ql_log_info, vha, 0xb02d,
3155                                     "Firmware version differs "
3156                                     "Previous version: %d:%d:%d - "
3157                                     "New version: %d:%d:%d\n",
3158                                     fw_major_version, fw_minor_version,
3159                                     fw_subminor_version,
3160                                     ha->fw_major_version,
3161                                     ha->fw_minor_version,
3162                                     ha->fw_subminor_version);
3163                                 /* Release MiniDump resources */
3164                                 qla82xx_md_free(vha);
3165                                 /* ALlocate MiniDump resources */
3166                                 qla82xx_md_prep(vha);
3167                         }
3168                 } else
3169                         ql_log(ql_log_info, vha, 0xb02e,
3170                             "Firmware dump available to retrieve\n");
3171         }
3172         return rval;
3173 }
3174
3175
3176 int
3177 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3178 {
3179         uint32_t fw_heartbeat_counter;
3180         int status = 0;
3181
3182         fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3183                 QLA82XX_PEG_ALIVE_COUNTER);
3184         /* all 0xff, assume AER/EEH in progress, ignore */
3185         if (fw_heartbeat_counter == 0xffffffff) {
3186                 ql_dbg(ql_dbg_timer, vha, 0x6003,
3187                     "FW heartbeat counter is 0xffffffff, "
3188                     "returning status=%d.\n", status);
3189                 return status;
3190         }
3191         if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3192                 vha->seconds_since_last_heartbeat++;
3193                 /* FW not alive after 2 seconds */
3194                 if (vha->seconds_since_last_heartbeat == 2) {
3195                         vha->seconds_since_last_heartbeat = 0;
3196                         status = 1;
3197                 }
3198         } else
3199                 vha->seconds_since_last_heartbeat = 0;
3200         vha->fw_heartbeat_counter = fw_heartbeat_counter;
3201         if (status)
3202                 ql_dbg(ql_dbg_timer, vha, 0x6004,
3203                     "Returning status=%d.\n", status);
3204         return status;
3205 }
3206
3207 /*
3208  * qla82xx_device_state_handler
3209  *      Main state handler
3210  *
3211  * Note:
3212  *      IDC lock must be held upon entry
3213  *
3214  * Return:
3215  *    Success : 0
3216  *    Failed  : 1
3217  */
3218 int
3219 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3220 {
3221         uint32_t dev_state;
3222         uint32_t old_dev_state;
3223         int rval = QLA_SUCCESS;
3224         unsigned long dev_init_timeout;
3225         struct qla_hw_data *ha = vha->hw;
3226         int loopcount = 0;
3227
3228         qla82xx_idc_lock(ha);
3229         if (!vha->flags.init_done)
3230                 qla82xx_set_drv_active(vha);
3231
3232         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3233         old_dev_state = dev_state;
3234         ql_log(ql_log_info, vha, 0x009b,
3235             "Device state is 0x%x = %s.\n",
3236             dev_state,
3237             dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3238
3239         /* wait for 30 seconds for device to go ready */
3240         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3241
3242         while (1) {
3243
3244                 if (time_after_eq(jiffies, dev_init_timeout)) {
3245                         ql_log(ql_log_fatal, vha, 0x009c,
3246                             "Device init failed.\n");
3247                         rval = QLA_FUNCTION_FAILED;
3248                         break;
3249                 }
3250                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3251                 if (old_dev_state != dev_state) {
3252                         loopcount = 0;
3253                         old_dev_state = dev_state;
3254                 }
3255                 if (loopcount < 5) {
3256                         ql_log(ql_log_info, vha, 0x009d,
3257                             "Device state is 0x%x = %s.\n",
3258                             dev_state,
3259                             dev_state < MAX_STATES ? qdev_state(dev_state) :
3260                             "Unknown");
3261                 }
3262
3263                 switch (dev_state) {
3264                 case QLA82XX_DEV_READY:
3265                         ha->flags.isp82xx_reset_owner = 0;
3266                         goto exit;
3267                 case QLA82XX_DEV_COLD:
3268                         rval = qla82xx_device_bootstrap(vha);
3269                         break;
3270                 case QLA82XX_DEV_INITIALIZING:
3271                         qla82xx_idc_unlock(ha);
3272                         msleep(1000);
3273                         qla82xx_idc_lock(ha);
3274                         break;
3275                 case QLA82XX_DEV_NEED_RESET:
3276                         if (!ql2xdontresethba)
3277                                 qla82xx_need_reset_handler(vha);
3278                         else {
3279                                 qla82xx_idc_unlock(ha);
3280                                 msleep(1000);
3281                                 qla82xx_idc_lock(ha);
3282                         }
3283                         dev_init_timeout = jiffies +
3284                             (ha->nx_dev_init_timeout * HZ);
3285                         break;
3286                 case QLA82XX_DEV_NEED_QUIESCENT:
3287                         qla82xx_need_qsnt_handler(vha);
3288                         /* Reset timeout value after quiescence handler */
3289                         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\
3290                                                          * HZ);
3291                         break;
3292                 case QLA82XX_DEV_QUIESCENT:
3293                         /* Owner will exit and other will wait for the state
3294                          * to get changed
3295                          */
3296                         if (ha->flags.quiesce_owner)
3297                                 goto exit;
3298
3299                         qla82xx_idc_unlock(ha);
3300                         msleep(1000);
3301                         qla82xx_idc_lock(ha);
3302
3303                         /* Reset timeout value after quiescence handler */
3304                         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\
3305                                                          * HZ);
3306                         break;
3307                 case QLA82XX_DEV_FAILED:
3308                         qla82xx_dev_failed_handler(vha);
3309                         rval = QLA_FUNCTION_FAILED;
3310                         goto exit;
3311                 default:
3312                         qla82xx_idc_unlock(ha);
3313                         msleep(1000);
3314                         qla82xx_idc_lock(ha);
3315                 }
3316                 loopcount++;
3317         }
3318 exit:
3319         qla82xx_idc_unlock(ha);
3320         return rval;
3321 }
3322
3323 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3324 {
3325         uint32_t temp, temp_state, temp_val;
3326         struct qla_hw_data *ha = vha->hw;
3327
3328         temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3329         temp_state = qla82xx_get_temp_state(temp);
3330         temp_val = qla82xx_get_temp_val(temp);
3331
3332         if (temp_state == QLA82XX_TEMP_PANIC) {
3333                 ql_log(ql_log_warn, vha, 0x600e,
3334                     "Device temperature %d degrees C exceeds "
3335                     " maximum allowed. Hardware has been shut down.\n",
3336                     temp_val);
3337                 return 1;
3338         } else if (temp_state == QLA82XX_TEMP_WARN) {
3339                 ql_log(ql_log_warn, vha, 0x600f,
3340                     "Device temperature %d degrees C exceeds "
3341                     "operating range. Immediate action needed.\n",
3342                     temp_val);
3343         }
3344         return 0;
3345 }
3346
3347 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3348 {
3349         struct qla_hw_data *ha = vha->hw;
3350
3351         if (ha->flags.mbox_busy) {
3352                 ha->flags.mbox_int = 1;
3353                 ha->flags.mbox_busy = 0;
3354                 ql_log(ql_log_warn, vha, 0x6010,
3355                     "Doing premature completion of mbx command.\n");
3356                 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3357                         complete(&ha->mbx_intr_comp);
3358         }
3359 }
3360
3361 void qla82xx_watchdog(scsi_qla_host_t *vha)
3362 {
3363         uint32_t dev_state, halt_status;
3364         struct qla_hw_data *ha = vha->hw;
3365
3366         /* don't poll if reset is going on */
3367         if (!ha->flags.isp82xx_reset_hdlr_active) {
3368                 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3369                 if (qla82xx_check_temp(vha)) {
3370                         set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3371                         ha->flags.isp82xx_fw_hung = 1;
3372                         qla82xx_clear_pending_mbx(vha);
3373                 } else if (dev_state == QLA82XX_DEV_NEED_RESET &&
3374                     !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3375                         ql_log(ql_log_warn, vha, 0x6001,
3376                             "Adapter reset needed.\n");
3377                         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3378                 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT &&
3379                         !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3380                         ql_log(ql_log_warn, vha, 0x6002,
3381                             "Quiescent needed.\n");
3382                         set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3383                 } else {
3384                         if (qla82xx_check_fw_alive(vha)) {
3385                                 ql_dbg(ql_dbg_timer, vha, 0x6011,
3386                                     "disabling pause transmit on port 0 & 1.\n");
3387                                 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3388                                     CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3389                                 halt_status = qla82xx_rd_32(ha,
3390                                     QLA82XX_PEG_HALT_STATUS1);
3391                                 ql_log(ql_log_info, vha, 0x6005,
3392                                     "dumping hw/fw registers:.\n "
3393                                     " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3394                                     " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3395                                     " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3396                                     " PEG_NET_4_PC: 0x%x.\n", halt_status,
3397                                     qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3398                                     qla82xx_rd_32(ha,
3399                                             QLA82XX_CRB_PEG_NET_0 + 0x3c),
3400                                     qla82xx_rd_32(ha,
3401                                             QLA82XX_CRB_PEG_NET_1 + 0x3c),
3402                                     qla82xx_rd_32(ha,
3403                                             QLA82XX_CRB_PEG_NET_2 + 0x3c),
3404                                     qla82xx_rd_32(ha,
3405                                             QLA82XX_CRB_PEG_NET_3 + 0x3c),
3406                                     qla82xx_rd_32(ha,
3407                                             QLA82XX_CRB_PEG_NET_4 + 0x3c));
3408                                 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3409                                         ql_log(ql_log_warn, vha, 0xb052,
3410                                             "Firmware aborted with "
3411                                             "error code 0x00006700. Device is "
3412                                             "being reset.\n");
3413                                 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3414                                         set_bit(ISP_UNRECOVERABLE,
3415                                             &vha->dpc_flags);
3416                                 } else {
3417                                         ql_log(ql_log_info, vha, 0x6006,
3418                                             "Detect abort  needed.\n");
3419                                         set_bit(ISP_ABORT_NEEDED,
3420                                             &vha->dpc_flags);
3421                                 }
3422                                 ha->flags.isp82xx_fw_hung = 1;
3423                                 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3424                                 qla82xx_clear_pending_mbx(vha);
3425                         }
3426                 }
3427         }
3428 }
3429
3430 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3431 {
3432         int rval;
3433         rval = qla82xx_device_state_handler(vha);
3434         return rval;
3435 }
3436
3437 void
3438 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3439 {
3440         struct qla_hw_data *ha = vha->hw;
3441         uint32_t dev_state;
3442
3443         dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3444         if (dev_state == QLA82XX_DEV_READY) {
3445                 ql_log(ql_log_info, vha, 0xb02f,
3446                     "HW State: NEED RESET\n");
3447                 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3448                         QLA82XX_DEV_NEED_RESET);
3449                 ha->flags.isp82xx_reset_owner = 1;
3450                 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3451                     "reset_owner is 0x%x\n", ha->portnum);
3452         } else
3453                 ql_log(ql_log_info, vha, 0xb031,
3454                     "Device state is 0x%x = %s.\n",
3455                     dev_state,
3456                     dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3457 }
3458
3459 /*
3460  *  qla82xx_abort_isp
3461  *      Resets ISP and aborts all outstanding commands.
3462  *
3463  * Input:
3464  *      ha           = adapter block pointer.
3465  *
3466  * Returns:
3467  *      0 = success
3468  */
3469 int
3470 qla82xx_abort_isp(scsi_qla_host_t *vha)
3471 {
3472         int rval;
3473         struct qla_hw_data *ha = vha->hw;
3474
3475         if (vha->device_flags & DFLG_DEV_FAILED) {
3476                 ql_log(ql_log_warn, vha, 0x8024,
3477                     "Device in failed state, exiting.\n");
3478                 return QLA_SUCCESS;
3479         }
3480         ha->flags.isp82xx_reset_hdlr_active = 1;
3481
3482         qla82xx_idc_lock(ha);
3483         qla82xx_set_reset_owner(vha);
3484         qla82xx_idc_unlock(ha);
3485
3486         rval = qla82xx_device_state_handler(vha);
3487
3488         qla82xx_idc_lock(ha);
3489         qla82xx_clear_rst_ready(ha);
3490         qla82xx_idc_unlock(ha);
3491
3492         if (rval == QLA_SUCCESS) {
3493                 ha->flags.isp82xx_fw_hung = 0;
3494                 ha->flags.isp82xx_reset_hdlr_active = 0;
3495                 qla82xx_restart_isp(vha);
3496         }
3497
3498         if (rval) {
3499                 vha->flags.online = 1;
3500                 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3501                         if (ha->isp_abort_cnt == 0) {
3502                                 ql_log(ql_log_warn, vha, 0x8027,
3503                                     "ISP error recover failed - board "
3504                                     "disabled.\n");
3505                                 /*
3506                                  * The next call disables the board
3507                                  * completely.
3508                                  */
3509                                 ha->isp_ops->reset_adapter(vha);
3510                                 vha->flags.online = 0;
3511                                 clear_bit(ISP_ABORT_RETRY,
3512                                     &vha->dpc_flags);
3513                                 rval = QLA_SUCCESS;
3514                         } else { /* schedule another ISP abort */
3515                                 ha->isp_abort_cnt--;
3516                                 ql_log(ql_log_warn, vha, 0x8036,
3517                                     "ISP abort - retry remaining %d.\n",
3518                                     ha->isp_abort_cnt);
3519                                 rval = QLA_FUNCTION_FAILED;
3520                         }
3521                 } else {
3522                         ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3523                         ql_dbg(ql_dbg_taskm, vha, 0x8029,
3524                             "ISP error recovery - retrying (%d) more times.\n",
3525                             ha->isp_abort_cnt);
3526                         set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3527                         rval = QLA_FUNCTION_FAILED;
3528                 }
3529         }
3530         return rval;
3531 }
3532
3533 /*
3534  *  qla82xx_fcoe_ctx_reset
3535  *      Perform a quick reset and aborts all outstanding commands.
3536  *      This will only perform an FCoE context reset and avoids a full blown
3537  *      chip reset.
3538  *
3539  * Input:
3540  *      ha = adapter block pointer.
3541  *      is_reset_path = flag for identifying the reset path.
3542  *
3543  * Returns:
3544  *      0 = success
3545  */
3546 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3547 {
3548         int rval = QLA_FUNCTION_FAILED;
3549
3550         if (vha->flags.online) {
3551                 /* Abort all outstanding commands, so as to be requeued later */
3552                 qla2x00_abort_isp_cleanup(vha);
3553         }
3554
3555         /* Stop currently executing firmware.
3556          * This will destroy existing FCoE context at the F/W end.
3557          */
3558         qla2x00_try_to_stop_firmware(vha);
3559
3560         /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3561         rval = qla82xx_restart_isp(vha);
3562
3563         return rval;
3564 }
3565
3566 /*
3567  * qla2x00_wait_for_fcoe_ctx_reset
3568  *    Wait till the FCoE context is reset.
3569  *
3570  * Note:
3571  *    Does context switching here.
3572  *    Release SPIN_LOCK (if any) before calling this routine.
3573  *
3574  * Return:
3575  *    Success (fcoe_ctx reset is done) : 0
3576  *    Failed  (fcoe_ctx reset not completed within max loop timout ) : 1
3577  */
3578 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3579 {
3580         int status = QLA_FUNCTION_FAILED;
3581         unsigned long wait_reset;
3582
3583         wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3584         while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3585             test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3586             && time_before(jiffies, wait_reset)) {
3587
3588                 set_current_state(TASK_UNINTERRUPTIBLE);
3589                 schedule_timeout(HZ);
3590
3591                 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3592                     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3593                         status = QLA_SUCCESS;
3594                         break;
3595                 }
3596         }
3597         ql_dbg(ql_dbg_p3p, vha, 0xb027,
3598                "%s: status=%d.\n", __func__, status);
3599
3600         return status;
3601 }
3602
3603 void
3604 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3605 {
3606         int i;
3607         unsigned long flags;
3608         struct qla_hw_data *ha = vha->hw;
3609
3610         /* Check if 82XX firmware is alive or not
3611          * We may have arrived here from NEED_RESET
3612          * detection only
3613          */
3614         if (!ha->flags.isp82xx_fw_hung) {
3615                 for (i = 0; i < 2; i++) {
3616                         msleep(1000);
3617                         if (qla82xx_check_fw_alive(vha)) {
3618                                 ha->flags.isp82xx_fw_hung = 1;
3619                                 qla82xx_clear_pending_mbx(vha);
3620                                 break;
3621                         }
3622                 }
3623         }
3624         ql_dbg(ql_dbg_init, vha, 0x00b0,
3625             "Entered %s fw_hung=%d.\n",
3626             __func__, ha->flags.isp82xx_fw_hung);
3627
3628         /* Abort all commands gracefully if fw NOT hung */
3629         if (!ha->flags.isp82xx_fw_hung) {
3630                 int cnt, que;
3631                 srb_t *sp;
3632                 struct req_que *req;
3633
3634                 spin_lock_irqsave(&ha->hardware_lock, flags);
3635                 for (que = 0; que < ha->max_req_queues; que++) {
3636                         req = ha->req_q_map[que];
3637                         if (!req)
3638                                 continue;
3639                         for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
3640                                 sp = req->outstanding_cmds[cnt];
3641                                 if (sp) {
3642                                         if (!sp->u.scmd.ctx ||
3643                                             (sp->flags & SRB_FCP_CMND_DMA_VALID)) {
3644                                                 spin_unlock_irqrestore(
3645                                                     &ha->hardware_lock, flags);
3646                                                 if (ha->isp_ops->abort_command(sp)) {
3647                                                         ql_log(ql_log_info, vha,
3648                                                             0x00b1,
3649                                                             "mbx abort failed.\n");
3650                                                 } else {
3651                                                         ql_log(ql_log_info, vha,
3652                                                             0x00b2,
3653                                                             "mbx abort success.\n");
3654                                                 }
3655                                                 spin_lock_irqsave(&ha->hardware_lock, flags);
3656                                         }
3657                                 }
3658                         }
3659                 }
3660                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3661
3662                 /* Wait for pending cmds (physical and virtual) to complete */
3663                 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3664                     WAIT_HOST) == QLA_SUCCESS) {
3665                         ql_dbg(ql_dbg_init, vha, 0x00b3,
3666                             "Done wait for "
3667                             "pending commands.\n");
3668                 }
3669         }
3670 }
3671
3672 /* Minidump related functions */
3673 static int
3674 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3675         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3676 {
3677         struct qla_hw_data *ha = vha->hw;
3678         struct qla82xx_md_entry_crb *crb_entry;
3679         uint32_t read_value, opcode, poll_time;
3680         uint32_t addr, index, crb_addr;
3681         unsigned long wtime;
3682         struct qla82xx_md_template_hdr *tmplt_hdr;
3683         uint32_t rval = QLA_SUCCESS;
3684         int i;
3685
3686         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3687         crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3688         crb_addr = crb_entry->addr;
3689
3690         for (i = 0; i < crb_entry->op_count; i++) {
3691                 opcode = crb_entry->crb_ctrl.opcode;
3692                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3693                         qla82xx_md_rw_32(ha, crb_addr,
3694                             crb_entry->value_1, 1);
3695                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
3696                 }
3697
3698                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3699                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3700                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3701                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
3702                 }
3703
3704                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3705                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3706                         read_value &= crb_entry->value_2;
3707                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
3708                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
3709                                 read_value |= crb_entry->value_3;
3710                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3711                         }
3712                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3713                 }
3714
3715                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3716                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3717                         read_value |= crb_entry->value_3;
3718                         qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3719                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
3720                 }
3721
3722                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3723                         poll_time = crb_entry->crb_strd.poll_timeout;
3724                         wtime = jiffies + poll_time;
3725                         read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3726
3727                         do {
3728                                 if ((read_value & crb_entry->value_2)
3729                                     == crb_entry->value_1)
3730                                         break;
3731                                 else if (time_after_eq(jiffies, wtime)) {
3732                                         /* capturing dump failed */
3733                                         rval = QLA_FUNCTION_FAILED;
3734                                         break;
3735                                 } else
3736                                         read_value = qla82xx_md_rw_32(ha,
3737                                             crb_addr, 0, 0);
3738                         } while (1);
3739                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3740                 }
3741
3742                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3743                         if (crb_entry->crb_strd.state_index_a) {
3744                                 index = crb_entry->crb_strd.state_index_a;
3745                                 addr = tmplt_hdr->saved_state_array[index];
3746                         } else
3747                                 addr = crb_addr;
3748
3749                         read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3750                         index = crb_entry->crb_ctrl.state_index_v;
3751                         tmplt_hdr->saved_state_array[index] = read_value;
3752                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3753                 }
3754
3755                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3756                         if (crb_entry->crb_strd.state_index_a) {
3757                                 index = crb_entry->crb_strd.state_index_a;
3758                                 addr = tmplt_hdr->saved_state_array[index];
3759                         } else
3760                                 addr = crb_addr;
3761
3762                         if (crb_entry->crb_ctrl.state_index_v) {
3763                                 index = crb_entry->crb_ctrl.state_index_v;
3764                                 read_value =
3765                                     tmplt_hdr->saved_state_array[index];
3766                         } else
3767                                 read_value = crb_entry->value_1;
3768
3769                         qla82xx_md_rw_32(ha, addr, read_value, 1);
3770                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3771                 }
3772
3773                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3774                         index = crb_entry->crb_ctrl.state_index_v;
3775                         read_value = tmplt_hdr->saved_state_array[index];
3776                         read_value <<= crb_entry->crb_ctrl.shl;
3777                         read_value >>= crb_entry->crb_ctrl.shr;
3778                         if (crb_entry->value_2)
3779                                 read_value &= crb_entry->value_2;
3780                         read_value |= crb_entry->value_3;
3781                         read_value += crb_entry->value_1;
3782                         tmplt_hdr->saved_state_array[index] = read_value;
3783                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3784                 }
3785                 crb_addr += crb_entry->crb_strd.addr_stride;
3786         }
3787         return rval;
3788 }
3789
3790 static void
3791 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3792         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3793 {
3794         struct qla_hw_data *ha = vha->hw;
3795         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3796         struct qla82xx_md_entry_rdocm *ocm_hdr;
3797         uint32_t *data_ptr = *d_ptr;
3798
3799         ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3800         r_addr = ocm_hdr->read_addr;
3801         r_stride = ocm_hdr->read_addr_stride;
3802         loop_cnt = ocm_hdr->op_count;
3803
3804         for (i = 0; i < loop_cnt; i++) {
3805                 r_value = RD_REG_DWORD((void *)(r_addr + ha->nx_pcibase));
3806                 *data_ptr++ = cpu_to_le32(r_value);
3807                 r_addr += r_stride;
3808         }
3809         *d_ptr = data_ptr;
3810 }
3811
3812 static void
3813 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3814         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3815 {
3816         struct qla_hw_data *ha = vha->hw;
3817         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3818         struct qla82xx_md_entry_mux *mux_hdr;
3819         uint32_t *data_ptr = *d_ptr;
3820
3821         mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3822         r_addr = mux_hdr->read_addr;
3823         s_addr = mux_hdr->select_addr;
3824         s_stride = mux_hdr->select_value_stride;
3825         s_value = mux_hdr->select_value;
3826         loop_cnt = mux_hdr->op_count;
3827
3828         for (i = 0; i < loop_cnt; i++) {
3829                 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3830                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3831                 *data_ptr++ = cpu_to_le32(s_value);
3832                 *data_ptr++ = cpu_to_le32(r_value);
3833                 s_value += s_stride;
3834         }
3835         *d_ptr = data_ptr;
3836 }
3837
3838 static void
3839 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3840         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3841 {
3842         struct qla_hw_data *ha = vha->hw;
3843         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3844         struct qla82xx_md_entry_crb *crb_hdr;
3845         uint32_t *data_ptr = *d_ptr;
3846
3847         crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3848         r_addr = crb_hdr->addr;
3849         r_stride = crb_hdr->crb_strd.addr_stride;
3850         loop_cnt = crb_hdr->op_count;
3851
3852         for (i = 0; i < loop_cnt; i++) {
3853                 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3854                 *data_ptr++ = cpu_to_le32(r_addr);
3855                 *data_ptr++ = cpu_to_le32(r_value);
3856                 r_addr += r_stride;
3857         }
3858         *d_ptr = data_ptr;
3859 }
3860
3861 static int
3862 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3863         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3864 {
3865         struct qla_hw_data *ha = vha->hw;
3866         uint32_t addr, r_addr, c_addr, t_r_addr;
3867         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3868         unsigned long p_wait, w_time, p_mask;
3869         uint32_t c_value_w, c_value_r;
3870         struct qla82xx_md_entry_cache *cache_hdr;
3871         int rval = QLA_FUNCTION_FAILED;
3872         uint32_t *data_ptr = *d_ptr;
3873
3874         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3875         loop_count = cache_hdr->op_count;
3876         r_addr = cache_hdr->read_addr;
3877         c_addr = cache_hdr->control_addr;
3878         c_value_w = cache_hdr->cache_ctrl.write_value;
3879
3880         t_r_addr = cache_hdr->tag_reg_addr;
3881         t_value = cache_hdr->addr_ctrl.init_tag_value;
3882         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3883         p_wait = cache_hdr->cache_ctrl.poll_wait;
3884         p_mask = cache_hdr->cache_ctrl.poll_mask;
3885
3886         for (i = 0; i < loop_count; i++) {
3887                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3888                 if (c_value_w)
3889                         qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3890
3891                 if (p_mask) {
3892                         w_time = jiffies + p_wait;
3893                         do {
3894                                 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3895                                 if ((c_value_r & p_mask) == 0)
3896                                         break;
3897                                 else if (time_after_eq(jiffies, w_time)) {
3898                                         /* capturing dump failed */
3899                                         ql_dbg(ql_dbg_p3p, vha, 0xb032,
3900                                             "c_value_r: 0x%x, poll_mask: 0x%lx, "
3901                                             "w_time: 0x%lx\n",
3902                                             c_value_r, p_mask, w_time);
3903                                         return rval;
3904                                 }
3905                         } while (1);
3906                 }
3907
3908                 addr = r_addr;
3909                 for (k = 0; k < r_cnt; k++) {
3910                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3911                         *data_ptr++ = cpu_to_le32(r_value);
3912                         addr += cache_hdr->read_ctrl.read_addr_stride;
3913                 }
3914                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3915         }
3916         *d_ptr = data_ptr;
3917         return QLA_SUCCESS;
3918 }
3919
3920 static void
3921 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3922         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3923 {
3924         struct qla_hw_data *ha = vha->hw;
3925         uint32_t addr, r_addr, c_addr, t_r_addr;
3926         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3927         uint32_t c_value_w;
3928         struct qla82xx_md_entry_cache *cache_hdr;
3929         uint32_t *data_ptr = *d_ptr;
3930
3931         cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3932         loop_count = cache_hdr->op_count;
3933         r_addr = cache_hdr->read_addr;
3934         c_addr = cache_hdr->control_addr;
3935         c_value_w = cache_hdr->cache_ctrl.write_value;
3936
3937         t_r_addr = cache_hdr->tag_reg_addr;
3938         t_value = cache_hdr->addr_ctrl.init_tag_value;
3939         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3940
3941         for (i = 0; i < loop_count; i++) {
3942                 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3943                 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3944                 addr = r_addr;
3945                 for (k = 0; k < r_cnt; k++) {
3946                         r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3947                         *data_ptr++ = cpu_to_le32(r_value);
3948                         addr += cache_hdr->read_ctrl.read_addr_stride;
3949                 }
3950                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3951         }
3952         *d_ptr = data_ptr;
3953 }
3954
3955 static void
3956 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3957         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3958 {
3959         struct qla_hw_data *ha = vha->hw;
3960         uint32_t s_addr, r_addr;
3961         uint32_t r_stride, r_value, r_cnt, qid = 0;
3962         uint32_t i, k, loop_cnt;
3963         struct qla82xx_md_entry_queue *q_hdr;
3964         uint32_t *data_ptr = *d_ptr;
3965
3966         q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3967         s_addr = q_hdr->select_addr;
3968         r_cnt = q_hdr->rd_strd.read_addr_cnt;
3969         r_stride = q_hdr->rd_strd.read_addr_stride;
3970         loop_cnt = q_hdr->op_count;
3971
3972         for (i = 0; i < loop_cnt; i++) {
3973                 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3974                 r_addr = q_hdr->read_addr;
3975                 for (k = 0; k < r_cnt; k++) {
3976                         r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3977                         *data_ptr++ = cpu_to_le32(r_value);
3978                         r_addr += r_stride;
3979                 }
3980                 qid += q_hdr->q_strd.queue_id_stride;
3981         }
3982         *d_ptr = data_ptr;
3983 }
3984
3985 static void
3986 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3987         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3988 {
3989         struct qla_hw_data *ha = vha->hw;
3990         uint32_t r_addr, r_value;
3991         uint32_t i, loop_cnt;
3992         struct qla82xx_md_entry_rdrom *rom_hdr;
3993         uint32_t *data_ptr = *d_ptr;
3994
3995         rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
3996         r_addr = rom_hdr->read_addr;
3997         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
3998
3999         for (i = 0; i < loop_cnt; i++) {
4000                 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4001                     (r_addr & 0xFFFF0000), 1);
4002                 r_value = qla82xx_md_rw_32(ha,
4003                     MD_DIRECT_ROM_READ_BASE +
4004                     (r_addr & 0x0000FFFF), 0, 0);
4005                 *data_ptr++ = cpu_to_le32(r_value);
4006                 r_addr += sizeof(uint32_t);
4007         }
4008         *d_ptr = data_ptr;
4009 }
4010
4011 static int
4012 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4013         qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4014 {
4015         struct qla_hw_data *ha = vha->hw;
4016         uint32_t r_addr, r_value, r_data;
4017         uint32_t i, j, loop_cnt;
4018         struct qla82xx_md_entry_rdmem *m_hdr;
4019         unsigned long flags;
4020         int rval = QLA_FUNCTION_FAILED;
4021         uint32_t *data_ptr = *d_ptr;
4022
4023         m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4024         r_addr = m_hdr->read_addr;
4025         loop_cnt = m_hdr->read_data_size/16;
4026
4027         if (r_addr & 0xf) {
4028                 ql_log(ql_log_warn, vha, 0xb033,
4029                     "Read addr 0x%x not 16 bytes alligned\n", r_addr);
4030                 return rval;
4031         }
4032
4033         if (m_hdr->read_data_size % 16) {
4034                 ql_log(ql_log_warn, vha, 0xb034,
4035                     "Read data[0x%x] not multiple of 16 bytes\n",
4036                     m_hdr->read_data_size);
4037                 return rval;
4038         }
4039
4040         ql_dbg(ql_dbg_p3p, vha, 0xb035,
4041             "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4042             __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4043
4044         write_lock_irqsave(&ha->hw_lock, flags);
4045         for (i = 0; i < loop_cnt; i++) {
4046                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4047                 r_value = 0;
4048                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4049                 r_value = MIU_TA_CTL_ENABLE;
4050                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4051                 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4052                 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4053
4054                 for (j = 0; j < MAX_CTL_CHECK; j++) {
4055                         r_value = qla82xx_md_rw_32(ha,
4056                             MD_MIU_TEST_AGT_CTRL, 0, 0);
4057                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
4058                                 break;
4059                 }
4060
4061                 if (j >= MAX_CTL_CHECK) {
4062                         printk_ratelimited(KERN_ERR
4063                             "failed to read through agent\n");
4064                         write_unlock_irqrestore(&ha->hw_lock, flags);
4065                         return rval;
4066                 }
4067
4068                 for (j = 0; j < 4; j++) {
4069                         r_data = qla82xx_md_rw_32(ha,
4070                             MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4071                         *data_ptr++ = cpu_to_le32(r_data);
4072                 }
4073                 r_addr += 16;
4074         }
4075         write_unlock_irqrestore(&ha->hw_lock, flags);
4076         *d_ptr = data_ptr;
4077         return QLA_SUCCESS;
4078 }
4079
4080 static int
4081 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4082 {
4083         struct qla_hw_data *ha = vha->hw;
4084         uint64_t chksum = 0;
4085         uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4086         int count = ha->md_template_size/sizeof(uint32_t);
4087
4088         while (count-- > 0)
4089                 chksum += *d_ptr++;
4090         while (chksum >> 32)
4091                 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4092         return ~chksum;
4093 }
4094
4095 static void
4096 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4097         qla82xx_md_entry_hdr_t *entry_hdr, int index)
4098 {
4099         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4100         ql_dbg(ql_dbg_p3p, vha, 0xb036,
4101             "Skipping entry[%d]: "
4102             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4103             index, entry_hdr->entry_type,
4104             entry_hdr->d_ctrl.entry_capture_mask);
4105 }
4106
4107 int
4108 qla82xx_md_collect(scsi_qla_host_t *vha)
4109 {
4110         struct qla_hw_data *ha = vha->hw;
4111         int no_entry_hdr = 0;
4112         qla82xx_md_entry_hdr_t *entry_hdr;
4113         struct qla82xx_md_template_hdr *tmplt_hdr;
4114         uint32_t *data_ptr;
4115         uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4116         int i = 0, rval = QLA_FUNCTION_FAILED;
4117
4118         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4119         data_ptr = (uint32_t *)ha->md_dump;
4120
4121         if (ha->fw_dumped) {
4122                 ql_log(ql_log_warn, vha, 0xb037,
4123                     "Firmware has been previously dumped (%p) "
4124                     "-- ignoring request.\n", ha->fw_dump);
4125                 goto md_failed;
4126         }
4127
4128         ha->fw_dumped = 0;
4129
4130         if (!ha->md_tmplt_hdr || !ha->md_dump) {
4131                 ql_log(ql_log_warn, vha, 0xb038,
4132                     "Memory not allocated for minidump capture\n");
4133                 goto md_failed;
4134         }
4135
4136         if (ha->flags.isp82xx_no_md_cap) {
4137                 ql_log(ql_log_warn, vha, 0xb054,
4138                     "Forced reset from application, "
4139                     "ignore minidump capture\n");
4140                 ha->flags.isp82xx_no_md_cap = 0;
4141                 goto md_failed;
4142         }
4143
4144         if (qla82xx_validate_template_chksum(vha)) {
4145                 ql_log(ql_log_info, vha, 0xb039,
4146                     "Template checksum validation error\n");
4147                 goto md_failed;
4148         }
4149
4150         no_entry_hdr = tmplt_hdr->num_of_entries;
4151         ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4152             "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4153
4154         ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4155             "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4156
4157         f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4158
4159         /* Validate whether required debug level is set */
4160         if ((f_capture_mask & 0x3) != 0x3) {
4161                 ql_log(ql_log_warn, vha, 0xb03c,
4162                     "Minimum required capture mask[0x%x] level not set\n",
4163                     f_capture_mask);
4164                 goto md_failed;
4165         }
4166         tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4167
4168         tmplt_hdr->driver_info[0] = vha->host_no;
4169         tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4170             (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4171             QLA_DRIVER_BETA_VER;
4172
4173         total_data_size = ha->md_dump_size;
4174
4175         ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4176             "Total minidump data_size 0x%x to be captured\n", total_data_size);
4177
4178         /* Check whether template obtained is valid */
4179         if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4180                 ql_log(ql_log_warn, vha, 0xb04e,
4181                     "Bad template header entry type: 0x%x obtained\n",
4182                     tmplt_hdr->entry_type);
4183                 goto md_failed;
4184         }
4185
4186         entry_hdr = (qla82xx_md_entry_hdr_t *) \
4187             (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4188
4189         /* Walk through the entry headers */
4190         for (i = 0; i < no_entry_hdr; i++) {
4191
4192                 if (data_collected > total_data_size) {
4193                         ql_log(ql_log_warn, vha, 0xb03e,
4194                             "More MiniDump data collected: [0x%x]\n",
4195                             data_collected);
4196                         goto md_failed;
4197                 }
4198
4199                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4200                     ql2xmdcapmask)) {
4201                         entry_hdr->d_ctrl.driver_flags |=
4202                             QLA82XX_DBG_SKIPPED_FLAG;
4203                         ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4204                             "Skipping entry[%d]: "
4205                             "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4206                             i, entry_hdr->entry_type,
4207                             entry_hdr->d_ctrl.entry_capture_mask);
4208                         goto skip_nxt_entry;
4209                 }
4210
4211                 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4212                     "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4213                     "entry_type: 0x%x, captrue_mask: 0x%x\n",
4214                     __func__, i, data_ptr, entry_hdr,
4215                     entry_hdr->entry_type,
4216                     entry_hdr->d_ctrl.entry_capture_mask);
4217
4218                 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4219                     "Data collected: [0x%x], Dump size left:[0x%x]\n",
4220                     data_collected, (ha->md_dump_size - data_collected));
4221
4222                 /* Decode the entry type and take
4223                  * required action to capture debug data */
4224                 switch (entry_hdr->entry_type) {
4225                 case QLA82XX_RDEND:
4226                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4227                         break;
4228                 case QLA82XX_CNTRL:
4229                         rval = qla82xx_minidump_process_control(vha,
4230                             entry_hdr, &data_ptr);
4231                         if (rval != QLA_SUCCESS) {
4232                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4233                                 goto md_failed;
4234                         }
4235                         break;
4236                 case QLA82XX_RDCRB:
4237                         qla82xx_minidump_process_rdcrb(vha,
4238                             entry_hdr, &data_ptr);
4239                         break;
4240                 case QLA82XX_RDMEM:
4241                         rval = qla82xx_minidump_process_rdmem(vha,
4242                             entry_hdr, &data_ptr);
4243                         if (rval != QLA_SUCCESS) {
4244                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4245                                 goto md_failed;
4246                         }
4247                         break;
4248                 case QLA82XX_BOARD:
4249                 case QLA82XX_RDROM:
4250                         qla82xx_minidump_process_rdrom(vha,
4251                             entry_hdr, &data_ptr);
4252                         break;
4253                 case QLA82XX_L2DTG:
4254                 case QLA82XX_L2ITG:
4255                 case QLA82XX_L2DAT:
4256                 case QLA82XX_L2INS:
4257                         rval = qla82xx_minidump_process_l2tag(vha,
4258                             entry_hdr, &data_ptr);
4259                         if (rval != QLA_SUCCESS) {
4260                                 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4261                                 goto md_failed;
4262                         }
4263                         break;
4264                 case QLA82XX_L1DAT:
4265                 case QLA82XX_L1INS:
4266                         qla82xx_minidump_process_l1cache(vha,
4267                             entry_hdr, &data_ptr);
4268                         break;
4269                 case QLA82XX_RDOCM:
4270                         qla82xx_minidump_process_rdocm(vha,
4271                             entry_hdr, &data_ptr);
4272                         break;
4273                 case QLA82XX_RDMUX:
4274                         qla82xx_minidump_process_rdmux(vha,
4275                             entry_hdr, &data_ptr);
4276                         break;
4277                 case QLA82XX_QUEUE:
4278                         qla82xx_minidump_process_queue(vha,
4279                             entry_hdr, &data_ptr);
4280                         break;
4281                 case QLA82XX_RDNOP:
4282                 default:
4283                         qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4284                         break;
4285                 }
4286
4287                 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4288                     "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4289
4290                 data_collected = (uint8_t *)data_ptr -
4291                     (uint8_t *)ha->md_dump;
4292 skip_nxt_entry:
4293                 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4294                     (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4295         }
4296
4297         if (data_collected != total_data_size) {
4298                 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4299                     "MiniDump data mismatch: Data collected: [0x%x],"
4300                     "total_data_size:[0x%x]\n",
4301                     data_collected, total_data_size);
4302                 goto md_failed;
4303         }
4304
4305         ql_log(ql_log_info, vha, 0xb044,
4306             "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4307             vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4308         ha->fw_dumped = 1;
4309         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4310
4311 md_failed:
4312         return rval;
4313 }
4314
4315 int
4316 qla82xx_md_alloc(scsi_qla_host_t *vha)
4317 {
4318         struct qla_hw_data *ha = vha->hw;
4319         int i, k;
4320         struct qla82xx_md_template_hdr *tmplt_hdr;
4321
4322         tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4323
4324         if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4325                 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4326                 ql_log(ql_log_info, vha, 0xb045,
4327                     "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4328                     ql2xmdcapmask);
4329         }
4330
4331         for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4332                 if (i & ql2xmdcapmask)
4333                         ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4334         }
4335
4336         if (ha->md_dump) {
4337                 ql_log(ql_log_warn, vha, 0xb046,
4338                     "Firmware dump previously allocated.\n");
4339                 return 1;
4340         }
4341
4342         ha->md_dump = vmalloc(ha->md_dump_size);
4343         if (ha->md_dump == NULL) {
4344                 ql_log(ql_log_warn, vha, 0xb047,
4345                     "Unable to allocate memory for Minidump size "
4346                     "(0x%x).\n", ha->md_dump_size);
4347                 return 1;
4348         }
4349         return 0;
4350 }
4351
4352 void
4353 qla82xx_md_free(scsi_qla_host_t *vha)
4354 {
4355         struct qla_hw_data *ha = vha->hw;
4356
4357         /* Release the template header allocated */
4358         if (ha->md_tmplt_hdr) {
4359                 ql_log(ql_log_info, vha, 0xb048,
4360                     "Free MiniDump template: %p, size (%d KB)\n",
4361                     ha->md_tmplt_hdr, ha->md_template_size / 1024);
4362                 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4363                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4364                 ha->md_tmplt_hdr = 0;
4365         }
4366
4367         /* Release the template data buffer allocated */
4368         if (ha->md_dump) {
4369                 ql_log(ql_log_info, vha, 0xb049,
4370                     "Free MiniDump memory: %p, size (%d KB)\n",
4371                     ha->md_dump, ha->md_dump_size / 1024);
4372                 vfree(ha->md_dump);
4373                 ha->md_dump_size = 0;
4374                 ha->md_dump = 0;
4375         }
4376 }
4377
4378 void
4379 qla82xx_md_prep(scsi_qla_host_t *vha)
4380 {
4381         struct qla_hw_data *ha = vha->hw;
4382         int rval;
4383
4384         /* Get Minidump template size */
4385         rval = qla82xx_md_get_template_size(vha);
4386         if (rval == QLA_SUCCESS) {
4387                 ql_log(ql_log_info, vha, 0xb04a,
4388                     "MiniDump Template size obtained (%d KB)\n",
4389                     ha->md_template_size / 1024);
4390
4391                 /* Get Minidump template */
4392                 rval = qla82xx_md_get_template(vha);
4393                 if (rval == QLA_SUCCESS) {
4394                         ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4395                             "MiniDump Template obtained\n");
4396
4397                         /* Allocate memory for minidump */
4398                         rval = qla82xx_md_alloc(vha);
4399                         if (rval == QLA_SUCCESS)
4400                                 ql_log(ql_log_info, vha, 0xb04c,
4401                                     "MiniDump memory allocated (%d KB)\n",
4402                                     ha->md_dump_size / 1024);
4403                         else {
4404                                 ql_log(ql_log_info, vha, 0xb04d,
4405                                     "Free MiniDump template: %p, size: (%d KB)\n",
4406                                     ha->md_tmplt_hdr,
4407                                     ha->md_template_size / 1024);
4408                                 dma_free_coherent(&ha->pdev->dev,
4409                                     ha->md_template_size,
4410                                     ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4411                                 ha->md_tmplt_hdr = 0;
4412                         }
4413
4414                 }
4415         }
4416 }
4417
4418 int
4419 qla82xx_beacon_on(struct scsi_qla_host *vha)
4420 {
4421
4422         int rval;
4423         struct qla_hw_data *ha = vha->hw;
4424         qla82xx_idc_lock(ha);
4425         rval = qla82xx_mbx_beacon_ctl(vha, 1);
4426
4427         if (rval) {
4428                 ql_log(ql_log_warn, vha, 0xb050,
4429                     "mbx set led config failed in %s\n", __func__);
4430                 goto exit;
4431         }
4432         ha->beacon_blink_led = 1;
4433 exit:
4434         qla82xx_idc_unlock(ha);
4435         return rval;
4436 }
4437
4438 int
4439 qla82xx_beacon_off(struct scsi_qla_host *vha)
4440 {
4441
4442         int rval;
4443         struct qla_hw_data *ha = vha->hw;
4444         qla82xx_idc_lock(ha);
4445         rval = qla82xx_mbx_beacon_ctl(vha, 0);
4446
4447         if (rval) {
4448                 ql_log(ql_log_warn, vha, 0xb051,
4449                     "mbx set led config failed in %s\n", __func__);
4450                 goto exit;
4451         }
4452         ha->beacon_blink_led = 0;
4453 exit:
4454         qla82xx_idc_unlock(ha);
4455         return rval;
4456 }