5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
8 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
9 select CMA if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
15 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
17 select HAVE_KPROBES if !XIP_KERNEL
18 select HAVE_KRETPROBES if (HAVE_KPROBES)
19 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
20 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
21 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
22 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
23 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
24 select HAVE_GENERIC_DMA_COHERENT
25 select HAVE_KERNEL_GZIP
26 select HAVE_KERNEL_LZO
27 select HAVE_KERNEL_LZMA
30 select HAVE_PERF_EVENTS
31 select PERF_USE_VMALLOC
32 select HAVE_REGS_AND_STACK_ACCESS_API
33 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
34 select HAVE_C_RECORDMCOUNT
35 select HAVE_GENERIC_HARDIRQS
36 select GENERIC_IRQ_SHOW
37 select CPU_PM if (SUSPEND || CPU_IDLE)
38 select GENERIC_PCI_IOMAP
39 select HAVE_BPF_JIT if NET
41 The ARM series is a line of low-power-consumption RISC chip designs
42 licensed by ARM Ltd and targeted at embedded applications and
43 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
44 manufactured, but legacy ARM-based PC hardware remains popular in
45 Europe. There is an ARM Linux project with a web page at
46 <http://www.arm.linux.org.uk/>.
48 config ARM_HAS_SG_CHAIN
51 config NEED_SG_DMA_LENGTH
54 config ARM_DMA_USE_IOMMU
55 select NEED_SG_DMA_LENGTH
56 select ARM_HAS_SG_CHAIN
65 config SYS_SUPPORTS_APM_EMULATION
71 config ARCH_USES_GETTIMEOFFSET
75 config GENERIC_CLOCKEVENTS
78 config GENERIC_CLOCKEVENTS_BROADCAST
80 depends on GENERIC_CLOCKEVENTS
89 select GENERIC_ALLOCATOR
100 The Extended Industry Standard Architecture (EISA) bus was
101 developed as an open alternative to the IBM MicroChannel bus.
103 The EISA bus provided some of the features of the IBM MicroChannel
104 bus while maintaining backward compatibility with cards made for
105 the older ISA bus. The EISA bus saw limited use between 1988 and
106 1995 when it was made obsolete by the PCI bus.
108 Say Y here if you are building a kernel for an EISA-based machine.
118 MicroChannel Architecture is found in some IBM PS/2 machines and
119 laptops. It is a bus system similar to PCI or ISA. See
120 <file:Documentation/mca.txt> (and especially the web page given
121 there) before attempting to build an MCA bus kernel.
123 config STACKTRACE_SUPPORT
127 config HAVE_LATENCYTOP_SUPPORT
132 config LOCKDEP_SUPPORT
136 config TRACE_IRQFLAGS_SUPPORT
140 config HARDIRQS_SW_RESEND
144 config GENERIC_IRQ_PROBE
148 config GENERIC_LOCKBREAK
151 depends on SMP && PREEMPT
153 config RWSEM_GENERIC_SPINLOCK
157 config RWSEM_XCHGADD_ALGORITHM
160 config ARCH_HAS_ILOG2_U32
163 config ARCH_HAS_ILOG2_U64
166 config ARCH_HAS_CPUFREQ
169 Internal node to signify that the ARCH has CPUFREQ support
170 and that the relevant menu configurations are displayed for
173 config ARCH_HAS_CPU_IDLE_WAIT
176 config GENERIC_HWEIGHT
180 config GENERIC_CALIBRATE_DELAY
184 config ARCH_MAY_HAVE_PC_FDC
190 config NEED_DMA_MAP_STATE
193 config ARCH_HAS_DMA_SET_COHERENT_MASK
196 config GENERIC_ISA_DMA
202 config NEED_RET_TO_USER
210 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
211 default DRAM_BASE if REMAP_VECTORS_TO_RAM
214 The base address of exception vectors.
216 config ARM_PATCH_PHYS_VIRT
217 bool "Patch physical to virtual translations at runtime" if EMBEDDED
219 depends on !XIP_KERNEL && MMU
220 depends on !ARCH_REALVIEW || !SPARSEMEM
222 Patch phys-to-virt and virt-to-phys translation functions at
223 boot and module load time according to the position of the
224 kernel in system memory.
226 This can only be used with non-XIP MMU kernels where the base
227 of physical memory is at a 16MB boundary.
229 Only disable this option if you know that you do not require
230 this feature (eg, building a kernel for a single machine) and
231 you need to shrink the kernel to the minimal size.
233 config NEED_MACH_IO_H
236 Select this when mach/io.h is required to provide special
237 definitions for this platform. The need for mach/io.h should
238 be avoided when possible.
240 config NEED_MACH_MEMORY_H
243 Select this when mach/memory.h is required to provide special
244 definitions for this platform. The need for mach/memory.h should
245 be avoided when possible.
248 hex "Physical address of main memory" if MMU
249 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
250 default DRAM_BASE if !MMU
252 Please provide the physical address corresponding to the
253 location of main memory in your system.
259 source "init/Kconfig"
261 source "kernel/Kconfig.freezer"
266 bool "MMU-based Paged Memory Management Support"
269 Select if you want MMU-based virtualised addressing space
270 support by paged memory management. If unsure, say 'Y'.
273 # The "ARM system type" choice list is ordered alphabetically by option
274 # text. Please add new entries in the option alphabetic order.
277 prompt "ARM system type"
278 default ARCH_VERSATILE
280 config ARCH_INTEGRATOR
281 bool "ARM Ltd. Integrator family"
283 select ARCH_HAS_CPUFREQ
285 select HAVE_MACH_CLKDEV
288 select GENERIC_CLOCKEVENTS
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_FPGA_IRQ
291 select NEED_MACH_IO_H
292 select NEED_MACH_MEMORY_H
295 Support for ARM's Integrator platform.
298 bool "ARM Ltd. RealView family"
301 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
304 select ARCH_WANT_OPTIONAL_GPIOLIB
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
307 select ARM_TIMER_SP804
308 select GPIO_PL061 if GPIOLIB
309 select NEED_MACH_MEMORY_H
311 This enables support for ARM Ltd RealView boards.
313 config ARCH_VERSATILE
314 bool "ARM Ltd. Versatile family"
318 select HAVE_MACH_CLKDEV
320 select GENERIC_CLOCKEVENTS
321 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLCD
324 select PLAT_VERSATILE_FPGA_IRQ
325 select ARM_TIMER_SP804
327 This enables support for ARM Ltd Versatile board.
330 bool "ARM Ltd. Versatile Express family"
331 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select ARM_TIMER_SP804
335 select HAVE_MACH_CLKDEV
336 select GENERIC_CLOCKEVENTS
338 select HAVE_PATA_PLATFORM
341 select PLAT_VERSATILE
342 select PLAT_VERSATILE_CLCD
344 This enables support for the ARM Ltd Versatile Express boards.
348 select ARCH_REQUIRE_GPIOLIB
352 select NEED_MACH_IO_H if PCCARD
354 This enables support for systems based on the Atmel AT91RM9200,
358 bool "Broadcom BCMRING"
362 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select ARCH_WANT_OPTIONAL_GPIOLIB
367 Support for Broadcom's BCMRing platform.
370 bool "Calxeda Highbank-based"
371 select ARCH_WANT_OPTIONAL_GPIOLIB
374 select ARM_TIMER_SP804
378 select GENERIC_CLOCKEVENTS
384 Support for the Calxeda Highbank SoC based boards.
387 bool "Cirrus Logic CLPS711x/EP721x-based"
389 select ARCH_USES_GETTIMEOFFSET
390 select NEED_MACH_MEMORY_H
392 Support for Cirrus Logic 711x/721x based boards.
395 bool "Cavium Networks CNS3XXX family"
397 select GENERIC_CLOCKEVENTS
399 select MIGHT_HAVE_CACHE_L2X0
400 select MIGHT_HAVE_PCI
401 select PCI_DOMAINS if PCI
403 Support for Cavium Networks CNS3XXX platform.
406 bool "Cortina Systems Gemini"
408 select ARCH_REQUIRE_GPIOLIB
409 select ARCH_USES_GETTIMEOFFSET
411 Support for the Cortina Systems Gemini family SoCs
414 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
417 select GENERIC_CLOCKEVENTS
419 select GENERIC_IRQ_CHIP
420 select MIGHT_HAVE_CACHE_L2X0
424 Support for CSR SiRFSoC ARM Cortex A9 Platform
431 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_IO_H
433 select NEED_MACH_MEMORY_H
435 This is an evaluation board for the StrongARM processor available
436 from Digital. It has limited hardware on-board, including an
437 Ethernet interface, two PCMCIA sockets, two serial ports and a
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_HAS_HOLES_MEMORYMODEL
448 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Freescale MXC/iMX-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
471 select GENERIC_IRQ_CHIP
472 select MULTI_IRQ_HANDLER
474 Support for Freescale MXC/iMX-based family of processors
477 bool "Freescale MXS-based"
478 select GENERIC_CLOCKEVENTS
479 select ARCH_REQUIRE_GPIOLIB
482 select HAVE_CLK_PREPARE
484 Support for Freescale MXS-based family of processors
487 bool "Hilscher NetX based"
491 select GENERIC_CLOCKEVENTS
493 This enables support for systems based on the Hilscher NetX Soc
496 bool "Hynix HMS720x-based"
499 select ARCH_USES_GETTIMEOFFSET
501 This enables support for systems based on the Hynix HMS720x
509 select ARCH_SUPPORTS_MSI
511 select NEED_MACH_IO_H
512 select NEED_MACH_MEMORY_H
513 select NEED_RET_TO_USER
515 Support for Intel's IOP13XX (XScale) family of processors.
521 select NEED_MACH_IO_H
522 select NEED_RET_TO_USER
525 select ARCH_REQUIRE_GPIOLIB
527 Support for Intel's 80219 and IOP32X (XScale) family of
534 select NEED_MACH_IO_H
535 select NEED_RET_TO_USER
538 select ARCH_REQUIRE_GPIOLIB
540 Support for Intel's IOP33X (XScale) family of processors.
547 select ARCH_USES_GETTIMEOFFSET
548 select NEED_MACH_IO_H
549 select NEED_MACH_MEMORY_H
551 Support for Intel's IXP23xx (XScale) family of processors.
554 bool "IXP2400/2800-based"
558 select ARCH_USES_GETTIMEOFFSET
559 select NEED_MACH_IO_H
560 select NEED_MACH_MEMORY_H
562 Support for Intel's IXP2400/2800 (XScale) family of processors.
567 select ARCH_HAS_DMA_SET_COHERENT_MASK
571 select GENERIC_CLOCKEVENTS
572 select MIGHT_HAVE_PCI
573 select NEED_MACH_IO_H
574 select DMABOUNCE if PCI
576 Support for Intel's IXP4XX (XScale) family of processors.
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
584 select NEED_MACH_IO_H
587 Support for the Marvell Dove SoC 88AP510
590 bool "Marvell Kirkwood"
593 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select NEED_MACH_IO_H
598 Support for the following Marvell Kirkwood series SoCs:
599 88F6180, 88F6192 and 88F6281.
605 select ARCH_REQUIRE_GPIOLIB
608 select USB_ARCH_HAS_OHCI
610 select GENERIC_CLOCKEVENTS
612 Support for the NXP LPC32XX family of processors
615 bool "Marvell MV78xx0"
618 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
620 select NEED_MACH_IO_H
623 Support for the following Marvell MV78xx0 series SoCs:
631 select ARCH_REQUIRE_GPIOLIB
632 select GENERIC_CLOCKEVENTS
635 Support for the following Marvell Orion 5x series SoCs:
636 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
637 Orion-2 (5281), Orion-1-90 (6183).
640 bool "Marvell PXA168/910/MMP2"
642 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
649 select GENERIC_ALLOCATOR
651 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
654 bool "Micrel/Kendin KS8695"
656 select ARCH_REQUIRE_GPIOLIB
657 select ARCH_USES_GETTIMEOFFSET
658 select NEED_MACH_MEMORY_H
660 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
661 System-on-Chip devices.
664 bool "Nuvoton W90X900 CPU"
666 select ARCH_REQUIRE_GPIOLIB
669 select GENERIC_CLOCKEVENTS
671 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
672 At present, the w90x900 has been renamed nuc900, regarding
673 the ARM series product line, you can login the following
674 link address to know more.
676 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
677 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
683 select GENERIC_CLOCKEVENTS
687 select MIGHT_HAVE_CACHE_L2X0
688 select NEED_MACH_IO_H if PCI
689 select ARCH_HAS_CPUFREQ
691 This enables support for NVIDIA Tegra based systems (Tegra APX,
692 Tegra 6xx and Tegra 2 series).
694 config ARCH_PICOXCELL
695 bool "Picochip picoXcell"
696 select ARCH_REQUIRE_GPIOLIB
697 select ARM_PATCH_PHYS_VIRT
701 select GENERIC_CLOCKEVENTS
708 This enables support for systems based on the Picochip picoXcell
709 family of Femtocell devices. The picoxcell support requires device tree
713 bool "Philips Nexperia PNX4008 Mobile"
716 select ARCH_USES_GETTIMEOFFSET
718 This enables support for Philips PNX4008 mobile platform.
721 bool "PXA2xx/PXA3xx-based"
724 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select GENERIC_CLOCKEVENTS
734 select MULTI_IRQ_HANDLER
735 select ARM_CPU_SUSPEND if PM
738 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
743 select GENERIC_CLOCKEVENTS
744 select ARCH_REQUIRE_GPIOLIB
747 Support for Qualcomm MSM/QSD based systems. This runs on the
748 apps processor of the MSM/QSD and depends on a shared memory
749 interface to the modem processor which runs the baseband
750 stack and controls some vital subsystems
751 (clock and power control, etc).
754 bool "Renesas SH-Mobile / R-Mobile"
757 select HAVE_MACH_CLKDEV
759 select GENERIC_CLOCKEVENTS
760 select MIGHT_HAVE_CACHE_L2X0
763 select MULTI_IRQ_HANDLER
764 select PM_GENERIC_DOMAINS if PM
765 select NEED_MACH_MEMORY_H
767 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
773 select ARCH_MAY_HAVE_PC_FDC
774 select HAVE_PATA_PLATFORM
777 select ARCH_SPARSEMEM_ENABLE
778 select ARCH_USES_GETTIMEOFFSET
780 select NEED_MACH_IO_H
781 select NEED_MACH_MEMORY_H
783 On the Acorn Risc-PC, Linux can support the internal IDE disk and
784 CD-ROM interface, serial and parallel port, and the floppy drive.
791 select ARCH_SPARSEMEM_ENABLE
793 select ARCH_HAS_CPUFREQ
795 select GENERIC_CLOCKEVENTS
798 select ARCH_REQUIRE_GPIOLIB
800 select NEED_MACH_MEMORY_H
803 Support for StrongARM 11x0 based boards.
806 bool "Samsung S3C24XX SoCs"
808 select ARCH_HAS_CPUFREQ
811 select ARCH_USES_GETTIMEOFFSET
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C_RTC if RTC_CLASS
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select NEED_MACH_IO_H
817 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
818 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
819 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
820 Samsung SMDK2410 development board (and derivatives).
823 bool "Samsung S3C64XX"
831 select ARCH_USES_GETTIMEOFFSET
832 select ARCH_HAS_CPUFREQ
833 select ARCH_REQUIRE_GPIOLIB
834 select SAMSUNG_CLKSRC
835 select SAMSUNG_IRQ_VIC_TIMER
836 select S3C_GPIO_TRACK
838 select USB_ARCH_HAS_OHCI
839 select SAMSUNG_GPIOLIB_4BIT
840 select HAVE_S3C2410_I2C if I2C
841 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 Samsung S3C64XX series based systems
846 bool "Samsung S5P6440 S5P6450"
852 select HAVE_S3C2410_WATCHDOG if WATCHDOG
853 select GENERIC_CLOCKEVENTS
854 select HAVE_S3C2410_I2C if I2C
855 select HAVE_S3C_RTC if RTC_CLASS
857 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
861 bool "Samsung S5PC100"
866 select ARCH_USES_GETTIMEOFFSET
867 select HAVE_S3C2410_I2C if I2C
868 select HAVE_S3C_RTC if RTC_CLASS
869 select HAVE_S3C2410_WATCHDOG if WATCHDOG
871 Samsung S5PC100 series based systems
874 bool "Samsung S5PV210/S5PC110"
876 select ARCH_SPARSEMEM_ENABLE
877 select ARCH_HAS_HOLES_MEMORYMODEL
882 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select HAVE_S3C2410_I2C if I2C
885 select HAVE_S3C_RTC if RTC_CLASS
886 select HAVE_S3C2410_WATCHDOG if WATCHDOG
887 select NEED_MACH_MEMORY_H
889 Samsung S5PV210/S5PC110 series based systems
892 bool "SAMSUNG EXYNOS"
894 select ARCH_SPARSEMEM_ENABLE
895 select ARCH_HAS_HOLES_MEMORYMODEL
899 select ARCH_HAS_CPUFREQ
900 select GENERIC_CLOCKEVENTS
901 select HAVE_S3C_RTC if RTC_CLASS
902 select HAVE_S3C2410_I2C if I2C
903 select HAVE_S3C2410_WATCHDOG if WATCHDOG
904 select NEED_MACH_MEMORY_H
906 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
915 select ARCH_USES_GETTIMEOFFSET
916 select NEED_MACH_MEMORY_H
917 select NEED_MACH_IO_H
919 Support for the StrongARM based Digital DNARD machine, also known
920 as "Shark" (<http://www.shark-linux.de/shark.html>).
923 bool "ST-Ericsson U300 Series"
929 select ARM_PATCH_PHYS_VIRT
931 select GENERIC_CLOCKEVENTS
933 select HAVE_MACH_CLKDEV
935 select ARCH_REQUIRE_GPIOLIB
937 Support for ST-Ericsson U300 series mobile platforms.
940 bool "ST-Ericsson U8500 Series"
944 select GENERIC_CLOCKEVENTS
946 select ARCH_REQUIRE_GPIOLIB
947 select ARCH_HAS_CPUFREQ
949 select MIGHT_HAVE_CACHE_L2X0
951 Support for ST-Ericsson's Ux500 architecture
954 bool "STMicroelectronics Nomadik"
959 select GENERIC_CLOCKEVENTS
960 select MIGHT_HAVE_CACHE_L2X0
961 select ARCH_REQUIRE_GPIOLIB
963 Support for the Nomadik platform by ST-Ericsson
967 select GENERIC_CLOCKEVENTS
968 select ARCH_REQUIRE_GPIOLIB
972 select GENERIC_ALLOCATOR
973 select GENERIC_IRQ_CHIP
974 select ARCH_HAS_HOLES_MEMORYMODEL
976 Support for TI's DaVinci platform.
981 select ARCH_REQUIRE_GPIOLIB
982 select ARCH_HAS_CPUFREQ
984 select GENERIC_CLOCKEVENTS
985 select ARCH_HAS_HOLES_MEMORYMODEL
987 Support for TI's OMAP platform (OMAP1/2/3/4).
992 select ARCH_REQUIRE_GPIOLIB
995 select GENERIC_CLOCKEVENTS
998 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1001 bool "VIA/WonderMedia 85xx"
1004 select ARCH_HAS_CPUFREQ
1005 select GENERIC_CLOCKEVENTS
1006 select ARCH_REQUIRE_GPIOLIB
1009 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1012 bool "Xilinx Zynq ARM Cortex A9 Platform"
1014 select GENERIC_CLOCKEVENTS
1015 select CLKDEV_LOOKUP
1019 select MIGHT_HAVE_CACHE_L2X0
1022 Support for Xilinx Zynq ARM Cortex A9 Platform
1026 # This is sorted alphabetically by mach-* pathname. However, plat-*
1027 # Kconfigs may be included either alphabetically (according to the
1028 # plat- suffix) or along side the corresponding mach-* source.
1030 source "arch/arm/mach-at91/Kconfig"
1032 source "arch/arm/mach-bcmring/Kconfig"
1034 source "arch/arm/mach-clps711x/Kconfig"
1036 source "arch/arm/mach-cns3xxx/Kconfig"
1038 source "arch/arm/mach-davinci/Kconfig"
1040 source "arch/arm/mach-dove/Kconfig"
1042 source "arch/arm/mach-ep93xx/Kconfig"
1044 source "arch/arm/mach-footbridge/Kconfig"
1046 source "arch/arm/mach-gemini/Kconfig"
1048 source "arch/arm/mach-h720x/Kconfig"
1050 source "arch/arm/mach-integrator/Kconfig"
1052 source "arch/arm/mach-iop32x/Kconfig"
1054 source "arch/arm/mach-iop33x/Kconfig"
1056 source "arch/arm/mach-iop13xx/Kconfig"
1058 source "arch/arm/mach-ixp4xx/Kconfig"
1060 source "arch/arm/mach-ixp2000/Kconfig"
1062 source "arch/arm/mach-ixp23xx/Kconfig"
1064 source "arch/arm/mach-kirkwood/Kconfig"
1066 source "arch/arm/mach-ks8695/Kconfig"
1068 source "arch/arm/mach-lpc32xx/Kconfig"
1070 source "arch/arm/mach-msm/Kconfig"
1072 source "arch/arm/mach-mv78xx0/Kconfig"
1074 source "arch/arm/plat-mxc/Kconfig"
1076 source "arch/arm/mach-mxs/Kconfig"
1078 source "arch/arm/mach-netx/Kconfig"
1080 source "arch/arm/mach-nomadik/Kconfig"
1081 source "arch/arm/plat-nomadik/Kconfig"
1083 source "arch/arm/plat-omap/Kconfig"
1085 source "arch/arm/mach-omap1/Kconfig"
1087 source "arch/arm/mach-omap2/Kconfig"
1089 source "arch/arm/mach-orion5x/Kconfig"
1091 source "arch/arm/mach-pxa/Kconfig"
1092 source "arch/arm/plat-pxa/Kconfig"
1094 source "arch/arm/mach-mmp/Kconfig"
1096 source "arch/arm/mach-realview/Kconfig"
1098 source "arch/arm/mach-sa1100/Kconfig"
1100 source "arch/arm/plat-samsung/Kconfig"
1101 source "arch/arm/plat-s3c24xx/Kconfig"
1102 source "arch/arm/plat-s5p/Kconfig"
1104 source "arch/arm/plat-spear/Kconfig"
1106 source "arch/arm/mach-s3c24xx/Kconfig"
1108 source "arch/arm/mach-s3c2412/Kconfig"
1109 source "arch/arm/mach-s3c2440/Kconfig"
1113 source "arch/arm/mach-s3c64xx/Kconfig"
1116 source "arch/arm/mach-s5p64x0/Kconfig"
1118 source "arch/arm/mach-s5pc100/Kconfig"
1120 source "arch/arm/mach-s5pv210/Kconfig"
1122 source "arch/arm/mach-exynos/Kconfig"
1124 source "arch/arm/mach-shmobile/Kconfig"
1126 source "arch/arm/mach-tegra/Kconfig"
1128 source "arch/arm/mach-u300/Kconfig"
1130 source "arch/arm/mach-ux500/Kconfig"
1132 source "arch/arm/mach-versatile/Kconfig"
1134 source "arch/arm/mach-vexpress/Kconfig"
1135 source "arch/arm/plat-versatile/Kconfig"
1137 source "arch/arm/mach-vt8500/Kconfig"
1139 source "arch/arm/mach-w90x900/Kconfig"
1141 # Definitions to make life easier
1147 select GENERIC_CLOCKEVENTS
1152 select GENERIC_IRQ_CHIP
1157 config PLAT_VERSATILE
1160 config ARM_TIMER_SP804
1163 select HAVE_SCHED_CLOCK
1165 source arch/arm/mm/Kconfig
1169 default 16 if ARCH_EP93XX
1173 bool "Enable iWMMXt support"
1174 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1175 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1177 Enable support for iWMMXt context switching at run time if
1178 running on a CPU that supports it.
1182 depends on CPU_XSCALE
1186 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1187 (!ARCH_OMAP3 || OMAP3_EMU)
1191 config MULTI_IRQ_HANDLER
1194 Allow each machine to specify it's own IRQ handler at run time.
1197 source "arch/arm/Kconfig-nommu"
1200 config ARM_ERRATA_326103
1201 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1204 Executing a SWP instruction to read-only memory does not set bit 11
1205 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1206 treat the access as a read, preventing a COW from occurring and
1207 causing the faulting task to livelock.
1209 config ARM_ERRATA_411920
1210 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1211 depends on CPU_V6 || CPU_V6K
1213 Invalidation of the Instruction Cache operation can
1214 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1215 It does not affect the MPCore. This option enables the ARM Ltd.
1216 recommended workaround.
1218 config ARM_ERRATA_430973
1219 bool "ARM errata: Stale prediction on replaced interworking branch"
1222 This option enables the workaround for the 430973 Cortex-A8
1223 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1224 interworking branch is replaced with another code sequence at the
1225 same virtual address, whether due to self-modifying code or virtual
1226 to physical address re-mapping, Cortex-A8 does not recover from the
1227 stale interworking branch prediction. This results in Cortex-A8
1228 executing the new code sequence in the incorrect ARM or Thumb state.
1229 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1230 and also flushes the branch target cache at every context switch.
1231 Note that setting specific bits in the ACTLR register may not be
1232 available in non-secure mode.
1234 config ARM_ERRATA_458693
1235 bool "ARM errata: Processor deadlock when a false hazard is created"
1238 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1239 erratum. For very specific sequences of memory operations, it is
1240 possible for a hazard condition intended for a cache line to instead
1241 be incorrectly associated with a different cache line. This false
1242 hazard might then cause a processor deadlock. The workaround enables
1243 the L1 caching of the NEON accesses and disables the PLD instruction
1244 in the ACTLR register. Note that setting specific bits in the ACTLR
1245 register may not be available in non-secure mode.
1247 config ARM_ERRATA_460075
1248 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1251 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1252 erratum. Any asynchronous access to the L2 cache may encounter a
1253 situation in which recent store transactions to the L2 cache are lost
1254 and overwritten with stale memory contents from external memory. The
1255 workaround disables the write-allocate mode for the L2 cache via the
1256 ACTLR register. Note that setting specific bits in the ACTLR register
1257 may not be available in non-secure mode.
1259 config ARM_ERRATA_742230
1260 bool "ARM errata: DMB operation may be faulty"
1261 depends on CPU_V7 && SMP
1263 This option enables the workaround for the 742230 Cortex-A9
1264 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1265 between two write operations may not ensure the correct visibility
1266 ordering of the two writes. This workaround sets a specific bit in
1267 the diagnostic register of the Cortex-A9 which causes the DMB
1268 instruction to behave as a DSB, ensuring the correct behaviour of
1271 config ARM_ERRATA_742231
1272 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1273 depends on CPU_V7 && SMP
1275 This option enables the workaround for the 742231 Cortex-A9
1276 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1277 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1278 accessing some data located in the same cache line, may get corrupted
1279 data due to bad handling of the address hazard when the line gets
1280 replaced from one of the CPUs at the same time as another CPU is
1281 accessing it. This workaround sets specific bits in the diagnostic
1282 register of the Cortex-A9 which reduces the linefill issuing
1283 capabilities of the processor.
1285 config PL310_ERRATA_588369
1286 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1287 depends on CACHE_L2X0
1289 The PL310 L2 cache controller implements three types of Clean &
1290 Invalidate maintenance operations: by Physical Address
1291 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1292 They are architecturally defined to behave as the execution of a
1293 clean operation followed immediately by an invalidate operation,
1294 both performing to the same memory location. This functionality
1295 is not correctly implemented in PL310 as clean lines are not
1296 invalidated as a result of these operations.
1298 config ARM_ERRATA_720789
1299 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1302 This option enables the workaround for the 720789 Cortex-A9 (prior to
1303 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1304 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1305 As a consequence of this erratum, some TLB entries which should be
1306 invalidated are not, resulting in an incoherency in the system page
1307 tables. The workaround changes the TLB flushing routines to invalidate
1308 entries regardless of the ASID.
1310 config PL310_ERRATA_727915
1311 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1312 depends on CACHE_L2X0
1314 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1315 operation (offset 0x7FC). This operation runs in background so that
1316 PL310 can handle normal accesses while it is in progress. Under very
1317 rare circumstances, due to this erratum, write data can be lost when
1318 PL310 treats a cacheable write transaction during a Clean &
1319 Invalidate by Way operation.
1321 config ARM_ERRATA_743622
1322 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1325 This option enables the workaround for the 743622 Cortex-A9
1326 (r2p*) erratum. Under very rare conditions, a faulty
1327 optimisation in the Cortex-A9 Store Buffer may lead to data
1328 corruption. This workaround sets a specific bit in the diagnostic
1329 register of the Cortex-A9 which disables the Store Buffer
1330 optimisation, preventing the defect from occurring. This has no
1331 visible impact on the overall performance or power consumption of the
1334 config ARM_ERRATA_751472
1335 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1338 This option enables the workaround for the 751472 Cortex-A9 (prior
1339 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1340 completion of a following broadcasted operation if the second
1341 operation is received by a CPU before the ICIALLUIS has completed,
1342 potentially leading to corrupted entries in the cache or TLB.
1344 config PL310_ERRATA_753970
1345 bool "PL310 errata: cache sync operation may be faulty"
1346 depends on CACHE_PL310
1348 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1350 Under some condition the effect of cache sync operation on
1351 the store buffer still remains when the operation completes.
1352 This means that the store buffer is always asked to drain and
1353 this prevents it from merging any further writes. The workaround
1354 is to replace the normal offset of cache sync operation (0x730)
1355 by another offset targeting an unmapped PL310 register 0x740.
1356 This has the same effect as the cache sync operation: store buffer
1357 drain and waiting for all buffers empty.
1359 config ARM_ERRATA_754322
1360 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1363 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1364 r3p*) erratum. A speculative memory access may cause a page table walk
1365 which starts prior to an ASID switch but completes afterwards. This
1366 can populate the micro-TLB with a stale entry which may be hit with
1367 the new ASID. This workaround places two dsb instructions in the mm
1368 switching code so that no page table walks can cross the ASID switch.
1370 config ARM_ERRATA_754327
1371 bool "ARM errata: no automatic Store Buffer drain"
1372 depends on CPU_V7 && SMP
1374 This option enables the workaround for the 754327 Cortex-A9 (prior to
1375 r2p0) erratum. The Store Buffer does not have any automatic draining
1376 mechanism and therefore a livelock may occur if an external agent
1377 continuously polls a memory location waiting to observe an update.
1378 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1379 written polling loops from denying visibility of updates to memory.
1381 config ARM_ERRATA_364296
1382 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1383 depends on CPU_V6 && !SMP
1385 This options enables the workaround for the 364296 ARM1136
1386 r0p2 erratum (possible cache data corruption with
1387 hit-under-miss enabled). It sets the undocumented bit 31 in
1388 the auxiliary control register and the FI bit in the control
1389 register, thus disabling hit-under-miss without putting the
1390 processor into full low interrupt latency mode. ARM11MPCore
1393 config ARM_ERRATA_764369
1394 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1395 depends on CPU_V7 && SMP
1397 This option enables the workaround for erratum 764369
1398 affecting Cortex-A9 MPCore with two or more processors (all
1399 current revisions). Under certain timing circumstances, a data
1400 cache line maintenance operation by MVA targeting an Inner
1401 Shareable memory region may fail to proceed up to either the
1402 Point of Coherency or to the Point of Unification of the
1403 system. This workaround adds a DSB instruction before the
1404 relevant cache maintenance functions and sets a specific bit
1405 in the diagnostic control register of the SCU.
1407 config PL310_ERRATA_769419
1408 bool "PL310 errata: no automatic Store Buffer drain"
1409 depends on CACHE_L2X0
1411 On revisions of the PL310 prior to r3p2, the Store Buffer does
1412 not automatically drain. This can cause normal, non-cacheable
1413 writes to be retained when the memory system is idle, leading
1414 to suboptimal I/O performance for drivers using coherent DMA.
1415 This option adds a write barrier to the cpu_idle loop so that,
1416 on systems with an outer cache, the store buffer is drained
1421 source "arch/arm/common/Kconfig"
1431 Find out whether you have ISA slots on your motherboard. ISA is the
1432 name of a bus system, i.e. the way the CPU talks to the other stuff
1433 inside your box. Other bus systems are PCI, EISA, MicroChannel
1434 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1435 newer boards don't support it. If you have ISA, say Y, otherwise N.
1437 # Select ISA DMA controller support
1442 # Select ISA DMA interface
1447 bool "PCI support" if MIGHT_HAVE_PCI
1449 Find out whether you have a PCI motherboard. PCI is the name of a
1450 bus system, i.e. the way the CPU talks to the other stuff inside
1451 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1452 VESA. If you have PCI, say Y, otherwise N.
1458 config PCI_NANOENGINE
1459 bool "BSE nanoEngine PCI support"
1460 depends on SA1100_NANOENGINE
1462 Enable PCI on the BSE nanoEngine board.
1467 # Select the host bridge type
1468 config PCI_HOST_VIA82C505
1470 depends on PCI && ARCH_SHARK
1473 config PCI_HOST_ITE8152
1475 depends on PCI && MACH_ARMCORE
1479 source "drivers/pci/Kconfig"
1481 source "drivers/pcmcia/Kconfig"
1485 menu "Kernel Features"
1487 source "kernel/time/Kconfig"
1492 This option should be selected by machines which have an SMP-
1495 The only effect of this option is to make the SMP-related
1496 options available to the user for configuration.
1499 bool "Symmetric Multi-Processing"
1500 depends on CPU_V6K || CPU_V7
1501 depends on GENERIC_CLOCKEVENTS
1504 select USE_GENERIC_SMP_HELPERS
1505 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1507 This enables support for systems with more than one CPU. If you have
1508 a system with only one CPU, like most personal computers, say N. If
1509 you have a system with more than one CPU, say Y.
1511 If you say N here, the kernel will run on single and multiprocessor
1512 machines, but will use only one CPU of a multiprocessor machine. If
1513 you say Y here, the kernel will run on many, but not all, single
1514 processor machines. On a single processor machine, the kernel will
1515 run faster if you say N here.
1517 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1518 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1519 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1521 If you don't know what to do here, say N.
1524 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1525 depends on EXPERIMENTAL
1526 depends on SMP && !XIP_KERNEL
1529 SMP kernels contain instructions which fail on non-SMP processors.
1530 Enabling this option allows the kernel to modify itself to make
1531 these instructions safe. Disabling it allows about 1K of space
1534 If you don't know what to do here, say Y.
1536 config ARM_CPU_TOPOLOGY
1537 bool "Support cpu topology definition"
1538 depends on SMP && CPU_V7
1541 Support ARM cpu topology definition. The MPIDR register defines
1542 affinity between processors which is then used to describe the cpu
1543 topology of an ARM System.
1546 bool "Multi-core scheduler support"
1547 depends on ARM_CPU_TOPOLOGY
1549 Multi-core scheduler support improves the CPU scheduler's decision
1550 making when dealing with multi-core CPU chips at a cost of slightly
1551 increased overhead in some places. If unsure say N here.
1554 bool "SMT scheduler support"
1555 depends on ARM_CPU_TOPOLOGY
1557 Improves the CPU scheduler's decision making when dealing with
1558 MultiThreading at a cost of slightly increased overhead in some
1559 places. If unsure say N here.
1564 This option enables support for the ARM system coherency unit
1571 This options enables support for the ARM timer and watchdog unit
1574 prompt "Memory split"
1577 Select the desired split between kernel and user memory.
1579 If you are not absolutely sure what you are doing, leave this
1583 bool "3G/1G user/kernel split"
1585 bool "2G/2G user/kernel split"
1587 bool "1G/3G user/kernel split"
1592 default 0x40000000 if VMSPLIT_1G
1593 default 0x80000000 if VMSPLIT_2G
1597 int "Maximum number of CPUs (2-32)"
1603 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1604 depends on SMP && HOTPLUG && EXPERIMENTAL
1606 Say Y here to experiment with turning CPUs off and on. CPUs
1607 can be controlled through /sys/devices/system/cpu.
1610 bool "Use local timer interrupts"
1613 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1615 Enable support for local timers on SMP platforms, rather then the
1616 legacy IPI broadcast method. Local timers allows the system
1617 accounting to be spread across the timer interval, preventing a
1618 "thundering herd" at every timer tick.
1622 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1623 default 355 if ARCH_U8500
1624 default 264 if MACH_H4700
1627 Maximum number of GPIOs in the system.
1629 If unsure, leave the default value.
1631 source kernel/Kconfig.preempt
1635 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1636 ARCH_S5PV210 || ARCH_EXYNOS4
1637 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1638 default AT91_TIMER_HZ if ARCH_AT91
1639 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1642 config THUMB2_KERNEL
1643 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1644 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1646 select ARM_ASM_UNIFIED
1649 By enabling this option, the kernel will be compiled in
1650 Thumb-2 mode. A compiler/assembler that understand the unified
1651 ARM-Thumb syntax is needed.
1655 config THUMB2_AVOID_R_ARM_THM_JUMP11
1656 bool "Work around buggy Thumb-2 short branch relocations in gas"
1657 depends on THUMB2_KERNEL && MODULES
1660 Various binutils versions can resolve Thumb-2 branches to
1661 locally-defined, preemptible global symbols as short-range "b.n"
1662 branch instructions.
1664 This is a problem, because there's no guarantee the final
1665 destination of the symbol, or any candidate locations for a
1666 trampoline, are within range of the branch. For this reason, the
1667 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1668 relocation in modules at all, and it makes little sense to add
1671 The symptom is that the kernel fails with an "unsupported
1672 relocation" error when loading some modules.
1674 Until fixed tools are available, passing
1675 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1676 code which hits this problem, at the cost of a bit of extra runtime
1677 stack usage in some cases.
1679 The problem is described in more detail at:
1680 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1682 Only Thumb-2 kernels are affected.
1684 Unless you are sure your tools don't have this problem, say Y.
1686 config ARM_ASM_UNIFIED
1690 bool "Use the ARM EABI to compile the kernel"
1692 This option allows for the kernel to be compiled using the latest
1693 ARM ABI (aka EABI). This is only useful if you are using a user
1694 space environment that is also compiled with EABI.
1696 Since there are major incompatibilities between the legacy ABI and
1697 EABI, especially with regard to structure member alignment, this
1698 option also changes the kernel syscall calling convention to
1699 disambiguate both ABIs and allow for backward compatibility support
1700 (selected with CONFIG_OABI_COMPAT).
1702 To use this you need GCC version 4.0.0 or later.
1705 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1706 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1709 This option preserves the old syscall interface along with the
1710 new (ARM EABI) one. It also provides a compatibility layer to
1711 intercept syscalls that have structure arguments which layout
1712 in memory differs between the legacy ABI and the new ARM EABI
1713 (only for non "thumb" binaries). This option adds a tiny
1714 overhead to all syscalls and produces a slightly larger kernel.
1715 If you know you'll be using only pure EABI user space then you
1716 can say N here. If this option is not selected and you attempt
1717 to execute a legacy ABI binary then the result will be
1718 UNPREDICTABLE (in fact it can be predicted that it won't work
1719 at all). If in doubt say Y.
1721 config ARCH_HAS_HOLES_MEMORYMODEL
1724 config ARCH_SPARSEMEM_ENABLE
1727 config ARCH_SPARSEMEM_DEFAULT
1728 def_bool ARCH_SPARSEMEM_ENABLE
1730 config ARCH_SELECT_MEMORY_MODEL
1731 def_bool ARCH_SPARSEMEM_ENABLE
1733 config HAVE_ARCH_PFN_VALID
1734 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1737 bool "High Memory Support"
1740 The address space of ARM processors is only 4 Gigabytes large
1741 and it has to accommodate user address space, kernel address
1742 space as well as some memory mapped IO. That means that, if you
1743 have a large amount of physical memory and/or IO, not all of the
1744 memory can be "permanently mapped" by the kernel. The physical
1745 memory that is not permanently mapped is called "high memory".
1747 Depending on the selected kernel/user memory split, minimum
1748 vmalloc space and actual amount of RAM, you may not need this
1749 option which should result in a slightly faster kernel.
1754 bool "Allocate 2nd-level pagetables from highmem"
1757 config HW_PERF_EVENTS
1758 bool "Enable hardware performance counter support for perf events"
1759 depends on PERF_EVENTS && CPU_HAS_PMU
1762 Enable hardware performance counter support for perf events. If
1763 disabled, perf events will use software events only.
1767 config FORCE_MAX_ZONEORDER
1768 int "Maximum zone order" if ARCH_SHMOBILE
1769 range 11 64 if ARCH_SHMOBILE
1770 default "9" if SA1111
1773 The kernel memory allocator divides physically contiguous memory
1774 blocks into "zones", where each zone is a power of two number of
1775 pages. This option selects the largest power of two that the kernel
1776 keeps in the memory allocator. If you need to allocate very large
1777 blocks of physically contiguous memory, then you may need to
1778 increase this value.
1780 This config option is actually maximum order plus one. For example,
1781 a value of 11 means that the largest free memory block is 2^10 pages.
1784 bool "Timer and CPU usage LEDs"
1785 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1786 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1787 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1788 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1789 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1790 ARCH_AT91 || ARCH_DAVINCI || \
1791 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1793 If you say Y here, the LEDs on your machine will be used
1794 to provide useful information about your current system status.
1796 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1797 be able to select which LEDs are active using the options below. If
1798 you are compiling a kernel for the EBSA-110 or the LART however, the
1799 red LED will simply flash regularly to indicate that the system is
1800 still functional. It is safe to say Y here if you have a CATS
1801 system, but the driver will do nothing.
1804 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1805 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1806 || MACH_OMAP_PERSEUS2
1808 depends on !GENERIC_CLOCKEVENTS
1809 default y if ARCH_EBSA110
1811 If you say Y here, one of the system LEDs (the green one on the
1812 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1813 will flash regularly to indicate that the system is still
1814 operational. This is mainly useful to kernel hackers who are
1815 debugging unstable kernels.
1817 The LART uses the same LED for both Timer LED and CPU usage LED
1818 functions. You may choose to use both, but the Timer LED function
1819 will overrule the CPU usage LED.
1822 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1824 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1825 || MACH_OMAP_PERSEUS2
1828 If you say Y here, the red LED will be used to give a good real
1829 time indication of CPU usage, by lighting whenever the idle task
1830 is not currently executing.
1832 The LART uses the same LED for both Timer LED and CPU usage LED
1833 functions. You may choose to use both, but the Timer LED function
1834 will overrule the CPU usage LED.
1836 config ALIGNMENT_TRAP
1838 depends on CPU_CP15_MMU
1839 default y if !ARCH_EBSA110
1840 select HAVE_PROC_CPU if PROC_FS
1842 ARM processors cannot fetch/store information which is not
1843 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1844 address divisible by 4. On 32-bit ARM processors, these non-aligned
1845 fetch/store instructions will be emulated in software if you say
1846 here, which has a severe performance impact. This is necessary for
1847 correct operation of some network protocols. With an IP-only
1848 configuration it is safe to say N, otherwise say Y.
1850 config UACCESS_WITH_MEMCPY
1851 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1852 depends on MMU && EXPERIMENTAL
1853 default y if CPU_FEROCEON
1855 Implement faster copy_to_user and clear_user methods for CPU
1856 cores where a 8-word STM instruction give significantly higher
1857 memory write throughput than a sequence of individual 32bit stores.
1859 A possible side effect is a slight increase in scheduling latency
1860 between threads sharing the same address space if they invoke
1861 such copy operations with large buffers.
1863 However, if the CPU data cache is using a write-allocate mode,
1864 this option is unlikely to provide any performance gain.
1868 prompt "Enable seccomp to safely compute untrusted bytecode"
1870 This kernel feature is useful for number crunching applications
1871 that may need to compute untrusted bytecode during their
1872 execution. By using pipes or other transports made available to
1873 the process as file descriptors supporting the read/write
1874 syscalls, it's possible to isolate those applications in
1875 their own address space using seccomp. Once seccomp is
1876 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1877 and the task is only allowed to execute a few safe syscalls
1878 defined by each seccomp mode.
1880 config CC_STACKPROTECTOR
1881 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1882 depends on EXPERIMENTAL
1884 This option turns on the -fstack-protector GCC feature. This
1885 feature puts, at the beginning of functions, a canary value on
1886 the stack just before the return address, and validates
1887 the value just before actually returning. Stack based buffer
1888 overflows (that need to overwrite this return address) now also
1889 overwrite the canary, which gets detected and the attack is then
1890 neutralized via a kernel panic.
1891 This feature requires gcc version 4.2 or above.
1893 config DEPRECATED_PARAM_STRUCT
1894 bool "Provide old way to pass kernel parameters"
1896 This was deprecated in 2001 and announced to live on for 5 years.
1897 Some old boot loaders still use this way.
1904 bool "Flattened Device Tree support"
1906 select OF_EARLY_FLATTREE
1909 Include support for flattened device tree machine descriptions.
1911 # Compressed boot loader in ROM. Yes, we really want to ask about
1912 # TEXT and BSS so we preserve their values in the config files.
1913 config ZBOOT_ROM_TEXT
1914 hex "Compressed ROM boot loader base address"
1917 The physical address at which the ROM-able zImage is to be
1918 placed in the target. Platforms which normally make use of
1919 ROM-able zImage formats normally set this to a suitable
1920 value in their defconfig file.
1922 If ZBOOT_ROM is not enabled, this has no effect.
1924 config ZBOOT_ROM_BSS
1925 hex "Compressed ROM boot loader BSS address"
1928 The base address of an area of read/write memory in the target
1929 for the ROM-able zImage which must be available while the
1930 decompressor is running. It must be large enough to hold the
1931 entire decompressed kernel plus an additional 128 KiB.
1932 Platforms which normally make use of ROM-able zImage formats
1933 normally set this to a suitable value in their defconfig file.
1935 If ZBOOT_ROM is not enabled, this has no effect.
1938 bool "Compressed boot loader in ROM/flash"
1939 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1941 Say Y here if you intend to execute your compressed kernel image
1942 (zImage) directly from ROM or flash. If unsure, say N.
1945 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1946 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1947 default ZBOOT_ROM_NONE
1949 Include experimental SD/MMC loading code in the ROM-able zImage.
1950 With this enabled it is possible to write the the ROM-able zImage
1951 kernel image to an MMC or SD card and boot the kernel straight
1952 from the reset vector. At reset the processor Mask ROM will load
1953 the first part of the the ROM-able zImage which in turn loads the
1954 rest the kernel image to RAM.
1956 config ZBOOT_ROM_NONE
1957 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1959 Do not load image from SD or MMC
1961 config ZBOOT_ROM_MMCIF
1962 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1964 Load image from MMCIF hardware block.
1966 config ZBOOT_ROM_SH_MOBILE_SDHI
1967 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1969 Load image from SDHI hardware block
1973 config ARM_APPENDED_DTB
1974 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1975 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1977 With this option, the boot code will look for a device tree binary
1978 (DTB) appended to zImage
1979 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1981 This is meant as a backward compatibility convenience for those
1982 systems with a bootloader that can't be upgraded to accommodate
1983 the documented boot protocol using a device tree.
1985 Beware that there is very little in terms of protection against
1986 this option being confused by leftover garbage in memory that might
1987 look like a DTB header after a reboot if no actual DTB is appended
1988 to zImage. Do not leave this option active in a production kernel
1989 if you don't intend to always append a DTB. Proper passing of the
1990 location into r2 of a bootloader provided DTB is always preferable
1993 config ARM_ATAG_DTB_COMPAT
1994 bool "Supplement the appended DTB with traditional ATAG information"
1995 depends on ARM_APPENDED_DTB
1997 Some old bootloaders can't be updated to a DTB capable one, yet
1998 they provide ATAGs with memory configuration, the ramdisk address,
1999 the kernel cmdline string, etc. Such information is dynamically
2000 provided by the bootloader and can't always be stored in a static
2001 DTB. To allow a device tree enabled kernel to be used with such
2002 bootloaders, this option allows zImage to extract the information
2003 from the ATAG list and store it at run time into the appended DTB.
2006 string "Default kernel command string"
2009 On some architectures (EBSA110 and CATS), there is currently no way
2010 for the boot loader to pass arguments to the kernel. For these
2011 architectures, you should supply some command-line options at build
2012 time by entering them here. As a minimum, you should specify the
2013 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2016 prompt "Kernel command line type" if CMDLINE != ""
2017 default CMDLINE_FROM_BOOTLOADER
2019 config CMDLINE_FROM_BOOTLOADER
2020 bool "Use bootloader kernel arguments if available"
2022 Uses the command-line options passed by the boot loader. If
2023 the boot loader doesn't provide any, the default kernel command
2024 string provided in CMDLINE will be used.
2026 config CMDLINE_EXTEND
2027 bool "Extend bootloader kernel arguments"
2029 The command-line arguments provided by the boot loader will be
2030 appended to the default kernel command string.
2032 config CMDLINE_FORCE
2033 bool "Always use the default kernel command string"
2035 Always use the default kernel command string, even if the boot
2036 loader passes other arguments to the kernel.
2037 This is useful if you cannot or don't want to change the
2038 command-line options your boot loader passes to the kernel.
2042 bool "Kernel Execute-In-Place from ROM"
2043 depends on !ZBOOT_ROM && !ARM_LPAE
2045 Execute-In-Place allows the kernel to run from non-volatile storage
2046 directly addressable by the CPU, such as NOR flash. This saves RAM
2047 space since the text section of the kernel is not loaded from flash
2048 to RAM. Read-write sections, such as the data section and stack,
2049 are still copied to RAM. The XIP kernel is not compressed since
2050 it has to run directly from flash, so it will take more space to
2051 store it. The flash address used to link the kernel object files,
2052 and for storing it, is configuration dependent. Therefore, if you
2053 say Y here, you must know the proper physical address where to
2054 store the kernel image depending on your own flash memory usage.
2056 Also note that the make target becomes "make xipImage" rather than
2057 "make zImage" or "make Image". The final kernel binary to put in
2058 ROM memory will be arch/arm/boot/xipImage.
2062 config XIP_PHYS_ADDR
2063 hex "XIP Kernel Physical Location"
2064 depends on XIP_KERNEL
2065 default "0x00080000"
2067 This is the physical address in your flash memory the kernel will
2068 be linked for and stored to. This address is dependent on your
2072 bool "Kexec system call (EXPERIMENTAL)"
2073 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2075 kexec is a system call that implements the ability to shutdown your
2076 current kernel, and to start another kernel. It is like a reboot
2077 but it is independent of the system firmware. And like a reboot
2078 you can start any kernel with it, not just Linux.
2080 It is an ongoing process to be certain the hardware in a machine
2081 is properly shutdown, so do not be surprised if this code does not
2082 initially work for you. It may help to enable device hotplugging
2086 bool "Export atags in procfs"
2090 Should the atags used to boot the kernel be exported in an "atags"
2091 file in procfs. Useful with kexec.
2094 bool "Build kdump crash kernel (EXPERIMENTAL)"
2095 depends on EXPERIMENTAL
2097 Generate crash dump after being started by kexec. This should
2098 be normally only set in special crash dump kernels which are
2099 loaded in the main kernel with kexec-tools into a specially
2100 reserved region and then later executed after a crash by
2101 kdump/kexec. The crash dump kernel must be compiled to a
2102 memory address not used by the main kernel
2104 For more details see Documentation/kdump/kdump.txt
2106 config AUTO_ZRELADDR
2107 bool "Auto calculation of the decompressed kernel image address"
2108 depends on !ZBOOT_ROM && !ARCH_U300
2110 ZRELADDR is the physical address where the decompressed kernel
2111 image will be placed. If AUTO_ZRELADDR is selected, the address
2112 will be determined at run-time by masking the current IP with
2113 0xf8000000. This assumes the zImage being placed in the first 128MB
2114 from start of memory.
2118 menu "CPU Power Management"
2122 source "drivers/cpufreq/Kconfig"
2125 tristate "CPUfreq driver for i.MX CPUs"
2126 depends on ARCH_MXC && CPU_FREQ
2128 This enables the CPUfreq driver for i.MX CPUs.
2130 config CPU_FREQ_SA1100
2133 config CPU_FREQ_SA1110
2136 config CPU_FREQ_INTEGRATOR
2137 tristate "CPUfreq driver for ARM Integrator CPUs"
2138 depends on ARCH_INTEGRATOR && CPU_FREQ
2141 This enables the CPUfreq driver for ARM Integrator CPUs.
2143 For details, take a look at <file:Documentation/cpu-freq>.
2149 depends on CPU_FREQ && ARCH_PXA && PXA25x
2151 select CPU_FREQ_TABLE
2152 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2157 Internal configuration node for common cpufreq on Samsung SoC
2159 config CPU_FREQ_S3C24XX
2160 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2161 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2164 This enables the CPUfreq driver for the Samsung S3C24XX family
2167 For details, take a look at <file:Documentation/cpu-freq>.
2171 config CPU_FREQ_S3C24XX_PLL
2172 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2173 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2175 Compile in support for changing the PLL frequency from the
2176 S3C24XX series CPUfreq driver. The PLL takes time to settle
2177 after a frequency change, so by default it is not enabled.
2179 This also means that the PLL tables for the selected CPU(s) will
2180 be built which may increase the size of the kernel image.
2182 config CPU_FREQ_S3C24XX_DEBUG
2183 bool "Debug CPUfreq Samsung driver core"
2184 depends on CPU_FREQ_S3C24XX
2186 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2188 config CPU_FREQ_S3C24XX_IODEBUG
2189 bool "Debug CPUfreq Samsung driver IO timing"
2190 depends on CPU_FREQ_S3C24XX
2192 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2194 config CPU_FREQ_S3C24XX_DEBUGFS
2195 bool "Export debugfs for CPUFreq"
2196 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2198 Export status information via debugfs.
2202 source "drivers/cpuidle/Kconfig"
2206 menu "Floating point emulation"
2208 comment "At least one emulation must be selected"
2211 bool "NWFPE math emulation"
2212 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2214 Say Y to include the NWFPE floating point emulator in the kernel.
2215 This is necessary to run most binaries. Linux does not currently
2216 support floating point hardware so you need to say Y here even if
2217 your machine has an FPA or floating point co-processor podule.
2219 You may say N here if you are going to load the Acorn FPEmulator
2220 early in the bootup.
2223 bool "Support extended precision"
2224 depends on FPE_NWFPE
2226 Say Y to include 80-bit support in the kernel floating-point
2227 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2228 Note that gcc does not generate 80-bit operations by default,
2229 so in most cases this option only enlarges the size of the
2230 floating point emulator without any good reason.
2232 You almost surely want to say N here.
2235 bool "FastFPE math emulation (EXPERIMENTAL)"
2236 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2238 Say Y here to include the FAST floating point emulator in the kernel.
2239 This is an experimental much faster emulator which now also has full
2240 precision for the mantissa. It does not support any exceptions.
2241 It is very simple, and approximately 3-6 times faster than NWFPE.
2243 It should be sufficient for most programs. It may be not suitable
2244 for scientific calculations, but you have to check this for yourself.
2245 If you do not feel you need a faster FP emulation you should better
2249 bool "VFP-format floating point maths"
2250 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2252 Say Y to include VFP support code in the kernel. This is needed
2253 if your hardware includes a VFP unit.
2255 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2256 release notes and additional status information.
2258 Say N if your target does not have VFP hardware.
2266 bool "Advanced SIMD (NEON) Extension support"
2267 depends on VFPv3 && CPU_V7
2269 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2274 menu "Userspace binary formats"
2276 source "fs/Kconfig.binfmt"
2279 tristate "RISC OS personality"
2282 Say Y here to include the kernel code necessary if you want to run
2283 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2284 experimental; if this sounds frightening, say N and sleep in peace.
2285 You can also say M here to compile this support as a module (which
2286 will be called arthur).
2290 menu "Power management options"
2292 source "kernel/power/Kconfig"
2294 config ARCH_SUSPEND_POSSIBLE
2295 depends on !ARCH_S5PC100
2296 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2297 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2300 config ARM_CPU_SUSPEND
2305 source "net/Kconfig"
2307 source "drivers/Kconfig"
2311 source "arch/arm/Kconfig.debug"
2313 source "security/Kconfig"
2315 source "crypto/Kconfig"
2317 source "lib/Kconfig"