qEntry.blockChanged = blockChanged;\r
qEntry.serviceId = NVM_SET_RAM_BLOCK_STATUS_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
\r
+ DET_VALIDATE_RV((rv == 0),NVM_SET_RAM_BLOCK_STATUS_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
/* req 3.1.5/NVM185 */\r
admPtr->ErrorStatus = NVM_REQ_PENDING;\r
\r
qEntry.dataPtr = (uint8_t *)NvM_DestPtr;\r
qEntry.serviceId = NVM_RESTORE_BLOCK_DEFAULTS_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
+\r
+ DET_VALIDATE_RV((rv == 0),NVM_RESTORE_BLOCK_DEFAULTS_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
\r
/* req 3.1.5/NVM185 */\r
admPtr->ErrorStatus = NVM_REQ_PENDING;\r
qEntry.dataPtr = NvM_DstPtr;\r
qEntry.serviceId = NVM_READ_BLOCK_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
\r
+ DET_VALIDATE_RV((rv == 0),NVM_READ_BLOCK_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
\r
/* req 3.1.5/NVM185 */\r
AdminBlock[blockId-1].ErrorStatus = NVM_REQ_PENDING;\r
qEntry.dataPtr = (uint8_t *)NvM_SrcPtr;\r
qEntry.serviceId = NVM_WRITE_BLOCK_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
+\r
+ DET_VALIDATE_RV((rv == 0),NVM_WRITE_BLOCK_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
\r
/* req 3.1.5/NVM185 */\r
admPtr->ErrorStatus = NVM_REQ_PENDING;\r
qEntry.dataIndex = dataIndex;\r
qEntry.serviceId = NVM_SET_DATA_INDEX_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
+ DET_VALIDATE_RV((rv == 0),NVM_SET_DATA_INDEX_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
\r
/* req 3.1.5/NVM185 */\r
admPtr->ErrorStatus = NVM_REQ_PENDING;\r
qEntry.dataPtr = dataIndexPtr;\r
qEntry.serviceId = NVM_GET_DATA_INDEX_ID;\r
rv = CirqBuffPush(&nvmQueue,&qEntry);\r
- NVM_ASSERT(rv == 0 );\r
+\r
+ DET_VALIDATE_RV((rv == 0),NVM_GET_DATA_INDEX_ID, NVM_E_LIST_OVERFLOW , E_NOT_OK);\r
\r
/* req 3.1.5/NVM185 */\r
admPtr->ErrorStatus = NVM_REQ_PENDING;\r