#include <string.h>\r
#include "Ramlog.h"\r
\r
+#include "core_cr4.h"\r
+\r
//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
\r
#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
\r
-\r
-\r
typedef struct {\r
uint32 lossOfLockCnt;\r
uint32 lossOfClockCnt;\r
} Mcu_Stats;\r
\r
+\r
+\r
+\r
+\r
+\r
/**\r
* Type that holds all global data for Mcu\r
*/\r
\r
Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)\r
{\r
-\r
+ /** @b Initialize @b Pll: */\r
+\r
+ /** - Setup pll control register 1:\r
+ * - Setup reset on oscillator slip\r
+ * - Setup bypass on pll slip\r
+ * - Setup Pll output clock divider\r
+ * - Setup reset on oscillator fail\r
+ * - Setup reference clock divider\r
+ * - Setup Pll multiplier\r
+ */\r
+ systemREG1->PLLCTL1 = 0x00000000U\r
+ | 0x20000000U\r
+ | (1U << 24U)\r
+ | 0x00000000U\r
+ | (4U << 16U)\r
+ | (119U << 8U);\r
+\r
+ /** - Setup pll control register 1\r
+ * - Enable/Disable frequency modulation\r
+ * - Setup spreading rate\r
+ * - Setup bandwidth adjustment\r
+ * - Setup internal Pll output divider\r
+ * - Setup spreading amount\r
+ */\r
+ systemREG1->PLLCTL2 = 0x00000000U\r
+ | (255U << 22U)\r
+ | (0U << 12U)\r
+ | (1U << 9U)\r
+ | 61U;\r
+\r
+\r
+ /** @b Initialize @b Clock @b Tree: */\r
+\r
+ /** - Start clock source lock */\r
+ systemREG1->CSDIS = 0x00000040U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000008U\r
+ | 0x00000004U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
+\r
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
+ systemREG1->GHVSRC = (SYS_PLL << 24U)\r
+ | (SYS_PLL << 16U)\r
+ | SYS_PLL;\r
+\r
+ /** - Power-up all peripharals */\r
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
+\r
+ /** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2 */\r
+ systemREG1->VCLKR = 15U;\r
+ systemREG1->VCLK2R = 1U;\r
+ systemREG1->VCLKR = 1U;\r
+\r
+ /** - Setup RTICLK1 and RTICLK2 clocks */\r
+ systemREG1->RCLKSRC = (1U << 24U)\r
+ | (SYS_VCLK << 16U)\r
+ | (1U << 8U)\r
+ | SYS_VCLK;\r
+\r
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */\r
+ systemREG1->VCLKASRC = (SYS_FR_PLL << 8U)\r
+ | SYS_VCLK;\r
+\r
+ /** - Enable Peripherals */\r
+ systemREG1->PENA = 1U;\r
return E_OK;\r
}\r
\r
\r
Mcu_PllStatusType Mcu_GetPllStatus(void) {\r
\r
- Mcu_PllStatusType rv;\r
+ if ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) {\r
+ return MCU_PLL_UNLOCKED;\r
+ }\r
\r
- return rv;\r
+ return MCU_PLL_LOCKED;\r
}\r
\r
//-------------------------------------------------------------------\r
--- /dev/null
+\r
+#include "Can.h"\r
+\r
+void Can_MainFunction_Write( void ) {\r
+ // Polled can not supported by this driver.\r
+}\r
+void Can_MainFunction_Read( void ) {\r
+ // Polled can not supported by this driver.\r
+}\r
+void Can_MainFunction_BusOff( void ) {\r
+ // Bus off not supported by this driver.\r
+}\r
+void Can_MainFunction_Wakeup( void ) {\r
+ // Wakeup not supported by this driver.\r
+}\r
+\r
+\r
+\r
+\r
+/* Global and Static Variables */\r
+\r
+#ifndef _little_endian__\r
+ static const unsigned s_canByteOrder[] = {3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U};\r
+#endif\r
+\r
+\r
+void canInit(void)\r
+{\r
+/* USER CODE BEGIN (4) */\r
+/* USER CODE END */\r
+ /** @b Initialize @b DCAN1: */\r
+\r
+ /** - Setup control register\r
+ * - Disable automatic wakeup on bus activity\r
+ * - Local power down mode disabled\r
+ * - Disable DMA request lines\r
+ * - Enable global Interrupt Line 0 and 1\r
+ * - Disable debug mode\r
+ * - Release from software reset\r
+ * - Disable parity and ECC\r
+ * - Enable/Disable auto bus on timer\r
+ * - Setup message completion before entering debug state\r
+ * - Setup normal operation mode\r
+ * - Request write access to the configuration registers\r
+ * - Setup automatic retransmission of messages\r
+ * - Disable error interrups\r
+ * - Disable status interrupts\r
+ * - Enter initialization mode\r
+ */\r
+ canREG1->CTL = 0x00000000U | 0x00000000U | 0x00021443U;\r
+\r
+ /** - Clear all pending error flags and reset current status */\r
+ canREG1->ES = 0x0000031FU;\r
+\r
+ /** - Assign interrupt level for messages */\r
+ canREG1->INTMUXx[0U] = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+ canREG1->INTMUXx[1U] = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+ /** - Setup auto bus on timer pewriod */\r
+ canREG1->ABOTR = 0U;\r
+\r
+ /** - Initialize message 1 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 1;\r
+\r
+ /** - Initialize message 2 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 2;\r
+\r
+ /** - Initialize message 3 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 3;\r
+\r
+ /** - Initialize message 4 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 4;\r
+\r
+ /** - Initialize message 5 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 5;\r
+\r
+ /** - Initialize message 6 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 6;\r
+\r
+ /** - Initialize message 7 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 7;\r
+\r
+ /** - Initialize message 8 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 8;\r
+\r
+ /** - Initialize message 9 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 9;\r
+\r
+ /** - Initialize message 10 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 10;\r
+\r
+ /** - Initialize message 11 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 11;\r
+\r
+ /** - Initialize message 12 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 12;\r
+\r
+ /** - Initialize message 13 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 13;\r
+\r
+ /** - Initialize message 14 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 14;\r
+\r
+ /** - Initialize message 15 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 15;\r
+\r
+ /** - Initialize message 16 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 16;\r
+\r
+ /** - Initialize message 17 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 17;\r
+\r
+ /** - Initialize message 18 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 18;\r
+\r
+ /** - Initialize message 19 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 19;\r
+\r
+ /** - Initialize message 20 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 20;\r
+\r
+ /** - Initialize message 21 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 21;\r
+\r
+ /** - Initialize message 22 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 22;\r
+\r
+ /** - Initialize message 23 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 23;\r
+\r
+ /** - Initialize message 24 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 24;\r
+\r
+ /** - Initialize message 25 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 25;\r
+\r
+ /** - Initialize message 26 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 26;\r
+\r
+ /** - Initialize message 27 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 27;\r
+\r
+ /** - Initialize message 28 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 28;\r
+\r
+ /** - Initialize message 29 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 29;\r
+\r
+ /** - Initialize message 30 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 30;\r
+\r
+ /** - Initialize message 31 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 31;\r
+\r
+ /** - Initialize message 32 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 32;\r
+\r
+ /** - Initialize message 33 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 33;\r
+\r
+ /** - Initialize message 34 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 34;\r
+\r
+ /** - Initialize message 35 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 35;\r
+\r
+ /** - Initialize message 36 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 36;\r
+\r
+ /** - Initialize message 37 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 37;\r
+\r
+ /** - Initialize message 38 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 38;\r
+\r
+ /** - Initialize message 39 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 39;\r
+\r
+ /** - Initialize message 40 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 40;\r
+\r
+ /** - Initialize message 41 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 41;\r
+\r
+ /** - Initialize message 42 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 42;\r
+\r
+ /** - Initialize message 43 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 43;\r
+\r
+ /** - Initialize message 44 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 44;\r
+\r
+ /** - Initialize message 45 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 45;\r
+\r
+ /** - Initialize message 46 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 46;\r
+\r
+ /** - Initialize message 47 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 47;\r
+\r
+ /** - Initialize message 48 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 48;\r
+\r
+ /** - Initialize message 49 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 49;\r
+\r
+ /** - Initialize message 50 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 50;\r
+\r
+ /** - Initialize message 51 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 51;\r
+\r
+ /** - Initialize message 52 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 52;\r
+\r
+ /** - Initialize message 53 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 53;\r
+\r
+ /** - Initialize message 54 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 54;\r
+\r
+ /** - Initialize message 55 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 55;\r
+\r
+ /** - Initialize message 56 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 56;\r
+\r
+ /** - Initialize message 57 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 57;\r
+\r
+ /** - Initialize message 58 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 58;\r
+\r
+ /** - Initialize message 59 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 59;\r
+\r
+ /** - Initialize message 60 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 60;\r
+\r
+ /** - Initialize message 61 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 61;\r
+\r
+ /** - Initialize message 62 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 62;\r
+\r
+ /** - Initialize message 63 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF1CMD = 0xF8;\r
+ canREG1->IF1NO = 63;\r
+\r
+ /** - Initialize message 64 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
+ canREG1->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG1->IF2CMD = 0xF8;\r
+ canREG1->IF2NO = 64;\r
+\r
+ /** - Setup IF1 for data transmission \r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1CMD = 0x87;\r
+\r
+ /** - Setup IF2 for reading data\r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG1->IF2STAT & 0x80);\r
+\r
+ canREG1->IF2CMD = 0x17;\r
+\r
+ /** - Setup bit timing \r
+ * - Setup baud rate prescaler extension\r
+ * - Setup TSeg2\r
+ * - Setup TSeg1\r
+ * - Setup sample jump width\r
+ * - Setup baud rate prescaler\r
+ */\r
+ canREG1->BTR = (0U << 16U) |\r
+ ((4U - 1U) << 12U) |\r
+ (((5U + 4U) - 1U) << 8U) |\r
+ ((4U - 1U) << 6U) |\r
+ 9U;\r
+\r
+ /** - Setup TX pin to functional output */\r
+ canREG1->TIOC = 0x0000004CU;\r
+\r
+ /** - Setup RX pin to functional input */\r
+ canREG1->RIOC = 0x00000048U;\r
+\r
+ /** - Leave configuration and initialization mode */\r
+ canREG1->CTL &= ~0x00000041U;\r
+\r
+ /** @b Initialize @b DCAN2: */\r
+\r
+ /** - Setup control register\r
+ * - Disable automatic wakeup on bus activity\r
+ * - Local power down mode disabled\r
+ * - Disable DMA request lines\r
+ * - Enable global Interrupt Line 0 and 1\r
+ * - Disable debug mode\r
+ * - Release from software reset\r
+ * - Disable parity and ECC\r
+ * - Enable/Disable auto bus on timer\r
+ * - Setup message completion before entering debug state\r
+ * - Setup normal operation mode\r
+ * - Request write access to the configuration registers\r
+ * - Setup automatic retransmission of messages\r
+ * - Disable error interrups\r
+ * - Disable status interrupts\r
+ * - Enter initialization mode\r
+ */\r
+ canREG2->CTL = 0x00000000U | 0x00000000U | 0x00021443U;\r
+\r
+ /** - Clear all pending error flags and reset current status */\r
+ canREG2->ES = 0x0000031FU;\r
+\r
+ /** - Assign interrupt level for messages */\r
+ canREG2->INTMUXx[0U] = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+ canREG2->INTMUXx[1U] = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+\r
+ /** - Setup auto bus on timer pewriod */\r
+ canREG2->ABOTR = 0U;\r
+\r
+ /** - Initialize message 1 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 1;\r
+\r
+ /** - Initialize message 2 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 2;\r
+\r
+ /** - Initialize message 3 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 3;\r
+\r
+ /** - Initialize message 4 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 4;\r
+\r
+ /** - Initialize message 5 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 5;\r
+\r
+ /** - Initialize message 6 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 6;\r
+\r
+ /** - Initialize message 7 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 7;\r
+\r
+ /** - Initialize message 8 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 8;\r
+\r
+ /** - Initialize message 9 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 9;\r
+\r
+ /** - Initialize message 10 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 10;\r
+\r
+ /** - Initialize message 11 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 11;\r
+\r
+ /** - Initialize message 12 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 12;\r
+\r
+ /** - Initialize message 13 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 13;\r
+\r
+ /** - Initialize message 14 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 14;\r
+\r
+ /** - Initialize message 15 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 15;\r
+\r
+ /** - Initialize message 16 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 16;\r
+\r
+ /** - Initialize message 17 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 17;\r
+\r
+ /** - Initialize message 18 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 18;\r
+\r
+ /** - Initialize message 19 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 19;\r
+\r
+ /** - Initialize message 20 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 20;\r
+\r
+ /** - Initialize message 21 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 21;\r
+\r
+ /** - Initialize message 22 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 22;\r
+\r
+ /** - Initialize message 23 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 23;\r
+\r
+ /** - Initialize message 24 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 24;\r
+\r
+ /** - Initialize message 25 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 25;\r
+\r
+ /** - Initialize message 26 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 26;\r
+\r
+ /** - Initialize message 27 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 27;\r
+\r
+ /** - Initialize message 28 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 28;\r
+\r
+ /** - Initialize message 29 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 29;\r
+\r
+ /** - Initialize message 30 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 30;\r
+\r
+ /** - Initialize message 31 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 31;\r
+\r
+ /** - Initialize message 32 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 32;\r
+\r
+ /** - Initialize message 33 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((33U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 33;\r
+\r
+ /** - Initialize message 34 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((34U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 34;\r
+\r
+ /** - Initialize message 35 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((35U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 35;\r
+\r
+ /** - Initialize message 36 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((36U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 36;\r
+\r
+ /** - Initialize message 37 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((37U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 37;\r
+\r
+ /** - Initialize message 38 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((38U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 38;\r
+\r
+ /** - Initialize message 39 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((39U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 39;\r
+\r
+ /** - Initialize message 40 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((40U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 40;\r
+\r
+ /** - Initialize message 41 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((41U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 41;\r
+\r
+ /** - Initialize message 42 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((42U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 42;\r
+\r
+ /** - Initialize message 43 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((43U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 43;\r
+\r
+ /** - Initialize message 44 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((44U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 44;\r
+\r
+ /** - Initialize message 45 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((45U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 45;\r
+\r
+ /** - Initialize message 46 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((46U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 46;\r
+\r
+ /** - Initialize message 47 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((47U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 47;\r
+\r
+ /** - Initialize message 48 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((48U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 48;\r
+\r
+ /** - Initialize message 49 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((49U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 49;\r
+\r
+ /** - Initialize message 50 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((50U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 50;\r
+\r
+ /** - Initialize message 51 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((51U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 51;\r
+\r
+ /** - Initialize message 52 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((52U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 52;\r
+\r
+ /** - Initialize message 53 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((53U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 53;\r
+\r
+ /** - Initialize message 54 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((54U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 54;\r
+\r
+ /** - Initialize message 55 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((55U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 55;\r
+\r
+ /** - Initialize message 56 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((56U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 56;\r
+\r
+ /** - Initialize message 57 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((57U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 57;\r
+\r
+ /** - Initialize message 58 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((58U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 58;\r
+\r
+ /** - Initialize message 59 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((59U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 59;\r
+\r
+ /** - Initialize message 60 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((60U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 60;\r
+\r
+ /** - Initialize message 61 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((61U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 61;\r
+\r
+ /** - Initialize message 62 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((62U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 62;\r
+\r
+ /** - Initialize message 63 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((63U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF1CMD = 0xF8;\r
+ canREG2->IF1NO = 63;\r
+\r
+ /** - Initialize message 64 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((64U & 0x1FFFFFFFU) << 0U);\r
+ canREG2->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG2->IF2CMD = 0xF8;\r
+ canREG2->IF2NO = 64;\r
+\r
+ /** - Setup IF1 for data transmission \r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1CMD = 0x87;\r
+\r
+ /** - Setup IF2 for reading data\r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG2->IF2STAT & 0x80);\r
+\r
+ canREG2->IF2CMD = 0x17;\r
+\r
+ /** - Setup bit timing \r
+ * - Setup baud rate prescaler extension\r
+ * - Setup TSeg2\r
+ * - Setup TSeg1\r
+ * - Setup sample jump width\r
+ * - Setup baud rate prescaler\r
+ */\r
+ canREG2->BTR = (0U << 16U) |\r
+ ((4U - 1U) << 12U) |\r
+ (((5U + 4U) - 1U) << 8U) |\r
+ ((4U - 1U) << 6U) |\r
+ 9U;\r
+\r
+ /** - Setup TX pin to functional output */\r
+ canREG2->TIOC = 0x0000004CU;\r
+\r
+ /** - Setup RX pin to functional input */\r
+ canREG2->RIOC = 0x00000048U;\r
+\r
+ /** - Leave configuration and initialization mode */\r
+ canREG2->CTL &= ~0x00000041U;\r
+\r
+#if 0\r
+ /** @b Initialize @b DCAN3: */\r
+\r
+ /** - Setup control register\r
+ * - Disable automatic wakeup on bus activity\r
+ * - Local power down mode disabled\r
+ * - Disable DMA request lines\r
+ * - Enable global Interrupt Line 0 and 1\r
+ * - Disable debug mode\r
+ * - Release from software reset\r
+ * - Disable parity and ECC\r
+ * - Enable/Disable auto bus on timer\r
+ * - Setup message completion before entering debug state\r
+ * - Setup normal operation mode\r
+ * - Request write access to the configuration registers\r
+ * - Setup automatic retransmission of messages\r
+ * - Disable error interrups\r
+ * - Disable status interrupts\r
+ * - Enter initialization mode\r
+ */\r
+ canREG3->CTL = 0x00000000U | 0x00000000U | 0x00021443U;\r
+\r
+ /** - Clear all pending error flags and reset current status */\r
+ canREG3->ES = 0x0000031FU;\r
+\r
+ /** - Assign interrupt level for messages */\r
+ canREG3->INTMUXx[0U] = 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U\r
+ | 0x00000000U;\r
+\r
+ /** - Setup auto bus on timer pewriod */\r
+ canREG3->ABOTR = 0U;\r
+\r
+ /** - Initialize message 1 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((1U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 1;\r
+\r
+ /** - Initialize message 2 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((2U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 2;\r
+\r
+ /** - Initialize message 3 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((3U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 3;\r
+\r
+ /** - Initialize message 4 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((4U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 4;\r
+\r
+ /** - Initialize message 5 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((5U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 5;\r
+\r
+ /** - Initialize message 6 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((6U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 6;\r
+\r
+ /** - Initialize message 7 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((7U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 7;\r
+\r
+ /** - Initialize message 8 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((8U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 8;\r
+\r
+ /** - Initialize message 9 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((9U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 9;\r
+\r
+ /** - Initialize message 10 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((10U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 10;\r
+\r
+ /** - Initialize message 11 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((11U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 11;\r
+\r
+ /** - Initialize message 12 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((12U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 12;\r
+\r
+ /** - Initialize message 13 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((13U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 13;\r
+\r
+ /** - Initialize message 14 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((14U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 14;\r
+\r
+ /** - Initialize message 15 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((15U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 15;\r
+\r
+ /** - Initialize message 16 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((16U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 16;\r
+\r
+ /** - Initialize message 17 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((17U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 17;\r
+\r
+ /** - Initialize message 18 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((18U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 18;\r
+\r
+ /** - Initialize message 19 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((19U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 19;\r
+\r
+ /** - Initialize message 20 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((20U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 20;\r
+\r
+ /** - Initialize message 21 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((21U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 21;\r
+\r
+ /** - Initialize message 22 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((22U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 22;\r
+\r
+ /** - Initialize message 23 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((23U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 23;\r
+\r
+ /** - Initialize message 24 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((24U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 24;\r
+\r
+ /** - Initialize message 25 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((25U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 25;\r
+\r
+ /** - Initialize message 26 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((26U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 26;\r
+\r
+ /** - Initialize message 27 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((27U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 27;\r
+\r
+ /** - Initialize message 28 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((28U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 28;\r
+\r
+ /** - Initialize message 29 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((29U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 29;\r
+\r
+ /** - Initialize message 30 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((30U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 30;\r
+\r
+ /** - Initialize message 31 \r
+ * - Wait until IF1 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF1 control byte\r
+ * - Set IF1 message number\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((31U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF1MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF1CMD = 0xF8;\r
+ canREG3->IF1NO = 31;\r
+\r
+ /** - Initialize message 32 \r
+ * - Wait until IF2 is ready for use \r
+ * - Set message mask\r
+ * - Set message control word\r
+ * - Set message arbitration\r
+ * - Set IF2 control byte\r
+ * - Set IF2 message number\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2MSK = 0xC0000000U | ((0x000007FFU & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2ARB = 0x00000000U | 0x40000000U | 0x20000000U | ((32U & 0x1FFFFFFFU) << 0U);\r
+ canREG3->IF2MCTL = 0x00001080U | 0x00000000U | 8U;\r
+ canREG3->IF2CMD = 0xF8;\r
+ canREG3->IF2NO = 32;\r
+\r
+ /** - Setup IF1 for data transmission \r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1CMD = 0x87;\r
+\r
+ /** - Setup IF2 for reading data\r
+ * - Wait until IF1 is ready for use \r
+ * - Set IF1 control byte\r
+ */\r
+ while (canREG3->IF2STAT & 0x80);\r
+\r
+ canREG3->IF2CMD = 0x17;\r
+\r
+ /** - Setup bit timing \r
+ * - Setup baud rate prescaler extension\r
+ * - Setup TSeg2\r
+ * - Setup TSeg1\r
+ * - Setup sample jump width\r
+ * - Setup baud rate prescaler\r
+ */\r
+ canREG3->BTR = (0U << 16U) |\r
+ ((4U - 1U) << 12U) |\r
+ (((5U + 4U) - 1U) << 8U) |\r
+ ((4U - 1U) << 6U) |\r
+ 9U;\r
+\r
+ /** - Setup TX pin to functional output */\r
+ canREG3->TIOC = 0x0000004CU;\r
+\r
+ /** - Setup RX pin to functional input */\r
+ canREG3->RIOC = 0x00000048U;\r
+\r
+ /** - Leave configuration and initialization mode */\r
+ canREG3->CTL &= ~0x00000041U;\r
+#endif\r
+\r
+ /** @note This function has to be called before the driver can be used.\n\r
+ * This function has to be executed in priviledged mode.\n\r
+ */\r
+\r
+/* USER CODE BEGIN (5) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn unsigned canTransmit(canBASE_t *node, unsigned messageBox, const unsigned char *data)\r
+* @brief Transmits a CAN message\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @param[in] data Pointer to CAN TX data\r
+* @return The function will return:\r
+* - 0: When the setup of the TX message box wasn't successful \r
+* - 1: When the setup of the TX message box was successful \r
+*\r
+* This function writes a CAN message into a CAN message box.\r
+*\r
+*/\r
+\r
+/* USER CODE BEGIN (6) */\r
+/* USER CODE END */\r
+\r
+unsigned canTransmit(canBASE_t *node, unsigned messageBox, const unsigned char *data)\r
+{\r
+ unsigned i;\r
+ unsigned success = 0U;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (7) */\r
+/* USER CODE END */\r
+\r
+ /** - Check for pending message:\r
+ * - pending message, return 0\r
+ * - no pending message, start new transmission \r
+ */\r
+ if (node->TXRQx[regIndex] & bitIndex)\r
+ {\r
+ return success;\r
+ }\r
+\r
+ /** - Wait until IF1 is ready for use */\r
+ while (node->IF1STAT & 0x80);\r
+\r
+ /** - Copy TX data into IF1 */\r
+ for (i = 0U; i < 8U; i++)\r
+ {\r
+#ifdef _little_endian__\r
+ node->IF1DATx[i] = *data++;\r
+#else\r
+ node->IF1DATx[s_canByteOrder[i]] = *data++;\r
+#endif\r
+ }\r
+\r
+ /** - Copy TX data into mesasge box */\r
+ node->IF1NO = messageBox;\r
+\r
+ success = 1U; \r
+\r
+ /** @note The function canInit has to be called before this function can be used.\n\r
+ * The user is responsible to initialize the message box.\r
+ */\r
+\r
+/* USER CODE BEGIN (8) */\r
+/* USER CODE END */\r
+\r
+ return success;\r
+}\r
+\r
+\r
+/** @fn unsigned canGetData(canBASE_t *node, unsigned messageBox, unsigned char * const data)\r
+* @brief Gets received a CAN message\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @param[out] data Pointer to store CAN RX data\r
+* @return The function will return:\r
+* - 0: When RX message box hasn't received new data \r
+* - 1: When RX data are stored in the data buffer \r
+* - 3: When RX data are stored in the data buffer and a message was lost \r
+*\r
+* This function writes a CAN message into a CAN message box.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (9) */\r
+/* USER CODE END */\r
+\r
+unsigned canGetData(canBASE_t *node, unsigned messageBox, unsigned char * const data)\r
+{\r
+ unsigned i;\r
+ unsigned size;\r
+ unsigned char *pData = (unsigned char *)data;\r
+ unsigned success = 0U;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (10) */\r
+/* USER CODE END */\r
+\r
+ /** - Check if new data have been arrived:\r
+ * - no new data, return 0\r
+ * - new data, get received message \r
+ */\r
+ if (!(node->NWDATx[regIndex] & bitIndex))\r
+ {\r
+ return success;\r
+ }\r
+\r
+ /** - Wait until IF2 is ready for use */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Copy data into IF2 */\r
+ node->IF2NO = messageBox;\r
+\r
+ /** - Wait until data are copied into IF2 */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Get number of received bytes */\r
+ size = node->IF2MCTL & 0xFU;\r
+\r
+ /** - Copy RX data into destination buffer */\r
+ for (i = 0U; i < size; i++)\r
+ {\r
+#ifdef _little_endian__\r
+ *pData++ = node->IF2DATx[i];\r
+#else\r
+ *pData++ = node->IF2DATx[s_canByteOrder[i]];\r
+#endif\r
+ }\r
+\r
+ success = 1U;\r
+\r
+ /** - Check if data have been lost:\r
+ * - no data lost, return 1\r
+ * - data lost, return 3 \r
+ */\r
+ if (node->IF2MCTL & 0x4000U)\r
+ {\r
+ success = 3U;\r
+ }\r
+\r
+ /** @note The function canInit has to be called before this function can be used.\n\r
+ * The user is responsible to initialize the message box.\r
+ */\r
+\r
+/* USER CODE BEGIN (11) */\r
+/* USER CODE END */\r
+\r
+ return success;\r
+}\r
+\r
+\r
+/** @fn unsigned canIsTxMessagePending(canBASE_t *node, unsigned messageBox)\r
+* @brief Gets Tx message box transmission status\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @return The function will return the tx request flag\r
+*\r
+* Checks to see if the Tx message box has a pending Tx request, returns\r
+* 0 is flag not set otherwise will return the Tx request flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (12) */\r
+/* USER CODE END */\r
+\r
+unsigned canIsTxMessagePending(canBASE_t *node, unsigned messageBox)\r
+{\r
+ unsigned flag;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (13) */\r
+/* USER CODE END */\r
+\r
+ /** - Read Tx request reigster */\r
+ flag = node->TXRQx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (14) */\r
+/* USER CODE END */\r
+\r
+ return flag;\r
+}\r
+\r
+\r
+/** @fn unsigned canIsRxMessageArrived(canBASE_t *node, unsigned messageBox)\r
+* @brief Gets Rx message box reception status\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @return The function will return the new data flag\r
+*\r
+* Checks to see if the Rx message box has pending Rx data, returns\r
+* 0 is flag not set otherwise will return the Tx request flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (15) */\r
+/* USER CODE END */\r
+\r
+unsigned canIsRxMessageArrived(canBASE_t *node, unsigned messageBox)\r
+{\r
+ unsigned flag;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (16) */\r
+/* USER CODE END */\r
+\r
+ /** - Read Tx request register */\r
+ flag = node->NWDATx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (17) */\r
+/* USER CODE END */\r
+\r
+ return flag;\r
+}\r
+\r
+\r
+/** @fn unsigned canIsMessageBoxValid(canBASE_t *node, unsigned messageBox)\r
+* @brief Chechs if message box is valid\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @return The function will return the new data flag\r
+*\r
+* Checks to see if the message box is valid for operation, returns\r
+* 0 is flag not set otherwise will return the validation flag itself.\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (18) */\r
+/* USER CODE END */\r
+\r
+unsigned canIsMessageBoxValid(canBASE_t *node, unsigned messageBox)\r
+{\r
+ unsigned flag;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (19) */\r
+/* USER CODE END */\r
+\r
+ /** - Read Tx request register */\r
+ flag = node->MSGVALx[regIndex] & bitIndex;\r
+\r
+/* USER CODE BEGIN (20) */\r
+/* USER CODE END */\r
+\r
+ return flag;\r
+}\r
+\r
+\r
+/** @fn unsigned canGetLastError(canBASE_t *node)\r
+* @brief Gets last RX/TX-Error of CAN message traffic\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @return The function will return:\r
+* - canERROR_OK (0): When no CAN error occured \r
+* - canERROR_STUFF (1): When a stuff error occured on RX message \r
+* - canERROR_FORMAT (2): When a form/format error occured on RX message \r
+* - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged \r
+* - canERROR_BIT1 (4): When a TX message monitored dominant level where recessive is expected \r
+* - canERROR_BIT0 (5): When a TX message monitored recessive level where dominant is expected \r
+* - canERROR_CRC (6): When a RX message has wrong CRC value \r
+* - canERROR_NO (7): When no error occured since last call of this function \r
+*\r
+* This function returns the last occured error code of an RX or TX message,\r
+* since the last call of this function.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (21) */\r
+/* USER CODE END */\r
+\r
+unsigned canGetLastError(canBASE_t *node)\r
+{\r
+ unsigned errorCode;\r
+\r
+/* USER CODE BEGIN (22) */\r
+/* USER CODE END */\r
+\r
+ /** - Get last error code */\r
+ errorCode = node->ES & 7U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+ return errorCode;\r
+}\r
+\r
+\r
+/** @fn unsigned canGetErrorLevel(canBASE_t *node)\r
+* @brief Gets error level of a CAN node\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @return The function will return:\r
+* - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 \r
+* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127 \r
+* - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and 255 \r
+* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 \r
+*\r
+* This function returns the current error level of a CAN node.\r
+*\r
+*/\r
+\r
+\r
+/* USER CODE BEGIN (24) */\r
+/* USER CODE END */\r
+\r
+unsigned canGetErrorLevel(canBASE_t *node)\r
+{\r
+ unsigned errorLevel;\r
+\r
+/* USER CODE BEGIN (25) */\r
+/* USER CODE END */\r
+\r
+ /** - Get error level */\r
+ errorLevel = node->ES & 0xE0U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (26) */\r
+/* USER CODE END */\r
+\r
+ return errorLevel;\r
+}\r
+\r
+\r
+/** @fn void canEnableErrorNotification(canBASE_t *node)\r
+* @brief Enable error notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+*\r
+* This function will enable the notification for the reaching the error levels warning, passive and bus off.\r
+*/\r
+\r
+/* USER CODE BEGIN (27) */\r
+/* USER CODE END */\r
+\r
+void canEnableErrorNotification(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (28) */\r
+/* USER CODE END */\r
+\r
+ node->CTL |= 8U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (29) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void canDisableErrorNotification(canBASE_t *node)\r
+* @brief Disable error notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+*\r
+* This function will disable the notification for the reaching the error levels warning, passive and bus off.\r
+*/\r
+\r
+/* USER CODE BEGIN (30) */\r
+/* USER CODE END */\r
+\r
+void canDisableErrorNotification(canBASE_t *node)\r
+{\r
+/* USER CODE BEGIN (31) */\r
+/* USER CODE END */\r
+\r
+ node->CTL &= ~8U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used. */\r
+\r
+/* USER CODE BEGIN (32) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn unsigned canEnableMessageNotification(canBASE_t *node, unsigned messageBox)\r
+* @brief Enable message notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @return The function will return:\r
+* - 0: When the interrupts are not enable (message is pending) \r
+* - 1: When the are enabled \r
+*\r
+* This function will enable the notification for sucessfully receiving or transmitting a message.\r
+*/\r
+\r
+/* USER CODE BEGIN (33) */\r
+/* USER CODE END */\r
+\r
+unsigned canEnableMessageNotification(canBASE_t *node, unsigned messageBox)\r
+{\r
+ unsigned success = 0U;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (34) */\r
+/* USER CODE END */\r
+\r
+ /** - Check for pending message:\r
+ * - pending message, return 0\r
+ * - no pending message, enable interrupts\r
+ */\r
+ if ((node->NWDATx[regIndex] & bitIndex) || (node->TXRQx[regIndex] & bitIndex))\r
+ {\r
+ return success;\r
+ }\r
+\r
+ /** - Wait until IF2 is ready for use */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Copy data into IF2 */\r
+ node->IF2NO = messageBox;\r
+\r
+ /** - Wait until data are copied into IF2 */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Wait until IF1 is ready for use */\r
+ while (node->IF1STAT & 0x80);\r
+\r
+ /** - Adapt IF1 command to enable the interrupts */\r
+ node->IF1CMD = 0x90;\r
+\r
+ /** - Enable message interrupt */\r
+ node->IF1MCTL = node->IF2MCTL | 0xC00U;\r
+\r
+ /** - Copy data into message box */\r
+ node->IF1NO = messageBox;\r
+\r
+ /** - Wait until IF1 is ready for use */\r
+ while (node->IF1STAT & 0x80);\r
+\r
+ /** - Reset IF1 command to normal operation */\r
+ node->IF1CMD = 0x87;\r
+\r
+ success = 1U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used.\n \r
+ * The function returns with 0 if the message box has a pending data.\r
+ */\r
+\r
+/* USER CODE BEGIN (35) */\r
+/* USER CODE END */\r
+\r
+ return success;\r
+}\r
+\r
+\r
+/** @fn unsigned canDisableMessageNotification(canBASE_t *node, unsigned messageBox)\r
+* @brief Disable message notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+* @return The function will return:\r
+* - 0: When the interrupts are not enable (message is pending) \r
+* - 1: When the are enabled \r
+*\r
+* This function will disable the notification for sucessfully receiving or transmitting a message.\r
+*/\r
+\r
+/* USER CODE BEGIN (36) */\r
+/* USER CODE END */\r
+\r
+unsigned canDisableMessageNotification(canBASE_t *node, unsigned messageBox)\r
+{\r
+ unsigned success = 0U;\r
+ unsigned regIndex = (messageBox - 1U) >> 5U;\r
+ unsigned bitIndex = 1U << ((messageBox - 1U) & 0x1FU);\r
+\r
+/* USER CODE BEGIN (37) */\r
+/* USER CODE END */\r
+\r
+ /** - Check for pending message:\r
+ * - pending message, return 0\r
+ * - no pending message, enable interrupts\r
+ */\r
+ if ((node->NWDATx[regIndex] & bitIndex) || (node->TXRQx[regIndex] & bitIndex))\r
+ {\r
+ return success;\r
+ }\r
+\r
+ /** - Wait until IF2 is ready for use */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Copy data into IF2 */\r
+ node->IF2NO = messageBox;\r
+\r
+ /** - Wait until data are copied into IF2 */\r
+ while (node->IF2STAT & 0x80);\r
+\r
+ /** - Wait until IF1 is ready for use */\r
+ while (node->IF1STAT & 0x80);\r
+\r
+ /** - Adapt IF1 command to disable the interrupts */\r
+ node->IF1CMD = 0x90;\r
+\r
+ /** - Disable message interrupt */\r
+ node->IF1MCTL = node->IF2MCTL & ~0xC00U;\r
+\r
+ /** - Copy data into message box */\r
+ node->IF1NO = messageBox;\r
+\r
+ /** - Wait until IF1 is ready for use */\r
+ while (node->IF1STAT & 0x80);\r
+\r
+ /** - Reset IF1 command to normal operation */\r
+ node->IF1CMD = 0x87;\r
+\r
+ success = 1U;\r
+\r
+ /** @note The function canInit has to be called before this function can be used.\n \r
+ * The function returns with 0 if the message box has a pending data.\r
+ */\r
+\r
+/* USER CODE BEGIN (38) */\r
+/* USER CODE END */\r
+\r
+ return success;\r
+}\r
+\r
+\r
+/** @fn void can1HighLevelInterrupt(void)\r
+* @brief DCAN1 High Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (39) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(can1HighLevelInterrupt, IRQ)\r
+#endif\r
+\r
+void can1HighLevelInterrupt(void)\r
+{\r
+ unsigned value = canREG1->INT;\r
+\r
+/* USER CODE BEGIN (40) */\r
+/* USER CODE END */\r
+\r
+ if (value == 0x8000U)\r
+ {\r
+ canErrorNotification(canREG1, canREG1->ES & 0xE0U);\r
+ return;\r
+ }\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1CMD = 0x08;\r
+ canREG1->IF1NO = value;\r
+\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG1, value);\r
+\r
+/* USER CODE BEGIN (41) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can1LowLevelInterrupt(void)\r
+* @brief DCAN1 Low Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (42) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(can1LowLevelInterrupt, IRQ)\r
+#endif\r
+\r
+void can1LowLevelInterrupt(void)\r
+{\r
+ unsigned messageBox = canREG1->INT >> 16U;\r
+\r
+/* USER CODE BEGIN (43) */\r
+/* USER CODE END */\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1CMD = 0x08;\r
+ canREG1->IF1NO = messageBox;\r
+\r
+ while (canREG1->IF1STAT & 0x80);\r
+\r
+ canREG1->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG1, messageBox);\r
+\r
+/* USER CODE BEGIN (44) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can2HighLevelInterrupt(void)\r
+* @brief DCAN2 High Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (45) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(can2HighLevelInterrupt, IRQ)\r
+#endif\r
+\r
+void can2HighLevelInterrupt(void)\r
+{\r
+ unsigned value = canREG2->INT;\r
+\r
+/* USER CODE BEGIN (46) */\r
+/* USER CODE END */\r
+\r
+ if (value == 0x8000U)\r
+ {\r
+ canErrorNotification(canREG2, canREG2->ES & 0xE0U);\r
+ return;\r
+ }\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1CMD = 0x08;\r
+ canREG2->IF1NO = value;\r
+\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG2, value);\r
+\r
+/* USER CODE BEGIN (47) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void can2LowLevelInterrupt(void)\r
+* @brief DCAN2 Low Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (48) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(can2LowLevelInterrupt, IRQ)\r
+#endif\r
+\r
+void can2LowLevelInterrupt(void)\r
+{\r
+ unsigned messageBox = canREG2->INT >> 16U;\r
+\r
+/* USER CODE BEGIN (49) */\r
+/* USER CODE END */\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1CMD = 0x08;\r
+ canREG2->IF1NO = messageBox;\r
+\r
+ while (canREG2->IF1STAT & 0x80);\r
+\r
+ canREG2->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG2, messageBox);\r
+\r
+/* USER CODE BEGIN (50) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+#if 0\r
+/** @fn void phantomInterrupt(void)\r
+* @brief DCAN3 High Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (51) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(phantomInterrupt, IRQ)\r
+#endif\r
+\r
+void phantomInterrupt(void)\r
+{\r
+ unsigned value = canREG3->INT;\r
+\r
+/* USER CODE BEGIN (52) */\r
+/* USER CODE END */\r
+\r
+ if (value == 0x8000U)\r
+ {\r
+ canErrorNotification(canREG3, canREG3->ES & 0xE0U);\r
+ return;\r
+ }\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1CMD = 0x08;\r
+ canREG3->IF1NO = value;\r
+\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG3, value);\r
+\r
+/* USER CODE BEGIN (53) */\r
+/* USER CODE END */\r
+}\r
+\r
+\r
+/** @fn void phantomInterrupt(void)\r
+* @brief DCAN3 Low Level Interrupt Handler\r
+*/\r
+\r
+/* USER CODE BEGIN (54) */\r
+/* USER CODE END */\r
+\r
+#if 0\r
+ #pragma INTERRUPT(phantomInterrupt, IRQ)\r
+#endif\r
+\r
+void phantomInterrupt(void)\r
+{\r
+ unsigned messageBox = canREG3->INT >> 16U;\r
+\r
+/* USER CODE BEGIN (55) */\r
+/* USER CODE END */\r
+\r
+ /** - Setup IF1 for clear pending interrupt flag */\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1CMD = 0x08;\r
+ canREG3->IF1NO = messageBox;\r
+\r
+ while (canREG3->IF1STAT & 0x80);\r
+\r
+ canREG3->IF1CMD = 0x87;\r
+\r
+ canMessageNotification(canREG3, messageBox);\r
+\r
+/* USER CODE BEGIN (56) */\r
+/* USER CODE END */\r
+}\r
+#endif\r
+\r
+#endif\r
--- /dev/null
+/** @file can.h\r
+* @brief CAN Driver Header File\r
+* @date 10.August.2009\r
+* @version 1.00.000\r
+* \r
+* This file contains:\r
+* - Definitions\r
+* - Types\r
+* - Interface Prototypes\r
+* .\r
+* which are relevant for the CAN driver.\r
+*/\r
+\r
+/* (c) Texas Instruments 2009, All rights reserved. */\r
+\r
+\r
+#ifndef __CAN_H__\r
+#define __CAN_H__\r
+\r
+/* USER CODE BEGIN (0) */\r
+/* USER CODE END */\r
+\r
+\r
+/* CAN General Definitions */\r
+\r
+/** @def canLEVEL_ACTIVE\r
+* @brief Alias name for CAN error operation level active (Error couter 0-95) \r
+*/\r
+#define canLEVEL_ACTIVE 0x00U\r
+\r
+/** @def canLEVEL_WARNING\r
+* @brief Alias name for CAN error operation level warning (Error couter 96-127) \r
+*/\r
+#define canLEVEL_WARNING 0x40U\r
+\r
+/** @def canLEVEL_PASSIVE\r
+* @brief Alias name for CAN error operation level passive (Error couter 128-255) \r
+*/\r
+#define canLEVEL_PASSIVE 0x20U\r
+\r
+/** @def canLEVEL_BUS_OFF\r
+* @brief Alias name for CAN error operation level bus off (Error couter 256) \r
+*/\r
+#define canLEVEL_BUS_OFF 0x80U\r
+\r
+/** @def canERROR_NO\r
+* @brief Alias name for no CAN error occured \r
+*/\r
+#define canERROR_OK 0U\r
+\r
+/** @def canERROR_STUFF\r
+* @brief Alias name for CAN stuff error an RX message \r
+*/\r
+#define canERROR_STUFF 1U\r
+\r
+/** @def canERROR_FORMAT\r
+* @brief Alias name for CAN form/format error an RX message \r
+*/\r
+#define canERROR_FORMAT 2U\r
+\r
+/** @def canERROR_ACKNOWLEDGE\r
+* @brief Alias name for CAN TX message wasn't acknowledged \r
+*/\r
+#define canERROR_ACKNOWLEDGE 3U\r
+\r
+/** @def canERROR_BIT1\r
+* @brief Alias name for CAN TX message sendig recessive level but monitoring dominant \r
+*/\r
+#define canERROR_BIT1 4U\r
+\r
+/** @def canERROR_BIT0\r
+* @brief Alias name for CAN TX message sendig dominant level but monitoring recessive \r
+*/\r
+#define canERROR_BIT0 5U\r
+\r
+/** @def canERROR_CRC\r
+* @brief Alias name for CAN RX message received wrong CRC \r
+*/\r
+#define canERROR_CRC 6U\r
+\r
+/** @def canERROR_NO\r
+* @brief Alias name for CAN no message has send or received sinced last call of canGetLastError \r
+*/\r
+#define canERROR_NO 7U\r
+\r
+/** @def canMESSAGE_BOX1\r
+* @brief Alias name for CAN message box 1\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX1 1U\r
+\r
+/** @def canMESSAGE_BOX2\r
+* @brief Alias name for CAN message box 2\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX2 2U\r
+\r
+/** @def canMESSAGE_BOX3\r
+* @brief Alias name for CAN message box 3\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX3 3U\r
+\r
+/** @def canMESSAGE_BOX4\r
+* @brief Alias name for CAN message box 4\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX4 4U\r
+\r
+/** @def canMESSAGE_BOX5\r
+* @brief Alias name for CAN message box 5\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX5 5U\r
+\r
+/** @def canMESSAGE_BOX6\r
+* @brief Alias name for CAN message box 6\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX6 6U\r
+\r
+/** @def canMESSAGE_BOX7\r
+* @brief Alias name for CAN message box 7\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX7 7U\r
+\r
+/** @def canMESSAGE_BOX8\r
+* @brief Alias name for CAN message box 8\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX8 8U\r
+\r
+/** @def canMESSAGE_BOX9\r
+* @brief Alias name for CAN message box 9\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX9 9U\r
+\r
+/** @def canMESSAGE_BOX10\r
+* @brief Alias name for CAN message box 10\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX10 10U\r
+\r
+/** @def canMESSAGE_BOX11\r
+* @brief Alias name for CAN message box 11\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX11 11U\r
+\r
+/** @def canMESSAGE_BOX12\r
+* @brief Alias name for CAN message box 12\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX12 12U\r
+\r
+/** @def canMESSAGE_BOX13\r
+* @brief Alias name for CAN message box 13\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX13 13U\r
+\r
+/** @def canMESSAGE_BOX14\r
+* @brief Alias name for CAN message box 14\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX14 14U\r
+\r
+/** @def canMESSAGE_BOX15\r
+* @brief Alias name for CAN message box 15\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX15 15U\r
+\r
+/** @def canMESSAGE_BOX16\r
+* @brief Alias name for CAN message box 16\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX16 16U\r
+\r
+/** @def canMESSAGE_BOX17\r
+* @brief Alias name for CAN message box 17\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX17 17U\r
+\r
+/** @def canMESSAGE_BOX18\r
+* @brief Alias name for CAN message box 18\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX18 18U\r
+\r
+/** @def canMESSAGE_BOX19\r
+* @brief Alias name for CAN message box 19\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX19 19U\r
+\r
+/** @def canMESSAGE_BOX20\r
+* @brief Alias name for CAN message box 20\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX20 20U\r
+\r
+/** @def canMESSAGE_BOX21\r
+* @brief Alias name for CAN message box 21\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX21 21U\r
+\r
+/** @def canMESSAGE_BOX22\r
+* @brief Alias name for CAN message box 22\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX22 22U\r
+\r
+/** @def canMESSAGE_BOX23\r
+* @brief Alias name for CAN message box 23\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX23 23U\r
+\r
+/** @def canMESSAGE_BOX24\r
+* @brief Alias name for CAN message box 24\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX24 24U\r
+\r
+/** @def canMESSAGE_BOX25\r
+* @brief Alias name for CAN message box 25\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX25 25U\r
+\r
+/** @def canMESSAGE_BOX26\r
+* @brief Alias name for CAN message box 26\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX26 26U\r
+\r
+/** @def canMESSAGE_BOX27\r
+* @brief Alias name for CAN message box 27\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX27 27U\r
+\r
+/** @def canMESSAGE_BOX28\r
+* @brief Alias name for CAN message box 28\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX28 28U\r
+\r
+/** @def canMESSAGE_BOX29\r
+* @brief Alias name for CAN message box 29\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX29 29U\r
+\r
+/** @def canMESSAGE_BOX30\r
+* @brief Alias name for CAN message box 30\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX30 30U\r
+\r
+/** @def canMESSAGE_BOX31\r
+* @brief Alias name for CAN message box 31\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX31 31U\r
+\r
+/** @def canMESSAGE_BOX32\r
+* @brief Alias name for CAN message box 32\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX32 32U\r
+\r
+/** @def canMESSAGE_BOX33\r
+* @brief Alias name for CAN message box 33\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX33 33U\r
+\r
+/** @def canMESSAGE_BOX34\r
+* @brief Alias name for CAN message box 34\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX34 34U\r
+\r
+/** @def canMESSAGE_BOX35\r
+* @brief Alias name for CAN message box 35\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX35 35U\r
+\r
+/** @def canMESSAGE_BOX36\r
+* @brief Alias name for CAN message box 36\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX36 36U\r
+\r
+/** @def canMESSAGE_BOX37\r
+* @brief Alias name for CAN message box 37\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX37 37U\r
+\r
+/** @def canMESSAGE_BOX38\r
+* @brief Alias name for CAN message box 38\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX38 38U\r
+\r
+/** @def canMESSAGE_BOX39\r
+* @brief Alias name for CAN message box 39\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX39 39U\r
+\r
+/** @def canMESSAGE_BOX40\r
+* @brief Alias name for CAN message box 40\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX40 40U\r
+\r
+/** @def canMESSAGE_BOX41\r
+* @brief Alias name for CAN message box 41\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX41 41U\r
+\r
+/** @def canMESSAGE_BOX42\r
+* @brief Alias name for CAN message box 42\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX42 42U\r
+\r
+/** @def canMESSAGE_BOX43\r
+* @brief Alias name for CAN message box 43\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX43 43U\r
+\r
+/** @def canMESSAGE_BOX44\r
+* @brief Alias name for CAN message box 44\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX44 44U\r
+\r
+/** @def canMESSAGE_BOX45\r
+* @brief Alias name for CAN message box 45\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX45 45U\r
+\r
+/** @def canMESSAGE_BOX46\r
+* @brief Alias name for CAN message box 46\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX46 46U\r
+\r
+/** @def canMESSAGE_BOX47\r
+* @brief Alias name for CAN message box 47\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX47 47U\r
+\r
+/** @def canMESSAGE_BOX48\r
+* @brief Alias name for CAN message box 48\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX48 48U\r
+\r
+/** @def canMESSAGE_BOX49\r
+* @brief Alias name for CAN message box 49\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX49 49U\r
+\r
+/** @def canMESSAGE_BOX50\r
+* @brief Alias name for CAN message box 50\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX50 50U\r
+\r
+/** @def canMESSAGE_BOX51\r
+* @brief Alias name for CAN message box 51\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX51 51U\r
+\r
+/** @def canMESSAGE_BOX52\r
+* @brief Alias name for CAN message box 52\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX52 52U\r
+\r
+/** @def canMESSAGE_BOX53\r
+* @brief Alias name for CAN message box 53\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX53 53U\r
+\r
+/** @def canMESSAGE_BOX54\r
+* @brief Alias name for CAN message box 54\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX54 54U\r
+\r
+/** @def canMESSAGE_BOX55\r
+* @brief Alias name for CAN message box 55\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX55 55U\r
+\r
+/** @def canMESSAGE_BOX56\r
+* @brief Alias name for CAN message box 56\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX56 56U\r
+\r
+/** @def canMESSAGE_BOX57\r
+* @brief Alias name for CAN message box 57\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX57 57U\r
+\r
+/** @def canMESSAGE_BOX58\r
+* @brief Alias name for CAN message box 58\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX58 58U\r
+\r
+/** @def canMESSAGE_BOX59\r
+* @brief Alias name for CAN message box 59\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX59 59U\r
+\r
+/** @def canMESSAGE_BOX60\r
+* @brief Alias name for CAN message box 60\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX60 60U\r
+\r
+/** @def canMESSAGE_BOX61\r
+* @brief Alias name for CAN message box 61\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX61 61U\r
+\r
+/** @def canMESSAGE_BOX62\r
+* @brief Alias name for CAN message box 62\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX62 62U\r
+\r
+/** @def canMESSAGE_BOX63\r
+* @brief Alias name for CAN message box 63\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX63 63U\r
+\r
+/** @def canMESSAGE_BOX64\r
+* @brief Alias name for CAN message box 64\r
+*\r
+* @note This value should be used for API argument @a messageBox\r
+*/\r
+#define canMESSAGE_BOX64 64U\r
+\r
+/* USER CODE BEGIN (1) */\r
+/* USER CODE END */\r
+\r
+\r
+/** @struct canBase\r
+* @brief CAN Register Frame Definition\r
+*\r
+* This type is used to access the CAN Registers.\r
+*/\r
+/** @typedef canBASE_t\r
+* @brief CAN Register Frame Type Definition\r
+*\r
+* This type is used to access the CAN Registers.\r
+*/\r
+typedef volatile struct canBase\r
+{\r
+ unsigned CTL; /**< 0x0000: Control Register */\r
+ unsigned ES; /**< 0x0004: Error and Status Register */\r
+ unsigned EERC; /**< 0x0008: Error Counter Register */\r
+ unsigned BTR; /**< 0x000C: Bit Timing Register */\r
+ unsigned INT; /**< 0x0010: Interrupt Register */\r
+ unsigned TEST; /**< 0x0014: Test Register */\r
+ unsigned : 32U; /**< 0x0018: Reserved */\r
+ unsigned PERR; /**< 0x001C: Parity/SECDED Error Code Register */\r
+ unsigned REL; /**< 0x0020: Core Release Register */\r
+ unsigned ECCDIAG; /**< 0x0024: ECC Diagnostic Register */\r
+ unsigned ECCDIADSTAT; /**< 0x0028: ECC Diagnostic Status Register */\r
+ unsigned : 32U; /**< 0x002C: Reserved */\r
+ unsigned : 32U; /**< 0x0030: Reserved */\r
+ unsigned : 32U; /**< 0x0034: Reserved */\r
+ unsigned : 32U; /**< 0x0038: Reserved */\r
+ unsigned : 32U; /**< 0x003C: Reserved */\r
+ unsigned : 32U; /**< 0x0040: Reserved */\r
+ unsigned : 32U; /**< 0x0044: Reserved */\r
+ unsigned : 32U; /**< 0x0048: Reserved */\r
+ unsigned : 32U; /**< 0x004C: Reserved */\r
+ unsigned : 32U; /**< 0x0050: Reserved */\r
+ unsigned : 32U; /**< 0x0054: Reserved */\r
+ unsigned : 32U; /**< 0x0058: Reserved */\r
+ unsigned : 32U; /**< 0x005C: Reserved */\r
+ unsigned : 32U; /**< 0x0060: Reserved */\r
+ unsigned : 32U; /**< 0x0064: Reserved */\r
+ unsigned : 32U; /**< 0x0068: Reserved */\r
+ unsigned : 32U; /**< 0x006C: Reserved */\r
+ unsigned : 32U; /**< 0x0070: Reserved */\r
+ unsigned : 32U; /**< 0x0074: Reserved */\r
+ unsigned : 32U; /**< 0x0078: Reserved */\r
+ unsigned : 32U; /**< 0x007C: Reserved */\r
+ unsigned ABOTR; /**< 0x0080: Auto Bus On Time Register */\r
+ unsigned TXRQX; /**< 0x0084: Transmission Request X Register */\r
+ unsigned TXRQx[4U]; /**< 0x0088-0x0094: Transmission Request Registers */\r
+ unsigned NWDATX; /**< 0x0098: New Data X Register */\r
+ unsigned NWDATx[4U]; /**< 0x009C-0x00A8: New Data Registers */\r
+ unsigned INTPNDX; /**< 0x00AC: Interrupt Pending X Register */\r
+ unsigned INTPNDx[4U]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */\r
+ unsigned MSGVALX; /**< 0x00C0: Message Valid X Register */\r
+ unsigned MSGVALx[4U]; /**< 0x00C4-0x00D0: Message Valid Registers */\r
+ unsigned : 32U; /**< 0x00D4: Reserved */\r
+ unsigned INTMUXx[4U]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */\r
+ unsigned : 32U; /**< 0x00E8: Reserved */\r
+ unsigned : 32U; /**< 0x00EC: Reserved */\r
+ unsigned : 32U; /**< 0x00F0: Reserved */\r
+ unsigned : 32U; /**< 0x00F4: Reserved */\r
+ unsigned : 32U; /**< 0x00F8: Reserved */\r
+ unsigned : 32U; /**< 0x00FC: Reserved */\r
+#ifdef _little_endian__\r
+ unsigned char IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */\r
+ unsigned char IF1STAT; /**< 0x0100: IF1 Command Register, Status */\r
+ unsigned char IF1CMD; /**< 0x0100: IF1 Command Register, Command */\r
+ unsigned : 8U; /**< 0x0100: IF1 Command Register, Reserved */\r
+#else\r
+ unsigned : 8U; /**< 0x0100: IF1 Command Register, Reserved */\r
+ unsigned char IF1CMD; /**< 0x0100: IF1 Command Register, Command */\r
+ unsigned char IF1STAT; /**< 0x0100: IF1 Command Register, Status */\r
+ unsigned char IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */\r
+#endif\r
+ unsigned IF1MSK; /**< 0x0104: IF1 Mask Register */\r
+ unsigned IF1ARB; /**< 0x0108: IF1 Arbitration Register */\r
+ unsigned IF1MCTL; /**< 0x010C: IF1 Message Control Register */\r
+ unsigned char IF1DATx[8U]; /**< 0x0110-0x0114: IF1 Data A and B Registers */\r
+ unsigned : 32U; /**< 0x0118: Reserved */\r
+ unsigned : 32U; /**< 0x011C: Reserved */\r
+#ifdef _little_endian__\r
+ unsigned char IF2NO; /**< 0x0100: IF2 Command Register, Msg No */\r
+ unsigned char IF2STAT; /**< 0x0100: IF2 Command Register, Status */\r
+ unsigned char IF2CMD; /**< 0x0100: IF2 Command Register, Command */\r
+ unsigned : 8U; /**< 0x0100: IF2 Command Register, Reserved */\r
+#else\r
+ unsigned : 8U; /**< 0x0100: IF2 Command Register, Reserved */\r
+ unsigned char IF2CMD; /**< 0x0100: IF2 Command Register, Command */\r
+ unsigned char IF2STAT; /**< 0x0100: IF2 Command Register, Status */\r
+ unsigned char IF2NO; /**< 0x0100: IF2 Command Register, Msg Number */\r
+#endif\r
+ unsigned IF2MSK; /**< 0x0124: IF2 Mask Register */\r
+ unsigned IF2ARB; /**< 0x0128: IF2 Arbitration Register */\r
+ unsigned IF2MCTL; /**< 0x012C: IF2 Message Control Register */\r
+ unsigned char IF2DATx[8U]; /**< 0x0130-0x0134: IF2 Data A and B Registers */\r
+ unsigned : 32U; /**< 0x0138: Reserved */\r
+ unsigned : 32U; /**< 0x013C: Reserved */\r
+ unsigned IF3OBS; /**< 0x0140: IF3 Observation Register */\r
+ unsigned IF3MSK; /**< 0x0144: IF3 Mask Register */\r
+ unsigned IF3ARB; /**< 0x0148: IF3 Arbitration Register */\r
+ unsigned IF3MCTL; /**< 0x014C: IF3 Message Control Register */\r
+ unsigned char IF3DATx[8U]; /**< 0x0150-0x0154: IF3 Data A and B Registers */\r
+ unsigned : 32U; /**< 0x0158: Reserved */\r
+ unsigned : 32U; /**< 0x015C: Reserved */\r
+ unsigned IF3UEy[4U]; /**< 0x0160-0x016C: IF3 Update Enable Registers */\r
+ unsigned : 32U; /**< 0x0170: Reserved */\r
+ unsigned : 32U; /**< 0x0174: Reserved */\r
+ unsigned : 32U; /**< 0x0178: Reserved */\r
+ unsigned : 32U; /**< 0x017C: Reserved */\r
+ unsigned : 32U; /**< 0x0180: Reserved */\r
+ unsigned : 32U; /**< 0x0184: Reserved */\r
+ unsigned : 32U; /**< 0x0188: Reserved */\r
+ unsigned : 32U; /**< 0x018C: Reserved */\r
+ unsigned : 32U; /**< 0x0190: Reserved */\r
+ unsigned : 32U; /**< 0x0194: Reserved */\r
+ unsigned : 32U; /**< 0x0198: Reserved */\r
+ unsigned : 32U; /**< 0x019C: Reserved */\r
+ unsigned : 32U; /**< 0x01A0: Reserved */\r
+ unsigned : 32U; /**< 0x01A4: Reserved */\r
+ unsigned : 32U; /**< 0x01A8: Reserved */\r
+ unsigned : 32U; /**< 0x01AC: Reserved */\r
+ unsigned : 32U; /**< 0x01B0: Reserved */\r
+ unsigned : 32U; /**< 0x01B4: Reserved */\r
+ unsigned : 32U; /**< 0x01B8: Reserved */\r
+ unsigned : 32U; /**< 0x01BC: Reserved */\r
+ unsigned : 32U; /**< 0x01C0: Reserved */\r
+ unsigned : 32U; /**< 0x01C4: Reserved */\r
+ unsigned : 32U; /**< 0x01C8: Reserved */\r
+ unsigned : 32U; /**< 0x01CC: Reserved */\r
+ unsigned : 32U; /**< 0x01D0: Reserved */\r
+ unsigned : 32U; /**< 0x01D4: Reserved */\r
+ unsigned : 32U; /**< 0x01D8: Reserved */\r
+ unsigned : 32U; /**< 0x01DC: Reserved */\r
+ unsigned TIOC; /**< 0x01E0: TX IO Control Register */\r
+ unsigned RIOC; /**< 0x01E4: RX IO Control Register */\r
+} canBASE_t;\r
+\r
+\r
+/** @def canREG1\r
+* @brief DCAN1 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the DCAN1 registers.\r
+*/\r
+#define canREG1 ((canBASE_t *)0xFFF7DC00U)\r
+\r
+/** @def canREG2\r
+* @brief DCAN2 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the DCAN2 registers.\r
+*/\r
+#define canREG2 ((canBASE_t *)0xFFF7DE00U)\r
+\r
+/** @def canREG3\r
+* @brief DCAN3 Register Frame Pointer\r
+*\r
+* This pointer is used by the CAN driver to access the DCAN3 registers.\r
+*/\r
+#define canREG3 ((canBASE_t *)0xFFF7E000U)\r
+\r
+/* USER CODE BEGIN (2) */\r
+/* USER CODE END */\r
+\r
+\r
+/* CAN Interface Functions */\r
+\r
+void canInit(void);\r
+unsigned canTransmit(canBASE_t *node, unsigned messageBox, const unsigned char *data);\r
+unsigned canGetData(canBASE_t *node, unsigned messageBox, unsigned char * const data);\r
+unsigned canIsTxMessagePending(canBASE_t *node, unsigned messageBox);\r
+unsigned canIsRxMessageArrived(canBASE_t *node, unsigned messageBox);\r
+unsigned canIsMessageBoxValid(canBASE_t *node, unsigned messageBox);\r
+unsigned canGetLastError(canBASE_t *node);\r
+unsigned canGetErrorLevel(canBASE_t *node);\r
+void canEnableErrorNotification(canBASE_t *node);\r
+void canDisableErrorNotification(canBASE_t *node);\r
+unsigned canEnableMessageNotification(canBASE_t *node, unsigned messageBox);\r
+unsigned canDisableMessageNotification(canBASE_t *node, unsigned messageBox);\r
+\r
+/** @fn void canErrorNotification(canBASE_t *node, unsigned notification)\r
+* @brief Error notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] notification Error notification code:\r
+* - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and 127 \r
+* - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 \r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void canErrorNotification(canBASE_t *node, unsigned notification);\r
+\r
+/** @fn void canMessageNotification(canBASE_t *node, unsigned messageBox)\r
+* @brief Message notification\r
+* @param[in] node Pointer to CAN node:\r
+* - canREG1: DCAN1 node pointer\r
+* - canREG2: DCAN2 node pointer\r
+* - canREG3: DCAN3 node pointer\r
+* @param[in] messageBox Message box number of CAN node:\r
+* - canMESSAGE_BOX1: CAN message box 1\r
+* - canMESSAGE_BOXn: CAN message box n [n: 1-64]\r
+* - canMESSAGE_BOX64: CAN message box 64\r
+*\r
+* @note This function has to be provide by the user.\r
+*/\r
+void canMessageNotification(canBASE_t *node, unsigned messageBox);\r
+\r
+/* USER CODE BEGIN (3) */\r
+/* USER CODE END */\r
+\r
+\r
+#endif\r
\r
#include "internal.h"\r
#include "stack.h"\r
-#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
+#include "core_cr4.h"\r
\r
\r
/**\r
#define IRQ_DISABLE() cpsid i\r
\r
\r
+\r
+\r
+\r
+\r
// lr\r
#define REG_SAVE r4-r8,r10,r11\r
\r
\r
Irq_Handler:\r
+ mov r2, #0xDF // Swich back to sys mode.\r
+ msr cpsr_c, r2\r
push {REG_SAVE,lr}\r
sub.w sp,sp,#C_SIZE\r
mov.w r4,#LC_PATTERN\r
bx lr\r
\r
// b os_lc_restore\r
- \r
+\r
\r
/**\r
* Fake an interrupt stack to be able to return to thread mode.\r
+++ /dev/null
-\r
-/******************************************************************************\r
- * @file: core_cm3.c\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-\r
-\r
-#include <stdint.h>\r
-\r
-\r
-/* define compiler specific symbols */\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for armcc */\r
- #define __INLINE __inline /*!< inline keyword for armcc */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for iarcc */\r
- #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for gcc */\r
- #define __INLINE inline /*!< inline keyword for gcc */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-__ASM uint32_t __get_PSP(void)\r
-{\r
- mrs r0, psp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- msr psp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-__ASM uint32_t __get_MSP(void)\r
-{\r
- mrs r0, msp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_MSP(uint32_t mainStackPointer)\r
-{\r
- msr msp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-__ASM uint32_t __REV16(uint16_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-__ASM int32_t __REVSH(int16_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-__ASM void __CLREX(void)\r
-{\r
- clrex\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-__ASM uint32_t __get_BASEPRI(void)\r
-{\r
- mrs r0, basepri\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-__ASM void __set_BASEPRI(uint32_t basePri)\r
-{\r
- msr basepri, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-__ASM uint32_t __get_PRIMASK(void)\r
-{\r
- mrs r0, primask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-__ASM void __set_PRIMASK(uint32_t priMask)\r
-{\r
- msr primask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-__ASM uint32_t __get_FAULTMASK(void)\r
-{\r
- mrs r0, faultmask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-__ASM void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- msr faultmask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-__ASM uint32_t __get_CONTROL(void)\r
-{\r
- mrs r0, control\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-__ASM void __set_CONTROL(uint32_t control)\r
-{\r
- msr control, r0\r
- bx lr\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-#pragma diag_suppress=Pe940\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void)\r
-{\r
- __ASM("mrs r0, psp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM("msr psp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void)\r
-{\r
- __ASM("mrs r0, msp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM("msr msp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- __ASM("rev16 r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- __ASM("rbit r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- __ASM("ldrexb r0, [r0]");\r
- __ASM("bx lr"); \r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- __ASM("ldrexh r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- __ASM("ldrex r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- __ASM("strexb r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- __ASM("strexh r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- __ASM("strex r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-#pragma diag_default=Pe940\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_PSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, psp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfProcStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_MSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, msp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfMainStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-uint32_t __REV(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int32_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-int32_t __REVSH(int16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- uint8_t result=0;\r
- \r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- uint16_t result=0;\r
- \r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+++ /dev/null
-\r
-/******************************************************************************\r
- * @file: core_cm3.h\r
- * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version: V1.20\r
- * @date: 22. May 2009\r
- *----------------------------------------------------------------------------\r
- *\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-Mx \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
-\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
-\r
-/**\r
- * Lint configuration \n\r
- * ----------------------- \n\r
- *\r
- * The following Lint messages will be suppressed and not shown: \n\r
- * \n\r
- * --- Error 10: --- \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';' \n\r
- * \n\r
- * --- Error 530: --- \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n\r
- * \n\r
- * --- Error 550: --- \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * } \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n\r
- * \n\r
- * --- Error 754: --- \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 750: --- \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 528: --- \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * --- Error 751: --- \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n\r
- * \n\r
- * \n\r
- * Note: To re-enable a Message, insert a space before 'lint' * \n\r
- *\r
- */\r
-\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-#include <stdint.h> /* Include standard types */\r
-\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
-#endif\r
-\r
-\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */\r
-#endif\r
-\r
-\r
-\r
-\r
-/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
-\r
-#ifdef __cplusplus\r
-#define __I volatile /*!< defines 'read only' permissions */\r
-#else\r
-#define __I volatile const /*!< defines 'read only' permissions */\r
-#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Register Abstraction\r
- ******************************************************************************/\r
-\r
-\r
-/* System Reset */\r
-#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */\r
-#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */\r
-#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */\r
-#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */\r
-\r
-/* Core Debug */\r
-#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */\r
-#define ITM_TCR_ITMENA 1 /*!< ITM enable */\r
-\r
-\r
-\r
-\r
-/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */\r
-typedef struct\r
-{\r
- __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Software Trigger Interrupt Register */\r
-} NVIC_Type;\r
-\r
-\r
-/* memory mapping struct for System Control Block */\r
-typedef struct\r
-{\r
- __I uint32_t CPUID; /*!< CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< System Control Register */\r
- __IO uint32_t CCR; /*!< Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Processor Feature Register */\r
- __I uint32_t DFR; /*!< Debug Feature Register */\r
- __I uint32_t ADR; /*!< Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< ISA Feature Register */\r
-} SCB_Type;\r
-\r
-\r
-/* memory mapping struct for SysTick */\r
-typedef struct\r
-{\r
- __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
-} SysTick_Type;\r
-\r
-\r
-/* memory mapping structur for ITM */\r
-typedef struct\r
-{\r
- __O union \r
- {\r
- __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __IO uint32_t IWR; /*!< ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __IO uint32_t LAR; /*!< ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< ITM Product ID Registers */\r
- __I uint32_t PID5;\r
- __I uint32_t PID6;\r
- __I uint32_t PID7;\r
- __I uint32_t PID0;\r
- __I uint32_t PID1;\r
- __I uint32_t PID2;\r
- __I uint32_t PID3;\r
- __I uint32_t CID0;\r
- __I uint32_t CID1;\r
- __I uint32_t CID2;\r
- __I uint32_t CID3;\r
-} ITM_Type;\r
-\r
-\r
-/* memory mapped struct for Interrupt Type */\r
-typedef struct\r
-{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
-\r
-\r
-/* Memory Protection Unit */\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-typedef struct\r
-{\r
- __I uint32_t TYPE; /*!< MPU Type Register */\r
- __IO uint32_t CTRL; /*!< MPU Control Register */\r
- __IO uint32_t RNR; /*!< MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type;\r
-#endif\r
-\r
-\r
-/* Core Debug Register */\r
-typedef struct\r
-{\r
- __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */\r
-} CoreDebug_Type;\r
-\r
-\r
-/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
-#endif\r
-\r
-\r
-\r
-/*******************************************************************************\r
- * Hardware Abstraction Layer\r
- ******************************************************************************/\r
-\r
-\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0x1ff);\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @param none\r
- * @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
-\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param uint32_t Process Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @param none\r
- * @return uint32_t Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param uint32_t Main Stack Pointer\r
- * @return none\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @param none\r
- * @return uint32_t BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param uint32_t BasePriority\r
- * @return none\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @param none\r
- * @return uint32_t PriMask\r
- *\r
- * Return the state of the priority mask bit from the priority mask\r
- * register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param uint32_t PriMask\r
- * @return none\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @param none\r
- * @return uint32_t FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param uint32_t faultMask value\r
- * @return none\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @param none\r
-* @return uint32_t Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param uint32_t Control value\r
- * @return none\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param uint16_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/*\r
- * Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param int16_t value to reverse\r
- * @return int32_t reversed value\r
- *\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param uint32_t value to reverse\r
- * @return uint32_t reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint8_t* address\r
- * @return uint8_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint16_t* address\r
- * @return uint16_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive\r
- *\r
- * @param uint32_t* address\r
- * @return uint32_t value of (*address)\r
- *\r
- * Exclusive LDR command\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint8_t *address\r
- * @param uint8_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint16_t *address\r
- * @param uint16_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive\r
- *\r
- * @param uint32_t *address\r
- * @param uint32_t value to store\r
- * @return uint32_t successful / failed\r
- *\r
- * Exclusive STR command\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param uint32_t priority_grouping is priority grouping field\r
- * @return none \r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
-{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */\r
- reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
-}\r
-\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @param none\r
- * @return uint32_t priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */\r
-}\r
-\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn_Type IRQn specifies the interrupt number\r
- * @return none \r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn_Type IRQn is the positive number of the external interrupt\r
- * @return none\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn_Type IRQn is the number of the device specifc interrupt\r
- * @return uint32_t 1 if pending interrupt else 0\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return none\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t 1 if active else 0\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @param priority is the priority for the interrupt\r
- * @return none\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt. \n\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
-{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
-}\r
-\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn_Type IRQn is the Number of the interrupt\r
- * @return uint32_t priority is the priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
-{\r
-\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
-}\r
-\r
-\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param uint32_t PriorityGroup is the used priority group\r
- * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)\r
- * @param uint32_t SubPriority is the sub priority value (starting from 0)\r
- * @return uint32_t the priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
- */\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
- );\r
-}\r
-\r
-\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param uint32_t Priority the priority for the interrupt\r
- * @param uint32_t PrioGroup is the used priority group\r
- * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)\r
- * @param uint32_t* pSubPrio is the sub priority value (starting from 0)\r
- * @return none\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
- */\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
-{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- uint32_t PreemptPriorityBits;\r
- uint32_t SubPriorityBits;\r
-\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
-}\r
-\r
-\r
-\r
-/* ################################## SysTick function ############################################ */\r
-\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
-\r
-/* SysTick constants */\r
-#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */\r
-#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */\r
-#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */\r
-#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */\r
-\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param uint32_t ticks is the number of ticks between two interrupts\r
- * @return none\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
- */\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
-\r
- SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
- SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
-\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-/* ################################## Reset function ############################################ */\r
-\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * @param none\r
- * @return none\r
- *\r
- * Initialize a system reset request to reset the MCU\r
- */\r
-static __INLINE void NVIC_SystemReset(void)\r
-{\r
- SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
-}\r
-\r
-\r
-/* ################################## Debug Output function ############################################ */\r
-\r
-\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param uint32_t character to output\r
- * @return uint32_t input character\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
- */\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
-{\r
- if (ch == '\n') ITM_SendChar('\r');\r
- \r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&\r
- (ITM->TCR & ITM_TCR_ITMENA) &&\r
- (ITM->TER & (1UL << 0)) ) \r
- {\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
- return (ch);\r
-}\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
--- /dev/null
+/*\r
+ * core_cr4.h\r
+ *\r
+ * Created on: 12 okt 2010\r
+ * Author: maek\r
+ */\r
+\r
+#ifndef CORE_CR4_H_\r
+#define CORE_CR4_H_\r
+\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+typedef volatile struct vimBase\r
+{\r
+ unsigned : 24U; /* 0x0000 */\r
+ unsigned IRQIVEC : 8U; /* 0x0000 */\r
+ unsigned : 24U; /* 0x0004 */\r
+ unsigned FIQIVEC : 8U; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned FIRQPR0; /* 0x0010 */\r
+ unsigned FIRQPR1; /* 0x0014 */\r
+ unsigned FIRQPR2; /* 0x0018 */\r
+ unsigned FIRQPR3; /* 0x001C */\r
+ unsigned INTREQ0; /* 0x0020 */\r
+ unsigned INTREQ1; /* 0x0024 */\r
+ unsigned INTREQ2; /* 0x0028 */\r
+ unsigned INTREQ3; /* 0x002C */\r
+ unsigned REQMASKSET0; /* 0x0030 */\r
+ unsigned REQMASKSET1; /* 0x0034 */\r
+ unsigned REQMASKSET2; /* 0x0038 */\r
+ unsigned REQMASKSET3; /* 0x003C */\r
+ unsigned REQMASKCLR0; /* 0x0040 */\r
+ unsigned REQMASKCLR1; /* 0x0044 */\r
+ unsigned REQMASKCLR2; /* 0x0048 */\r
+ unsigned REQMASKCLR3; /* 0x004C */\r
+ unsigned WAKEMASKSET0; /* 0x0050 */\r
+ unsigned WAKEMASKSET1; /* 0x0054 */\r
+ unsigned WAKEMASKSET2; /* 0x0058 */\r
+ unsigned WAKEMASKSET3; /* 0x005C */\r
+ unsigned WAKEMASKCLR0; /* 0x0060 */\r
+ unsigned WAKEMASKCLR1; /* 0x0064 */\r
+ unsigned WAKEMASKCLR2; /* 0x0068 */\r
+ unsigned WAKEMASKCLR3; /* 0x006C */\r
+ unsigned IRQVECREG; /* 0x0070 */\r
+ unsigned FIQVECREQ; /* 0x0074 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC1 : 7U; /* 0x0078 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC0 : 7U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned char CHANMAP[64U]; /* 0x0080-0x017C */\r
+} vimBASE_t;\r
+\r
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)\r
+\r
+\r
+\r
+typedef volatile struct rtiBase\r
+{\r
+ unsigned GCTRL; /**< 0x0000: Global Control Register */\r
+ unsigned TBCTRL; /**< 0x0004: Timebase Control Register */\r
+ unsigned CAPCTRL; /**< 0x0008: Capture Control Register */\r
+ unsigned COMPCTRL; /**< 0x000C: Compare Control Register */\r
+ struct\r
+ {\r
+ unsigned FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */\r
+ unsigned UCx; /**< 0x0014,0x0034: Up Counter x Register */\r
+ unsigned CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */\r
+ unsigned : 32; /**< 0x001C,0x003C: Reserved */\r
+ unsigned CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */\r
+ unsigned CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */\r
+ unsigned : 32; /**< 0x0028,0x0048: Reserved */\r
+ unsigned : 32; /**< 0x002C,0x004C: Reserved */\r
+ } CNT[2U]; /**< Counter x selection:\r
+ - 0: Counter 0\r
+ - 1: Counter 1 */\r
+ struct\r
+ {\r
+ unsigned COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */\r
+ unsigned UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */\r
+ } CMP[4U]; /**< Compare x selection:\r
+ - 0: Compare 0\r
+ - 1: Compare 1\r
+ - 2: Compare 2\r
+ - 3: Compare 3 */\r
+ unsigned TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */\r
+ unsigned TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */\r
+ unsigned : 32; /**< 0x0078: Reserved */\r
+ unsigned : 32; /**< 0x007C: Reserved */\r
+ unsigned SETINT; /**< 0x0080: Set/Status Interrupt Register */\r
+ unsigned CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */\r
+ unsigned INTFLAG; /**< 0x008C: Interrupt Flag Register */\r
+} rtiBASE_t;\r
+\r
+/** @def rtiREG1\r
+* @brief RTI1 Register Frame Pointer\r
+*\r
+* This pointer is used by the RTI driver to access the RTI1 registers.\r
+*/\r
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00)\r
+\r
+\r
+enum systemClockSource\r
+{\r
+ SYS_OSC = 0, /**< Alias for oscillator clock Source */\r
+ SYS_PLL = 1, /**< Alias for Pll clock Source */\r
+ SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */\r
+ SYS_EXTERNAL = 3, /**< Alias for external clock Source */\r
+ SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */\r
+ SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */\r
+ SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */\r
+ SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */\r
+};\r
+\r
+typedef volatile struct systemBase1\r
+{\r
+ unsigned SYSPC1; /* 0x0000 */\r
+ unsigned SYSPC2; /* 0x0004 */\r
+ unsigned SYSPC3; /* 0x0008 */\r
+ unsigned SYSPC4; /* 0x000C */\r
+ unsigned SYSPC5; /* 0x0010 */\r
+ unsigned SYSPC6; /* 0x0014 */\r
+ unsigned SYSPC7; /* 0x0018 */\r
+ unsigned SYSPC8; /* 0x001C */\r
+ unsigned SYSPC9; /* 0x0020 */\r
+ unsigned SSWPLL1; /* 0x0024 */\r
+ unsigned SSWPLL2; /* 0x0028 */\r
+ unsigned SSWPLL3; /* 0x002C */\r
+ unsigned CSDIS; /* 0x0030 */\r
+ unsigned CSDISSET; /* 0x0034 */\r
+ unsigned CSDISCLR; /* 0x0038 */\r
+ unsigned CSDDIS; /* 0x003C */\r
+ unsigned CSDDISSET; /* 0x0040 */\r
+ unsigned CSDDISCLR; /* 0x0044 */\r
+ unsigned GHVSRC; /* 0x0048 */\r
+ unsigned VCLKASRC; /* 0x004C */\r
+ unsigned RCLKSRC; /* 0x0050 */\r
+ unsigned CSVSTAT; /* 0x0054 */\r
+ unsigned MSTGCR; /* 0x0058 */\r
+ unsigned MINITGCR; /* 0x005C */\r
+ unsigned MSINENA; /* 0x0060 */\r
+ unsigned MSTFAIL; /* 0x0064 */\r
+ unsigned MSTCGSTAT; /* 0x0068 */\r
+ unsigned MINISTAT; /* 0x006C */\r
+ unsigned PLLCTL1; /* 0x0070 */\r
+ unsigned PLLCTL2; /* 0x0074 */\r
+ unsigned UERFLAG; /* 0x0078 */\r
+ unsigned DIEIDL; /* 0x007C */\r
+ unsigned DIEIDH; /* 0x0080 */\r
+ unsigned VRCTL; /* 0x0084 */\r
+ unsigned LPOMONCTL; /* 0x0088 */\r
+ unsigned CLKTEST; /* 0x008C */\r
+ unsigned DFTCTRLREG1; /* 0x0090 */\r
+ unsigned DFTCTRLREG2; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned GPREG1; /* 0x00A0 */\r
+ unsigned BTRMSEL; /* 0x00A4 */\r
+ unsigned IMPFASTS; /* 0x00A8 */\r
+ unsigned IMPFTADD; /* 0x00AC */\r
+ unsigned SSISR1; /* 0x00B0 */\r
+ unsigned SSISR2; /* 0x00B4 */\r
+ unsigned SSISR3; /* 0x00B8 */\r
+ unsigned SSISR4; /* 0x00BC */\r
+ unsigned RAMGCR; /* 0x00C0 */\r
+ unsigned BMMCR1; /* 0x00C4 */\r
+ unsigned BMMCR2; /* 0x00C8 */\r
+ unsigned MMUGCR; /* 0x00CC */\r
+#ifdef _little_endian__\r
+ unsigned : 8U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+#else\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 8U; /* 0x00D0 */\r
+#endif\r
+ unsigned : 32U; /* 0x00D4 */\r
+ unsigned DSPGCR; /* 0x00D8 */\r
+ unsigned DEVCR1; /* 0x00DC */\r
+ unsigned SYSECR; /* 0x00E0 */\r
+ unsigned SYSESR; /* 0x00E4 */\r
+ unsigned ITIFLAG; /* 0x00E8 */\r
+ unsigned GBLSTAT; /* 0x00EC */\r
+ unsigned DEV; /* 0x00F0 */\r
+ unsigned SSIVEC; /* 0x00F4 */\r
+ unsigned SSIF; /* 0x00F8 */\r
+} systemBASE1_t;\r
+\r
+\r
+/** @def systemREG1\r
+* @brief System Register Frame 1 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 1 registers.\r
+*/\r
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)\r
+\r
+\r
+/** @def PRE1\r
+* @brief Alias name for RTI1CLK PRE clock source\r
+*\r
+* This is an alias name for the RTI1CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE1 SYS_PLL\r
+\r
+/** @def PRE2\r
+* @brief Alias name for RTI2CLK pre clock source\r
+*\r
+* This is an alias name for the RTI2CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE2 SYS_PLL\r
+\r
+typedef volatile struct systemBase2\r
+{\r
+ unsigned PLLCTL3; /* 0x0000 */\r
+ unsigned : 32U; /* 0x0004 */\r
+ unsigned STCCLKDIV; /* 0x0008 */\r
+ unsigned CLKHB_GLBREG; /* 0x000C */\r
+ unsigned CLKHB_RTIDREG; /* 0x0010 */\r
+ unsigned HBCD_STAT; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned CLKTRMI1; /* 0x0020 */\r
+ unsigned ECPCNTRL0; /* 0x0024 */\r
+ unsigned ECPCNTRL1; /* 0x0028 */\r
+ unsigned ECPCNTRL2; /* 0x002C */\r
+ unsigned ECPCNTRL3; /* 0x0030 */\r
+} systemBASE2_t;\r
+\r
+\r
+/** @def systemREG2\r
+* @brief System Register Frame 2 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 2 registers.\r
+*/\r
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)\r
+\r
+typedef volatile struct pcrBase\r
+{\r
+ unsigned PMPROTSET0; /* 0x0000 */\r
+ unsigned PMPROTSET1; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned PMPROTCLR0; /* 0x0010 */\r
+ unsigned PMPROTCLR1; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned PPROTSET0; /* 0x0020 */\r
+ unsigned PPROTSET1; /* 0x0024 */\r
+ unsigned PPROTSET2; /* 0x0028 */\r
+ unsigned PPROTSET3; /* 0x002C */\r
+ unsigned : 32U; /* 0x0030 */\r
+ unsigned : 32U; /* 0x0034 */\r
+ unsigned : 32U; /* 0x0038 */\r
+ unsigned : 32U; /* 0x003C */\r
+ unsigned PPROTCLR0; /* 0x0040 */\r
+ unsigned PPROTCLR1; /* 0x0044 */\r
+ unsigned PPROTCLR2; /* 0x0048 */\r
+ unsigned PPROTCLR3; /* 0x004C */\r
+ unsigned : 32U; /* 0x0050 */\r
+ unsigned : 32U; /* 0x0054 */\r
+ unsigned : 32U; /* 0x0058 */\r
+ unsigned : 32U; /* 0x005C */\r
+ unsigned PCSPWRDWNSET0; /* 0x0060 */\r
+ unsigned PCSPWRDWNSET1; /* 0x0064 */\r
+ unsigned : 32U; /* 0x0068 */\r
+ unsigned : 32U; /* 0x006C */\r
+ unsigned PCSPWRDWNCLR0; /* 0x0070 */\r
+ unsigned PCSPWRDWNCLR1; /* 0x0074 */\r
+ unsigned : 32U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned PSPWRDWNSET0; /* 0x0080 */\r
+ unsigned PSPWRDWNSET1; /* 0x0084 */\r
+ unsigned PSPWRDWNSET2; /* 0x0088 */\r
+ unsigned PSPWRDWNSET3; /* 0x008C */\r
+ unsigned : 32U; /* 0x0090 */\r
+ unsigned : 32U; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned PSPWRDWNCLR0; /* 0x00A0 */\r
+ unsigned PSPWRDWNCLR1; /* 0x00A4 */\r
+ unsigned PSPWRDWNCLR2; /* 0x00A8 */\r
+ unsigned PSPWRDWNCLR3; /* 0x00AC */\r
+} pcrBASE_t;\r
+\r
+/** @def pcrREG\r
+* @brief Pcr Register Frame Pointer\r
+*\r
+* This pointer is used by the system driver to access the Pcr registers.\r
+*/\r
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
+\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+static inline void __disable_irq() {\r
+ __asm volatile("CPSID if");\r
+}\r
+static inline void __enable_irq() {\r
+ __asm volatile("CPSIE if");\r
+\r
+ /*\r
+ __asm volatile("MRS R1, CPSR");\r
+ __asm volatile("BIC R1, R1, #0x80");\r
+ __asm volatile("MSR CPSR, R1");\r
+\r
+ __asm volatile("MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0");\r
+ __asm volatile("ORR R1 ,R1 ,#0x01000000"); //Mask 0-31 bits except bit 24 in Sys ; Ctrl Reg of CORTEX-R4\r
+ __asm volatile("MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0"); //; Enable bit 24\r
+ //__asm volatile("SVC #1");\r
+ */\r
+\r
+}\r
+\r
+\r
+\r
+\r
+#endif /* CORE_CR4_H_ */\r
#include "internal.h"
#include "task_i.h"
#include "hooks.h"
-#include "stm32f10x.h"
#include "irq.h"
-#include "core_cm3.h"
+#include "core_cr4.h"
extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
#define AIRCR_VECTKEY ((uint32_t)0x05FA0000)
/** Set NVIC prio group */
+/* TODO remove
static void NVIC_SetPrioGroup(uint32_t prioGroup)
{
SCB->AIRCR = AIRCR_VECTKEY | (prioGroup<<8);
}
+*/
-void Irq_Init( void ) {
- //NVIC_SetPrioGroup(3); // No sub prioritys
+
+
+static inline void Irq_Setup() {
+ vimREG->FIRQPR0 = 0x0;
+ vimREG->FIRQPR1 = 0x0;
}
-void Irq_EOI( void ) {
- /* Note!
- * This is not applicable on the Cortex-M3 since we
- * can't terminate the interrupt request without popping
- * back registers..have to be solved in the context switches
- * themselves.
- */
+void Irq_Init( void ) {
+ Irq_Setup();
+ Irq_Enable();
}
+
#define ICSR_VECTACTIVE 0x1ff
/**
* Registers. INTISR[0] has vector number 16.
*
*/
+/* TODO remove
static uint32_t NVIC_GetActiveVector( void) {
return (SCB->ICSR & ICSR_VECTACTIVE);
}
+*/
/**
* Init NVIC vector. We do not use subriority
* @param vector The IRQ number
* @param prio NVIC priority, 0-15, 0-high prio
*/
+/* TODO remove
static void NVIC_InitVector(IRQn_Type vector, uint32_t prio)
{
// Set prio
//NVIC_EnableIRQ(vector);
NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
}
+*/
/**
*
*/
void *Irq_Entry( void *stack_p )
{
- uint32_t vector = 0;
uint32_t *stack;
+ // Get the active interrupt channel
+ uint8 channel = IrqGetCurrentInterruptSource();
+
Irq_Disable();
stack = (uint32_t *)stack_p;
- /* 0. Set the default handler here....
- * 1. Grab the vector from the interrupt controller
- * INT_CTRL_ST[VECTACTIVE]
- * 2. Irq_VectorTable[vector] is odd -> ISR1
- * Irq_VectorTable[vector] is even-> ISR2
- */
-
-
- vector = NVIC_GetActiveVector();
+ stack = Os_Isr(stack, (void *)Irq_VectorTable[channel]);
- stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);
Irq_Enable();
return stack;
}
OsPcbType *pcb;
pcb = os_find_task(tid);
- Irq_VectorTable[vector+16] = (void *)pcb;
+ Irq_VectorTable[vector] = (void *)pcb;
+ IrqActivateChannel(vector);
- NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
+ // TOdo replace NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
}
*/
void Irq_GenerateSoftInt( IrqType vector ) {
- NVIC->STIR = (vector);
+ // Todo replace NVIC->STIR = (vector);
}
/**
#ifndef IRQ_TYPES_H\r
#define IRQ_TYPES_H\r
\r
-#include "stm32f10x.h"\r
+#define IrqGetCurrentInterruptSource() \\r
+ (((uint8)vimREG->IRQIVEC) - 1)\r
+\r
+/** IrqActivateChannel turns the selected channel on in the VIM */\r
+#define IrqActivateChannel(_channel) \\r
+ vimREG->REQMASKSET0 |= (1 << _channel)\r
+\r
+\r
+/** IrqDeactivateChannel turns the selected channel off in the VIM */\r
+#define IrqDeactivateChannel(_channel) \\r
+ vimREG->REQMASKCLR0 = (1 << _channel)\r
+\r
+\r
+#define Irq_SOI() \\r
+ uint8 channel = IrqGetCurrentInterruptSource(); \\r
+ IrqDeactivateChannel(channel)\r
+\r
+\r
+#define Irq_EOI() \\r
+ IrqActivateChannel(channel)\r
+\r
+\r
+\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\r
+\r
+/****** STM32 specific Interrupt Numbers *********************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMPER_IRQn = 2, /*!< Tamper Interrupt */\r
+ RTC_IRQn = 3, /*!< RTC global Interrupt */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\r
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\r
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\r
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\r
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
+\r
+#ifdef STM32F10X_LD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+#endif /* STM32F10X_LD */\r
+\r
+#ifdef STM32F10X_MD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+#endif /* STM32F10X_MD */\r
+\r
+#ifdef STM32F10X_HD\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\r
+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\r
+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+#endif /* STM32F10X_HD */\r
+\r
+#ifdef STM32F10X_CL\r
+ CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\r
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\r
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */\r
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */\r
+#endif /* STM32F10X_CL */\r
+} IRQn_Type;\r
\r
typedef IRQn_Type IrqType;\r
\r
/* Offset from start of exceptions to interrupts\r
* Exceptions have negative offsets while interrupts have positive\r
*/\r
-#define IRQ_INTERRUPT_OFFSET 16\r
+//#define IRQ_INTERRUPT_OFFSET 16\r
\r
/* Total number of interrupts and exceptions\r
*/\r
-\r
-#if defined(STM32F10X_LD) || defined(STM32F10X_MD)\r
-#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS (USBWakeUp_IRQn+IRQ_INTERRUPT_OFFSET)\r
-#elif defined(STM32F10X_HD)\r
-#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS (DMA2_Channel4_5_IRQn+IRQ_INTERRUPT_OFFSET)\r
-#elif defined(STM32F10X_CL)\r
-#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS (OTG_FS_IRQn+IRQ_INTERRUPT_OFFSET)\r
-#else\r
-#error No device selected\r
-#endif\r
-\r
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 65\r
\r
typedef enum {\r
PERIPHERAL_CLOCK_AHB,\r
.type Reset_Handler, %function\r
Reset_Handler: \r
\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
+/* Set big endian state */\r
+ SETEND BE\r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+ movs r1, #0\r
+\r
+\r
+Init_Registers:\r
+\r
+ mov r0, #0x0000\r
+ mov r1, #0x0000\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mov r1, #0x03D0\r
+ orr r2, r1, #0x0001\r
+ msr cpsr_cxsf, r2\r
+ msr spsr_cxsf, r2\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r12, r1, #0x0002\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0007\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x000B\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0003\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+\r
+ /* System level configuration */\r
+ mrc p15,0,r11,c1,c0,0 /* Read current system configuration */\r
+ mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
+ orr r12, r12, r11\r
+ mcr p15,0,r12,c1,c0,0 /* Write new configuration */\r
+\r
+\r
+Init_Stack_Pointers:\r
+\r
+user: .word _estack\r
+svc: .word _estack\r
+fiq: .word _estack\r
+irq: .word _estack\r
+abort: .word _estack\r
+undef: .word _estack\r
+\r
+ mov r2, #0xD1\r
+ msr cpsr_c, r2\r
+ ldr sp, fiq\r
+\r
+ mov r2, #0xD2\r
+ msr cpsr_c, r2\r
+ ldr sp, irq\r
+\r
+ mov r2, #0xD7\r
+ msr cpsr_c, r2\r
+ ldr sp, abort\r
+\r
+ mov r2, #0xDB\r
+ msr cpsr_c, r2\r
+ ldr sp, undef\r
+\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ ldr sp, user\r
+\r
+ mov r2, #0xD3\r
+ msr cpsr_c, r2\r
+ ldr sp, svc\r
+\r
+\r
+CopyInitializedData:\r
+ ldr r0, =_sdata /* r0 holds start of data in ram */\r
+ ldr r3, =_edata /* r3 holds end of data in ram */\r
+ ldr r5, =_sidata /* r5 start of data in flash */\r
+ movs r1, #0 /* r1 is the counter */\r
+ b LoopCopyDataInit\r
\r
CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
+ ldr r4, [r5, r1] /* read current position in flash */\r
+ str r4, [r0, r1] /* store current position in ram */\r
+ adds r1, r1, #4 /* increment counter */\r
\r
LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
+ adds r2, r0, r1 /* are we at the final position? */\r
+ cmp r2, r3 /* ... */\r
+ bcc CopyDataInit /* nope, continue */\r
+\r
+/* Fill zero areas */\r
+ ldr r2, =_sbss /* r2 holds the start address */\r
+ ldr r5, =_ebss /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+ ldr r2, =_sstack /* r2 holds the start address */\r
+ ldr r5, =_estack /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+/* Call the application's entry point.*/\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ bl main\r
+ bx lr\r
+\r
/* Zero fill the bss segment. */ \r
-FillZerobss:\r
+FillZero:\r
movs r3, #0\r
- str r3, [r2], #4\r
+ str r3, [r2], #4\r
\r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
+LoopFillZero:\r
+ cmp r2, r5\r
+ bcc FillZero\r
+ bx lr\r
+\r
+Dummy_Irq:\r
+ nop\r
+ nop\r
+ b Dummy_Irq\r
+\r
.size Reset_Handler, .-Reset_Handler\r
\r
/**\r
Infinite_Loop:\r
b Infinite_Loop\r
.size Default_Handler, .-Default_Handler\r
+\r
+\r
/******************************************************************************\r
-* Vector table for a Cortex M3. Vectors start at addr 0x0.\r
+* Interrupt and exception vectors. Vectors start at addr 0x0.\r
******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
-\r
+ .section .int_vecs,"ax",%progbits\r
.extern Irq_Handler\r
\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
+ b Dummy_Irq /* Reset? */\r
+ b Dummy_Irq /* Undef? */\r
+ b Dummy_Irq /* SVC */\r
+ b Dummy_Irq /* Prefetch */\r
+ b Dummy_Irq /* data */\r
+ b Dummy_Irq /* ? */\r
+ b Irq_Handler /* IRQ */\r
+ b Irq_Handler /* FIR */\r
\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; sys_core.asm\r
+;\r
+; (c) Texas Instruments 2009, All rights reserved.\r
+;\r
+\r
+ .text\r
+ .arm\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initialize CPU Registers\r
+\r
+ .global _coreInitRegisters_\r
+ .asmfunc\r
+\r
+_coreInitRegisters_:\r
+\r
+ mov r0, lr\r
+ mov r1, #0x03D0\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r13, r1, #0x0001\r
+ msr cpsr_cxsf, r13\r
+ msr spsr_cxsf, r13\r
+ mov lr, r0\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r13, r1, #0x0002\r
+ msr cpsr_c, r13\r
+ msr spsr_cxsf, r13\r
+ mov lr, r0\r
+ orr r13, r1, #0x0007\r
+ msr cpsr_c, r13\r
+ msr spsr_cxsf, r13\r
+ mov lr, r0\r
+ orr r13, r1, #0x000B\r
+ msr cpsr_c, r13\r
+ msr spsr_cxsf, r13\r
+ mov lr, r0\r
+ orr r13, r1, #0x0003\r
+ msr cpsr_c, r13\r
+ msr spsr_cxsf, r13\r
+\r
+ .if 1\r
+ fmdrr d0, r1, r1\r
+ fmdrr d1, r1, r1\r
+ fmdrr d2, r1, r1\r
+ fmdrr d3, r1, r1\r
+ fmdrr d4, r1, r1\r
+ fmdrr d5, r1, r1\r
+ fmdrr d6, r1, r1\r
+ fmdrr d7, r1, r1\r
+ fmdrr d8, r1, r1\r
+ fmdrr d9, r1, r1\r
+ fmdrr d10, r1, r1\r
+ fmdrr d11, r1, r1\r
+ fmdrr d12, r1, r1\r
+ fmdrr d13, r1, r1\r
+ fmdrr d14, r1, r1\r
+ fmdrr d15, r1, r1\r
+ .endif\r
+\r
+ bl $+4\r
+ bl $+4\r
+ bl $+4\r
+ bl $+4\r
+ bx r0\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Initialize Stack Pointers\r
+\r
+ .global _coreInitStackPointer_\r
+ .asmfunc\r
+\r
+_coreInitStackPointer_:\r
+\r
+ msr cpsr_c, #0xD1\r
+ ldr sp, fiq\r
+ msr cpsr_c, #0xD2\r
+ ldr sp, irq\r
+ msr cpsr_c, #0xD7\r
+ ldr sp, abort\r
+ msr cpsr_c, #0xDB\r
+ ldr sp, undef\r
+ msr cpsr_c, #0xDF\r
+ ldr sp, user\r
+ msr cpsr_c, #0xD3\r
+ ldr sp, svc\r
+ bx lr\r
+\r
+user: .word 0x08000000+0x00001000\r
+svc: .word 0x08000000+0x00001000+0x00000100\r
+fiq: .word 0x08000000+0x00001000+0x00000100+0x00000100\r
+irq: .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100\r
+abort: .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100\r
+undef: .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable VFP Unit\r
+\r
+ .global _coreEnableVfp_\r
+ .asmfunc\r
+\r
+_coreEnableVfp_:\r
+\r
+ .if 1\r
+ mrc p15, #0x00, r0, c1, c0, #0x02\r
+ orr r0, r0, #0xF00000\r
+ mcr p15, #0x00, r0, c1, c0, #0x02\r
+ mov r0, #0x40000000\r
+ fmxr fpexc, r0\r
+ .endif\r
+\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Event Bus Export\r
+\r
+ .global _coreEnableEventBusExport_\r
+ .asmfunc\r
+\r
+_coreEnableEventBusExport_:\r
+\r
+ mrc p15, #0x00, r0, c9, c12, #0x00\r
+ orr r0, r0, #0x10\r
+ mcr p15, #0x00, r0, c9, c12, #0x00\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Event Bus Export\r
+\r
+ .global _coreDisableEventBusExport_\r
+ .asmfunc\r
+\r
+_coreDisableEventBusExport_:\r
+\r
+ mrc p15, #0x00, r0, c9, c12, #0x00\r
+ bic r0, r0, #0x10\r
+ mcr p15, #0x00, r0, c9, c12, #0x00\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable RAM ECC Support\r
+\r
+ .global _coreEnableRamEcc_\r
+ .asmfunc\r
+\r
+_coreEnableRamEcc_:\r
+\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ orr r0, r0, #0x0C000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable RAM ECC Support\r
+\r
+ .global _coreDisableRamEcc_\r
+ .asmfunc\r
+\r
+_coreDisableRamEcc_:\r
+\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ bic r0, r0, #0x0C000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Flash ECC Support\r
+\r
+ .global _coreEnableFlashEcc_\r
+ .asmfunc\r
+\r
+_coreEnableFlashEcc_:\r
+\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ orr r0, r0, #0x02000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Disable Flash ECC Support\r
+\r
+ .global _coreDisableFlashEcc_\r
+ .asmfunc\r
+\r
+_coreDisableFlashEcc_:\r
+\r
+ mrc p15, #0x00, r0, c1, c0, #0x01\r
+ bic r0, r0, #0x02000000\r
+ mcr p15, #0x00, r0, c1, c0, #0x01\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Enable Offset via Vic controller\r
+\r
+ .global _coreEnableIrqVicOffset_\r
+ .asmfunc\r
+\r
+_coreEnableIrqVicOffset_:\r
+\r
+ mrc p15, #0, r0, c1, c0, #0\r
+ orr r0, r0, #0x01000000\r
+ mcr p15, #0, r0, c1, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get data fault status register\r
+\r
+ .global _coreGetDataFault_\r
+ .asmfunc\r
+\r
+_coreGetDataFault_:\r
+\r
+ mrc p15, #0, r0, c5, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear data fault status register\r
+\r
+ .global _coreClearDataFault_\r
+ .asmfunc\r
+\r
+_coreClearDataFault_:\r
+\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get instruction fault status register\r
+\r
+ .global _coreGetInstructionFault_\r
+ .asmfunc\r
+\r
+_coreGetInstructionFault_:\r
+\r
+ mrc p15, #0, r0, c5, c0, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear instruction fault status register\r
+\r
+ .global _coreClearInstructionFault_\r
+ .asmfunc\r
+\r
+_coreClearInstructionFault_:\r
+\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c0, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get data fault address register\r
+\r
+ .global _coreGetDataFaultAddress_\r
+ .asmfunc\r
+\r
+_coreGetDataFaultAddress_:\r
+\r
+ mrc p15, #0, r0, c6, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear data fault address register\r
+\r
+ .global _coreClearDataFaultAddress_\r
+ .asmfunc\r
+\r
+_coreClearDataFaultAddress_:\r
+\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c6, c0, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get instruction fault address register\r
+\r
+ .global _coreGetInstructionFaultAddress_\r
+ .asmfunc\r
+\r
+_coreGetInstructionFaultAddress_:\r
+\r
+ mrc p15, #0, r0, c6, c0, #2\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear instruction fault address register\r
+\r
+ .global _coreClearInstructionFaultAddress_\r
+ .asmfunc\r
+\r
+_coreClearInstructionFaultAddress_:\r
+\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c6, c0, #2\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get auxiliary data fault status register\r
+\r
+ .global _coreGetAuxiliaryDataFault_\r
+ .asmfunc\r
+\r
+_coreGetAuxiliaryDataFault_:\r
+\r
+ mrc p15, #0, r0, c5, c1, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear auxiliary data fault status register\r
+\r
+ .global _coreClearAuxiliaryDataFault_\r
+ .asmfunc\r
+\r
+_coreClearAuxiliaryDataFault_:\r
+\r
+ mov r0, #0\r
+ mcr p15, #0, r0, c5, c1, #0\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Get auxiliary instruction fault status register\r
+\r
+ .global _coreGetAuxiliaryInstructionFault_\r
+ .asmfunc\r
+\r
+_coreGetAuxiliaryInstructionFault_:\r
+\r
+ mrc p15, #0, r0, c5, c1, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Clear auxiliary instruction fault status register\r
+\r
+ .global _coreClearAuxiliaryInstructionFault_\r
+ .asmfunc\r
+\r
+_coreClearAuxiliaryInstructionFault_:\r
+\r
+ mov r0, #0\r
+ mrc p15, #0, r0, c5, c1, #1\r
+ bx lr\r
+\r
+ .endasmfunc\r
+ \r
+ \r
+;-------------------------------------------------------------------------------\r
+; C++ construct table pointers\r
+\r
+ .global __TI_PINIT_Base, __TI_PINIT_Limit\r
+ .weak SHT$$INIT_ARRAY$$Base, SHT$$INIT_ARRAY$$Limit\r
+\r
+__TI_PINIT_Base: .long SHT$$INIT_ARRAY$$Base\r
+__TI_PINIT_Limit: .long SHT$$INIT_ARRAY$$Limit\r
+\r
+;-------------------------------------------------------------------------------\r
+\r
\r
#include "Os.h"\r
#include "internal.h"\r
-#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
+#include "core_cr4.h"\r
#include "irq.h"\r
#include "arc.h"\r
\r
*/\r
void Os_SysTickInit( void ) {\r
TaskType tid;\r
- tid = Os_Arc_CreateIsr(OsTick,6/*prio*/,"OsTick");\r
- Irq_AttachIsr2(tid,NULL, SysTick_IRQn);\r
+ tid = Os_Arc_CreateIsr(OsTick,6,"OsTick");\r
+ Irq_AttachIsr2(tid,NULL, 2);\r
+}\r
+\r
+\r
+static inline uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+\r
+ /** - Setup NTU source, debug options and disable both counter blocks */\r
+ rtiREG1->GCTRL = 0x0;\r
+\r
+ /** - Setup timebase for free running counter 0 */\r
+ rtiREG1->TBCTRL = 0x0;\r
+\r
+ /** - Enable/Disable capture event sources for both counter blocks */\r
+ rtiREG1->CAPCTRL = 0x0;\r
+\r
+ /** - Setup input source compare 0-3 */\r
+ rtiREG1->COMPCTRL = 0x0;\r
+\r
+ /** - Reset up counter 0 */\r
+ rtiREG1->CNT[0U].UCx = 0x00000000U;\r
+\r
+ /** - Reset free running counter 0 */\r
+ rtiREG1->CNT[0U].FRCx = 0x00000000U;\r
+\r
+ /** - Setup up counter 0 compare value\r
+ * - 0x00000000: Divide by 2^32\r
+ * - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)\r
+ */\r
+ rtiREG1->CNT[0U].CPUCx = 4U;\r
+\r
+ /** - Setup compare 0 value. This value is compared with selected free running counter. */\r
+ rtiREG1->CMP[0U].COMPx = 9360U;\r
+\r
+ /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */\r
+ rtiREG1->CMP[0U].UDCPx = 9360U;\r
+\r
+ /** - Clear all pending interrupts */\r
+ rtiREG1->INTFLAG = 0x0;\r
+\r
+ /** - Disable all interrupts */\r
+ rtiREG1->CLEARINT = 0x0;\r
+\r
+ return (0); /* Function successful */\r
}\r
\r
/**\r
* @param period_ticks How long the period in timer ticks should be.\r
*\r
*/\r
-\r
void Os_SysTickStart(uint32_t period_ticks) {\r
\r
/* Cortex-M3 have a 24-bit system timer that counts down\r
*/\r
\r
SysTick_Config(period_ticks);\r
+ rtiREG1->GCTRL = 0x1;\r
+ rtiREG1->SETINT = 0x1;\r
+\r
\r
/* Set SysTick Priority to 3 */\r
- NVIC_SetPriority(SysTick_IRQn, 0x0C);\r
+ // TODO removeNVIC_SetPriority(SysTick_IRQn, 0x0C);\r
\r
#if 0\r
// SysTick interrupt each 250ms with counter clock equal to 9MHz\r
\r
uint32_t Os_SysTickGetValue( void )\r
{\r
- return (SysTick->LOAD) - (SysTick->VAL);\r
+ //return (SysTick->LOAD) - (SysTick->VAL);\r
+ return 0;\r
}\r
\r
\r
uint32_t curr;\r
uint32_t max;\r
\r
+ /*\r
curr = (SysTick->VAL);\r
max = (SysTick->LOAD);\r
+ */\r
+ curr = 0;\r
+ max = 0;\r
return Os_CounterDiff((max - curr),preValue,max);\r
}\r
\r
# prefered version\r
CC_VERSION=4.5.1\r
# ARMv7, Thumb-2, little endian, soft-float. \r
-cflags-y += -mthumb -mcpu=cortex-r4 #-mfix-cortex-m3-ldrd\r
-cflags-y += -ggdb\r
+cflags-y += -mthumb -mcpu=cortex-r4f -mbig-endian #-mfix-cortex-m3-ldrd\r
+cflags-y += -ggdb -mbig-endian\r
\r
lib-y += -lgcc -lc\r
-ASFLAGS += -mcpu=cortex-r4 -mthumb\r
-\r
+ASFLAGS += -mcpu=cortex-r4f -mbig-endian -mthumb\r
\r
+LDFLAGS +=
\ No newline at end of file
* _etext - ?\r
*/\r
\r
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm")\r
+OUTPUT_FORMAT("elf32-bigarm")\r
OUTPUT_ARCH(arm)\r
ENTRY(Reset_Handler)\r
\r
SECTIONS\r
{\r
\r
- .isr_vector :\r
+ .int_vecs :\r
{\r
- . = ALIGN(4);\r
- KEEP(*(.isr_vector))\r
- . = ALIGN(4);\r
- } > flash\r
+ KEEP(*(.int_vecs))\r
+ } > intvecs\r
\r
.text :\r
{\r
/* Read-only data section. */\r
.rodata : { \r
*(.rodata .rodata.* .gnu.linkonce.r.*)\r
- _sidata = .;\r
+ _sidata = ALIGN(.,4);\r
} > flash\r
\r
.data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
- _sdata = .; \r
+ _sdata = ALIGN(.,4); \r
*(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
- _edata = .; \r
+ _edata = ALIGN(.,4); \r
} > ram\r
\r
.t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
\r
.init_stack ALIGN(16) (NOLOAD) : \r
{ \r
- . = . + 200; \r
+ _sstack = .;\r
+ . = . + 8000; \r
_estack = .; \r
+ . = . + 1;\r
+ . = ALIGN(4);\r
} > ram\r
\r
/* Fls RAM section */\r
projects / arc.git / commitdiff