#define SPR_PIR 286\r
#define SPR_PVR 287\r
\r
-#define CORE_PVR_E200Z1 0x81440000UL\r
-#define CORE_PVR_E200Z0 0x81710000UL\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL
+#define CORE_PVR_E200Z3 0x81120000UL\r
\r
\r
typedef struct {\r
{\r
.name = "MPC5516",\r
.pvr = CORE_PVR_E200Z0,\r
- },\r
+ },
+ {
+ .name = "MPC563X",
+ .pvr = CORE_PVR_E200Z3,
+ },
};\r
\r
core_info_t core_info_list[] = {\r
.name = "CORE_E200Z1",\r
.pvr = CORE_PVR_E200Z1,\r
},\r
+ {
+ .name = "CORE_E200Z3",
+ .pvr = CORE_PVR_E200Z3,
+ },
};\r
\r
// TODO: move\r
\r
-\r
-\r
# prefered version\r
CC_VERSION=4.1.2\r
# ARMv7, Thumb-2, little endian, soft-float. \r
cflags-y += -mthumb -mcpu=cortex-m3 -mfix-cortex-m3-ldrd\r
cflags-y += -ggdb\r
-# experimental\r
-#cflags-y += -mno-common\r
-\r
-#cflags-y += -mno-common\r
\r
lib-y += -lgcc -lc\r
ASFLAGS += -mcpu=cortex-m3 -mthumb\r
#include "Dma.h"\r
#include "Det.h"\r
#if defined(USE_KERNEL)\r
-#include "Os.h"\r
+#include "Os.h"
+#include "int_ctrl.h"
#endif\r
\r
\r
#include <stdlib.h>\r
#include <string.h>\r
#if defined(USE_KERNEL)\r
-#include "Os.h"\r
+#include "Os.h"
+#include "int_ctrl.h"\r
#endif\r
\r
\r
/* CONFIGURATION NOTES\r
* ------------------------------------------------------------------\r
- * - CanHandleType must be CAN_ECORE_HANDLE_TYPE_BASIC\r
- * i.e. CanHandleType=CAN_ECORE_HANDLE_TYPE_FULL NOT supported\r
+ * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC\r
+ * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported\r
* i.e CanIdValue is NOT supported\r
- * - All CanXXXProcessing must be CAN_ECORE_PROCESS_TYPE_INTERRUPT\r
- * ie CAN_ECORE_PROCESS_TYPE_POLLED not supported\r
- * - To select the Mailboxes to use in the CAN controller use CanEcoreMbMask\r
+ * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT\r
+ * ie CAN_ARC_PROCESS_TYPE_POLLED not supported\r
+ * - To select the Mailboxes to use in the CAN controller use Can_Arc_MbMask\r
* - HOH's for Tx are global and Rx are for each controller\r
* - CanControllerTimeQuanta is NOT used. The other CanControllerXXX selects\r
* the proper time-quanta\r
- * - CanEcoreMbMask for Tx HOH must NOT overlap CanEcoreMbMask for Rx.\r
+ * - Can_Arc_MbMask for Tx HOH must NOT overlap Can_Arc_MbMask for Rx.\r
* - ONLY global mask is supported( NOT 14,15 and individual )\r
* - Numbering the CanObjectId for Tx:\r
* To do this correctly there are a number of things that are good to know\r
* 1. HTH's have unique numbers.\r
* 2. One HTH/HRH is maped to one HOH\r
- * 3. The extension CanEcoreMbMask binds FULL CAN boxes together.\r
+ * 3. The extension Can_Arc_MbMask binds FULL CAN boxes together.\r
*\r
* Example:\r
*\r
* 1 F 0 1\r
* ..\r
* 16 B 0 16 |\r
- * 17 | The use of CanEcoreMbMask=0x000f0000 binds these to HTH 16\r
+ * 17 | The use of Can_Arc_MbMask=0x000f0000 binds these to HTH 16\r
* 18 | ( bits 16 to 19 set here )\r
* 19 |\r
* ...\r
#endif\r
\r
// Mapping between HRH and Controller//HOH\r
-typedef struct Can_EcoreObjectHOHMapStruct\r
+typedef struct Can_Arc_ObjectHOHMapStruct\r
{\r
uint32 HxHRef; // Reference to HRH or HTH\r
CanControllerIdType CanControllerRef; // Reference to controller\r
const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.\r
-} Can_EcoreObjectHOHMapType;\r
+} Can_Arc_ObjectHOHMapType;\r
\r
/* Type for holding global information used by the driver */\r
typedef struct {\r
\r
// This is a map that maps the HTH:s with the controller and Hoh. It is built\r
// during Can_Init and is used to make things faster during a transmit.\r
- Can_EcoreObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
+ Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
} Can_GlobalType;\r
\r
// Global config\r
CanIf_ControllerModeType state;\r
uint32 lock_cnt;\r
// Interrupt masks that is for all Mb's in this controller\r
- uint32 CanEcoreRxMbMask;\r
- uint32 CanEcoreTxMbMask;\r
+ uint32 Can_Arc_RxMbMask;\r
+ uint32 Can_Arc_TxMbMask;\r
\r
// Used at IFLG in controller at startup\r
uint32 iflagStart;\r
\r
// Statistics\r
- Can_EcoreStatisticsType stats;\r
+ Can_Arc_StatisticsType stats;\r
\r
// Data stored for Txconfirmation callbacks to CanIf\r
PduIdType swPduHandles[MAX_NUM_OF_MAILBOXES];\r
* @param hth The transmit handle\r
* @returns Ptr to the Hoh\r
*/\r
-static const Can_HardwareObjectType * Can_FindHoh( Can_EcoreHTHType hth , uint32* controller)\r
+static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)\r
{\r
const Can_HardwareObjectType *hohObj;\r
- const Can_EcoreObjectHOHMapType *map;\r
+ const Can_Arc_ObjectHOHMapType *map;\r
const Can_ControllerConfigType *canHwConfig;\r
\r
map = &Can_Global.CanHTHMap[hth];\r
\r
static void Can_Err( int unit ) {\r
flexcan_t *canHw = GET_CONTROLLER(unit);\r
- Can_EcoreErrorType err;\r
+ Can_Arc_ErrorType err;\r
ESRType esr;\r
err.R = 0;\r
\r
err.B.RXWRN = esr.B.RXWRN;\r
err.B.TXWRN = esr.B.TXWRN;\r
\r
- if (GET_CALLBACKS()->EcoreError != NULL)\r
+ if (GET_CALLBACKS()->Arc_Error != NULL)\r
{\r
- GET_CALLBACKS()->EcoreError(unit, err );\r
+ GET_CALLBACKS()->Arc_Error(unit, err );\r
}\r
// Clear ERRINT\r
canHw->ESR.B.ERRINT = 1;\r
uint8 mbNr;\r
\r
// Find our Tx boxes.\r
- mbMask = canUnit->CanEcoreTxMbMask;\r
+ mbMask = canUnit->Can_Arc_TxMbMask;\r
\r
// Loop over the Mb's set to abort\r
for (; mbMask; mbMask&=~(1<<mbNr)) {\r
}\r
\r
// Ack tx interrupts\r
- canHw->IFRL.R = canUnit->CanEcoreTxMbMask;\r
- canUnit->iflagStart = canUnit->CanEcoreTxMbMask;\r
+ canHw->IFRL.R = canUnit->Can_Arc_TxMbMask;\r
+ canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;\r
}\r
\r
//-------------------------------------------------------------------\r
static void Can_BusOff( int unit ) {\r
flexcan_t *canHw = GET_CONTROLLER(unit);\r
Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
- Can_EcoreErrorType err;\r
+ Can_Arc_ErrorType err;\r
err.R = 0;\r
\r
if ( canHw->ESR.B.TWRNINT )\r
\r
if (err.R != 0)\r
{\r
- if (GET_CALLBACKS()->EcoreError != NULL)\r
+ if (GET_CALLBACKS()->Arc_Error != NULL)\r
{\r
- GET_CALLBACKS()->EcoreError( unit, err );\r
+ GET_CALLBACKS()->Arc_Error( unit, err );\r
}\r
}\r
\r
//\r
\r
// Rx\r
- hohObj= canHwConfig->CanEcoreHoh;\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
--hohObj;\r
do {\r
++hohObj;\r
\r
- mbMask = hohObj->CanEcoreMbMask & iFlagLow;\r
+ mbMask = hohObj->Can_Arc_MbMask & iFlagLow;\r
\r
if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
{\r
canHw->IFRL.R = (1<<mbNr);\r
}\r
}\r
- } while ( !hohObj->CanEcoreEOL);\r
+ } while ( !hohObj->Can_Arc_EOL);\r
\r
// Tx\r
- hohObj= canHwConfig->CanEcoreHoh;\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
--hohObj;\r
do {\r
++hohObj;\r
\r
if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
{\r
- mbMask = hohObj->CanEcoreMbMask & iFlagLow;\r
+ mbMask = hohObj->Can_Arc_MbMask & iFlagLow;\r
\r
// Loop over the Mb's for this Hoh\r
for (; mbMask; mbMask&=~(1<<mbNr)) {\r
canHw->IFRL.R = (1<<mbNr);\r
}\r
}\r
- } while ( !hohObj->CanEcoreEOL);\r
+ } while ( !hohObj->Can_Arc_EOL);\r
#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
} // FIFO code\r
#endif\r
// - Interupt on a masked box\r
}\r
\r
- if (canHwConfig->CanEcoreFifo) {\r
+ if (canHwConfig->Can_Arc_Fifo) {\r
/* Note\r
* NOT tested at all\r
*/\r
Can_Global.initRun = CAN_READY;\r
\r
\r
- for (int configId=0; configId < CAN_ECORE_CTRL_CONFIG_CNT; configId++) {\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
ctlrId = canHwConfig->CanControllerId;\r
\r
canUnit->lock_cnt = 0;\r
\r
// Clear stats\r
- memset(&canUnit->stats, 0, sizeof(Can_EcoreStatisticsType));\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
\r
Can_InitController(ctlrId, canHwConfig);\r
\r
// Loop through all Hoh:s and map them into the HTHMap\r
const Can_HardwareObjectType* hoh;\r
- hoh = canHwConfig->CanEcoreHoh;\r
+ hoh = canHwConfig->Can_Arc_Hoh;\r
hoh--;\r
do\r
{\r
Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;\r
Can_Global.CanHTHMap[hoh->CanObjectId].HxHRef = hoh->CanObjectId;\r
}\r
- } while (!hoh->CanEcoreEOL);\r
+ } while (!hoh->Can_Arc_EOL);\r
\r
// Note!\r
// Could install handlers depending on HW objects to trap more errors\r
const Can_ControllerConfigType *canHwConfig;\r
uint32 ctlrId;\r
\r
- for (int configId=0; configId < CAN_ECORE_CTRL_CONFIG_CNT; configId++) {\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
ctlrId = canHwConfig->CanControllerId;\r
\r
canUnit->lock_cnt = 0;\r
\r
// Clear stats\r
- memset(&canUnit->stats, 0, sizeof(Can_EcoreStatisticsType));\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
}\r
\r
Can_Global.config = NULL;\r
#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
// Note!\r
// FIFO implemenation not tested\r
- if( config->CanEcoreFifo ) {\r
+ if( config->Can_Arc_Fifo ) {\r
canHw->MCR.B.FEN = 1; // Enable FIFO\r
canHw->MCR.B.IDAM = 0; // We want extended id's to match with\r
}\r
canHw->MCR.B.MAXMB = MAX_NUM_OF_MAILBOXES - 1;\r
\r
/* Disable selfreception */\r
- canHw->MCR.B.SRXDIS = !config->CanEcoreLoopback;\r
+ canHw->MCR.B.SRXDIS = !config->Can_Arc_Loopback;\r
\r
// Clock calucation\r
// -------------------------------------------------------------------\r
canHw->CR.B.PSEG1 = config->CanControllerSeg1;\r
canHw->CR.B.PSEG2 = config->CanControllerSeg2;\r
canHw->CR.B.SMP = 1; // 3 samples better than 1 ??\r
- canHw->CR.B.LPB = config->CanEcoreLoopback;\r
+ canHw->CR.B.LPB = config->Can_Arc_Loopback;\r
canHw->CR.B.BOFFREC = 1; // Disable bus off recovery\r
\r
#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
// Check if we use individual masks. If so accept anything(=0) for now\r
if( canHw->MCR.B.BCC ) {\r
- i = (config->CanEcoreFifo ? 8 : 0 );\r
+ i = (config->Can_Arc_Fifo ? 8 : 0 );\r
for(;i<63;i++) {\r
canHw->RXIMR[i].R = 0;\r
}\r
#else\r
#endif\r
// Set the id's\r
- if( config->CanEcoreFifo ) {\r
+ if( config->Can_Arc_Fifo ) {\r
// Clear ID's in FIFO also, MUST set extended bit here\r
uint32_t *fifoId = (uint32_t*)(((uint8_t *)canHw)+0xe0);\r
for(int k=0;k<8;k++) {\r
}\r
\r
// Mark all slots as inactive( depending on fifo )\r
- i = (config->CanEcoreFifo ? 8 : 0 );\r
+ i = (config->Can_Arc_Fifo ? 8 : 0 );\r
for(; i < 63; i++) {\r
//canHw->BUF[i].CS.B.CODE = 0;\r
canHw->BUF[i].CS.R = 0;\r
Can_FilterMaskType mask = 0xffffffff;\r
\r
// Rx\r
- hohObj = canHwConfig->CanEcoreHoh;\r
+ hohObj = canHwConfig->Can_Arc_Hoh;\r
--hohObj;\r
do {\r
++hohObj;\r
\r
- mbMask = hohObj->CanEcoreMbMask;\r
+ mbMask = hohObj->Can_Arc_MbMask;\r
mbNr = 0;\r
\r
if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
}\r
\r
// Add to global mask\r
- canUnit->CanEcoreRxMbMask |= hohObj->CanEcoreMbMask;\r
+ canUnit->Can_Arc_RxMbMask |= hohObj->Can_Arc_MbMask;\r
if( hohObj->CanFilterMaskRef != NULL ) {\r
mask &= *hohObj->CanFilterMaskRef;\r
}\r
}\r
else\r
{\r
- canUnit->CanEcoreTxMbMask |= hohObj->CanEcoreMbMask;\r
+ canUnit->Can_Arc_TxMbMask |= hohObj->Can_Arc_MbMask;\r
}\r
- } while( !hohObj->CanEcoreEOL );\r
+ } while( !hohObj->Can_Arc_EOL );\r
\r
\r
// Set global mask\r
canHw->RX15MASK.R = 0;\r
}\r
\r
- canUnit->iflagStart = canUnit->CanEcoreTxMbMask;\r
+ canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;\r
\r
canUnit->state = CANIF_CS_STOPPED;\r
Can_EnableControllerInterrupts(cId);\r
canHw->IMRH.R = 0;\r
canHw->IMRL.R = 0;\r
\r
- if( canHwConfig->CanRxProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
/* Turn on the interrupt mailboxes */\r
- canHw->IMRL.R = canUnit->CanEcoreRxMbMask;\r
+ canHw->IMRL.R = canUnit->Can_Arc_RxMbMask;\r
}\r
\r
- if( canHwConfig->CanTxProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
/* Turn on the interrupt mailboxes */\r
- canHw->IMRL.R |= canUnit->CanEcoreTxMbMask;\r
+ canHw->IMRL.R |= canUnit->Can_Arc_TxMbMask;\r
}\r
\r
// BusOff here represents all errors and warnings\r
- if( canHwConfig->CanBusOffProcessing == CAN_ECORE_PROCESS_TYPE_INTERRUPT ) {\r
+ if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
canHw->MCR.B.WRNEN = 1; /* Turn On warning int */\r
\r
canHw->CR.B.ERRMSK = 1; /* Enable error interrupt */\r
return;\r
}\r
\r
-Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo ) {\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {\r
uint16_t timer;\r
uint32_t iflag;\r
Can_ReturnType rv = CAN_OK;\r
\r
canHw = GET_CONTROLLER(controller);\r
oldMsr = McuE_EnterCriticalSection();\r
- iflag = canHw->IFRL.R & canUnit->CanEcoreTxMbMask;\r
+ iflag = canHw->IFRL.R & canUnit->Can_Arc_TxMbMask;\r
\r
// check for any free box\r
// Normally we would just use the iflag to get the free box\r
* @param stats Pointer to data to copy statistics to\r
*/\r
\r
-void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType *stats)\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)\r
{\r
Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
*stats = canUnit->stats;\r
return E_OK;\r
}\r
\r
-Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo )\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )\r
{\r
// Write to mailbox on controller here.\r
DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");\r
void Can_MainFunction_BusOff( void ){}\r
void Can_MainFunction_Wakeup( void ){}\r
\r
-void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType * stat){}\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}\r
\r
#endif\r
\r
EEP_ERASE,
EEP_READ,
EEP_WRITE,
-} Eep_EcoreJobType;
+} Eep_Arc_JobType;
/* Spi job state */
typedef enum {
Eep_AddressType eepAddr;
uint32 left;
Job_StateType state;
- Eep_EcoreJobType mainState;
+ Eep_Arc_JobType mainState;
Spi_SequenceType currSeq;
uint32 chunkSize;
} Eep_JobInfoType;
// Status of driver
MemIf_StatusType status;
MemIf_JobResultType jobResultType;
- Eep_EcoreJobType jobType;
+ Eep_Arc_JobType jobType;
// Saved information from API calls.
MemIf_AddressType e2Addr;
FLS_JOB_ERASE,
FLS_JOB_READ,
FLS_JOB_WRITE,
-} Fls_EcoreJobType;
+} Fls_Arc_JobType;
#if 0
typedef struct {
MemIf_StatusType status;
MemIf_JobResultType jobResultType;
- Fls_EcoreJobType jobType;
+ Fls_Arc_JobType jobType;
MemIf_AddressType sourceAddr;
uint8 *targetAddr;
MemIf_LengthType length;
MemIf_StatusType status;
MemIf_JobResultType jobResultType;
- Fls_EcoreJobType jobType;
+ Fls_Arc_JobType jobType;
MemIf_AddressType sourceAddr;
uint8 *targetAddr;
MemIf_LengthType length;
#define SPR_PIR 286\r
#define SPR_PVR 287\r
\r
-#define CORE_PVR_E200Z1 0x81440000UL\r
-#define CORE_PVR_E200Z0 0x81710000UL\r
-#define CORE_PVR_E200Z6 0x81170000UL\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL
+#define CORE_PVR_E200Z3 0x81120000UL\r
+#define CORE_PVR_E200Z6 0x81170000UL\r
\r
\r
typedef struct {\r
{\r
.name = "MPC5516",\r
.pvr = CORE_PVR_E200Z0,\r
- },\r
+ },
#elif defined(CFG_MPC5567)\r
{\r
.name = "MPC5567",\r
.pvr = CORE_PVR_E200Z6,\r
- }\r
+ }
+#elif defined(CFG_MPC5633)
+ {
+ .name = "MPC563X",
+ .pvr = CORE_PVR_E200Z3,
+ },
#endif\r
};\r
\r
{\r
.name = "CORE_E200Z6",\r
.pvr = CORE_PVR_E200Z6,\r
- }\r
+ }
+#elif defined(CFG_MPC5633)
+ {
+ .name = "CORE_E200Z3",
+ .pvr = CORE_PVR_E200Z3,
+ },\r
#endif\r
};\r
\r
* System clock calculation\r
*\r
* 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
- * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));\r
+ * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
+ * 563x - We run in legacy mode = 5567
*/\r
#if defined(CFG_MPC5516)\r
uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;\r
uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;\r
uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;\r
-#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)\r
uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
uint32_t f_sys;\r
uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
\r
- f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+ f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
return f_sys;\r
}\r
#endif\r
#include "Mcu.h"\r
\r
-#if PWM_DEV_EROR_DETECT==ON\r
+#if PWM_DEV_EROR_DETECT==STD_ON\r
#define PWM_VALIDATE(_exp, _errid) \\r
if (!(_exp)) { \\r
Pwm_ReportError(_errid); \\r
typedef struct {\r
Pwm_ChannelClassType Class;\r
\r
- #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ #if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
Pwm_NotificationHandlerType NotificationRoutine;\r
Pwm_EdgeNotificationType NotificationState;\r
#endif\r
void inline Pwm_InitChannel(Pwm_ChannelType Channel);\r
void inline Pwm_DeInitChannel(Pwm_ChannelType Channel);\r
\r
-#if PWM_NOTIFICATION_SUPPORTED==ON\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
static void Pwm_Isr(void);\r
#endif\r
\r
Pwm_ChannelType channel_iterator;\r
\r
Pwm_VALIDATE_UNINITIALIZED();\r
- #if PWM_DEV_EROR_DETECT==ON\r
+ #if PWM_DEV_EROR_DETECT==STD_ON\r
/*\r
* PWM046: If development error detection is enabled for the Pwm module,\r
* the function Pwm_Init shall raise development error PWM_E_PARAM_CONFIG\r
#endif\r
#endif\r
\r
- #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ #if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
// Create a task for our interrupt service routine.\r
TaskType tid = Os_CreateIsr(Pwm_Isr, PWM_ISR_PRIORITY /*prio*/, "PwmIsr");\r
#endif\r
(void*) &ConfigPtr->Channels[channel_iterator].r,\r
sizeof(Pwm_ChannelRegisterType));\r
\r
- #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ #if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
/*\r
* PWM052: The function Pwm_Init shall disable all notifications.\r
*\r
}\r
}\r
\r
-#if PWM_DEINIT_API==ON\r
+#if PWM_DEINIT_API==STD_ON\r
\r
// TODO: Test that this function in fact turns the channel off.\r
void inline Pwm_DeInitChannel(Pwm_ChannelType Channel) {\r
/*\r
* PWM052: The function Pwm_DeInit shall disable all notifications.\r
*/\r
- #if PWM_NOTIFICATION_SUPPORTED==ON\r
+ #if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
Pwm_DisableNotification(Channel);\r
#endif\r
}\r
* PWM083: The function Pwm_SetPeriodAndDuty shall be pre compile time\r
* changeable ON/OFF by the configuration parameter PwmSetPeriodAndDuty.\r
*/\r
-#if PWM_SET_PERIOD_AND_DUTY==ON\r
+#if PWM_SET_PERIOD_AND_DUTY==STD_ON\r
void Pwm_SetPeriodAndDuty(Pwm_ChannelType Channel, Pwm_PeriodType Period,\r
Pwm_DutyCycleType DutyCycle) {\r
\r
* PWM085: The function Pwm_GetOutputState shall be pre compile configurable\r
* ON/OFF by the configuration parameter PwmGetOutputState\r
*/\r
-#if PWM_GET_OUTPUT_STATE==ON\r
+#if PWM_GET_OUTPUT_STATE==STD_ON\r
/*\r
* PWM022: The function Pwm_GetOutputState shall read the internal state\r
* of the PWM output signal and return it.\r
}\r
#endif\r
\r
-#if PWM_NOTIFICATION_SUPPORTED==ON\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
void Pwm_DisableNotification(Pwm_ChannelType Channel) {\r
Pwm_VALIDATE_CHANNEL(Channel);\r
Pwm_VALIDATE_INITIALIZED();\r
}\r
}\r
\r
-#endif /* PWM_NOTIFICATION_SUPPORED == ON */\r
+#endif /* PWM_NOTIFICATION_SUPPORED == STD_ON */\r
--- /dev/null
+/**************************************************************************/\r
+/* FILE NAME: mpc563m.h COPYRIGHT (c) Freescale 2008 */\r
+/* VERSION: 1.2 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC563m. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 1.0 G. Emerson 31/OCT/07 Initial version. */\r
+/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */\r
+/* Added ESYNCR1 ESYNCR2 SYNFMMR */\r
+/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */\r
+/* 8 channels in the middle of the range */\r
+/* do not exist */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC563M_H_\r
+#define _MPC563M_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:13;\r
+ } B;\r
+ } SYNCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYNSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EMODE:1;\r
+ vuint32_t CLKCFG:3;\r
+ vuint32_t:8;\r
+ vuint32_t EPREDIV:4;\r
+ vuint32_t:9;\r
+ vuint32_t EMFD:7;\r
+ } B;\r
+ } ESYNCR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:17;\r
+ vuint32_t ERFD:2;\r
+ } B;\r
+ } ESYNCR2;\r
+\r
+ int32_t FMPLL_reserved0[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MODEN:1;\r
+ vuint32_t MODSEL:1;\r
+ vuint32_t MODPERIOD:13;\r
+ vuint32_t:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } SYNFMMR;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct CAL_CS_tag {\r
+ union { /* Calibration Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Calibration Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+/* Calibration registers */\r
+ uint32_t EBI_reserved2[4];\r
+ struct CAL_CS_tag CAL_CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t PRD:1; /* Include PRD Field */\r
+\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t MLOCK:4;\r
+ vuint32_t LLOCK:16;\r
+ } B;\r
+ } LMLR;\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:3;\r
+ vuint32_t HBLOCK:28;\r
+ } B;\r
+ } HLR;\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t SMLOCK:4;\r
+ vuint32_t SLLOCK:16;\r
+ } B;\r
+ } SLMLR;\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t MSEL:4;\r
+ vuint32_t LSEL:16;\r
+ } B;\r
+ } LMSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t HBSEL:28;\r
+ } B;\r
+ } HSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } AR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:11;\r
+\r
+ vuint32_t:1;\r
+\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t DPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t IPFEN:1;\r
+\r
+ vuint32_t PFLIM:3;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } BIUCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:22;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } BIUAPR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LBCFG:2;\r
+ vuint32_t:30;\r
+ } B;\r
+ } BIUCR2;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t MASKNUM:16;\r
+ } B;\r
+ } MIDR;\r
+ int32_t SIU_reserved00;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS:1;\r
+ vuint32_t:8;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t SERF:1;\r
+ vuint32_t WKPCFG:1;\r
+ vuint32_t:12;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t RGF:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t SER:1;\r
+ vuint32_t:14;\r
+ vuint32_t CRE:1;\r
+ vuint32_t:15;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ int32_t SIU_reserved1[3];\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:3;\r
+ vuint16_t PA:3;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t DSC:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SRC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[512];\r
+\r
+ int16_t SIU_reserved_0[224];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[256];\r
+\r
+ int32_t SIU_reserved_3[64];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[256];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL5:2;\r
+ vuint32_t TSEL4:2;\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } ETISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } EIISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SINSELA:2;\r
+ vuint32_t SSSELA:2;\r
+ vuint32_t SCKSELA:2;\r
+ vuint32_t TRIGSELA:2;\r
+ vuint32_t SINSELB:2;\r
+ vuint32_t SSSELB:2;\r
+ vuint32_t SCKSELB:2;\r
+ vuint32_t TRIGSELB:2;\r
+ vuint32_t SINSELC:2;\r
+ vuint32_t SSSELC:2;\r
+ vuint32_t SCKSELC:2;\r
+ vuint32_t TRIGSELC:2;\r
+ vuint32_t SINSELD:2;\r
+ vuint32_t SSSELD:2;\r
+ vuint32_t SCKSELD:2;\r
+ vuint32_t TRIGSELD:2;\r
+ } B;\r
+ } DISR;\r
+\r
+ int32_t SIU_reserved2[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t ENGDIV:6;\r
+ vuint32_t:4;\r
+ vuint32_t EBTS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRL;\r
+\r
+ int32_t SIU_reserved3[2];\r
+\r
+ union { /* System Clock Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t BYPASS:1;\r
+ vuint32_t SYSCLKDIV:2;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYSDIV;\r
+\r
+ union {\r
+ vuint32_t R;\r
+\r
+ } HLT;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } HLTACK;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR; /* Output Update Disable Register */\r
+\r
+ uint32_t emios_reserved[5];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ } CADR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ } CBDR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ } CCNTR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR; /* Channel Status Register */\r
+ uint32_t emios_channel_reserved[3];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE :ETPU */\r
+/****************************************************************************/\r
+\r
+/***************************Configuration Registers**************************/\r
+\r
+ struct ETPU_tag {\r
+ union { /* MODULE CONFIGURATION REGISTER */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GEC:1; /* Global Exception Clear */\r
+ vuint32_t:3;\r
+ vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t:3;\r
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */\r
+ vuint32_t:5;\r
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */\r
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */\r
+ vuint32_t:2;\r
+ vuint32_t VIS:1; /* SCM Visability */\r
+ vuint32_t:5;\r
+ vuint32_t GTBE:1; /* Global Time Base Enable */\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* COHERENT DUAL-PARAMETER CONTROL */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STS:1; /* Start Status bit */\r
+ vuint32_t CTBASE:5; /* Channel Transfer Base */\r
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */\r
+ vuint32_t PWIDTH:1; /* Parameter Width */\r
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */\r
+ vuint32_t WR:1;\r
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */\r
+ } B;\r
+ } CDCR;\r
+\r
+ uint32_t etpu_reserved1;\r
+\r
+ union { /* MISC Compare Register */\r
+ vuint32_t R;\r
+ } MISCCMPR;\r
+\r
+ union { /* SCM off-range Date Register */\r
+ vuint32_t R;\r
+ } SCMOFFDATAR;\r
+\r
+ union { /* ETPU_A Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_A;\r
+ uint32_t etpu_reserved3; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved4;\r
+\r
+ union { /* ETPU_A Timebase Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ vuint32_t:1;\r
+ vuint32_t AM:1; /* Angle Mode */\r
+ vuint32_t:3;\r
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ vuint32_t:6;\r
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_A;\r
+\r
+ union { /* ETPU_A TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_A;\r
+\r
+ union { /* ETPU_A TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_A;\r
+\r
+ union { /* ETPU_A STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_A;\r
+\r
+ uint32_t etpu_reserved5[4];\r
+ uint32_t etpu_reserved6[4]; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved7[108];\r
+\r
+/*****************************Status and Control Registers**************************/\r
+\r
+ union { /* ETPU_A Channel Interrut Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */\r
+ } B;\r
+ } CISR_A;\r
+ uint32_t etpu_reserved8; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved9[2];\r
+\r
+ union { /* ETPU_A Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_A;\r
+ uint32_t etpu_reserved10; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved11[2];\r
+\r
+ union { /* ETPU_A Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_A;\r
+ uint32_t etpu_reserved12; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved13[2];\r
+\r
+ union { /* ETPU_A Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_A;\r
+ uint32_t etpu_reserved14; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved15[2];\r
+\r
+ union { /* ETPU_A Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_A;\r
+ uint32_t etpu_reserved16; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved17[2];\r
+\r
+ union { /* ETPU_A Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_A;\r
+ uint32_t etpu_reserved19; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20[10];\r
+ union { /* ETPU_A Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_A;\r
+ uint32_t etpu_reserved22; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20a[2];\r
+\r
+ union { /* ETPU_A Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_A;\r
+ uint32_t etpu_reserved22a; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved23[90];\r
+\r
+/*****************************Channels********************************/\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel Configuration Register */\r
+ struct {\r
+ vuint32_t CIE:1; /* Channel Interruput Enable */\r
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */\r
+ vuint32_t CPR:2; /* Channel Priority */\r
+ vuint32_t:3;\r
+ vuint32_t ETCS:1; /* Entry Table Condition Select */\r
+ vuint32_t:3;\r
+ vuint32_t CFS:5; /* Channel Function Select */\r
+ vuint32_t ODIS:1; /* Output disable */\r
+ vuint32_t OPOL:1; /* output polarity */\r
+ vuint32_t:3;\r
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */\r
+ } B;\r
+ } CR;\r
+ union {\r
+ vuint32_t R; /* Channel Status Control Register */\r
+ struct {\r
+ vuint32_t CIS:1; /* Channel Interruput Status */\r
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t DTRS:1; /* Data Transfer Status */\r
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t IPS:1; /* Input Pin State */\r
+ vuint32_t OPS:1; /* Output Pin State */\r
+ vuint32_t OBE:1; /* Output Buffer Enable */\r
+ vuint32_t:11;\r
+ vuint32_t FM1:1; /* Function mode */\r
+ vuint32_t FM0:1; /* Function mode */\r
+ } B;\r
+ } SCR;\r
+ union {\r
+ vuint32_t R; /* Channel Host Service Request Register */\r
+ struct {\r
+ vuint32_t:29; /* Host Service Request */\r
+ vuint32_t HSR:3;\r
+ } B;\r
+ } HSRR;\r
+ uint32_t etpu_reserved23;\r
+ } CHAN[127];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : XBAR CrossBar */\r
+/****************************************************************************/\r
+ struct XBAR_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR0; /* Master Priority Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR0; /* General Purpose Control Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved2[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR1; /* Master Priority Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR1; /* General Purpose Control Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved4[123];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR3; /* Master Priority Register for Slave Port 3 */\r
+\r
+ uint32_t xbar_reserved5[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR3; /* General Purpose Control Register for Slave Port 3 */\r
+ uint32_t xbar_reserved6[187];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR6; /* Master Priority Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved7[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR6; /* General Purpose Control Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved8[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR7; /* Master Priority Register for Slave Port 7 */\r
+\r
+ uint32_t xbar_reserved9[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR7; /* General Purpose Control Register for Slave Port 7 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+ struct ECSM_tag {\r
+\r
+ uint32_t ecsm_reserved1[5];\r
+\r
+ uint16_t ecsm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t ecsm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t ecsm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t ecsm_reserved5a[1];\r
+ uint32_t ecsm_reserved5b[1];\r
+\r
+ uint32_t ecsm_reserved5c[6];\r
+\r
+ uint8_t ecsm_reserved6[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t ecsm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t ecsm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEAR:32;\r
+ } B;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t ecsm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDH:32;\r
+ } B;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDL:32;\r
+ } B;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t ecsm_reserved12[2];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDH:32;\r
+ } B;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDL:32;\r
+ } B;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t GRP3PRI:2;\r
+ vuint32_t GRP2PRI:2;\r
+ vuint32_t GRP1PRI:2;\r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+ uint32_t edma_reserved_erqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ31:1;\r
+ vuint32_t ERQ30:1;\r
+ vuint32_t ERQ29:1;\r
+ vuint32_t ERQ28:1;\r
+ vuint32_t ERQ27:1;\r
+ vuint32_t ERQ26:1;\r
+ vuint32_t ERQ25:1;\r
+ vuint32_t ERQ24:1;\r
+ vuint32_t ERQ23:1;\r
+ vuint32_t ERQ22:1;\r
+ vuint32_t ERQ21:1;\r
+ vuint32_t ERQ20:1;\r
+ vuint32_t ERQ19:1;\r
+ vuint32_t ERQ18:1;\r
+ vuint32_t ERQ17:1;\r
+ vuint32_t ERQ16:1;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+ uint32_t edma_reserved_eeirh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI31:1;\r
+ vuint32_t EEI30:1;\r
+ vuint32_t EEI29:1;\r
+ vuint32_t EEI28:1;\r
+ vuint32_t EEI27:1;\r
+ vuint32_t EEI26:1;\r
+ vuint32_t EEI25:1;\r
+ vuint32_t EEI24:1;\r
+ vuint32_t EEI23:1;\r
+ vuint32_t EEI22:1;\r
+ vuint32_t EEI21:1;\r
+ vuint32_t EEI20:1;\r
+ vuint32_t EEI19:1;\r
+ vuint32_t EEI18:1;\r
+ vuint32_t EEI17:1;\r
+ vuint32_t EEI16:1;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+ uint32_t edma_reserved_irqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT31:1;\r
+ vuint32_t INT30:1;\r
+ vuint32_t INT29:1;\r
+ vuint32_t INT28:1;\r
+ vuint32_t INT27:1;\r
+ vuint32_t INT26:1;\r
+ vuint32_t INT25:1;\r
+ vuint32_t INT24:1;\r
+ vuint32_t INT23:1;\r
+ vuint32_t INT22:1;\r
+ vuint32_t INT21:1;\r
+ vuint32_t INT20:1;\r
+ vuint32_t INT19:1;\r
+ vuint32_t INT18:1;\r
+ vuint32_t INT17:1;\r
+ vuint32_t INT16:1;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+ uint32_t edma_reserved_erh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR31:1;\r
+ vuint32_t ERR30:1;\r
+ vuint32_t ERR29:1;\r
+ vuint32_t ERR28:1;\r
+ vuint32_t ERR27:1;\r
+ vuint32_t ERR26:1;\r
+ vuint32_t ERR25:1;\r
+ vuint32_t ERR24:1;\r
+ vuint32_t ERR23:1;\r
+ vuint32_t ERR22:1;\r
+ vuint32_t ERR21:1;\r
+ vuint32_t ERR20:1;\r
+ vuint32_t ERR19:1;\r
+ vuint32_t ERR18:1;\r
+ vuint32_t ERR17:1;\r
+ vuint32_t ERR16:1;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+\r
+ } B;\r
+ } CPR[64]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[944];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR; /* Current Priority Register */\r
+\r
+ uint32_t intc_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA:21;\r
+ vuint32_t INTVEC:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR; /* Interrupt Acknowledge Register */\r
+\r
+ uint32_t intc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR; /* End of Interrupt Register */\r
+\r
+ uint32_t intc_reserved3;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved4[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[358]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t ICEA0:1;\r
+ vuint32_t ICEA1:1;\r
+ vuint32_t:1;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t EQADC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:3;\r
+ vuint32_t TSBC:1;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t TSBCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t:4;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:4;\r
+ vuint32_t DPCS1_7:1;\r
+ vuint32_t DPCS1_6:1;\r
+ vuint32_t DPCS1_5:1;\r
+ vuint32_t DPCS1_4:1;\r
+ vuint32_t DPCS1_3:1;\r
+ vuint32_t DPCS1_2:1;\r
+ vuint32_t DPCS1_1:1;\r
+ vuint32_t DPCS1_0:1;\r
+ } B;\r
+ } DSICR1; /* DSI Configuration Register 1 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t SCISDOZ:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t M2:1;\r
+ vuint16_t INPOL:1;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_12_13_bit_tag {\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R12:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t ERR:1;\r
+ vuint16_t:1;\r
+ vuint16_t D:12;\r
+ } B;\r
+ } DR; /* Data Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN2_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t WRNEN:1;\r
+\r
+ vuint32_t MDISACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t MBFEN:1;\r
+ vuint32_t:10;\r
+\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t:2;\r
+\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+ int32_t FLEXCAN_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t flexcan2_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[32];\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Decimation Filter (DECFIL) */\r
+/****************************************************************************/\r
+ struct DECFIL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t SRES:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDEN:1;\r
+ vuint32_t ODEN:1;\r
+ vuint32_t ERREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FTYPE:2;\r
+ vuint32_t:1;\r
+ vuint32_t SCAL:2;\r
+ vuint32_t:1;\r
+ vuint32_t SAT:1;\r
+ vuint32_t ISEL:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_RATE:4;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BSY:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_COUNTER:4;\r
+ vuint32_t IDFC:1;\r
+ vuint32_t ODFC:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVFC:1;\r
+ vuint32_t OVRC:1;\r
+ vuint32_t IVRC:1;\r
+ vuint32_t:6;\r
+ vuint32_t IDF:1;\r
+ vuint32_t ODF:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVF:1;\r
+ vuint32_t OVR:1;\r
+ vuint32_t IVR:1;\r
+ } B;\r
+ } MSR; /* Status Register */\r
+\r
+ uint32_t decfil_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t PREFILL:1;\r
+ vuint32_t FLUSH:1;\r
+ vuint32_t INPBUF:16;\r
+ } B;\r
+ } IB;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t OUTTEG:4;\r
+ vuint32_t OUTBUF:16;\r
+ } B;\r
+ } OB;\r
+\r
+ uint32_t decfil_reserved2[2];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } COEF[9]; /* Filter Coefficient Registers */\r
+\r
+ uint32_t decfil_reserved3[13];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } TAP[8]; /* Filter TAP Registers */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Periodic Interval Timer (PIT) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:29;\r
+ vuint32_t MDIS_RTI:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } MCR; /* PIT Module Control Register */\r
+\r
+ uint32_t pit_reserved1[59];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } RTI; /* RTI Channel */\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } TIMER[4]; /* Timer Channels */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : System Timer Module (STM) */\r
+/****************************************************************************/\r
+ struct STM_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t:6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR; /* STM Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CNT; /* STM Counter Value */\r
+\r
+ uint32_t stm_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR0; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR0; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP0; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR1; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR1; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP1; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR2; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR2; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP2; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved4;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR3; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR3; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP3; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved5;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Software Watchdog Timer (SWT) */\r
+/****************************************************************************/\r
+ struct SWT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t:15;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WNO:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR; /* SWT Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR; /* SWT Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TO; /* SWT Time-out Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } WN; /* SWT Window Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR; /* SWT Service Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CO; /* Counter Output Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Power Management Controller (PMC) */\r
+/****************************************************************************/\r
+ struct PMC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LVIRR:1;\r
+ vuint32_t LVIHR:1;\r
+ vuint32_t LVI5R:1;\r
+ vuint32_t LVI3R:1;\r
+ vuint32_t LVI1R:1;\r
+ vuint32_t BRW:1;\r
+ vuint32_t BGS1:1;\r
+ vuint32_t BGS2:1;\r
+ vuint32_t LVIRE:1;\r
+ vuint32_t LVIHE:1;\r
+ vuint32_t LVI5E:1;\r
+ vuint32_t LVI3E:1;\r
+ vuint32_t LVI1E:1;\r
+ vuint32_t:2;\r
+ vuint32_t TLK:1;\r
+ vuint32_t LVIRC:1;\r
+ vuint32_t LVIHC:1;\r
+ vuint32_t LVI5C:1;\r
+ vuint32_t LVI3C:1;\r
+ vuint32_t LVI1C:1;\r
+ vuint32_t:3;\r
+ vuint32_t LVIRF:1;\r
+ vuint32_t LVIHF:1;\r
+ vuint32_t LVI5F:1;\r
+ vuint32_t LVI3F:1;\r
+ vuint32_t LVI1F:1;\r
+ vuint32_t:3;\r
+ } B;\r
+ } CFGR; /* Configuration and status register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t LVI50TRIM:4;\r
+ vuint32_t V33TRIM:4;\r
+ vuint32_t LVI33TRIM:4;\r
+ vuint32_t V12TRIM:4;\r
+ vuint32_t LVI12TRIM:4;\r
+ } B;\r
+ } TRIMR; /* Trimming register */\r
+ };\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0xC000\r
+#define SRAM_END 0x4000BFFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x100000\r
+#define FLASH_END 0xFFFFF\r
+\r
+/* Define instances of modules */\r
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)\r
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)\r
+#define FLASH (*( volatile struct FLASH_tag *) 0xC3F88000)\r
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)\r
+\r
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)\r
+#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)\r
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)\r
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)\r
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)\r
+#define ETPU_DATA_RAM_END 0xC3FC89FC\r
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)\r
+\r
+#define PBRIDGE (*( struct PBRIDGE_tag *) 0xFFF00000)\r
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)\r
+#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)\r
+#define STM (*( volatile struct STM_tag *) 0xFFF3C000)\r
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)\r
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)\r
+#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000)\r
+\r
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)\r
+\r
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006)\r
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)\r
+#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006)\r
+\r
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)\r
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC563M_H */\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
--- /dev/null
+/**************************************************************************\r
+ * FILE NAME: $RCSfile: mpc563m_vars.h,v $ COPYRIGHT (c) Freescale 2005 *\r
+ * DESCRIPTION: All Rights Reserved *\r
+ * Variables that define some features of the MPC563M. *\r
+ * !!!!This file must only be included once in every project!!!! *\r
+ *========================================================================*\r
+ * ORIGINAL AUTHOR: Geoff Emerson [r47354] *\r
+ * $Log: mpc563m_vars.h,v $\r
+ * Revision 1.1 2007/11/09 08:48:41 r47354\r
+ * *** empty log message ***\r
+ *\r
+\r
+ *\r
+ **************************************************************************/\r
+\r
+/* eTPU characteristics definition */\r
+struct eTPU_struct *eTPU = (struct eTPU_struct *)0xC3FC0000;\r
+\r
+uint32_t fs_etpu_code_start = 0xC3FD0000;\r
+uint32_t fs_etpu_data_ram_start = 0xC3FC8000;\r
+uint32_t fs_etpu_data_ram_end = 0xC3FC89FC;\r
+uint32_t fs_etpu_data_ram_ext = 0xC3FCC000;\r
+\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
+\r
+\r
ramlog_dec(20);
// TODO: The 5516 simulator still thinks it's a 5554 so setup the rest
-#if (defined(CFG_SIMULATOR) && defined(CFG_MPC5516)) || defined(CFG_MPC5567) || defined(CFG_MPC5554)
+#if (defined(CFG_SIMULATOR) && defined(CFG_MPC5516)) || defined(CFG_MPC5567) || defined(CFG_MPC5554) || defined(CFG_MPC5633)
set_spr(SPR_IVOR0,((uint32_t)&exception_tbl+0x0) );
set_spr(SPR_IVOR1,((uint32_t)&exception_tbl+0x10) );
set_spr(SPR_IVOR2,((uint32_t)&exception_tbl+0x20) );
#if defined(CFG_MPC5516)
INTC.MCR.B.HVEN_PRC0 = 0; // Soft vector mode
INTC.MCR.B.VTES_PRC0 = 0; // 4 byte offset between entries
- #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
INTC.MCR.B.HVEN = 0; // Soft vector mode
INTC.MCR.B.VTES = 0; // 4 byte offset between entries
#endif
assert( (((uint32_t)&Irq_VectorTable[0]) & 0x7ff) == 0 );
#if defined(CFG_MPC5516)
INTC.IACKR_PRC0.R = (uint32_t) & Irq_VectorTable[0]; // Set INTC ISR vector table
- #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
INTC.IACKR.R = (uint32_t) & Irq_VectorTable[0]; // Set INTC ISR vector table
#endif
#endif
{
#if defined(CFG_MPC5516)
INTC.EOIR_PRC0.R = 0;
- #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
INTC.EOIR.R = 0;
#endif
}
// Accept interrupts
#if defined(CFG_MPC5516)
INTC.CPR_PRC0.B.PRI = 0;
- #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
+ #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
INTC.CPR.B.PRI = 0;
#endif
#if defined(CFG_MPC5516)
struct INTC_tag *intc = &INTC;
intc->EOIR_PRC0.R = 0;
-#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567) || defined(CFG_MPC5633)
volatile struct INTC_tag *intc = &INTC;
intc->EOIR.R = 0;
#endif
#if defined(CFG_MPC5516)
struct INTC_tag *intc = &INTC;
vector = (intc->IACKR_PRC0.B.INTVEC_PRC0);
-#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567) || defined(CFG_MPC5633)
volatile struct INTC_tag *intc = &INTC;
vector = (intc->IACKR.B.INTVEC);
#endif
} else if ( cpu == CPU_Z0 ) {
prio = INTC.CPR_PRC1.B.PRI;
}
-#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)|| defined(CFG_MPC5633)
prio = INTC.CPR.B.PRI;
#endif
EDMA_INTL_INT13,
EDMA_INTL_INT14,
EDMA_INTL_INT15, // 26
-#if defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
EDMA_INTL_INT16,
EDMA_INTL_INT17,
EDMA_INTL_INT18,
EMISOS200_FLAG_F21,
EMISOS200_FLAG_F22,
EMISOS200_FLAG_F23, // 16-81
-#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
ETPU_GLOBAL, // 54-67
ETPU_A_CIS_0,
ETPU_A_CIS_1,
DSPI_B_ISR_TFFF,
DSPI_B_ISR_TCF,
DSPI_B_ISR_RFDF,
-#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
DSPI_B_COMB, // 54-131
DSPI_B_ISR_EOQF,
DSPI_B_ISR_TFFF,
RESERVED_SPACE_BEFORE_EXCEPTIONS25,
#endif
-#if defined(CFG_MPC5554)||defined(CFG_MPC5567)
+#if defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
/* FlexCAN C */
FLEXCAN_C_ESR_BOFF_INT = 173,
FLEXCAN_C_ESR_ERR_INT,
DUMMY_DUMMY = 319,
-#endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567) */
+#endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633) */
CRITICAL_INPUT_EXCEPTION,
MACHINE_CHECK_EXCEPTION,
+++ /dev/null
-BDIR=system/kernel,system/kernel/testsystem
-CROSS_COMPILE=/opt/arm-elf/bin/arm-elf-
+++ /dev/null
-export BOARDDIR=mpc5554sim
-export MCU=MPC5554
-export ARCH=mpc55xx
-export ARCH_FAM=ppc
# Can\r
obj-$(USE_CAN) += Can.o\r
obj-$(USE_CAN) += Can_Lcfg.o\r
+\r
+# CanIf\r
obj-$(USE_CANIF) += CanIf.o\r
obj-$(USE_CANIF) += CanIf_Cfg.o\r
+vpath-$(USE_CANIF) += $(ROOTDIR)/communication/CanIf\r
+inc-$(USE_CANIF) += $(ROOTDIR)/communication/CanIf\r
\r
obj-$(USE_DIO) += Dio.o\r
obj-$(USE_DIO) += Dio_Lcfg.o\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
-#include "Mcu_Cfg.h"\r
+#include "Mcu.h"\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
// Imported structs from Can_Lcfg.c\r
extern const Can_ControllerConfigType CanControllerConfigData[];\r
extern const Can_ConfigSetType CanConfigSetData;\r
-\r
+
+// Contains the mapping from CanIf-specific Channels to Can Controllers
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {
+ CAN_CTRL_A, // CANIF_CHANNEL_0
+ CAN_CTRL_C, // CANIF_CHANNEL_1
+};\r
\r
// Container that gets slamed into CanIf_InitController()\r
// Inits ALL controllers\r
// Multiplicity 1..*\r
const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
{\r
- { // This is the ConfigurationIndex in CanIf_InitController()\r
- .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_A,\r
- .CanIfDriverNameRef = "FLEXCAN", // Not used\r
- .CanIfInitControllerRef = &CanControllerConfigData[0],\r
- },\r
- {\r
- .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_C,\r
- .CanIfDriverNameRef = "FLEXCAN", // Not used\r
- .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ { // CANIF_CHANNEL_0_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[0],
+ },
+ { // CANIF_CHANNEL_1_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_1,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[1],
}\r
};\r
\r
const CanIf_HthConfigType CanIfHthConfigData[] =\r
{\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_0,\r
.CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_1,\r
.CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
{\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
.CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_1,\r
.CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
//-------------------------------------------------------------------\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, //NULL,\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on channel 0,\r
.PduIdRef = NULL,\r
},\r
{\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = NULL,\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on controller C,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on channel 1,\r
.PduIdRef = NULL,\r
},\r
//Added by mattias\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, // NULL\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on channel 0,\r
.PduIdRef = NULL,\r
},\r
};\r
.CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL, // Changed by Mattias to test PDU router and Com layer.\r
.CanIfUserRxIndication = NULL, // No indication\r
- .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on channel 0,\r
.PduIdRef = NULL, // Could be used by upper layers\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
.CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, //\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL,\r
.CanIfUserRxIndication = NULL, // No indication\r
- .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on controller C\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on channel 0,\r
.PduIdRef = NULL, //\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
.CanConfigSet = &CanConfigSetData,\r
.CanIfHrhConfig = CanIfHrhConfigData,\r
.CanIfHthConfig = CanIfHthConfigData,\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
.ControllerConfig = CanIfControllerConfig,\r
.DispatchConfig = &CanIfDispatchConfig,\r
.InitConfig = &CanIfInitConfig,\r
- .TransceiverConfig = NULL, // Not used\r
+ .TransceiverConfig = NULL, // Not used
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap,\r
};\r
\r
#define CANIF_CFG_H_\r
\r
#include "Can.h"\r
+
+// Identifiers for the elements in CanIfControllerConfig[]
+// This is the ConfigurationIndex in CanIf_InitController()
+typedef enum {
+ CANIF_CHANNEL_0_CONFIG_0 = 0,
+
+ CANIF_CHANNEL_1_CONFIG_0 = 1,
+
+ CANIF_CHANNEL_CONFIGURATION_CNT
+} CanIf_Arc_ConfigurationIndexType;
+
+typedef enum {
+ CANIF_CHANNEL_0,
+ CANIF_CHANNEL_1,
+ CANIF_CHANNEL_CNT,
+} CanIf_Arc_ChannelIdType;
\r
typedef enum {\r
CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
void (*RxIndication)(void *); //(const Can_PduType *);\r
void (*ControllerBusOff)(uint8);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,uint32);\r
+ void (*Arc_Error)(uint8,uint32);\r
} CanIf_CallbackType;\r
\r
\r
typedef struct {\r
// Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
// configured, software filtering is enabled.\r
- Can_EcoreHohType CanIfHrhType;\r
+ Can_Arc_HohType CanIfHrhType;\r
\r
// Selects the hardware receive objects by using the HRH range/list from\r
// CAN Driver configuration to define, for which HRH a software filtering has\r
\r
// Reference to controller Id to which the HRH belongs to. A controller can\r
// contain one or more HRHs.\r
- uint8 CanIfCanControllerHrhIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
\r
// The parameter refers to a particular HRH object in the CAN Driver Module\r
// configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+ Can_Arc_HRHType CanIfHrhIdSymRef ;\r
\r
// Defines the parameters required for configuraing multiple\r
// CANID ranges for a given same HRH.\r
const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HrhConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
typedef struct {\r
// Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
- Can_EcoreHohType CanIfHthType;\r
+ Can_Arc_HohType CanIfHthType;\r
\r
// Reference to controller Id to which the HTH belongs to. A controller\r
// can contain one or more HTHs\r
- uint8 CanIfCanControllerIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
\r
// The parameter refers to a particular HTH object in the CAN Driver Module\r
// configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHTHType CanIfHthIdSymRef ;\r
+ Can_Arc_HTHType CanIfHthIdSymRef ;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HthConfigType;\r
\r
//-------------------------------------------------------------------\r
const CanIf_HthConfigType *CanIfHthConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_InitHohConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
// Acceptance filters, 1 - care, 0 - don't care.\r
// Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
- // Ecore exension\r
+ // ArcCore exension\r
uint32 CanIfCanRxPduCanIdMask;\r
\r
} CanIf_RxPduConfigType;\r
// This is the type supplied to CanIf_InitController()\r
typedef struct {\r
CanIf_WakeupSupportType WakeupSupport; // Not used\r
-\r
- CanControllerIdType CanIfControllerIdRef;\r
+
+ // CanIf-specific id of the controller\r
+ CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
\r
const char CanIfDriverNameRef[8]; // Not used\r
\r
// Multiplicity: 0..1\r
void (*CanIfWakeupValidNotification)();\r
\r
- // Ecore ext.\r
- void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+ // ArcCore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
\r
} CanIf_DispatchConfigType;\r
\r
// addressed CAN transceivers by each underlying CAN\r
// Transceiver Driver.\r
// Multiplicity: 1..*\r
- const CanIf_TransceiverConfigType *TransceiverConfig;\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;
+
+ // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers
+ const CanControllerIdType *Arc_ChannelToControllerMap;\r
} CanIf_ConfigType;\r
\r
\r
#define CAN_CFG_H_\r
\r
// Number of controller configs\r
-#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+#define CAN_ARC_CTRL_CONFIG_CNT 2\r
\r
#define CAN_DEV_ERROR_DETECT STD_ON\r
#define CAN_VERSION_INFO_API STD_ON\r
} Can_ObjectTypeType;\r
\r
typedef enum {\r
- CAN_ECORE_HANDLE_TYPE_BASIC,\r
- CAN_ECORE_HANDLE_TYPE_FULL\r
-} Can_EcoreHohType;\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
\r
// HTH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HTH_A_1 = 0,\r
CAN_HTH_C_1,\r
NUM_OF_HTHS\r
-} Can_EcoreHTHType;\r
+} Can_Arc_HTHType;\r
\r
// HRH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HRH_A_1 = 0,\r
CAN_HRH_C_1,\r
NUM_OF_HRHS\r
-} Can_EcoreHRHType;\r
+} Can_Arc_HRHType;\r
\r
// Non-standard type\r
typedef struct {\r
void (*ControllerBusOff)(uint8);\r
void (*TxConfirmation)(PduIdType);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
} Can_CallbackType;\r
\r
/*\r
//Objects.\r
typedef struct Can_HardwareObjectStruct {\r
// Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
- Can_EcoreHohType CanHandleType;\r
+ Can_Arc_HohType CanHandleType;\r
\r
// Specifies whether the IdValue is of type - standard identifier - extended\r
// identifier - mixed mode ImplementationType: Can_IdType\r
\r
// A "1" in this mask tells the driver that that HW Message Box should be\r
// occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
- uint32 CanEcoreMbMask;\r
+ uint32 Can_Arc_MbMask;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanEcoreEOL;\r
+ boolean Can_Arc_EOL;\r
\r
} Can_HardwareObjectType;\r
\r
* CanController container\r
*/\r
typedef enum {\r
- CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- CAN_ECORE_PROCESS_TYPE_POLLING,\r
-} Can_EcoreProcessType;\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
\r
typedef struct {\r
\r
// Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
// events in polling mode.\r
// INTERRUPT or POLLING\r
- Can_EcoreProcessType CanBusOffProcessing;\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
\r
// Defines if a CAN controller is used in the configuration.\r
boolean CanControllerActivation;\r
\r
// Enables / disables API Can_MainFunction_Read() for handling PDU\r
// reception events in polling mode.\r
- Can_EcoreProcessType CanRxProcessing;\r
+ Can_Arc_ProcessType CanRxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Write() for handling PDU\r
// transmission events in polling mode.\r
- Can_EcoreProcessType CanTxProcessing;\r
+ Can_Arc_ProcessType CanTxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
// events in polling mode.\r
- Can_EcoreProcessType CanWakeupProcessing;\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
\r
// Reference to the CPU clock configuration, which is set in the MCU driver\r
// configuration\r
uint32 CanWakeupSourceRef;\r
\r
//\r
- // Ecore stuff\r
+ // ArcCore stuff\r
//\r
\r
// List of Hoh id's that belong to this controller\r
- const Can_HardwareObjectType *CanEcoreHoh;\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
\r
- boolean CanEcoreLoopback;\r
+ boolean Can_Arc_Loopback;\r
\r
// Set this to use the fifo\r
- boolean CanEcoreFifo;\r
+ boolean Can_Arc_Fifo;\r
\r
} Can_ControllerConfigType;\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
- .CanEcoreLoopback = 0,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .Can_Arc_Loopback = 0,\r
+ .Can_Arc_Fifo = 0,\r
\r
},{\r
.CanControllerActivation = TRUE,\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
- .CanEcoreLoopback = 1,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .Can_Arc_Loopback = 1,\r
+ .Can_Arc_Fifo = 0,\r
}\r
};\r
\r
CanIf_ControllerBusOff,\r
CanIf_TxConfirmation,\r
NULL, //CanIf_ControllerWakeup,\r
- CanIf_EcoreError,\r
+ CanIf_Arc_Error,\r
};\r
\r
/* Configset configuration information\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
}\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComIPduGroupHandleId = 0\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 16,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 16,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
//.ComTimeoutNotification = NULL,\r
//.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 42,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
- .ComEcoreIsSignalGroup = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
+ .Com_Arc_IsSignalGroup = 1,\r
.ComGroupSignal = {\r
&HardwareTest_ComGroupSignal[0],\r
&HardwareTest_ComGroupSignal[1],\r
}*/\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComIPduGroupHandleId = 2\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
-#include "Mcu_Cfg.h"\r
-#include "Lin_Cfg.h"\r
+#include "Mcu.h"\r
+#include "Lin.h"\r
\r
const Lin_ChannelConfigType LinChannelConfigData[] = {\r
{\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
-#include "Mcu_Cfg.h"\r
+#include "Mcu.h"\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
#ifndef SPI_CFG_H_
#define SPI_CFG_H_
-#include "Dma_Cfg.h"
+#include "Dma.h"
#include "mpc55xx.h"
-#include "Mcu_Cfg.h"
+#include "Mcu.h"
#define DSPI_CTRL_A 0
#define DSPI_CTRL_B 1
typedef enum
{
- SPI_ECORE_TRANSFER_START_LSB,
- SPI_ECORE_TRANSFER_START_MSB,
-} Spi_EcoreTransferStartType;
+ SPI_ARC_TRANSFER_START_LSB,
+ SPI_ARC_TRANSFER_START_MSB,
+} Spi_Arc_TransferStartType;
typedef enum {
Spi_NumberOfDataType SpiIbNBuffers;
// This parameter defines the first starting bit for transmission.
- Spi_EcoreTransferStartType SpiTransferStart;
+ Spi_Arc_TransferStartType SpiTransferStart;
//
_Bool SpiDmaNoIncreaseSrc;
// Timing between PCS and first edge of SCK. Unit ns.
uint32 SpiTimeCs2Clk;
- // Ecore extension...
+ // ArcCore extension...
// The controller ID(0..3)
//uint32 SpiControllerId;
#define CANIF_CFG_H_\r
\r
#include "Can.h"\r
+
+// Identifiers for the elements in CanIfControllerConfig[]
+// This is the ConfigurationIndex in CanIf_InitController()
+typedef enum {
+ CANIF_CHANNEL_0_CONFIG_0 = 0,
+
+ CANIF_CHANNEL_1_CONFIG_0 = 1,
+
+ CANIF_CHANNEL_CONFIGURATION_CNT
+} CanIf_Arc_ConfigurationIndexType;
+
+typedef enum {
+ CANIF_CHANNEL_0,
+ CANIF_CHANNEL_1,
+ CANIF_CHANNEL_CNT,
+} CanIf_Arc_ChannelIdType;
\r
typedef enum {\r
CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
void (*RxIndication)(void *); //(const Can_PduType *);\r
void (*ControllerBusOff)(uint8);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,uint32);\r
+ void (*Arc_Error)(uint8,uint32);\r
} CanIf_CallbackType;\r
\r
\r
typedef struct {\r
// Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
// configured, software filtering is enabled.\r
- Can_EcoreHohType CanIfHrhType;\r
+ Can_Arc_HohType CanIfHrhType;\r
\r
// Selects the hardware receive objects by using the HRH range/list from\r
// CAN Driver configuration to define, for which HRH a software filtering has\r
\r
// Reference to controller Id to which the HRH belongs to. A controller can\r
// contain one or more HRHs.\r
- uint8 CanIfCanControllerHrhIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
\r
// The parameter refers to a particular HRH object in the CAN Driver Module\r
// configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+ Can_Arc_HRHType CanIfHrhIdSymRef ;\r
\r
// Defines the parameters required for configuraing multiple\r
// CANID ranges for a given same HRH.\r
const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HrhConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
typedef struct {\r
// Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
- Can_EcoreHohType CanIfHthType;\r
+ Can_Arc_HohType CanIfHthType;\r
\r
// Reference to controller Id to which the HTH belongs to. A controller\r
// can contain one or more HTHs\r
- uint8 CanIfCanControllerIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
\r
// The parameter refers to a particular HTH object in the CAN Driver Module\r
// configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHTHType CanIfHthIdSymRef ;\r
+ Can_Arc_HTHType CanIfHthIdSymRef ;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HthConfigType;\r
\r
//-------------------------------------------------------------------\r
const CanIf_HthConfigType *CanIfHthConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_InitHohConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
// Acceptance filters, 1 - care, 0 - don't care.\r
// Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
- // Ecore exension\r
+ // ArcCore exension\r
uint32 CanIfCanRxPduCanIdMask;\r
\r
} CanIf_RxPduConfigType;\r
// This is the type supplied to CanIf_InitController()\r
typedef struct {\r
CanIf_WakeupSupportType WakeupSupport; // Not used\r
-\r
- CanControllerIdType CanIfControllerIdRef;\r
+
+ // CanIf-specific id of the controller
+ CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
\r
const char CanIfDriverNameRef[8]; // Not used\r
\r
// Multiplicity: 0..1\r
void (*CanIfWakeupValidNotification)();\r
\r
- // Ecore ext.\r
- void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+ // ArcCore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
\r
} CanIf_DispatchConfigType;\r
\r
// addressed CAN transceivers by each underlying CAN\r
// Transceiver Driver.\r
// Multiplicity: 1..*\r
- const CanIf_TransceiverConfigType *TransceiverConfig;\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;
+
+ // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers
+ const CanControllerIdType *Arc_ChannelToControllerMap;\r
} CanIf_ConfigType;\r
\r
\r
#define CAN_CFG_H_\r
\r
// Number of controller configs\r
-#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+#define CAN_ARC_CTRL_CONFIG_CNT 2\r
\r
#define CAN_DEV_ERROR_DETECT STD_ON\r
#define CAN_VERSION_INFO_API STD_ON\r
} Can_ObjectTypeType;\r
\r
typedef enum {\r
- CAN_ECORE_HANDLE_TYPE_BASIC,\r
- CAN_ECORE_HANDLE_TYPE_FULL\r
-} Can_EcoreHohType;\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
\r
// HTH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HTH_A_1 = 0,\r
CAN_HTH_C_1,\r
NUM_OF_HTHS\r
-} Can_EcoreHTHType;\r
+} Can_Arc_HTHType;\r
\r
// HRH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HRH_A_1 = 0,\r
CAN_HRH_C_1,\r
NUM_OF_HRHS\r
-} Can_EcoreHRHType;\r
+} Can_Arc_HRHType;\r
\r
// Non-standard type\r
typedef struct {\r
void (*ControllerBusOff)(uint8);\r
void (*TxConfirmation)(PduIdType);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
} Can_CallbackType;\r
\r
/*\r
//Objects.\r
typedef struct Can_HardwareObjectStruct {\r
// Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
- Can_EcoreHohType CanHandleType;\r
+ Can_Arc_HohType CanHandleType;\r
\r
// Specifies whether the IdValue is of type - standard identifier - extended\r
// identifier - mixed mode ImplementationType: Can_IdType\r
\r
// A "1" in this mask tells the driver that that HW Message Box should be\r
// occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
- uint32 CanEcoreMbMask;\r
+ uint32 Can_Arc_MbMask;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanEcoreEOL;\r
+ boolean Can_Arc_EOL;\r
\r
} Can_HardwareObjectType;\r
\r
* CanController container\r
*/\r
typedef enum {\r
- CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- CAN_ECORE_PROCESS_TYPE_POLLING,\r
-} Can_EcoreProcessType;\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
\r
typedef struct {\r
\r
// Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
// events in polling mode.\r
// INTERRUPT or POLLING\r
- Can_EcoreProcessType CanBusOffProcessing;\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
\r
// Defines if a CAN controller is used in the configuration.\r
boolean CanControllerActivation;\r
\r
// Enables / disables API Can_MainFunction_Read() for handling PDU\r
// reception events in polling mode.\r
- Can_EcoreProcessType CanRxProcessing;\r
+ Can_Arc_ProcessType CanRxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Write() for handling PDU\r
// transmission events in polling mode.\r
- Can_EcoreProcessType CanTxProcessing;\r
+ Can_Arc_ProcessType CanTxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
// events in polling mode.\r
- Can_EcoreProcessType CanWakeupProcessing;\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
\r
// Reference to the CPU clock configuration, which is set in the MCU driver\r
// configuration\r
uint32 CanWakeupSourceRef;\r
\r
//\r
- // Ecore stuff\r
+ // ArcCore stuff\r
//\r
\r
// List of Hoh id's that belong to this controller\r
- const Can_HardwareObjectType *CanEcoreHoh;\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
\r
- boolean CanEcoreLoopback;\r
+ boolean Can_Arc_Loopback;\r
\r
// Set this to use the fifo\r
- boolean CanEcoreFifo;\r
+ boolean Can_Arc_Fifo;\r
\r
} Can_ControllerConfigType;\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
- .CanEcoreLoopback = 0,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .Can_Arc_Loopback = 0,\r
+ .Can_Arc_Fifo = 0,\r
\r
},{\r
.CanControllerActivation = TRUE,\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
- .CanEcoreLoopback = 1,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .Can_Arc_Loopback = 1,\r
+ .Can_Arc_Fifo = 0,\r
}\r
};\r
\r
CanIf_ControllerBusOff,\r
CanIf_TxConfirmation,\r
NULL, //CanIf_ControllerWakeup,\r
- CanIf_EcoreError,\r
+ CanIf_Arc_Error,\r
};\r
\r
/* Configset configuration information\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
-#include "Mcu_Cfg.h"\r
+#include "Mcu.h"\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
-#include "Mcu_Cfg.h"\r
+#include "Mcu.h"\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
// Imported structs from Can_Lcfg.c\r
extern const Can_ControllerConfigType CanControllerConfigData[];\r
extern const Can_ConfigSetType CanConfigSetData;\r
-\r
+
+// Contains the mapping from CanIf-specific Channels to Can Controllers
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {
+ CAN_CTRL_A, // CANIF_CHANNEL_0
+ CAN_CTRL_C, // CANIF_CHANNEL_1
+};
\r
// Container that gets slamed into CanIf_InitController()\r
// Inits ALL controllers\r
// Multiplicity 1..*\r
const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
{\r
- { // This is the ConfigurationIndex in CanIf_InitController()\r
- .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_A,\r
- .CanIfDriverNameRef = "FLEXCAN", // Not used\r
- .CanIfInitControllerRef = &CanControllerConfigData[0],\r
- },\r
- {\r
- .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_C,\r
- .CanIfDriverNameRef = "FLEXCAN", // Not used\r
- .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ { // CANIF_CHANNEL_0_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[0],
+ },
+ { // CANIF_CHANNEL_1_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_1,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[1],
}\r
};\r
\r
const CanIf_HthConfigType CanIfHthConfigData[] =\r
{\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_0,\r
.CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_1,\r
.CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
{\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
.CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_1,\r
.CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
//-------------------------------------------------------------------\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, //NULL,\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on channel 0,\r
.PduIdRef = NULL,\r
},\r
{\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = NULL,\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on controller C,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[1], // Send on channel 1,\r
.PduIdRef = NULL,\r
},\r
//Added by mattias\r
#endif\r
.CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfUserTxConfirmation = PduR_CanIfTxConfirmation, // NULL\r
- .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on controller A,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData[0], // Send on channel 0,\r
.PduIdRef = NULL,\r
},\r
};\r
.CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL, // Changed by Mattias to test PDU router and Com layer.\r
.CanIfUserRxIndication = NULL, // No indication\r
- .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on channel 0,\r
.PduIdRef = NULL, // Could be used by upper layers\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
.CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29, //\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR, // CANIF_USER_TYPE_CAN_SPECIAL,\r
.CanIfUserRxIndication = NULL, // No indication\r
- .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on controller C\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], //&CanIfHrhConfigData[1], // Received on channel 0,\r
.PduIdRef = NULL, //\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
.CanConfigSet = &CanConfigSetData,\r
.CanIfHrhConfig = CanIfHrhConfigData,\r
.CanIfHthConfig = CanIfHthConfigData,\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
.ControllerConfig = CanIfControllerConfig,\r
.DispatchConfig = &CanIfDispatchConfig,\r
.InitConfig = &CanIfInitConfig,\r
- .TransceiverConfig = NULL, // Not used\r
+ .TransceiverConfig = NULL, // Not used
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap,\r
};\r
\r
#define CANIF_CFG_H_\r
\r
#include "Can.h"\r
+
+// Identifiers for the elements in CanIfControllerConfig[]
+// This is the ConfigurationIndex in CanIf_InitController()
+typedef enum {
+ CANIF_CHANNEL_0_CONFIG_0 = 0,
+
+ CANIF_CHANNEL_1_CONFIG_0 = 1,
+
+ CANIF_CHANNEL_CONFIGURATION_CNT
+} CanIf_Arc_ConfigurationIndexType;
+
+typedef enum {
+ CANIF_CHANNEL_0,
+ CANIF_CHANNEL_1,
+ CANIF_CHANNEL_CNT,
+} CanIf_Arc_ChannelIdType;
\r
typedef enum {\r
CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
void (*RxIndication)(void *); //(const Can_PduType *);\r
void (*ControllerBusOff)(uint8);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,uint32);\r
+ void (*Arc_Error)(uint8,uint32);\r
} CanIf_CallbackType;\r
\r
\r
typedef struct {\r
// Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
// configured, software filtering is enabled.\r
- Can_EcoreHohType CanIfHrhType;\r
+ Can_Arc_HohType CanIfHrhType;\r
\r
// Selects the hardware receive objects by using the HRH range/list from\r
// CAN Driver configuration to define, for which HRH a software filtering has\r
\r
// Reference to controller Id to which the HRH belongs to. A controller can\r
// contain one or more HRHs.\r
- uint8 CanIfCanControllerHrhIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
\r
// The parameter refers to a particular HRH object in the CAN Driver Module\r
// configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHRHType CanIfHrhIdSymRef ;\r
+ Can_Arc_HRHType CanIfHrhIdSymRef ;\r
\r
// Defines the parameters required for configuraing multiple\r
// CANID ranges for a given same HRH.\r
const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HrhConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
typedef struct {\r
// Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
- Can_EcoreHohType CanIfHthType;\r
+ Can_Arc_HohType CanIfHthType;\r
\r
// Reference to controller Id to which the HTH belongs to. A controller\r
// can contain one or more HTHs\r
- uint8 CanIfCanControllerIdRef;\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
\r
// The parameter refers to a particular HTH object in the CAN Driver Module\r
// configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
// are defined in the CAN Driver Module and hence it is derived from CAN\r
// Driver Configuration.\r
- Can_EcoreHTHType CanIfHthIdSymRef ;\r
+ Can_Arc_HTHType CanIfHthIdSymRef ;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_HthConfigType;\r
\r
//-------------------------------------------------------------------\r
const CanIf_HthConfigType *CanIfHthConfig;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanIfEcoreEOL;\r
+ boolean CanIf_Arc_EOL;\r
} CanIf_InitHohConfigType;\r
\r
//-------------------------------------------------------------------\r
\r
// Acceptance filters, 1 - care, 0 - don't care.\r
// Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
- // Ecore exension\r
+ // ArcCore exension\r
uint32 CanIfCanRxPduCanIdMask;\r
\r
} CanIf_RxPduConfigType;\r
// This is the type supplied to CanIf_InitController()\r
typedef struct {\r
CanIf_WakeupSupportType WakeupSupport; // Not used\r
-\r
- CanControllerIdType CanIfControllerIdRef;\r
+
+ // CanIf-specific id of the controller
+ CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
\r
const char CanIfDriverNameRef[8]; // Not used\r
\r
// Multiplicity: 0..1\r
void (*CanIfWakeupValidNotification)();\r
\r
- // Ecore ext.\r
- void (*CanIfErrorNotificaton)(uint8,Can_EcoreErrorType);\r
+ // ArcCore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
\r
} CanIf_DispatchConfigType;\r
\r
// addressed CAN transceivers by each underlying CAN\r
// Transceiver Driver.\r
// Multiplicity: 1..*\r
- const CanIf_TransceiverConfigType *TransceiverConfig;\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;
+
+ // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers
+ const CanControllerIdType *Arc_ChannelToControllerMap;\r
} CanIf_ConfigType;\r
\r
\r
#define CAN_CFG_H_\r
\r
// Number of controller configs\r
-#define CAN_ECORE_CTRL_CONFIG_CNT 2\r
+#define CAN_ARC_CTRL_CONFIG_CNT 2\r
\r
#define CAN_DEV_ERROR_DETECT STD_ON\r
#define CAN_VERSION_INFO_API STD_ON\r
} Can_ObjectTypeType;\r
\r
typedef enum {\r
- CAN_ECORE_HANDLE_TYPE_BASIC,\r
- CAN_ECORE_HANDLE_TYPE_FULL\r
-} Can_EcoreHohType;\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
\r
// HTH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HTH_A_1 = 0,\r
CAN_HTH_C_1,\r
NUM_OF_HTHS\r
-} Can_EcoreHTHType;\r
+} Can_Arc_HTHType;\r
\r
// HRH definitions\r
// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
CAN_HRH_A_1 = 0,\r
CAN_HRH_C_1,\r
NUM_OF_HRHS\r
-} Can_EcoreHRHType;\r
+} Can_Arc_HRHType;\r
\r
// Non-standard type\r
typedef struct {\r
void (*ControllerBusOff)(uint8);\r
void (*TxConfirmation)(PduIdType);\r
void (*ControllerWakeup)(uint8);\r
- void (*EcoreError)(uint8,Can_EcoreErrorType);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
} Can_CallbackType;\r
\r
/*\r
//Objects.\r
typedef struct Can_HardwareObjectStruct {\r
// Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
- Can_EcoreHohType CanHandleType;\r
+ Can_Arc_HohType CanHandleType;\r
\r
// Specifies whether the IdValue is of type - standard identifier - extended\r
// identifier - mixed mode ImplementationType: Can_IdType\r
\r
// A "1" in this mask tells the driver that that HW Message Box should be\r
// occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
- uint32 CanEcoreMbMask;\r
+ uint32 Can_Arc_MbMask;\r
\r
// End Of List. Set to TRUE is this is the last object in the list.\r
- boolean CanEcoreEOL;\r
+ boolean Can_Arc_EOL;\r
\r
} Can_HardwareObjectType;\r
\r
* CanController container\r
*/\r
typedef enum {\r
- CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- CAN_ECORE_PROCESS_TYPE_POLLING,\r
-} Can_EcoreProcessType;\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
\r
typedef struct {\r
\r
// Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
// events in polling mode.\r
// INTERRUPT or POLLING\r
- Can_EcoreProcessType CanBusOffProcessing;\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
\r
// Defines if a CAN controller is used in the configuration.\r
boolean CanControllerActivation;\r
\r
// Enables / disables API Can_MainFunction_Read() for handling PDU\r
// reception events in polling mode.\r
- Can_EcoreProcessType CanRxProcessing;\r
+ Can_Arc_ProcessType CanRxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Write() for handling PDU\r
// transmission events in polling mode.\r
- Can_EcoreProcessType CanTxProcessing;\r
+ Can_Arc_ProcessType CanTxProcessing;\r
\r
// Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
// events in polling mode.\r
- Can_EcoreProcessType CanWakeupProcessing;\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
\r
// Reference to the CPU clock configuration, which is set in the MCU driver\r
// configuration\r
uint32 CanWakeupSourceRef;\r
\r
//\r
- // Ecore stuff\r
+ // ArcCore stuff\r
//\r
\r
// List of Hoh id's that belong to this controller\r
- const Can_HardwareObjectType *CanEcoreHoh;\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
\r
- boolean CanEcoreLoopback;\r
+ boolean Can_Arc_Loopback;\r
\r
// Set this to use the fifo\r
- boolean CanEcoreFifo;\r
+ boolean Can_Arc_Fifo;\r
\r
} Can_ControllerConfigType;\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_A[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_EXTENDED,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_A_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
const Can_HardwareObjectType CanHardwareObjectConfig_CTRL_C[] =\r
{\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
.CanObjectId = CAN_HRH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0x00ff0000,\r
- .CanEcoreEOL = 0,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0x00ff0000,\r
+ .Can_Arc_EOL = 0,\r
},\r
{\r
- .CanHandleType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIdType = CAN_ID_TYPE_STANDARD,\r
.CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
.CanObjectId = CAN_HTH_C_1,\r
.CanFilterMaskRef = &Can_FilterMaskConfigData,\r
- // Ecore\r
- .CanEcoreMbMask = 0xff000000,\r
- .CanEcoreEOL = 1,\r
+ // ArcCore\r
+ .Can_Arc_MbMask = 0xff000000,\r
+ .Can_Arc_EOL = 1,\r
},\r
};\r
\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_A[0],\r
- .CanEcoreLoopback = 0,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_A[0],\r
+ .Can_Arc_Loopback = 0,\r
+ .Can_Arc_Fifo = 0,\r
\r
},{\r
.CanControllerActivation = TRUE,\r
.CanControllerPropSeg = 4,\r
.CanControllerSeg1 = 4,\r
.CanControllerSeg2 = 4,\r
- .CanBusOffProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanRxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanTxProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
- .CanWakeupProcessing = CAN_ECORE_PROCESS_TYPE_INTERRUPT,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
.CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_C,\r
- // Ecore\r
- .CanEcoreHoh = &CanHardwareObjectConfig_CTRL_C[0],\r
- .CanEcoreLoopback = 1,\r
- .CanEcoreFifo = 0,\r
+ // ArcCore\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CTRL_C[0],\r
+ .Can_Arc_Loopback = 1,\r
+ .Can_Arc_Fifo = 0,\r
}\r
};\r
\r
CanIf_ControllerBusOff,\r
CanIf_TxConfirmation,\r
NULL, //CanIf_ControllerWakeup,\r
- CanIf_EcoreError,\r
+ CanIf_Arc_Error,\r
};\r
\r
/* Configset configuration information\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 0,\r
- .ComSignalEcoreUseUpdateBit = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
}\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComIPduGroupHandleId = 0\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 16,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
.ComTimeoutNotification = NULL,\r
.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 16,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
.ComFilter = {\r
.ComFilterAlgorithm = ALWAYS,\r
.ComFilterMask = 0,\r
//.ComTimeoutNotification = NULL,\r
//.ComTransferProperty = TRIGGERED,\r
.ComUpdateBitPosition = 42,\r
- .ComSignalEcoreUseUpdateBit = 1,\r
- .ComEcoreIsSignalGroup = 1,\r
+ .ComSignalArcUseUpdateBit = 1,\r
+ .Com_Arc_IsSignalGroup = 1,\r
.ComGroupSignal = {\r
&HardwareTest_ComGroupSignal[0],\r
&HardwareTest_ComGroupSignal[1],\r
}*/\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComIPduGroupHandleId = 2\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
-#include "Mcu_Cfg.h"\r
-#include "Lin_Cfg.h"\r
+#include "Mcu.h"\r
+#include "Lin.h"\r
\r
const Lin_ChannelConfigType LinChannelConfigData[] = {\r
{\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
-#include "Mcu_Cfg.h"\r
+#include "Mcu.h"\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
#define MCU_VERSION_INFO_API STD_ON\r
\r
#include "Std_Types.h"\r
-#include "Mcu_Cfg.h"\r
\r
/* FMPLL modes( atleast in 5553/5554 ) */\r
\r
#ifndef SPI_CFG_H_
#define SPI_CFG_H_
-#include "Dma_Cfg.h"
-#include "Mcu_Cfg.h"
+#include "Dma.h"
+#include "Mcu.h"
#define DSPI_CTRL_A 0
#define DSPI_CTRL_B 1
typedef enum
{
- SPI_ECORE_TRANSFER_START_LSB,
- SPI_ECORE_TRANSFER_START_MSB,
-} Spi_EcoreTransferStartType;
+ SPI_ARC_TRANSFER_START_LSB,
+ SPI_ARC_TRANSFER_START_MSB,
+} Spi_Arc_TransferStartType;
typedef enum {
Spi_NumberOfDataType SpiIbNBuffers;
// This parameter defines the first starting bit for transmission.
- Spi_EcoreTransferStartType SpiTransferStart;
+ Spi_Arc_TransferStartType SpiTransferStart;
//
_Bool SpiDmaNoIncreaseSrc;
// Timing between PCS and first edge of SCK. Unit ns.
uint32 SpiTimeCs2Clk;
- // Ecore extension...
+ // ArcCore extension...
// The controller ID(0..3)
//uint32 SpiControllerId;
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5633
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM T32_TERM WINIDEA_TERM PWM CAN CANIF COM ADC DMA SIMPLE_PRINTF
+
+# Needed by us
+MOD_USE=KERNEL MCU
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 40000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
#define DET_REPORTERROR(_x,_y,_z,_q)
#endif
-#define GET_CONTROLLER_CNT() CAN_ECORE_CTRL_CONFIG_CNT
+
+// Helper to get the Can Controller refered to by a CanIf Channel
+#define ARC_GET_CHANNEL_CONTROLLER(_channel) \
+ CanIf_ConfigPtr->Arc_ChannelToControllerMap[channel]
/* Global configure */
static const CanIf_ConfigType *CanIf_ConfigPtr;
// Struct of controller private data.
-typedef struct CanIf_ControllerPrivateStruct
+typedef struct
{
CanIf_ControllerModeType ControllerMode;
- CanIf_ChannelGetModeType ChannelMode;
-} CanIf_ControllerPrivateType;
+ CanIf_ChannelGetModeType PduMode;
+} CanIf_ChannelPrivateType;
typedef struct
{
boolean initRun;
- CanIf_ControllerPrivateType controllerData[GET_CONTROLLER_CNT()];
+ CanIf_ChannelPrivateType channelData[CANIF_CHANNEL_CNT];
} CanIf_GlobalType;
-static sint8 CanIf_FindHrhCtrl( Can_EcoreHRHType hrh )
+static CanIf_Arc_ChannelIdType CanIf_Arc_FindHrhChannel( Can_Arc_HRHType hrh )
{
const CanIf_HrhConfigType *hrhConfig;
hrhConfig++;
if (hrhConfig->CanIfHrhIdSymRef == hrh)
return hrhConfig->CanIfCanControllerHrhIdRef;
- } while(!hrhConfig->CanIfEcoreEOL);
+ } while(!hrhConfig->CanIf_Arc_EOL);
DET_REPORTERROR(MODULE_ID_CANIF, 0, CANIF_RXINDICATION_ID, CANIF_E_PARAM_HRH);
CanIf_ConfigPtr = ConfigPtr;
- for (uint16 i = 0; i < GET_CONTROLLER_CNT(); i++)
+ for (uint16 i = 0; i < CANIF_CHANNEL_CNT; i++)
{
- CanIf_Global.controllerData[i].ControllerMode = CANIF_CS_STOPPED;
- CanIf_Global.controllerData[i].ChannelMode = CANIF_GET_OFFLINE;
+ CanIf_Global.channelData[i].ControllerMode = CANIF_CS_STOPPED;
+ CanIf_Global.channelData[i].PduMode = CANIF_GET_OFFLINE;
}
// NOTE!
// Do NOT initialise the Can Drivers and Tranceivers, see CANIF085
- //
CanIf_Global.initRun = TRUE;
}
-//-------------------------------------------------------------------
+
+
+//-------------------------------------------------------------------
+/*
+ * Controller :: CanIf_Arc_ChannelIdType (CanIf-specific id to abstract from Can driver/controllers)
+ * ConfigurationIndex :: CanIf_Arc_ConfigurationIndexType
+ * /tojo
+ */
void CanIf_InitController(uint8 Controller, uint8 ConfigurationIndex)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_INIT_CONTROLLER_ID, CANIF_E_UNINIT );
- VALIDATE_NO_RV(Controller < GET_CONTROLLER_CNT(), CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
- VALIDATE_NO_RV(ConfigurationIndex < CAN_ECORE_CTRL_CONFIG_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_POINTER);
+ VALIDATE_NO_RV(channel < CANIF_CHANNEL_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
+ VALIDATE_NO_RV(ConfigurationIndex < CANIF_CHANNEL_CONFIGURATION_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_POINTER);
#if (CANIF_DEV_ERROR_DETECT == STD_ON)
CanIf_ControllerModeType mode;
- if (CanIf_GetControllerMode(Controller, &mode) == E_OK)
+ if (CanIf_GetControllerMode(channel, &mode) == E_OK)
{
VALIDATE_NO_RV((mode != CANIF_CS_UNINIT), CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE );
}
}
#endif
- if (CanIf_GetControllerMode(Controller, &mode) == E_OK)
+ if (CanIf_GetControllerMode(channel, &mode) == E_OK)
{
if (mode == CANIF_CS_STARTED)
{
- CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED); // CANIF092
+ CanIf_SetControllerMode(channel, CANIF_CS_STOPPED); // CANIF092
}
else if (mode != CANIF_CS_STOPPED)
{
// Grab the configuration from the Can Controller
const Can_ControllerConfigType *canConfig;
+ const CanControllerIdType canControllerId = ARC_GET_CHANNEL_CONTROLLER(channel);
- // Validate that the configuration index match the right controller
- VALIDATE_NO_RV(CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfControllerIdRef == Controller, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
+ // Validate that the configuration at the index match the right channel
+ VALIDATE_NO_RV(CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfControllerIdRef == channel, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
canConfig = CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfInitControllerRef;
- Can_InitController(Controller, canConfig);
+ // Validate that the CanIfControllerConfig points to configuration for the right Can Controller
+ VALIDATE_NO_RV(canConfig->CanControllerId == canControllerId, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);
+
+ Can_InitController(canControllerId, canConfig);
// Set mode to stopped
- CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED);
+ CanIf_SetControllerMode(channel, CANIF_CS_STOPPED);
}
//-------------------------------------------------------------------
Std_ReturnType CanIf_SetControllerMode(uint8 Controller,
CanIf_ControllerModeType ControllerMode)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
+
CanIf_ControllerModeType oldMode;
VALIDATE( CanIf_Global.initRun, CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_UNINIT );
- VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE( channel < CANIF_CHANNEL_CNT, CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
- oldMode = CanIf_Global.controllerData[Controller].ControllerMode;
+ oldMode = CanIf_Global.channelData[channel].ControllerMode;
if (oldMode == CANIF_CS_UNINIT)
{
VALIDATE(FALSE, CANIF_SET_CONTROLLER_MODE_ID, CANIF_E_UNINIT); // See figure 32, 33
return E_NOT_OK;
}
-
+ CanControllerIdType canControllerId = ARC_GET_CHANNEL_CONTROLLER(Controller);
switch (ControllerMode)
{
case CANIF_CS_STARTED: // Figure 32
switch (oldMode)
{
case CANIF_CS_SLEEP:
- if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)
return E_NOT_OK;
- CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;
break;
default:
// Just fall through
break;
}
- CanIf_SetPduMode(Controller, CANIF_SET_ONLINE);
- if (Can_SetControllerMode(Controller, CAN_T_START) == CAN_NOT_OK)
+ CanIf_SetPduMode(channel, CANIF_SET_ONLINE);
+ if (Can_SetControllerMode(canControllerId, CAN_T_START) == CAN_NOT_OK)
return E_NOT_OK;
- CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STARTED;
+ CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STARTED;
}
break;
{
switch (oldMode) {
case CANIF_CS_STARTED:
- if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)
return E_NOT_OK;
- CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;
break;
default:
// Just fall through for other cases
break;
}
- if (Can_SetControllerMode(Controller, CAN_T_SLEEP) == CAN_NOT_OK)
+ if (Can_SetControllerMode(canControllerId, CAN_T_SLEEP) == CAN_NOT_OK)
return E_NOT_OK;
- CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_SLEEP;
+ CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_SLEEP;
}
case CANIF_CS_STOPPED:
switch (oldMode)
{
case CANIF_CS_SLEEP:
- if (Can_SetControllerMode(Controller, CAN_T_WAKEUP) == CAN_NOT_OK)
+ if (Can_SetControllerMode(canControllerId, CAN_T_WAKEUP) == CAN_NOT_OK)
return E_NOT_OK;
break;
default:
break;
}
- CanIf_SetPduMode(Controller, CANIF_SET_OFFLINE);
- if (Can_SetControllerMode(Controller, CAN_T_STOP) == CAN_NOT_OK)
+ CanIf_SetPduMode(channel, CANIF_SET_OFFLINE);
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)
return E_NOT_OK;
- CanIf_Global.controllerData[Controller].ControllerMode = CANIF_CS_STOPPED;
+ CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;
}
case CANIF_CS_UNINIT:
- // Jusr fall through
+ // Just fall through
break;
}
return E_OK;
Std_ReturnType CanIf_GetControllerMode(uint8 Controller,
CanIf_ControllerModeType *ControllerModePtr)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE(CanIf_Global.initRun, CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_UNINIT );
- VALIDATE(Controller < GET_CONTROLLER_CNT(), CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE(channel < CANIF_CHANNEL_CNT, CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_PARAM_CONTROLLER );
VALIDATE(ControllerModePtr != NULL, CANIF_GET_CONTROLLER_MODE_ID, CANIF_E_PARAM_POINTER );
- *ControllerModePtr = CanIf_Global.controllerData[Controller].ControllerMode;
+ *ControllerModePtr = CanIf_Global.channelData[channel].ControllerMode;
return E_OK;
}
return E_NOT_OK;
}
- uint8 controller = txEntry->CanIfCanTxPduHthRef->CanIfCanControllerIdRef;
+ CanIf_Arc_ChannelIdType channel = txEntry->CanIfCanTxPduHthRef->CanIfCanControllerIdRef;
// Get and verify the controller mode
- if (CanIf_GetControllerMode(controller, &csMode) == E_NOT_OK)
+ if (CanIf_GetControllerMode(channel, &csMode) == E_NOT_OK)
return E_NOT_OK;
if (csMode != CANIF_CS_STARTED) // CANIF_161
return E_NOT_OK;
// Get and verify the PDU channel mode control
- if (CanIf_GetPduMode(controller, &pduMode) == E_NOT_OK)
+ if (CanIf_GetPduMode(channel, &pduMode) == E_NOT_OK)
return E_NOT_OK;
if ((pduMode != CANIF_GET_TX_ONLINE) && (pduMode != CANIF_GET_ONLINE))
Std_ReturnType CanIf_SetPduMode(uint8 Controller,
CanIf_ChannelSetModeType PduModeRequest)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE( CanIf_Global.initRun, CANIF_SETPDUMODE_ID, CANIF_E_UNINIT );
- VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_SETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE( channel < CANIF_CHANNEL_CNT, CANIF_SETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
- CanIf_ChannelGetModeType oldMode = CanIf_Global.controllerData[Controller].ChannelMode;
+ CanIf_ChannelGetModeType oldMode = CanIf_Global.channelData[channel].PduMode;
switch(PduModeRequest)
{
case CANIF_SET_OFFLINE:
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;
break;
case CANIF_SET_RX_OFFLINE:
if (oldMode == CANIF_GET_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;
else if (oldMode == CANIF_GET_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;
// Other oldmodes don't care
break;
case CANIF_SET_RX_ONLINE:
if (oldMode == CANIF_GET_OFFLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;
else if (oldMode == CANIF_GET_TX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
// Other oldmodes don't care
break;
case CANIF_SET_TX_OFFLINE:
if (oldMode == CANIF_GET_TX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;
else if (oldMode == CANIF_GET_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;
// Other oldmodes don't care
break;
case CANIF_SET_TX_ONLINE:
if (oldMode == CANIF_GET_OFFLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;
else if (oldMode == CANIF_GET_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_TX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;
else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;
// Other oldmodes don't care
break;
case CANIF_SET_ONLINE:
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;
break;
case CANIF_SET_TX_OFFLINE_ACTIVE:
if (oldMode == CANIF_GET_OFFLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;
else if (oldMode == CANIF_GET_RX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
else if (oldMode == CANIF_GET_TX_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;
else if (oldMode == CANIF_GET_ONLINE)
- CanIf_Global.controllerData[Controller].ChannelMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
+ CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;
// Other oldmodes don't care
break;
Std_ReturnType CanIf_GetPduMode(uint8 Controller,
CanIf_ChannelGetModeType *PduModePtr)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE( CanIf_Global.initRun, CANIF_GETPDUMODE_ID, CANIF_E_UNINIT );
- VALIDATE( Controller < GET_CONTROLLER_CNT(), CANIF_GETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE( channel < CANIF_CHANNEL_CNT, CANIF_GETPDUMODE_ID, CANIF_E_PARAM_CONTROLLER );
- *PduModePtr = CanIf_Global.controllerData[Controller].ChannelMode;
+ *PduModePtr = CanIf_Global.channelData[channel].PduMode;
return E_OK;
}
}
// Check that this is a dymanic PDU
- if (txEntry->CanIfCanTxPduType != ECORE_PDU_TYPE_DYNAMIC)
+ if (txEntry->CanIfCanTxPduType != ARC_PDU_TYPE_DYNAMIC)
{
VALIDATE_NO_RV(FALSE, CANIF_SETDYNAMICTX_ID, CANIF_E_INVALID_TXPDUID);
return;
}
// Check that this is an extended or standard id
- if (((CanId & 0x80000000) && (txEntry->CanIfTxPduIdCanIdType == ECORE_CAN_ID_TYPE_29)) ||
- (((CanId & 0x80000000) == 0) && (txEntry->CanIfTxPduIdCanIdType == ECORE_CAN_ID_TYPE_11)))
+ if (((CanId & 0x80000000) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_29)) ||
+ (((CanId & 0x80000000) == 0) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_11)))
{
// Update the CanID
//txEntry->CanIfCanTxPduIdCanId = CanId; // TODO How do we fix this from a const pointer
/* Check PDU mode before continue processing */
CanIf_ChannelGetModeType mode;
- sint8 controller = CanIf_FindHrhCtrl(Hrh);
- if (controller == -1) // Invalid HRH
+ CanIf_Arc_ChannelIdType channel = CanIf_Arc_FindHrhChannel(Hrh);
+ if (channel == -1) // Invalid HRH
{
return;
}
- if (CanIf_GetPduMode(controller, &mode) == E_OK)
+ if (CanIf_GetPduMode(channel, &mode) == E_OK)
{
if (mode == CANIF_GET_OFFLINE || mode == CANIF_GET_TX_ONLINE ||
mode == CANIF_GET_OFFLINE_ACTIVE)
if (entry->CanIfCanRxPduHrhRef->CanIfHrhIdSymRef == Hrh)
{
// Software filtering
- if (entry->CanIfCanRxPduHrhRef->CanIfHrhType == CAN_ECORE_HANDLE_TYPE_BASIC)
+ if (entry->CanIfCanRxPduHrhRef->CanIfHrhType == CAN_ARC_HANDLE_TYPE_BASIC)
{
if (entry->CanIfCanRxPduHrhRef->CanIfSoftwareFilterHrh)
{
void CanIf_ControllerBusOff(uint8 Controller)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_CONTROLLER_BUSOFF_ID, CANIF_E_UNINIT );
- VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_CONTROLLER_BUSOFF_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE_NO_RV( Controller < CANIF_CHANNEL_CNT, CANIF_CONTROLLER_BUSOFF_ID, CANIF_E_PARAM_CONTROLLER );
// According to figure 35 in canif spec this should be done in
// Can driver but it is better to do it here
- CanIf_SetControllerMode(Controller, CANIF_CS_STOPPED);
+ CanIf_SetControllerMode(channel, CANIF_CS_STOPPED);
if (CanIf_ConfigPtr->DispatchConfig->CanIfBusOffNotification != NULL)
{
- CanIf_ConfigPtr->DispatchConfig->CanIfBusOffNotification(Controller);
+ CanIf_ConfigPtr->DispatchConfig->CanIfBusOffNotification(channel);
}
}
void CanIf_SetWakeupEvent(uint8 Controller)
{
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
VALIDATE_NO_RV(FALSE, CANIF_SETWAKEUPEVENT_ID, CANIF_E_NOK_NOSUPPORT);
VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_SETWAKEUPEVENT_ID, CANIF_E_UNINIT );
- VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_SETWAKEUPEVENT_ID, CANIF_E_PARAM_CONTROLLER );
+ VALIDATE_NO_RV( channel < CANIF_CHANNEL_CNT, CANIF_SETWAKEUPEVENT_ID, CANIF_E_PARAM_CONTROLLER );
// Not supported
}
-void CanIf_EcoreError(uint8 Controller, Can_EcoreErrorType Error)
+void CanIf_Arc_Error(uint8 Controller, Can_Arc_ErrorType Error)
{
- VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_ECOREERROR_ID, CANIF_E_UNINIT );
- VALIDATE_NO_RV( Controller < GET_CONTROLLER_CNT(), CANIF_ECOREERROR_ID, CANIF_E_PARAM_CONTROLLER );
+ // We call this a CanIf channel. Hopefully makes it easier to follow.
+ CanIf_Arc_ChannelIdType channel = Controller;
+
+ VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_ARCERROR_ID, CANIF_E_UNINIT );
+ VALIDATE_NO_RV( channel < CANIF_CHANNEL_CNT, CANIF_ARCERROR_ID, CANIF_E_PARAM_CONTROLLER );
if (CanIf_ConfigPtr->DispatchConfig->CanIfErrorNotificaton != NULL)
{
\r
const Com_ConfigType * ComConfig;\r
\r
-ComEcoreIPdu_type ComEcoreIPdu[COM_MAX_NR_IPDU];\r
-ComEcoreSignal_type ComEcoreSignal[COM_MAX_NR_SIGNAL];\r
-ComEcoreGroupSignal_type ComEcoreGroupSignal[COM_MAX_NR_GROUPSIGNAL];\r
-\r
-ComEcoreConfig_type ComEcoreConfig = {\r
- .ComIPdu = ComEcoreIPdu,\r
- .ComSignal = ComEcoreSignal,\r
- .ComGroupSignal = ComEcoreGroupSignal\r
+Com_Arc_IPdu_type Com_Arc_IPdu[COM_MAX_NR_IPDU];\r
+Com_Arc_Signal_type Com_Arc_Signal[COM_MAX_NR_SIGNAL];\r
+Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_MAX_NR_GROUPSIGNAL];\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = Com_Arc_GroupSignal\r
};\r
\r
\r
uint32 earliestDeadline;\r
uint32 firstTimeout;\r
\r
- ComEcoreConfig.OutgoingPdu.SduDataPtr = malloc(8);\r
+ Com_Arc_Config.OutgoingPdu.SduDataPtr = malloc(8);\r
\r
// Initialize each IPdu\r
//ComIPdu_type *IPdu;\r
- //ComEcoreIPdu_type *EcoreIPdu;\r
+ //Com_Arc_IPdu_type *Arc_IPdu;\r
const ComSignal_type *Signal;\r
const ComGroupSignal_type *GroupSignal;\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
- ComEcoreConfig.ComNIPdu++;\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
+ Com_Arc_Config.ComNIPdu++;\r
\r
ComGetIPdu(i);\r
- ComGetEcoreIPdu(i);\r
+ ComGetArcIPdu(i);\r
\r
if (i >= COM_MAX_NR_IPDU) {\r
DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_TOO_MANY_IPDU);\r
// If this is a TX and cyclic IPdu, configure the first deadline.\r
if (IPdu->ComIPduDirection == SEND &&\r
(IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC || IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED)) {\r
- //IPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
+ //IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
}\r
\r
\r
firstTimeout = -1;\r
\r
// Reserve memory for all defined signals.\r
- EcoreIPdu->ComIPduDataPtr = malloc(IPdu->ComIPduSize);\r
- if (EcoreIPdu->ComIPduDataPtr == NULL) {\r
+ Arc_IPdu->ComIPduDataPtr = malloc(IPdu->ComIPduSize);\r
+ if (Arc_IPdu->ComIPduDataPtr == NULL) {\r
failure = 1;\r
}\r
\r
// Initialize the memory with the default value.\r
if (IPdu->ComIPduDirection == SEND) {\r
- memset(EcoreIPdu->ComIPduDataPtr, IPdu->ComTxIPdu.ComTxIPduUnusedAreasDefault, IPdu->ComIPduSize);\r
+ memset(Arc_IPdu->ComIPduDataPtr, IPdu->ComTxIPdu.ComTxIPduUnusedAreasDefault, IPdu->ComIPduSize);\r
}\r
\r
// For each signal in this PDU.\r
for (int j = 0; IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
Signal = IPdu->ComIPduSignalRef[j];\r
- ComGetEcoreSignal(Signal->ComHandleId);\r
+ ComGetArcSignal(Signal->ComHandleId);\r
\r
// If this signal already has been configured this is most likely an error.\r
- if (EcoreSignal->ComIPduDataPtr != NULL) {\r
+ if (Arc_Signal->ComIPduDataPtr != NULL) {\r
DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_SIGNAL_CONFIGURATION);\r
failure = 1;\r
}\r
// Configure signal deadline monitoring if used.\r
if (Signal->ComTimeoutFactor > 0) {\r
\r
- if (Signal->ComSignalEcoreUseUpdateBit) {\r
+ if (Signal->ComSignalArcUseUpdateBit) {\r
// This signal uses an update bit, and hence has its own deadline monitoring.\r
- EcoreSignal->ComEcoreDeadlineCounter = Signal->ComFirstTimeoutFactor; // Configure the deadline counter\r
- EcoreSignal->ComTimeoutFactor = Signal->ComTimeoutFactor;\r
+ Arc_Signal->Com_Arc_DeadlineCounter = Signal->ComFirstTimeoutFactor; // Configure the deadline counter\r
+ Arc_Signal->ComTimeoutFactor = Signal->ComTimeoutFactor;\r
\r
} else {\r
// This signal does not use an update bit, and should therefore use per I-PDU deadline monitoring.\r
}\r
\r
// Increment helper counters\r
- EcoreIPdu->NComIPduSignalRef = j + 1;\r
+ Arc_IPdu->NComIPduSignalRef = j + 1;\r
\r
- //IPdu->ComEcoreNIPduSignalGroupRef = j + 1;\r
+ //IPdu->Com_Arc_NIPduSignalGroupRef = j + 1;\r
\r
- EcoreSignal->ComIPduDataPtr = EcoreIPdu->ComIPduDataPtr;\r
- EcoreSignal->ComIPduHandleId = i;\r
+ Arc_Signal->ComIPduDataPtr = Arc_IPdu->ComIPduDataPtr;\r
+ Arc_Signal->ComIPduHandleId = i;\r
\r
// Clear update bits\r
- if (Signal->ComSignalEcoreUseUpdateBit) {\r
- clearBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ if (Signal->ComSignalArcUseUpdateBit) {\r
+ clearBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
// If this signal is a signal group\r
- if (Signal->ComEcoreIsSignalGroup) {\r
- EcoreSignal->ComEcoreShadowBuffer = malloc(IPdu->ComIPduSize);\r
+ if (Signal->Com_Arc_IsSignalGroup) {\r
+ Arc_Signal->Com_Arc_ShadowBuffer = malloc(IPdu->ComIPduSize);\r
\r
- if (EcoreSignal->ComEcoreShadowBuffer == NULL) {\r
+ if (Arc_Signal->Com_Arc_ShadowBuffer == NULL) {\r
failure = 1;\r
}\r
\r
// For each group signal of this signal group.\r
for(int h = 0; Signal->ComGroupSignal[h] != NULL; h++) {\r
GroupSignal = Signal->ComGroupSignal[h];\r
- ComGetEcoreGroupSignal(GroupSignal->ComHandleId);\r
+ ComGetArcGroupSignal(GroupSignal->ComHandleId);\r
// Set pointer to shadow buffer\r
- EcoreGroupSignal->ComEcoreShadowBuffer = EcoreSignal->ComEcoreShadowBuffer;\r
+ Arc_GroupSignal->Com_Arc_ShadowBuffer = Arc_Signal->Com_Arc_ShadowBuffer;\r
// Initialize group signal data.\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, &GroupSignal->ComSignalInitValue, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, &GroupSignal->ComSignalInitValue, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
}\r
\r
} else {\r
// Initialize signal data.\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, &Signal->ComSignalInitValue, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, &Signal->ComSignalInitValue, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
}\r
\r
// Check filter configuration\r
// Configure per I-PDU based deadline monitoring.\r
for (int j = 0; IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
Signal = IPdu->ComIPduSignalRef[j];\r
- ComGetEcoreSignal(Signal->ComHandleId);\r
+ ComGetArcSignal(Signal->ComHandleId);\r
\r
- if (Signal->ComTimeoutFactor > 0 && !Signal->ComSignalEcoreUseUpdateBit) {\r
- EcoreSignal->ComTimeoutFactor = earliestDeadline;\r
- EcoreSignal->ComEcoreDeadlineCounter = firstTimeout;\r
+ if (Signal->ComTimeoutFactor > 0 && !Signal->ComSignalArcUseUpdateBit) {\r
+ Arc_Signal->ComTimeoutFactor = earliestDeadline;\r
+ Arc_Signal->Com_Arc_DeadlineCounter = firstTimeout;\r
}\r
}\r
}\r
// An error occurred.\r
if (failure) {\r
// Free allocated memory\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
// Release memory for all defined signals.\r
//free(ComConfig->ComIPdu[i].ComIPduDataPtr);\r
}\r
}\r
\r
void Com_IpduGroupStart(Com_PduGroupIdType IpduGroupId,boolean Initialize) {\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
- ComEcoreConfig.ComIPdu[i].ComEcoreIpduStarted = 1;\r
+ Com_Arc_Config.ComIPdu[i].Com_Arc_IpduStarted = 1;\r
}\r
}\r
}\r
\r
void Com_IpduGroupStop(Com_PduGroupIdType IpduGroupId) {\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
- ComEcoreConfig.ComIPdu[i].ComEcoreIpduStarted = 0;\r
+ Com_Arc_Config.ComIPdu[i].Com_Arc_IpduStarted = 0;\r
}\r
}\r
}\r
typedef struct {\r
- uint32 ComFilterEcoreN;\r
- uint32 ComFilterEcoreNewValue;\r
- uint32 ComFilterEcoreOldValue;\r
-} ComEcoreFilter_type;\r
+ uint32 ComFilterArcN;\r
+ uint32 ComFilterArcNewValue;\r
+ uint32 ComFilterArcOldValue;\r
+} Com_Arc_Filter_type;\r
\r
typedef struct {\r
\r
- ComEcoreFilter_type ComFilter;\r
+ Com_Arc_Filter_type ComFilter;\r
\r
- uint32 ComEcoreDeadlineCounter;\r
+ uint32 Com_Arc_DeadlineCounter;\r
uint32 ComTimeoutFactor;\r
void *ComIPduDataPtr;\r
\r
uint8 ComIPduHandleId;\r
uint8 ComSignalUpdated;\r
- //uint8 ComEcoreEOL;\r
- //uint8 ComEcoreIsSignalGroup;\r
+ //uint8 Com_Arc_EOL;\r
+ //uint8 Com_Arc_IsSignalGroup;\r
\r
/* For signal groups */\r
- void *ComEcoreShadowBuffer;\r
+ void *Com_Arc_ShadowBuffer;\r
\r
-} ComEcoreSignal_type;\r
+} Com_Arc_Signal_type;\r
\r
\r
typedef struct {\r
- void *ComEcoreShadowBuffer;\r
+ void *Com_Arc_ShadowBuffer;\r
//uint8 ComIPduHandleId;\r
\r
uint8 ComSignalUpdated;\r
- uint8 ComEcoreEOL;\r
-} ComEcoreGroupSignal_type;\r
+ uint8 Com_Arc_EOL;\r
+} Com_Arc_GroupSignal_type;\r
\r
\r
/*\r
typedef struct {\r
- void *ComEcoreShadowBuffer;\r
- void *ComEcoreIPduDataPtr;\r
- uint8 ComEcoreEOL;\r
-} ComEcoreSignalGroup_type;\r
+ void *Com_Arc_ShadowBuffer;\r
+ void *Com_Arc_IPduDataPtr;\r
+ uint8 Com_Arc_EOL;\r
+} Com_Arc_SignalGroup_type;\r
*/\r
\r
typedef struct {\r
uint32 ComTxModeRepetitionPeriodTimer;\r
uint32 ComTxIPduMinimumDelayTimer;\r
uint32 ComTxModeTimePeriodTimer;\r
-} ComEcoreTxIPduTimer_type;\r
+} Com_Arc_TxIPduTimer_type;\r
\r
typedef struct {\r
\r
- ComEcoreTxIPduTimer_type ComEcoreTxIPduTimers;\r
+ Com_Arc_TxIPduTimer_type Com_Arc_TxIPduTimers;\r
void *ComIPduDataPtr;\r
\r
- uint8 ComEcoreNIPduSignalGroupRef;\r
+ uint8 Com_Arc_NIPduSignalGroupRef;\r
\r
uint8 NComIPduSignalRef;\r
\r
- uint8 ComEcoreIpduStarted;\r
+ uint8 Com_Arc_IpduStarted;\r
\r
-} ComEcoreIPdu_type;\r
+} Com_Arc_IPdu_type;\r
\r
typedef struct {\r
uint16 ComNIPdu;\r
- ComEcoreIPdu_type *ComIPdu; // Only used in PduIdCheck()\r
- //ComEcoreIPduGroup_type *ComIPduGroup;\r
- ComEcoreSignal_type *ComSignal;\r
- //ComEcoreSignalGroup_type *ComSignalGroup;\r
- ComEcoreGroupSignal_type *ComGroupSignal;\r
+ Com_Arc_IPdu_type *ComIPdu; // Only used in PduIdCheck()\r
+ //Com_Arc_IPduGroup_type *ComIPduGroup;\r
+ Com_Arc_Signal_type *ComSignal;\r
+ //Com_Arc_SignalGroup_type *ComSignalGroup;\r
+ Com_Arc_GroupSignal_type *ComGroupSignal;\r
PduInfoType OutgoingPdu;\r
-} ComEcoreConfig_type;\r
+} Com_Arc_Config_type;\r
COM_VALIDATE_SIGNAL(SignalId, 0x0a, E_NOT_OK);\r
// Store pointer to signal for easier coding.\r
ComGetSignal(SignalId);\r
- ComGetEcoreSignal(SignalId);\r
- ComGetIPdu(EcoreSignal->ComIPduHandleId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetArcSignal(SignalId);\r
+ ComGetIPdu(Arc_Signal->ComIPduHandleId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
//DEBUG(DEBUG_LOW, "Com_SendSignal: id %d, nBytes %d, BitPosition %d, intVal %d\n", SignalId, nBytes, signal->ComBitPosition, (uint32)*(uint8 *)SignalDataPtr);\r
\r
\r
}\r
\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, dataPtr, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, dataPtr, Signal->ComBitSize, Signal->ComBitPosition, 0);\r
\r
// If the signal has an update bit. Set it!\r
- if (Signal->ComSignalEcoreUseUpdateBit) {\r
- setBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ if (Signal->ComSignalArcUseUpdateBit) {\r
+ setBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
/*\r
* If signal has triggered transmit property, trigger a transmission!\r
*/\r
if (Signal->ComTransferProperty == TRIGGERED) {\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
}\r
return E_OK;\r
}\r
* COM395: This function must override the IPdu callouts used in Com_TriggerIPduTransmit();\r
*/\r
ComGetIPdu(ComTxPduId);\r
- ComGetEcoreIPdu(ComTxPduId);\r
+ ComGetArcIPdu(ComTxPduId);\r
\r
- memcpy(SduPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ memcpy(SduPtr, Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
return E_OK;\r
}\r
\r
\r
//DEBUG(DEBUG_MEDIUM, "Com_TriggerIPduSend sending IPdu %d... ", ComTxPduId);\r
ComGetIPdu(ComTxPduId);\r
- ComGetEcoreIPdu(ComTxPduId);\r
+ ComGetArcIPdu(ComTxPduId);\r
\r
// Is the IPdu ready for transmission?\r
- if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
//DEBUG(DEBUG_MEDIUM, "success!\n", ComTxPduId);\r
\r
/*\r
.SduDataPtr = malloc(IPdu->ComIPduSize),\r
.SduLength = ComConfig->ComIPdu[ComTxPduId].ComIPduSize\r
};\r
- memcpy((void *)PduInfoPackage.SduDataPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ memcpy((void *)PduInfoPackage.SduDataPtr, Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
*/\r
\r
- ComEcoreConfig.OutgoingPdu.SduLength = ComConfig->ComIPdu[ComTxPduId].ComIPduSize;\r
- memcpy((void *)ComEcoreConfig.OutgoingPdu.SduDataPtr, EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
+ Com_Arc_Config.OutgoingPdu.SduLength = ComConfig->ComIPdu[ComTxPduId].ComIPduSize;\r
+ memcpy((void *)Com_Arc_Config.OutgoingPdu.SduDataPtr, Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
// Check callout status\r
if (IPdu->ComIPduCallout != NULL) {\r
- if (!IPdu->ComIPduCallout(ComTxPduId, EcoreIPdu->ComIPduDataPtr)) {\r
+ if (!IPdu->ComIPduCallout(ComTxPduId, Arc_IPdu->ComIPduDataPtr)) {\r
// TODO Report error to DET.\r
// Det_ReportError();\r
return;\r
}\r
\r
// Send IPdu!\r
- if (PduR_ComTransmit(ComTxPduId, &ComEcoreConfig.OutgoingPdu) == E_OK) {\r
+ if (PduR_ComTransmit(ComTxPduId, &Com_Arc_Config.OutgoingPdu) == E_OK) {\r
// Clear all update bits for the contained signals\r
- for (int i = 0; i < EcoreIPdu->NComIPduSignalRef; i++) {\r
- if (IPdu->ComIPduSignalRef[i]->ComSignalEcoreUseUpdateBit) {\r
- clearBit(EcoreIPdu->ComIPduDataPtr, IPdu->ComIPduSignalRef[i]->ComUpdateBitPosition);\r
+ for (int i = 0; i < Arc_IPdu->NComIPduSignalRef; i++) {\r
+ if (IPdu->ComIPduSignalRef[i]->ComSignalArcUseUpdateBit) {\r
+ clearBit(Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSignalRef[i]->ComUpdateBitPosition);\r
}\r
}\r
}\r
//free(PduInfoPackage.SduDataPtr);\r
\r
// Reset miminum delay timer.\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer = IPdu->ComTxIPdu.ComTxIPduMinimumDelayFactor;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer = IPdu->ComTxIPdu.ComTxIPduMinimumDelayFactor;\r
\r
} else {\r
//DEBUG(DEBUG_MEDIUM, "failed (MDT)!\n", ComTxPduId);\r
PduIdCheck(ComRxPduId, 0x14, E_NOT_OK);\r
\r
ComGetIPdu(ComRxPduId);\r
- ComGetEcoreIPdu(ComRxPduId);\r
+ ComGetArcIPdu(ComRxPduId);\r
\r
// If Ipdu is stopped\r
- if (!EcoreIPdu->ComEcoreIpduStarted) {\r
+ if (!Arc_IPdu->Com_Arc_IpduStarted) {\r
return E_OK;\r
}\r
\r
}\r
\r
// Copy IPDU data\r
- memcpy(EcoreIPdu->ComIPduDataPtr, SduPtr, IPdu->ComIPduSize);\r
+ memcpy(Arc_IPdu->ComIPduDataPtr, SduPtr, IPdu->ComIPduSize);\r
\r
// For each signal.\r
const ComSignal_type *signal;\r
for (int i = 0; IPdu->ComIPduSignalRef[i] != NULL; i++) {\r
signal = IPdu->ComIPduSignalRef[i];\r
- ComGetEcoreSignal(signal->ComHandleId);\r
+ ComGetArcSignal(signal->ComHandleId);\r
\r
// If this signal uses an update bit, then it is only considered if this bit is set.\r
- if (!signal->ComSignalEcoreUseUpdateBit ||\r
- (signal->ComSignalEcoreUseUpdateBit && testBit(EcoreIPdu->ComIPduDataPtr, signal->ComUpdateBitPosition))) {\r
+ if (!signal->ComSignalArcUseUpdateBit ||\r
+ (signal->ComSignalArcUseUpdateBit && testBit(Arc_IPdu->ComIPduDataPtr, signal->ComUpdateBitPosition))) {\r
\r
if (signal->ComTimeoutFactor > 0) { // If reception deadline monitoring is used.\r
// Reset the deadline monitoring timer.\r
- EcoreSignal->ComEcoreDeadlineCounter = signal->ComTimeoutFactor;\r
+ Arc_Signal->Com_Arc_DeadlineCounter = signal->ComTimeoutFactor;\r
}\r
\r
/*\r
// Zero new filter value.\r
- IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterEcoreNewValue = 0;\r
+ IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterArcNewValue = 0;\r
\r
//Fix this!!!\r
- Com_CopyFromSignal(IPdu->ComIPduSignalRef[i], &IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterEcoreNewValue);\r
+ Com_CopyFromSignal(IPdu->ComIPduSignalRef[i], &IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterArcNewValue);\r
*/\r
// Perform filtering\r
//if (Com_Filter(IPdu->ComIPduSignalRef[i])) {\r
\r
} else {\r
// Signal processing mode is DEFERRED, mark the signal as updated.\r
- EcoreSignal->ComSignalUpdated = 1;\r
+ Arc_Signal->ComSignalUpdated = 1;\r
}\r
//}\r
} else {\r
Std_ReturnType Com_SendSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
//#warning Com_SendSignalGroup should be performed atomically. Should we disable interrupts here?\r
ComGetSignal(SignalGroupId);\r
- ComGetEcoreSignal(SignalGroupId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
- ComGetIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetArcSignal(SignalGroupId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ ComGetIPdu(Arc_Signal->ComIPduHandleId);\r
\r
\r
// Copy shadow buffer to Ipdu data space\r
const ComGroupSignal_type *groupSignal;\r
for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
groupSignal = Signal->ComGroupSignal[i];\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, EcoreSignal->ComEcoreShadowBuffer, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, Arc_Signal->Com_Arc_ShadowBuffer, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
}\r
\r
// If the signal has an update bit. Set it!\r
- if (Signal->ComSignalEcoreUseUpdateBit) {\r
- setBit(EcoreIPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ if (Signal->ComSignalArcUseUpdateBit) {\r
+ setBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
/*\r
* If signal has triggered transmit property, trigger a transmission!\r
*/\r
if (Signal->ComTransferProperty == TRIGGERED) {\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeNumberOfRepetitions + 1;\r
}\r
\r
return E_OK;\r
Std_ReturnType Com_ReceiveSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
//#warning Com_ReceiveSignalGroup should be performed atomically. Should we disable interrupts here?\r
ComGetSignal(SignalGroupId);\r
- ComGetEcoreSignal(SignalGroupId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetArcSignal(SignalGroupId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Copy Ipdu data buffer to shadow buffer.\r
const ComGroupSignal_type *groupSignal;\r
for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
groupSignal = Signal->ComGroupSignal[i];\r
- Com_CopyData(EcoreSignal->ComEcoreShadowBuffer, EcoreIPdu->ComIPduDataPtr, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
+ Com_CopyData(Arc_Signal->Com_Arc_ShadowBuffer, Arc_IPdu->ComIPduDataPtr, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
}\r
\r
\r
\r
void Com_UpdateShadowSignal(Com_SignalIdType SignalId, const void *SignalDataPtr) {\r
ComGetGroupSignal(SignalId);\r
- ComGetEcoreGroupSignal(SignalId);\r
- Com_CopyData(EcoreGroupSignal->ComEcoreShadowBuffer, SignalDataPtr, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
+ ComGetArcGroupSignal(SignalId);\r
+ Com_CopyData(Arc_GroupSignal->Com_Arc_ShadowBuffer, SignalDataPtr, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
}\r
\r
void Com_ReceiveShadowSignal(Com_SignalIdType SignalId, void *SignalDataPtr) {\r
ComGetGroupSignal(SignalId);\r
- ComGetEcoreGroupSignal(SignalId);\r
- Com_CopyData(SignalDataPtr, EcoreGroupSignal->ComEcoreShadowBuffer, GroupSignal->ComBitSize, 0, GroupSignal->ComBitPosition);\r
+ ComGetArcGroupSignal(SignalId);\r
+ Com_CopyData(SignalDataPtr, Arc_GroupSignal->Com_Arc_ShadowBuffer, GroupSignal->ComBitSize, 0, GroupSignal->ComBitPosition);\r
}\r
void Com_MainFunctionRx() {\r
//DEBUG(DEBUG_MEDIUM, "Com_MainFunctionRx() excecuting\n");\r
const ComSignal_type *signal;\r
- for (int i = 0; !ComConfig->ComSignal[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComSignal[i].Com_Arc_EOL; i++) {\r
signal = &ComConfig->ComSignal[i];\r
- ComGetEcoreSignal(signal->ComHandleId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
+ ComGetArcSignal(signal->ComHandleId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Monitor signal reception deadline\r
- if (EcoreIPdu->ComEcoreIpduStarted && EcoreSignal->ComTimeoutFactor > 0) {\r
+ if (Arc_IPdu->Com_Arc_IpduStarted && Arc_Signal->ComTimeoutFactor > 0) {\r
\r
// Decrease deadline monitoring timer.\r
- timerDec(EcoreSignal->ComEcoreDeadlineCounter);\r
+ timerDec(Arc_Signal->Com_Arc_DeadlineCounter);\r
\r
// Check if a timeout has occurred.\r
- if (EcoreSignal->ComEcoreDeadlineCounter == 0) {\r
+ if (Arc_Signal->Com_Arc_DeadlineCounter == 0) {\r
if (signal->ComRxDataTimeoutAction == COM_TIMEOUT_DATA_ACTION_REPLACE) {\r
// Replace signal data.\r
uint32 signalInitData;\r
memset(&signalInitData, signal->ComSignalInitValue, sizeof(uint32));\r
\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, &signalInitData, signal->ComBitSize, signal->ComBitPosition, 0);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, &signalInitData, signal->ComBitSize, signal->ComBitPosition, 0);\r
\r
}\r
\r
}\r
\r
// Restart timer\r
- EcoreSignal->ComEcoreDeadlineCounter = EcoreSignal->ComTimeoutFactor;\r
+ Arc_Signal->Com_Arc_DeadlineCounter = Arc_Signal->ComTimeoutFactor;\r
}\r
}\r
\r
- if (EcoreSignal->ComSignalUpdated) {\r
+ if (Arc_Signal->ComSignalUpdated) {\r
ComConfig->ComSignal[i].ComNotification();\r
- EcoreSignal->ComSignalUpdated = 0;\r
+ Arc_Signal->ComSignalUpdated = 0;\r
}\r
}\r
}\r
//DEBUG(DEBUG_MEDIUM, "Com_MainFunctionTx() excecuting\n");\r
// Decrease timers.\r
const ComIPdu_type *IPdu;\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
IPdu = &ComConfig->ComIPdu[i];\r
- ComGetEcoreIPdu(i);\r
+ ComGetArcIPdu(i);\r
\r
// Is this a IPdu that should be transmitted?\r
- if (IPdu->ComIPduDirection == SEND && EcoreIPdu->ComEcoreIpduStarted) {\r
+ if (IPdu->ComIPduDirection == SEND && Arc_IPdu->Com_Arc_IpduStarted) {\r
// Decrease minimum delay timer\r
- timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer);\r
+ timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer);\r
\r
// If IPDU has periodic or mixed transmission mode.\r
if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC\r
|| IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED) {\r
\r
- timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer);\r
+ timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer);\r
\r
// Is it time for a direct transmission?\r
if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED\r
- && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
+ && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
\r
- timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
+ timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
\r
// Is it time for a transmission?\r
- if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer == 0\r
- && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0\r
+ && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
\r
Com_TriggerIPduSend(IPdu->ComIPduRxHandleId);\r
\r
// Reset periodic timer\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
\r
// Register this nth-transmission.\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
}\r
}\r
\r
// Is it time for a cyclic transmission?\r
- if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer == 0 && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer == 0 && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
\r
Com_TriggerIPduSend(IPdu->ComIPduRxHandleId); // Send IPDU!\r
\r
// Reset periodic timer.\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimePeriodFactor;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimePeriodFactor;\r
}\r
\r
// If IPDU has direct transmission mode.\r
} else if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == DIRECT) {\r
// Do we need to transmit anything?\r
- if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
- timerDec(EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
+ if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
+ timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
\r
// Is it time for a transmission?\r
- if (EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer == 0 && EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0 && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
Com_TriggerIPduSend(IPdu->ComIPduRxHandleId);\r
\r
// Reset periodic timer\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeRepetitionPeriodFactor;\r
\r
// Register this nth-transmission.\r
- EcoreIPdu->ComEcoreTxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
+ Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft--;\r
}\r
}\r
\r
\r
// Send scheduled packages.\r
// Cyclic\r
- for (int i = 0; !ComConfig->ComIPdu[i].ComEcoreEOL; i++) {\r
+ for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
if (ComConfig->ComIPdu[i].ComIPduDirection == SEND) {\r
\r
}\r
uint8 destByte;\r
\r
// Pointer to a byte of the source and dest respectively.\r
- ComGetEcoreSignal(signal->ComHandleId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
- uint8 *source = (uint8 *)EcoreIPdu->ComIPduDataPtr;\r
+ ComGetArcSignal(signal->ComHandleId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ uint8 *source = (uint8 *)Arc_IPdu->ComIPduDataPtr;\r
uint8 *dest = (uint8 *)Destination;\r
\r
uint8 signBit = 0;\r
\r
\r
void Com_CopyToSignal(ComSignal_type *signal, const void *Source) {\r
- ComGetEcoreSignal(signal->ComHandleId);\r
- ComGetEcoreIPdu(EcoreSignal->ComIPduHandleId);\r
- Com_CopyData(EcoreIPdu->ComIPduDataPtr, Source, signal->ComBitSize, signal->ComBitPosition, 0);\r
+ ComGetArcSignal(signal->ComHandleId);\r
+ ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ Com_CopyData(Arc_IPdu->ComIPduDataPtr, Source, signal->ComBitSize, signal->ComBitPosition, 0);\r
}\r
\r
uint8 Com_CopyData(void *Destination, const void *Source, uint8 numBits, uint8 destOffset, uint8 sourceOffset) {\r
\r
\r
uint8 Com_Filter(ComSignal_type *signal) {\r
- ComGetEcoreSignal(signal->ComHandleId);\r
+ ComGetArcSignal(signal->ComHandleId);\r
const ComFilter_type * filter = &signal->ComFilter;\r
uint8 success = 0;\r
if (filter->ComFilterAlgorithm == ALWAYS) {\r
success = filter->ComFilterPeriodFactor;\r
\r
} else {\r
- if (filter->ComFilterEcoreN == 0) {\r
+ if (filter->ComFilterArcN == 0) {\r
success = 1;\r
} else {\r
success = 0;\r
}\r
- EcoreSignal->ComFilter.ComFilterEcoreN++;\r
- if (filter->ComFilterEcoreN >= filter->ComFilterPeriodFactor) {\r
- EcoreSignal->ComFilter.ComFilterEcoreN = 0;\r
+ Arc_Signal->ComFilter.ComFilterArcN++;\r
+ if (filter->ComFilterArcN >= filter->ComFilterPeriodFactor) {\r
+ Arc_Signal->ComFilter.ComFilterArcN = 0;\r
}\r
}\r
\r
} else if (filter->ComFilterAlgorithm == NEW_IS_OUTSIDE) {\r
- if ((filter->ComFilterMin > filter->ComFilterEcoreNewValue)\r
- || (filter->ComFilterEcoreNewValue > filter->ComFilterMax)) {\r
+ if ((filter->ComFilterMin > filter->ComFilterArcNewValue)\r
+ || (filter->ComFilterArcNewValue > filter->ComFilterMax)) {\r
success = 1;\r
} else {\r
success = 0;\r
\r
\r
} else if (filter->ComFilterAlgorithm == NEW_IS_WITHIN) {\r
- if (filter->ComFilterMin <= filter->ComFilterEcoreNewValue\r
- && filter->ComFilterEcoreNewValue <= filter->ComFilterMax) {\r
+ if (filter->ComFilterMin <= filter->ComFilterArcNewValue\r
+ && filter->ComFilterArcNewValue <= filter->ComFilterMax) {\r
success = 1;\r
} else {\r
success = 0;\r
\r
\r
} else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_MASKED_OLD) {\r
- if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask)\r
- != (filter->ComFilterEcoreNewValue & filter->ComFilterMask)) {\r
+ if ((filter->ComFilterArcNewValue & filter->ComFilterMask)\r
+ != (filter->ComFilterArcNewValue & filter->ComFilterMask)) {\r
success = 1;\r
} else {\r
success = 0;\r
}\r
\r
} else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_X) {\r
- if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask) != filter->ComFilterX) {\r
+ if ((filter->ComFilterArcNewValue & filter->ComFilterMask) != filter->ComFilterX) {\r
success = 1;\r
} else {\r
success = 0;\r
}\r
\r
} else if (filter->ComFilterAlgorithm == MASKED_NEW_EQUALS_X) {\r
- if ((filter->ComFilterEcoreNewValue & filter->ComFilterMask) == filter->ComFilterX) {\r
+ if ((filter->ComFilterArcNewValue & filter->ComFilterMask) == filter->ComFilterX) {\r
success = 1;\r
} else {\r
success = 0;\r
}\r
\r
if (success) {\r
- EcoreSignal->ComFilter.ComFilterEcoreOldValue = filter->ComFilterEcoreNewValue;\r
+ Arc_Signal->ComFilter.ComFilterArcOldValue = filter->ComFilterArcNewValue;\r
return 1;\r
} else return 0;\r
}\r
int bufferNr = 0;\r
int i = 0;\r
PduRRoutingPath_type *path;\r
- for (i = 0; !PduRConfig->PduRRoutingTable->PduRRoutingPath[i].PduREcoreEOL && !failed; i++) {\r
+ for (i = 0; !PduRConfig->PduRRoutingTable->PduRRoutingPath[i].PduR_Arc_EOL && !failed; i++) {\r
PduRConfig->PduRRoutingTable->NRoutingPaths++;\r
path = &PduRConfig->PduRRoutingTable->PduRRoutingPath[i];\r
\r
\r
typedef struct {\r
/*\r
- * Not part of autosar standard. Added by Ecore.
+ * Not part of autosar standard. Added by ArcCore.
*/\r
int BufferId;\r
PduR_DataProvisionType BufferType;\r
\r
\r
typedef struct {\r
- uint8 PduREcoreDummy; // Needed in order to compile without errors.\r
+ uint8 PduR_Arc_Dummy; // Needed in order to compile without errors.\r
PduRDefaultValueElement_type *PduRDefaultValueElement;\r
} PduRDefaultValue_type;\r
\r
* Not part of standard
*/\r
PduR_FctPtrType *FctPtrs;\r
- uint8 PduREcoreEOL;\r
+ uint8 PduR_Arc_EOL;\r
uint8 PduR_GatewayMode;\r
\r
/*\r
+++ /dev/null
-\r
-\r
-obj-y += xfls_test.o\r
-obj-y += lin_test.o\r
-\r
-VPATH += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/source\r
-inc-y += $(ROOTDIR)/arch/$(ARCH)/delivery/mpc5500_h7f/include\r
-\r
-\r
-#linkfile\r
-ldcmdfile-$(CFG_ARCH_ppc55xx) = -T $(ROOTDIR)/arch/$(ARCH)/scripts/linkscript_gcc.ldf\r
-\r
-build-exe-y = ../../../$(target)_$(ARCH).$(TE)\r
-\r
-\r
-\r
-\r
-INCLUDE = $(ROOTDIR)/include\r
-DRIVER_INCLUDE = $(ROOTDIR)/drivers/include\r
-TYPEDEFS_INCLUDE = $(ROOTDIR)/arch/ppc55xx/drivers\r
-BOARD_INCLUDE = $(ROOTDIR)/boards/mpc5516it/config\r
-DEM_INCLUDE = $(ROOTDIR)/drivers/Dem\r
-\r
-gcc -I$(INCLUDE) -I$(DRIVER_INCLUDE) -I$(TYPEDEFS_INCLUDE) -I$(BOARD_INCLUDE) -I$(DEM_INCLUDE) -o$(ROOTDIR)/drivers/PduR/PduR $(ROOTDIR)/drivers/Det/Det.c $(ROOTDIR)/drivers/PduR/PduR_PbCfg.c $(ROOTDIR)/drivers/PduR/PduR_Com.c $(ROOTDIR)/drivers/PduR/PduR_CanIf.c $(ROOTDIR)/drivers/PduR/PduR_LinIf.c $(ROOTDIR)/drivers/PduR/PduR_Ipdum.c $(ROOTDIR)/drivers/PduR/PduR.c $(ROOTDIR)/drivers/PduR/PduR_Test.c\r
\r
\r
static uint8 index[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\r
-#define SINE_TABLE_SIZE 38\r
+#define SINE_TABLE_SIZE 39
const Pwm_PeriodType sine_table[SINE_TABLE_SIZE] = {0x4a03, 0x53c6, 0x5d0e, 0x659e, 0x6d41, 0x73c6,\r
0x7906, 0x7cde, 0x7f36, 0x7fff, 0x7f36, 0x7cde, 0x7906, 0x73c6,\r
0x6d41, 0x659e, 0x5d0e, 0x53c6, 0x4a03, 0x4000, 0x35fc, 0x2c39,\r
#include "Os.h"
+#include "Mcu.h"
#include <stdio.h>
#include <assert.h>
#define USE_TRACE 1
#include "Trace.h"
-//#include "Hooks.h"
#if 0
#if !defined(USE_SIMULATOR)
// Quick fix
//#include "kernel_offset.h"
-#include "Mcu.h"
extern uint8_t pcb_list[];
/*\r
* RTE.c\r
*\r
- * Created on: 2009-jul-10\r
- * Author: rosa\r
+ * Author: tojo
*/\r
\r
#include "Dio.h"\r
-\r
+#include "Rte.h"
\r
void RTE_blinker_blink(uint8 arg){\r
- Dio_WriteChannel(LED_K2, arg);\r
+ Dio_WriteChannel(LED_CHANNEL, arg);
}\r
-
-
-
/*\r
* RTE.h\r
*\r
- * Created on: 2009-jul-10\r
- * Author: rosa\r
+ * Author: tojo
*/\r
\r
#ifndef RTE_H_\r
#define RTE_H_\r
#include "RTE_blinker.h"\r
+
+// Select DIO channel
+#if defined(CFG_BRD_MPC5516IT)
+#define LED_CHANNEL LEDS_LED5
+
+#elif defined(CFG_BRD_MPC5567QRTECH)
+#define LED_CHANNEL LED_K2
+
+#else
+#warning "Unknown board or CFG_BRD_* undefined"
+
+#endif
\r
#endif /* RTE_H_ */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>blinker_node</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"></SD>\r
+ <SD GID="COPYRIGHT"></SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask10</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Startup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask10</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/bTask10</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/blinker_node/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
\r
// --- COUNTERS ---\r
GEN_COUNTER_HEAD {\r
- GEN_COUNTER( OS_TICK_COUNTER,\r
- "OS_TICK_COUNTER",\r
+ GEN_COUNTER( COUNTER_ID_OsTick,
+ "COUNTER_ID_OsTick",
COUNTER_TYPE_HARD,\r
COUNTER_UNIT_NANO,\r
0xffff,1,1,0 ),\r
-};\r
+};
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;
\r
// --- ALARMS ---\r
GEN_ALARM_HEAD {\r
{\r
.expire_val = 10,\r
.active = FALSE,\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],
+ .counter_id = COUNTER_ID_OsTick,
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
{\r
.expire_val = 25,\r
.active = FALSE,\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],
+ .counter_id = COUNTER_ID_OsTick,
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
{\r
.expire_val = 100,\r
.active = FALSE,\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],
+ .counter_id = COUNTER_ID_OsTick,
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
\r
// --- MISC ---\r
uint32 os_dbg_mask = 0;\r
-\r
-// D_MASTER_PRINT |\\r
-// D_ISR_MASTER_PRINT |\\r
-// D_STDOUT |\\r
-// D_ISR_STDOUT |\r
-// D_ALARM | D_TASK;\r
-\r
+/*
+ D_MASTER_PRINT |\
+ D_ISR_MASTER_PRINT |\
+ D_STDOUT |\
+ D_ISR_STDOUT |\
+ D_ALARM | D_TASK;
+*/
\r
#include "os_config_funcs.h"\r
\r
void bTask10( void );\r
void bTask25( void );\r
void bTask100( void );\r
+
+// COUNTERS
+#define COUNTER_ID_OsTick 0
\r
// ALARMS\r
#define ALARM_USE\r
\r
// --- COUNTERS ---\r
GEN_COUNTER_HEAD {\r
- GEN_COUNTER( OS_TICK_COUNTER,\r
- "OS_TICK_COUNTER",\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "COUNTER_ID_OsTick",\r
COUNTER_TYPE_HARD,\r
COUNTER_UNIT_NANO,\r
0xffff,1,1,0 ),\r
-};\r
+};
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
\r
// --- ALARMS ---\r
GEN_ALARM_HEAD {\r
{\r
.expire_val = 25,\r
.active = FALSE,\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
{\r
.expire_val = 100,\r
.active = FALSE,\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
\r
// --- MISC ---\r
uint32 os_dbg_mask = 0;\r
-\r
-// D_MASTER_PRINT |\\r
-// D_ISR_MASTER_PRINT |\\r
-// D_STDOUT |\\r
-// D_ISR_STDOUT |\r
-// D_ALARM | D_TASK;\r
-\r
+/*
+ D_MASTER_PRINT |\
+ D_ISR_MASTER_PRINT |\
+ D_STDOUT |\
+ D_ISR_STDOUT |
+ D_ALARM | D_TASK;
+*/
\r
#include "os_config_funcs.h"\r
\r
void Startup( void );\r
void bTask25( void );\r
void bTask100( void );\r
+
+// COUNTERS
+#define COUNTER_ID_OsTick 0
\r
// ALARMS\r
#define ALARM_USE\r
PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 3000, 0x6000, PWM_CHANNEL_PRESCALER_4, PWM_HIGH),\r
PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 2000, 0x2000, PWM_CHANNEL_PRESCALER_2, PWM_LOW)\r
},\r
-#if PWM_NOTIFICATION_SUPPORTED==ON\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
.NotificationHandlers = {\r
MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
NULL // PWM_CHANNEL_2\r
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-/*\r
- * Pwm_Cfg.h\r
- *\r
- * Created on: 2009-jul-09\r
- * Author: nian\r
- */\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
\r
-/****************************************************************************\r
- * Global configuration options and defines\r
+/*
+ * PwmGeneral
*/\r
\r
-#define ON 1\r
-#define OFF 0\r
-\r
/*\r
* PWM003: The detection of development errors is configurable (ON/OFF) at\r
* pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
* the detection of all development errors\r
- */\r
-#define PWM_DEV_EROR_DETECT ON\r
-#define PWM_GET_OUTPUT_STATE ON\r
-#define PWM_STATICALLY_CONFIGURED OFF\r
-#define PWM_NOTIFICATION_SUPPORTED ON\r
+ */
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
\r
-#define PWM_SET_PERIOD_AND_DUTY ON\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+
+/*
+ * PWM106: This is implementation specific but not all values may be valid
+ * within the type. This shall be chosen in order to have the most efficient
+ * implementation on a specific microcontroller platform.
+ *
+ * PWM106 => Pwm_ChannelType == eemios channel id.
+ */
+typedef uint8 Pwm_ChannelType;
+
+/*
+ * PWM070: All time units used within the API services of the PWM module shall
+ * be of the unit ticks.
+ */
+typedef uint16 Pwm_PeriodType;
+
\r
/*\r
* PWM132: Switch for enabling the update of duty cycle parameter at the end\r
*\r
* Note: Currently only ON mode is supported.\r
*/\r
-#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD ON\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
\r
/****************************************************************************\r
* Not defined in AUTOSAR.\r
* Setting to ON freezes the current output state of a PWM channel when in\r
* debug mode.\r
*/\r
-#define PWM_FREEZE_ENABLE ON\r
+#define PWM_FREEZE_ENABLE STD_ON\r
\r
/****************************************************************************\r
* Enumeration of channels\r
#endif\r
PWM_NUMBER_OF_CHANNELS = 2\r
} Pwm_NamedChannelsType;\r
+
+typedef enum {
+ PWM_CHANNEL_PRESCALER_1=0,
+ PWM_CHANNEL_PRESCALER_2,
+ PWM_CHANNEL_PRESCALER_3,
+ PWM_CHANNEL_PRESCALER_4,
+} Pwm_ChannelPrescalerType;
+
+/*
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,
+ * the following macro can be used to convert between that format and the
+ * mpc5516 format.
+ */
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period
+
+#if defined(CFG_MPC5516)
+ /* Mode is buffered PWM output (OPWM) */
+ /* Mode is buffered Output PW and frequency modulation mode */
+#define PWM_EMIOS_OPWM 0x5A
+#elif defined(CFG_MPC5567)
+ /* Mode is buffered OPWM with frequency modulation (allows change of
+ * period) */
+#define PWM_EMIOS_OPWM 0x19
+#endif
+
+
+typedef struct {
+ /* Number of duty ticks */
+ uint32_t duty:32;
+ /* Length of period, in ticks */
+ uint32_t period:32;
+ /* Counter */
+ uint32_t counter:32;
+ /* Enable freezing the channel when in debug mode */
+ uint32_t freezeEnable:1;
+ /* Disable output */
+ uint32_t outputDisable:1;
+ /* Select which bus disables the bus
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */
+ uint32_t outputDisableSelect:2;
+ /* Prescale the emios clock some more? */
+ Pwm_ChannelPrescalerType prescaler:2;
+ /* Prescale the emios clock some more? */
+ uint32_t usePrescaler:1;
+ /* Whether to use DMA. Currently unsupported */
+ uint32_t useDma:1;
+ uint32_t reserved_2:1;
+ /* Input filter. Ignored in output mode. */
+ uint32_t inputFilter:4;
+ /* Input filter clock source. Ignored in output mode */
+ uint32_t filterClockSelect:1;
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */
+ uint32_t flagEnable:1;
+ uint32_t reserved_3:3;
+ /* Trigger a match on channel A */
+ uint32_t forceMatchA:1;
+ /* Triggers a match on channel B */
+ uint32_t forceMatchB:1;
+ uint32_t reserved_4:1;
+ /* We can use different buses for the counter. Use the internal counter */
+ uint32_t busSelect:2;
+ /* What edges to flag on? */
+ uint32_t edgeSelect:1;
+ /* Polarity of the channel */
+ uint32_t edgePolarity:1;
+ /* EMIOS mode. 0x58 for buffered output PWM */
+ uint32_t mode:7;
+} Pwm_ChannelRegisterType;
+
+typedef struct {
+ Pwm_ChannelRegisterType r;
+ Pwm_ChannelType channel;
+} Pwm_ChannelConfigurationType;
+
+
+typedef struct {
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];
+#endif
+} Pwm_ConfigType;
+
+// Channel configuration macro.
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \
+ {\
+ .channel = _hwchannel,\
+ .r = {\
+ DUTY_AND_PERIOD(_duty, _period),\
+ .freezeEnable = 1,\
+ .outputDisable = 0,\
+ .usePrescaler = 1,\
+ .prescaler = _prescaler,\
+ .useDma = 0,\
+ .flagEnable = 0, /* See PWM052 */ \
+ .busSelect = 3, /* Use the internal counter bus */\
+ .edgePolarity = _polarity,\
+ .mode = PWM_EMIOS_OPWM\
+ }\
+ }
\r
#endif /* PWM_CFG_H_ */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>pwm_node_mpc551x</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">MPC551x</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"/>\r
+ <SD GID="COPYRIGHT"/>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Startup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Pwm</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM_CHANNEL_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>13</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmArcticCoreChannelPrescaler</DEFINITION-REF>\r
+ <VALUE>PWM_CHANNEL_PRESCALER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>0.0096</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>PWM_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM_CHANNEL_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmArcticCoreChannelPrescaler</DEFINITION-REF>\r
+ <VALUE>PWM_CHANNEL_PRESCALER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>0.0032</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Port</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>eMIOS[12]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>52</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_PWM</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>eMIOS[13]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>53</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_PWM</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>pwm_node_mpc5567</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">MPC5567</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"></SD>\r
+ <SD GID="COPYRIGHT"></SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc5567/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc5567/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc5567/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Startup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc5567/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc5567/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc5567/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc5567/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Pwm</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM_CHANNEL_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmArcticCoreChannelPrescaler</DEFINITION-REF>\r
+ <VALUE>PWM_CHANNEL_PRESCALER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>0.0096</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM_CHANNEL_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmArcticCoreChannelPrescaler</DEFINITION-REF>\r
+ <VALUE>PWM_CHANNEL_PRESCALER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>0.0032</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Port</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>EMIOS[10]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>189</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_PWM</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>EMIOS[12]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>191</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_PWM</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
#include <assert.h>
#define USE_TRACE 1
#include "Trace.h"
-//#include "Hooks.h"
+#include "Mcu.h"
#if 0
#if !defined(USE_SIMULATOR)
// Quick fix
//#include "Kernel_Offset.h"
-#include "Mcu.h"
extern uint8_t pcb_list[];
#include "Trace.h"\r
#include "Com.h"\r
#include "Adc.h"\r
-\r
+#include "pwm_node2_helpers.h"
\r
void OsIdle( void ) {\r
for(;;);\r
// Imported structs from Can_Lcfg.c\r
extern const Can_ControllerConfigType CanControllerConfigData[];\r
extern const Can_ConfigSetType CanConfigSetData;\r
-\r
+
+// Contains the mapping from CanIf-specific Channels to Can Controllers
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {
+ CAN_CTRL_A, // CANIF_CHANNEL_0
+ CAN_CTRL_C, // CANIF_CHANNEL_1
+};\r
\r
// Container that gets slamed into CanIf_InitController()\r
// Inits ALL controllers\r
// Multiplicity 1..*\r
const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
{\r
- { // This is the ConfigurationIndex in CanIf_InitController()\r
- .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_A,\r
- .CanIfDriverNameRef = "FLEXCAN", // Not used\r
- .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ { // CANIF_CHANNEL_0_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[0],
},\r
- {\r
+ { // CANIF_CHANNEL_1_CONFIG_0\r
.WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_C,\r
+ .CanIfControllerIdRef = CANIF_CHANNEL_1,\r
.CanIfDriverNameRef = "FLEXCAN", // Not used\r
.CanIfInitControllerRef = &CanControllerConfigData[1],\r
}\r
const CanIf_HthConfigType CanIfHthConfigData[] =\r
{\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_0,\r
.CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_C,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_1,\r
.CanIfHthIdSymRef = CAN_HTH_C_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
{\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
.CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_C,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_1,\r
.CanIfHrhIdSymRef = CAN_HRH_C_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
//-------------------------------------------------------------------\r
.CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
.CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
.CanIfUserRxIndication = PduR_CanIfRxIndication, // No indication\r
- .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on controller A\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData[0], // Received on channel 0\r
.PduIdRef = NULL, // Could be used by upper layers\r
.CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK, // Not enabled in HRH\r
.CanIfCanRxPduCanIdMask = 0xFFF,\r
.CanConfigSet = &CanConfigSetData,\r
.CanIfHrhConfig = CanIfHrhConfigData,\r
.CanIfHthConfig = CanIfHthConfigData,\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
.ControllerConfig = CanIfControllerConfig,\r
.DispatchConfig = &CanIfDispatchConfig,\r
.InitConfig = &CanIfInitConfig,\r
- .TransceiverConfig = NULL, // Not used\r
+ .TransceiverConfig = NULL, // Not used
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap,\r
};\r
\r
*/\r
ComGroupSignal_type ComGroupSignal[] = {\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComBitSize = 16,\r
.ComSignalEndianess = BIG_ENDIAN,\r
.ComSignalType = UINT16,
- .ComEcoreIsSignalGroup = 0,\r
+ .Com_Arc_IsSignalGroup = 0,\r
\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.alarm_base.tickperbase = 1,\r
.alarm_base.mincycle = 0,\r
},\r
-};\r
+};
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
\r
// ################################## ALARMS ################################\r
alarm_obj_t alarm_list[] = {\r
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-/*\r
- * Pwm_Cfg.h\r
- *\r
- * Created on: 2009-jul-09\r
- * Author: nian\r
- */\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
\r
-/****************************************************************************\r
- * Global configuration options and defines\r
+/*
+ * PwmGeneral
*/\r
\r
-#define ON 1\r
-#define OFF 0\r
-\r
/*\r
* PWM003: The detection of development errors is configurable (ON/OFF) at\r
* pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
* the detection of all development errors\r
*/\r
-#define PWM_DEV_EROR_DETECT ON\r
-#define PWM_GET_OUTPUT_STATE ON\r
-#define PWM_STATICALLY_CONFIGURED OFF\r
-#define PWM_NOTIFICATION_SUPPORTED ON\r
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
\r
-#define PWM_SET_PERIOD_AND_DUTY ON\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
\r
/*\r
* PWM132: Switch for enabling the update of duty cycle parameter at the end\r
*\r
* Note: Currently only ON mode is supported.\r
*/\r
-#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD ON\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+
+/*
+ * PWM106: This is implementation specific but not all values may be valid
+ * within the type. This shall be chosen in order to have the most efficient
+ * implementation on a specific microcontroller platform.
+ *
+ * PWM106 => Pwm_ChannelType == eemios channel id.
+ */
+typedef uint8 Pwm_ChannelType;
+
+/*
+ * PWM070: All time units used within the API services of the PWM module shall
+ * be of the unit ticks.
+ */
+typedef uint16 Pwm_PeriodType;
+
\r
/****************************************************************************\r
* Not defined in AUTOSAR.\r
* Setting to ON freezes the current output state of a PWM channel when in\r
* debug mode.\r
*/\r
-#define PWM_FREEZE_ENABLE ON\r
+#define PWM_FREEZE_ENABLE STD_ON\r
\r
/****************************************************************************\r
* Enumeration of channels\r
* is available on pin 54 of the\r
* ERNI 154822 connector\r
*/\r
- PWM_CHANNEL_2 = 12, /* Channel 12 goes to PCR191, also\r
- * available on the ERNI 154822 connector\r
- */\r
#else\r
#warning "Unknown board or CFG_BRD_* undefined"\r
#endif\r
PWM_NUMBER_OF_CHANNELS = 1,\r
} Pwm_NamedChannelsType;\r
+
+typedef enum {
+ PWM_CHANNEL_PRESCALER_1=0,
+ PWM_CHANNEL_PRESCALER_2,
+ PWM_CHANNEL_PRESCALER_3,
+ PWM_CHANNEL_PRESCALER_4,
+} Pwm_ChannelPrescalerType;
+
+/*
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,
+ * the following macro can be used to convert between that format and the
+ * mpc5516 format.
+ */
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period
+
+#if defined(CFG_MPC5516)
+ /* Mode is buffered PWM output (OPWM) */
+ /* Mode is buffered Output PW and frequency modulation mode */
+#define PWM_EMIOS_OPWM 0x5A
+#elif defined(CFG_MPC5567)
+ /* Mode is buffered OPWM with frequency modulation (allows change of
+ * period) */
+#define PWM_EMIOS_OPWM 0x19
+#endif
+
+
+typedef struct {
+ /* Number of duty ticks */
+ uint32_t duty:32;
+ /* Length of period, in ticks */
+ uint32_t period:32;
+ /* Counter */
+ uint32_t counter:32;
+ /* Enable freezing the channel when in debug mode */
+ uint32_t freezeEnable:1;
+ /* Disable output */
+ uint32_t outputDisable:1;
+ /* Select which bus disables the bus
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */
+ uint32_t outputDisableSelect:2;
+ /* Prescale the emios clock some more? */
+ Pwm_ChannelPrescalerType prescaler:2;
+ /* Prescale the emios clock some more? */
+ uint32_t usePrescaler:1;
+ /* Whether to use DMA. Currently unsupported */
+ uint32_t useDma:1;
+ uint32_t reserved_2:1;
+ /* Input filter. Ignored in output mode. */
+ uint32_t inputFilter:4;
+ /* Input filter clock source. Ignored in output mode */
+ uint32_t filterClockSelect:1;
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */
+ uint32_t flagEnable:1;
+ uint32_t reserved_3:3;
+ /* Trigger a match on channel A */
+ uint32_t forceMatchA:1;
+ /* Triggers a match on channel B */
+ uint32_t forceMatchB:1;
+ uint32_t reserved_4:1;
+ /* We can use different buses for the counter. Use the internal counter */
+ uint32_t busSelect:2;
+ /* What edges to flag on? */
+ uint32_t edgeSelect:1;
+ /* Polarity of the channel */
+ uint32_t edgePolarity:1;
+ /* EMIOS mode. 0x58 for buffered output PWM */
+ uint32_t mode:7;
+} Pwm_ChannelRegisterType;
+
+typedef struct {
+ Pwm_ChannelRegisterType r;
+ Pwm_ChannelType channel;
+} Pwm_ChannelConfigurationType;
+
+
+typedef struct {
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];
+#endif
+} Pwm_ConfigType;
+
+// Channel configuration macro.
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \
+ {\
+ .channel = _hwchannel,\
+ .r = {\
+ DUTY_AND_PERIOD(_duty, _period),\
+ .freezeEnable = 1,\
+ .outputDisable = 0,\
+ .usePrescaler = 1,\
+ .prescaler = _prescaler,\
+ .useDma = 0,\
+ .flagEnable = 0, /* See PWM052 */ \
+ .busSelect = 3, /* Use the internal counter bus */\
+ .edgePolarity = _polarity,\
+ .mode = PWM_EMIOS_OPWM\
+ }\
+ }
\r
#endif /* PWM_CFG_H_ */\r
\r
-#include "Adc.h"\r
#include "Com.h"\r
#include "Trace.h"\r
#include "RTE_fading_led.h"\r
\r
uint16 rx_data = 0;\r
\r
-void can_node_receive(void) {\r
+void pwm_node2_receive(void) {\r
Com_ReceiveSignal(SetLedLevelRx, &rx_data);\r
fading_led_set_level(rx_data);\r
}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef PWM_NODE2_HELPERS_H_\r
+#define PWM_NODE2_HELPERS_H_\r
+\r
+void pwm_node2_receive(void);\r
+\r
+#endif /* PWM_NODE2_HELPERS_H_ */\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>pwm_node_mpc551x</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">MPC551x</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"/>\r
+ <SD GID="COPYRIGHT"/>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/EcuC</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Com</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Can</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/CanIf</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc551x/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>StartupTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComAlarm</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Os/ComTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>EcuC</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuC</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/EcuC</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PduCollection</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuC/PduCollection</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>LedCommandRx</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuC/PduCollection/Pdu</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuC/PduCollection/Pdu/PduLength</DEFINITION-REF>\r
+ <VALUE>64</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Com</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Com</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Com</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComConfigurationId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>RxGroup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPduGroup</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPduGroup/ComIPduGroupHandleId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>LedCommandRx</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduCallout</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduRxHandleId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduSignalProcessing</DEFINITION-REF>\r
+ <VALUE>IMMEDIATE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduDirection</DEFINITION-REF>\r
+ <VALUE>RECEIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduGroupRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Com/ComConfig/RxGroup</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/PduIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/EcuC/PduCollection/LedCommandRx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduSignalRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Com/ComConfig/SetLedLevelRx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxIPdu</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxIPduMinimumDelayTimeFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxIPduUnusedAreasDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxModeTrue</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxMode</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPduComTxModeTrue/ComTxMode</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeMode</DEFINITION-REF>\r
+ <VALUE>DIRECT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeNumberOfRepetitions</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeRepetitionPeriodFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeTimeOffsetFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeTimePeriodFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>SetLedLevelRx</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComSignal</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComBitPosition</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComBitSize</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComFirstTimeoutFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComHandleId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalEndianess</DEFINITION-REF>\r
+ <VALUE>BIG_ENDIAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalInitValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalLength</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalType</DEFINITION-REF>\r
+ <VALUE>UINT16</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
+ <VALUE>TRIGGERED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComGeneral/ComConfigurationTimeBase</DEFINITION-REF>\r
+ </FLOAT-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComGeneral/ComConfigurationUseDet</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Can</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Can_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerLoopback</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerBaudRate</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>FLEXCAN_A</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/CanFilterMaskValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>HWObj_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>RECEIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>16711680</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Can/CanConfigSet/Can_A</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Can/CanConfigSet/Can_A/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>CanIf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/CanIf</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/CanIf</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfDispatchConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDispatchConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfDriverConfig</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfBusoffNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfReceiveIndication</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTransmitCancellation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTxConfirmation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfInitConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanTXPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfDynamicCanTXPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Hoh_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Hrh_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfHrhType</DEFINITION-REF>\r
+ <VALUE>BASIC_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfSoftwareFilterHrh</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfCanControllerHrhIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/CanIf/CHANNEL_0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfHrhIdSymRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Can/CanConfigSet/HWObj_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Rx_PDU_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfCanRxPduCanId</DEFINITION-REF>\r
+ <VALUE>291</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfCanRxPduDlc</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfCanRxPduId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfReadRxPduData</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfReadRxPduNotifyStatus</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfRxPduIdCanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfRxUserType</DEFINITION-REF>\r
+ <VALUE>PDUR</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfUserRxIndication</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfCanRxPduHrhRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/CanIf/CanIfInitConfiguration/Hoh_1/Hrh_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/PduIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/EcuC/PduCollection/LedCommandRx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfPrivateConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfDlcCheck</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfNumberOfTxBuffers</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfSoftwareFilterType</DEFINITION-REF>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfPublicConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfPublicConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfMultipleDriverSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfNumberOfCanHwUnits</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadRxPduDataApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadRxPduNotifyStatusApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadTxPduNotifyStatusApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfSetDynamicTxIdApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfWakeupEventApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfTransceiverDrvConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig/CanIfTrcvWakeupNotification</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CHANNEL_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfControllerConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfControllerConfig/CanIfWakeupSupport</DEFINITION-REF>\r
+ <VALUE>NO_WAKEUP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfControllerConfig/CanIfControllerIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/pwm_node_mpc551x/Can/CanConfigSet/Can_A</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Pwm</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM_CHANNEL_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmArcticCoreChannelPrescaler</DEFINITION-REF>\r
+ <VALUE>PWM_CHANNEL_PRESCALER_1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>0.0010</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Port</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>eMIOS[12]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>52</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_PWM</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CAN</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CNTX_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CNRX_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Simple</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL></REVISION-LABEL>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"></SD>\r
+ <SD GID="COPYRIGHT"></SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/Simple/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsCounter</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Alarm_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/Simple/Os/OsCounter</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>RELATIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>SetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF>/Simple/Os/Event_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/Simple/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Event_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Event_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Event_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
\r
// --- COUNTERS ---\r
GEN_COUNTER_HEAD {\r
- GEN_COUNTER( OS_TICK_COUNTER,\r
- "OS_TICK_COUNTER",\r
+ GEN_COUNTER( COUNTER_ID_OsTick,
+ "COUNTER_ID_OsTick",
COUNTER_TYPE_HARD,\r
COUNTER_UNIT_NANO,\r
0xffff,1,1,0 ),\r
-};\r
+};
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;
\r
// --- MESSAGES ---\r
\r
#define ALARM_USE\r
\r
GEN_ALARM_HEAD {\r
- GEN_ALARM( 0,"Alarm1",OS_TICK_COUNTER,\r
+ GEN_ALARM( 0,"Alarm1",COUNTER_ID_OsTick,
1,100,10,0, /*active,start,cycle,app_mask */\r
ALARM_ACTION_SETEVENT, TASK_ID_etask_1, 2, 0 ),\r
};\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
\r
-/* os_config.h */\r
+#define COUNTER_ID_OsTick 0
\r
#define APPLICATION_ID_application_1 0\r
#define APPLICATION_CNT 1\r
//#define TASK_ID_os_tick 8\r
\r
\r
-// OS_TICK_COUNTER located in Os.h\r
+// COUNTER_ID_OsTick located in Os.h\r
\r
// NOT GENERATED( for test system only )\r
#define SYSTEM_COUNTER_PERIOD 100\r
switch(service) {\r
case OSServiceId_SetRelAlarm:\r
{\r
- // Read the arguments to the faulty functions...\r
+ // Read the arguments to the faulty functions...
+ /* (Commented to remove warnings)
AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;\r
TickType increment = OSError_SetRelAlarm_Increment;\r
- TickType cycle = OSError_SetRelAlarm_Cycle;\r
+ TickType cycle = OSError_SetRelAlarm_Cycle; */
// ... Handle this some way.\r
break;\r
}\r
#include <assert.h>
#define USE_TRACE 1
#include "Trace.h"
-//#include "Hooks.h"
+#include "Mcu.h"
#if 0
#if !defined(USE_SIMULATOR)
// Quick fix
//#include "Kernel_Offset.h"
-#include "Mcu.h"
extern uint8_t pcb_list[];
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
#ifndef ADC_CFG_H_\r
#define ADC_CFG_H_\r
+
+#include "Dma.h"
\r
#define ADC_PRIORITY_HW 0\r
#define ADC_PRIORITY_HW_SW 1\r
#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
#define ADC_READ_GROUP_API STD_ON\r
#define ADC_VERSION_API STD_ON /* Not implemented. */\r
-\r
-/* Group definitions. */\r
-\r
-\r
-typedef enum\r
-{\r
- ADC_SWITCHES,\r
- ADC_POTENTIOMETERS\r
-}Adc_GroupType_NiceNames;\r
-\r
-typedef enum\r
-{\r
- ADC_GROUP0,\r
- ADC_GROUP1,\r
- ADC_NBR_OF_GROUPS\r
-}Adc_GroupType;\r
-\r
-typedef enum\r
-{\r
- ADC_CH0,\r
- ADC_CH1,\r
- ADC_CH2,\r
- ADC_CH3,\r
- ADC_CH4,\r
- ADC_CH5,\r
- ADC_CH6,\r
- ADC_CH7,\r
- ADC_CH8,\r
- ADC_CH9,\r
- ADC_CH10,\r
- ADC_CH11,\r
- ADC_CH12,\r
- ADC_CH13,\r
- ADC_CH14,\r
- ADC_CH15,\r
- ADC_CH16,\r
- ADC_CH17,\r
- ADC_CH18,\r
- ADC_CH19,\r
- ADC_CH20,\r
- ADC_NBR_OF_CHANNELS,\r
-}Adc_ChannelType;\r
-\r
-typedef enum\r
-{\r
- ADC_SWITCH_RED,\r
- ADC_SWITCH_BLACK,\r
- ADC_NBR_OF_SWITCH_CHANNELS,\r
-}Adc_SwitchesSignalType;\r
-\r
-typedef enum\r
-{\r
- ADC_POTENTIOMETER_NOT_USED,\r
- ADC_POTENTIOMETER_0,\r
-\r
- ADC_POTENTIOMETER_1,\r
- ADC_NBR_OF_POTENTIOMETER_CHANNELS,\r
-}Adc_PotentiometersSignals;\r
+
+/* Group definitions. */
+
+typedef enum
+{
+ ADC_SWITCHES,
+ ADC_POTENTIOMETERS
+}Adc_GroupType_NiceNames;
+
+typedef enum
+{
+ ADC_GROUP0,
+ ADC_GROUP1,
+ ADC_NBR_OF_GROUPS
+}Adc_GroupType;
+
+typedef enum
+{
+ ADC_CH0,
+ ADC_CH1,
+ ADC_CH2,
+ ADC_CH3,
+ ADC_CH4,
+ ADC_CH5,
+ ADC_CH6,
+ ADC_CH7,
+ ADC_CH8,
+ ADC_CH9,
+ ADC_CH10,
+ ADC_CH11,
+ ADC_CH12,
+ ADC_CH13,
+ ADC_CH14,
+ ADC_CH15,
+ ADC_CH16,
+ ADC_CH17,
+ ADC_CH18,
+ ADC_CH19,
+ ADC_CH20,
+ ADC_NBR_OF_CHANNELS,
+}Adc_ChannelType;
+
+typedef enum
+{
+ ADC_SWITCH_RED,
+ ADC_SWITCH_BLACK,
+ ADC_NBR_OF_SWITCH_CHANNELS,
+}Adc_SwitchesSignalType;
+
+typedef enum
+{
+ ADC_POTENTIOMETER_NOT_USED,
+ ADC_POTENTIOMETER_0,
+
+ ADC_POTENTIOMETER_1,
+ ADC_NBR_OF_POTENTIOMETER_CHANNELS,
+}Adc_PotentiometersSignals;
+
+
+typedef uint16_t Adc_ValueGroupType;
+
+
+/* Non-standard type */
+typedef union
+{
+ vuint32_t R;
+ struct
+ {
+ vuint32_t EOQ:1;
+ vuint32_t PAUSE:1;
+ vuint32_t :4;
+ vuint32_t BN:1;
+ vuint32_t CAL:1;
+ vuint32_t MESSAGE_TAG:4;
+ vuint32_t LST:2;
+ vuint32_t TSR:1;
+ vuint32_t FMT:1;
+ vuint32_t CHANNEL_NUMBER:8;
+ vuint32_t :8;
+ } B;
+}Adc_CommandType;
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_SYSTEM_CLOCK
+}Adc_ClockSourceType;
+
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_SYSTEM_CLOCK_DISABLED,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,
+}Adc_PrescaleType;
+
+/* Non-standard type */
+typedef struct
+{
+ Adc_ClockSourceType clockSource;
+ uint8_t hwUnitId;
+ Adc_PrescaleType adcPrescale;
+}Adc_HWConfigurationType;
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_REFERENCE_VOLTAGE_GROUND,
+ ADC_REFERENCE_VOLTAGE_5V,
+}Adc_VoltageSourceType;
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_CONVERSION_TIME_2_CLOCKS,
+ ADC_CONVERSION_TIME_8_CLOCKS,
+ ADC_CONVERSION_TIME_64_CLOCKS,
+ ADC_CONVERSION_TIME_128_CLOCKS
+}Adc_ConversionTimeType;
+
+/* Non-standard type */
+typedef enum
+{
+ ADC_CALIBRATION_DISABLED,
+ ADC_CALIBRATION_ENABLED
+}Adc_CalibrationType;
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_RESOLUTION_12BITS
+}Adc_ResolutionType;
+
+/* Non-standard type */
+/* Channel definitions. */
+typedef struct
+{
+ Adc_ConversionTimeType adcChannelConvTime;
+ Adc_VoltageSourceType adcChannelRefVoltSrcLow;
+ Adc_VoltageSourceType adcChannelRefVoltSrcHigh;
+ Adc_ResolutionType adcChannelResolution;
+ Adc_CalibrationType adcChannelCalibrationEnable;
+}Adc_ChannelConfigurationType;
+
+
+/* TODO list timer sources here. */
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_NO_TIMER,
+}Adc_HwTriggerTimerType;
+
+
+/* Std-type, supplier defined */
+typedef uint16_t Adc_StreamNumSampleType;
+
+/* Std-type, supplier defined */
+typedef enum
+{
+ ADC_CONV_MODE_DISABLED,
+ ADC_CONV_MODE_ONESHOT = 1,
+ ADC_CONV_MODE_CONTINOUS = 9,
+}Adc_GroupConvModeType;
+
+
+/* Used ?? */
+typedef struct
+{
+ uint8 notifictionEnable;
+ Adc_ValueGroupType *resultBufferPtr;
+ Adc_StatusType groupStatus;
+}Adc_GroupStatus;
+
+
+/* Implementation specific */
+typedef struct
+{
+ Adc_GroupAccessModeType accessMode;
+ Adc_GroupConvModeType conversionMode;
+ Adc_TriggerSourceType triggerSrc;
+ Adc_HwTriggerSignalType hwTriggerSignal;
+ Adc_HwTriggerTimerType hwTriggerTimer;
+ void (*groupCallback)(void);
+ Adc_StreamBufferModeType streamBufferMode;
+ Adc_StreamNumSampleType streamNumSamples;
+ const Adc_ChannelType *channelList;
+ Adc_ValueGroupType *resultBuffer;
+ Adc_CommandType *commandBuffer;
+ Adc_ChannelType numberOfChannels;
+ Adc_GroupStatus *status;
+ Dma_ChannelType dmaCommandChannel;
+ Dma_ChannelType dmaResultChannel;
+ const struct tcd_t *groupDMACommands;
+ const struct tcd_t *groupDMAResults;
+}Adc_GroupDefType;
+
+
+/* Impl. specific */
+typedef struct
+{
+ const Adc_HWConfigurationType* hwConfigPtr;
+ const Adc_ChannelConfigurationType* channelConfigPtr;
+ const uint16_t nbrOfChannels;
+ const Adc_GroupDefType* groupConfigPtr;
+ const uint16_t nbrOfGroups;
+}Adc_ConfigType;
+
+extern const Adc_ConfigType AdcConfig [];
\r
extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
// Imported structs from Can_Lcfg.c\r
extern const Can_ControllerConfigType CanControllerConfigData[];\r
extern const Can_ConfigSetType CanConfigSetData;\r
+
+// Contains the mapping from CanIf-specific Channels to Can Controllers
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {
+ CAN_CTRL_A, // CANIF_CHANNEL_0
+ CAN_CTRL_C, // CANIF_CHANNEL_1
+};
\r
-\r
-// Container that gets slamed into CanIf_InitController()\r
-// Inits ALL controllers\r
-// Multiplicity 1..*\r
const CanIf_ControllerConfigType CanIfControllerConfig[] =\r
{\r
- { // This is the ConfigurationIndex in CanIf_InitController()\r
+ { // CANIF_CHANNEL_0_CONFIG_0\r
.WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- .CanIfControllerIdRef = CAN_CTRL_A,\r
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,\r
.CanIfDriverNameRef = "FLEXCAN", // Not used\r
.CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },
+ { // CANIF_CHANNEL_1_CONFIG_0
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,
+ .CanIfControllerIdRef = CANIF_CHANNEL_1,
+ .CanIfDriverNameRef = "FLEXCAN", // Not used
+ .CanIfInitControllerRef = &CanControllerConfigData[1],
},\r
};\r
\r
const CanIf_HthConfigType CanIfHthConfigData[] =\r
{\r
{\r
- .CanIfHthType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
- .CanIfCanControllerIdRef = CAN_CTRL_A,\r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_0,\r
.CanIfHthIdSymRef = CAN_HTH_A_1, // Ref to the HTH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
};\r
\r
const CanIf_HrhConfigType CanIfHrhConfigData[] =\r
{\r
{\r
- .CanIfHrhType = CAN_ECORE_HANDLE_TYPE_BASIC,\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE, // Disable software filtering\r
- .CanIfCanControllerHrhIdRef = CAN_CTRL_A,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
.CanIfHrhIdSymRef = CAN_HRH_A_1, // Ref to the HRH\r
- .CanIfEcoreEOL = 0,\r
+ .CanIf_Arc_EOL = 0,\r
},\r
};\r
//-------------------------------------------------------------------\r
.CanConfigSet = &CanConfigSetData,\r
.CanIfHrhConfig = CanIfHrhConfigData,\r
.CanIfHthConfig = CanIfHthConfigData,\r
- .CanIfEcoreEOL = 1,\r
+ .CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
.ControllerConfig = CanIfControllerConfig,\r
.DispatchConfig = &CanIfDispatchConfig,\r
.InitConfig = &CanIfInitConfig,\r
- .TransceiverConfig = NULL, // Not used\r
+ .TransceiverConfig = NULL, // Not used
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap,\r
};\r
\r
*/\r
ComGroupSignal_type ComGroupSignal[] = {\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.ComBitSize = 16,\r
.ComSignalEndianess = BIG_ENDIAN,\r
.ComSignalType = UINT16,
- .ComEcoreIsSignalGroup = 0,\r
+ .Com_Arc_IsSignalGroup = 0,\r
\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
},\r
},\r
{\r
- .ComEcoreEOL = 1\r
+ .Com_Arc_EOL = 1\r
}\r
};\r
\r
.alarm_base.mincycle = 0,\r
},\r
};\r
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;
\r
// ################################## ALARMS ################################\r
alarm_obj_t alarm_list[] = {\r
/*\r
* ADC callback. This function is called each time the switches are read.\r
*/\r
-static uint8 ModeSwitchCounter = 0; // Add some delay to the mode switch\r
static Adc_ValueGroupType switchValues[ADC_NBR_OF_SWITCH_CHANNELS];\r
void switch_node_switches_callback(void) {\r
\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.0">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>switch_node_mpc551x</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Autocore::Options">\r
+ <SD GID="ARCCORE_FORMAT_VERSION">1.1.0</SD>\r
+ <SD GID="MCU">MPC551x</SD>\r
+ <SD GID="LOCAL_VALIDATION">ON</SD>\r
+ <SD GID="AUTHOR"/>\r
+ <SD GID="COPYRIGHT"/>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/EcuC</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/CanIf</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/Can</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/Com</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Os</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS-TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ReadSwitches</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>StartupTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComAlarm</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Os/ComTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ReadSwAlarm</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Os/ReadSwitches</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>EcuC</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuC</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/EcuC</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PduCollection</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuC/PduCollection</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>LedCommandTx</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuC/PduCollection/Pdu</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuC/PduCollection/Pdu/PduLength</DEFINITION-REF>\r
+ <VALUE>64</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>CanIf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/CanIf</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/CanIf</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfDispatchConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDispatchConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfDriverConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDriverConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfBusoffNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfReceiveIndication</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTransmitCancellation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTxConfirmation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfInitConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanTXPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfDynamicCanTXPduIds</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Hoh_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Hth_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfHthType</DEFINITION-REF>\r
+ <VALUE>BASIC_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfCanControllerIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/CanIf/CHANNEL_0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfHthIdSymRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Can/CanConfigSet/Tx1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Tx_PDU_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfCanTxPduId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfCanTxPduIdCanId</DEFINITION-REF>\r
+ <VALUE>291</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfCanTxPduIdDlc</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfCanTxPduType</DEFINITION-REF>\r
+ <VALUE>STATIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfReadTxPduNotifyStatus</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfTxPduIdCanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfTxUserType</DEFINITION-REF>\r
+ <VALUE>PDUR</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfUserTxConfirmation</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <VALUE-REF>/switch_node_mpc551x/CanIf/CanIfInitConfiguration/Hoh_1/Hth_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/PduIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/EcuC/PduCollection/LedCommandTx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfPrivateConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfDlcCheck</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfNumberOfTxBuffers</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfSoftwareFilterType</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfPublicConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfPublicConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfMultipleDriverSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfNumberOfCanHwUnits</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadRxPduDataApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadRxPduNotifyStatusApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfReadTxPduNotifyStatusApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfSetDynamicTxIdApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfPublicConfiguration/CanIfWakeupEventApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanIfTransceiverDrvConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig/CanIfTrcvWakeupNotification</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CHANNEL_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfControllerConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfControllerConfig/CanIfWakeupSupport</DEFINITION-REF>\r
+ <VALUE>NO_WAKEUP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfControllerConfig/CanIfControllerIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Can/CanConfigSet/Can_A</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Can</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Can_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerLoopback</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerBaudRate</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>FLEXCAN_A</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/CanFilterMaskValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Tx1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>TRANSMIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>4278190080</VALUE>\r
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+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
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+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CanGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Com</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Com</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Com</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComConfigurationId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>TxGroup</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPduGroup/ComIPduGroupHandleId</DEFINITION-REF>\r
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+ </PARAMETER-VALUES>\r
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+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>LedCommandTx</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduCallout</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
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+ </INTEGER-VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduDirection</DEFINITION-REF>\r
+ <VALUE>SEND</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <REFERENCE-VALUE>\r
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+ <VALUE-REF>/switch_node_mpc551x/Com/ComConfig/TxGroup</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/PduIdRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/EcuC/PduCollection/LedCommandTx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="CHOICE-REFERENCE-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduSignalRef</DEFINITION-REF>\r
+ <VALUE-REF>/switch_node_mpc551x/Com/ComConfig/SetLedLevelTx</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxIPdu</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxIPduMinimumDelayTimeFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxIPduUnusedAreasDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxModeTrue</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComTxMode</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPduComTxModeTrue/ComTxMode</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeMode</DEFINITION-REF>\r
+ <VALUE>DIRECT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeNumberOfRepetitions</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeRepetitionPeriodFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeTimeOffsetFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComTxIPdu/ComTxModeTrue/ComTxMode/ComTxModeTimePeriodFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>SetLedLevelTx</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComConfig/ComSignal</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComBitPosition</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComBitSize</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComFirstTimeoutFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComHandleId</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalEndianess</DEFINITION-REF>\r
+ <VALUE>BIG_ENDIAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalInitValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalLength</DEFINITION-REF>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalType</DEFINITION-REF>\r
+ <VALUE>UINT16</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutFactor</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutNotification</DEFINITION-REF>\r
+ </FUNCTION-NAME-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
+ <VALUE>TRIGGERED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES/>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>ComGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Com/ComGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComGeneral/ComConfigurationTimeBase</DEFINITION-REF>\r
+ </FLOAT-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Com/ComGeneral/ComConfigurationUseDet</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION>\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Autocore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <MODULE-DESCRIPTION-REF>/ArcCore/Port</MODULE-DESCRIPTION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Adc</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>AN[8]/ANW</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_ADC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>AN[9]/ANX</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>9</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_ADC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>AN[10]/ANY</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_ADC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>AN[11]/ANZ</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>11</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_ADC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>AN[12]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_ADC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <PARAMETER-VALUES/>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CNTX_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>CNRX_A</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER>\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS/>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>
\ No newline at end of file
\r
// --- COUNTERS ---\r
GEN_COUNTER_HEAD {\r
- GEN_COUNTER( OS_TICK_COUNTER,\r
- "OS_TICK_COUNTER",\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "COUNTER_ID_OsTick",\r
COUNTER_TYPE_HARD,\r
COUNTER_UNIT_NANO,\r
0xffff,1,1,0 ),\r
-};\r
+};
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
\r
// --- MESSAGES ---\r
\r
#define ALARM_USE\r
\r
GEN_ALARM_HEAD {\r
- GEN_ALARM( 0,"Alarm_4ms",OS_TICK_COUNTER,\r
+ GEN_ALARM( 0,"Alarm_4ms",COUNTER_ID_OsTick,\r
1,100,2,0, /*active,start,cycle,app_mask */\r
ALARM_ACTION_SETEVENT, TASK_ID_etask_1, 2, 0 ),\r
};\r
\r
//#define TASK_ID_os_tick 8\r
\r
-\r
-// OS_TICK_COUNTER located in Os.h\r
+#define COUNTER_ID_OsTick 0
\r
// NOT GENERATED( for test system only )\r
#define SYSTEM_COUNTER_PERIOD 100
uint32 boffCnt;\r
uint32 fifoOverflow;\r
uint32 fifoWarning;\r
-} Can_EcoreStatisticsType;\r
+} Can_Arc_StatisticsType;\r
\r
\r
// uint16: if only Standard IDs are used\r
volatile uint32_t TXWRN:1;\r
volatile uint32_t RXWRN:1;\r
} B;\r
- } Can_EcoreErrorType;\r
+ } Can_Arc_ErrorType;\r
\r
// Each controller has 32 hth's, so the division of 32 will give the\r
// controller.\r
// Hth - for Flexcan, the hardware message box number... .We don't care\r
\r
\r
-Can_ReturnType Can_Write( Can_EcoreHTHType hth, Can_PduType *pduInfo );\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo );\r
\r
void Can_Cbk_CheckWakeup( uint8 controller );\r
void Can_MainFunction_Write( void );\r
void Can_MainFunction_BusOff( void );\r
void Can_MainFunction_Wakeup( void );\r
\r
-void Can_EcoreGetStatistics( uint8 controller, Can_EcoreStatisticsType * stat);\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat);\r
\r
#endif /*CAN_H_*/\r
#define CANIF_CONTROLLER_BUSOFF_ID 0x16
#define CANIF_SETWAKEUPEVENT_ID 0x40
-#define CANIF_ECOREERROR_ID 0x41
+#define CANIF_ARCERROR_ID 0x41
void CanIf_Init(const CanIf_ConfigType *ConfigPtr);
void CanIf_ControllerBusOff( uint8 Controller );\r
void CanIf_SetWakeupEvent( uint8 Controller );\r
\r
-/* Ecore extensions */\r
-void CanIf_EcoreError( uint8 Controller, Can_EcoreErrorType Error );\r
+/* ArcCore extensions */\r
+void CanIf_Arc_Error( uint8 Controller, Can_Arc_ErrorType Error );\r
\r
#endif /*CANIF_CBK_H_*/\r
#define COM_H_\r
\r
#include "Std_Types.h"\r
-#include "Com_Types.h"\r
-#include "Com_EcoreTypes.h"\r
+#include "ComStack_Types.h"\r
+#include "Com_Arc_Types.h"\r
\r
\r
#ifdef COM_DEV_ERROR_DETECT\r
#define COM_SW_MINOR_VERSION 0
#define COM_SW_PATCH_VERSION 0
\r
-#include "Com_Cfg.h"\r
+#include "Com_Cfg.h"
+#include "Com_Types.h"\r
#include "Com_PbCfg.h"\r
#include "Com_Com.h"\r
#include "Com_Sched.h"\r
\r
const Com_ConfigType * ComConfig;\r
\r
-ComEcoreConfig_type ComEcoreConfig;\r
+Com_Arc_Config_type Com_Arc_Config;\r
\r
\r
\r
\r
// Define macro for parameter check.\r
#define PduIdCheck(PduId,ApiId,...) \\r
- if (PduId >= ComEcoreConfig.ComNIPdu) { \\r
+ if (PduId >= Com_Arc_Config.ComNIPdu) { \\r
DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_INVALID_PDU_ID); \\r
return __VA_ARGS__; \\r
} \\r
\r
#define COM_VALIDATE_SIGNAL(SignalId, ApiId, ...) \\r
- if (ComConfig->ComSignal[SignalId].ComEcoreIsSignalGroup) { \\r
+ if (ComConfig->ComSignal[SignalId].Com_Arc_IsSignalGroup) { \\r
DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_ERROR_SIGNAL_IS_SIGNALGROUP); \\r
return __VA_ARGS__; \\r
} \\r
#define ComGetSignal(SignalId) \\r
const ComSignal_type * Signal = &ComConfig->ComSignal[SignalId]\\r
\r
-#define ComGetEcoreSignal(SignalId) \\r
- ComEcoreSignal_type * EcoreSignal = &ComEcoreConfig.ComSignal[SignalId]\\r
+#define ComGetArcSignal(SignalId) \\r
+ Com_Arc_Signal_type * Arc_Signal = &Com_Arc_Config.ComSignal[SignalId]\\r
\r
#define ComGetIPdu(IPduId) \\r
const ComIPdu_type *IPdu = &ComConfig->ComIPdu[IPduId]\\r
\r
-#define ComGetEcoreIPdu(IPduId) \\r
- ComEcoreIPdu_type *EcoreIPdu = &ComEcoreConfig.ComIPdu[IPduId]\\r
+#define ComGetArcIPdu(IPduId) \\r
+ Com_Arc_IPdu_type *Arc_IPdu = &Com_Arc_Config.ComIPdu[IPduId]\\r
\r
#define ComGetGroupSignal(GroupSignalId) \\r
const ComGroupSignal_type *GroupSignal = &ComConfig->ComGroupSignal[GroupSignalId]\\r
\r
-#define ComGetEcoreGroupSignal(GroupSignalId) \\r
- ComEcoreGroupSignal_type *EcoreGroupSignal = &ComEcoreConfig.ComGroupSignal[GroupSignalId]\\r
+#define ComGetArcGroupSignal(GroupSignalId) \\r
+ Com_Arc_GroupSignal_type *Arc_GroupSignal = &Com_Arc_Config.ComGroupSignal[GroupSignalId]\\r
\r
//-------------------------------------------------------------------\r
// From OSEK_VDX spec...\r
#ifndef COMSTACK_TYPES_H_\r
#define COMSTACK_TYPES_H_\r
+
+#define ECUC_SW_MAJOR_VERSION 1
+#define ECUC_SW_MINOR_VERSION 0
+#define ECUC_SW_PATCH_VERSION 0
\r
#include "Std_Types.h"\r
\r
uint32 ComFilterX;\r
\r
\r
- uint32 ComFilterEcoreN;\r
- uint32 ComFilterEcoreNewValue;\r
- uint32 ComFilterEcoreOldValue;\r
+ uint32 ComFilterArcN;\r
+ uint32 ComFilterArcNewValue;\r
+ uint32 ComFilterArcOldValue;\r
\r
} ComFilter_type;\r
\r
*\r
* Comment: This is initialized by Com_Init() and should not be configured.\r
*/\r
- //void *ComEcoreShadowBuffer;\r
+ //void *Com_Arc_ShadowBuffer;\r
\r
\r
/* IPDU id of the IPDU that this signal belongs to.\r
//const uint8 ComIPduHandleId;\r
//const uint8 ComSignalUpdated;\r
\r
- const uint8 ComEcoreEOL;\r
+ const uint8 Com_Arc_EOL;\r
} ComGroupSignal_type;\r
\r
typedef struct {\r
* - Receive\r
* - Not required.\r
*/\r
- //const uint32 ComEcoreDeadlineCounter;\r
+ //const uint32 Com_Arc_DeadlineCounter;\r
const uint32 ComTimeoutFactor;\r
\r
/* Timeout notification function\r
* - Send and receive.\r
* - Not required.\r
*\r
- * Comment: Range 0 to 63. If update bit is used for this signal, then the corresponding parameter ComSignalEcoreUseUpdateBit\r
+ * Comment: Range 0 to 63. If update bit is used for this signal, then the corresponding parameter ComSignalArcUseUpdateBit\r
* needs to be set to one.
*/\r
const uint8 ComUpdateBitPosition;\r
- const uint8 ComSignalEcoreUseUpdateBit;\r
+ const uint8 ComSignalArcUseUpdateBit;\r
\r
/* Filter for this signal\r
*\r
\r
\r
/**** SIGNAL GROUP DATA ****/\r
- const uint8 ComEcoreIsSignalGroup;\r
+ const uint8 Com_Arc_IsSignalGroup;\r
const ComGroupSignal_type *ComGroupSignal[COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP];\r
- //void *ComEcoreShadowBuffer;\r
- //void *ComEcoreIPduDataPtr;\r
+ //void *Com_Arc_ShadowBuffer;\r
+ //void *Com_Arc_IPduDataPtr;\r
\r
\r
/* Pointer to the data storage of this signals IPDU.\r
//const uint8 ComSignalUpdated;\r
\r
\r
- const uint8 ComEcoreEOL;\r
+ const uint8 Com_Arc_EOL;\r
} ComSignal_type;\r
\r
\r
// reference to the group that this group possibly belongs to.\r
//struct ComIPduGroup_type *ComIPduGroupRef;\r
\r
- const uint8 ComEcoreEOL;\r
+ const uint8 Com_Arc_EOL;\r
} ComIPduGroup_type;\r
\r
\r
*\r
* Comment: These are internal variables and should not be configured.
*/\r
- //ComTxIPduTimer_type ComEcoreTxIPduTimers;\r
+ //ComTxIPduTimer_type Com_Arc_TxIPduTimers;\r
\r
/* Pointer to data storage of this IPDU.\r
*\r
*\r
* Comment: It probably makes little sense not to define at least one signal for each IPDU.\r
*/\r
- //const uint8 ComEcoreNIPduSignalGroupRef;\r
+ //const uint8 Com_Arc_NIPduSignalGroupRef;\r
const ComSignal_type *ComIPduSignalGroupRef[COM_MAX_NR_SIGNALS_PER_IPDU];\r
\r
\r
/*\r
* The following two variables are used to control the per I-PDU based Rx/Tx-deadline monitoring.\r
*/\r
- //const uint32 ComEcoreDeadlineCounter;\r
- //const uint32 ComEcoreTimeoutFactor;\r
+ //const uint32 Com_Arc_DeadlineCounter;\r
+ //const uint32 Com_Arc_TimeoutFactor;\r
\r
- const uint8 ComEcoreEOL;\r
+ const uint8 Com_Arc_EOL;\r
\r
} ComIPdu_type;\r
\r
// IPDU definitions. At least one\r
const ComIPdu_type *ComIPdu;\r
\r
- //uint16 ComEcoreNIPdu;\r
+ //uint16 Com_Arc_NIPdu;\r
\r
// IPDU group definitions\r
const ComIPduGroup_type *ComIPduGroup;\r
\r
typedef uint32_t imask_t;\r
\r
-/* ecore extensions */\r
+/* ArcCore extensions */\r
void IntCtrl_InstallVector(void (*func)(), IrqType vector, uint8_t priority, Cpu_t cpu );\r
void IntCtrl_GenerateSoftInt( IrqType vector );\r
uint8_t IntCtrl_GetCurrentPriority( Cpu_t cpu);\r
* -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-/*\r
- * (C) Copyright 2008 ecore, www.ecore.se\r
- */
\r
#ifndef OS_H_\r
#define OS_H_\r
#endif\r
\r
#define RES_SCHEDULER 0\r
-//DeclareResource(RES_SCHEDULER);\r
+//DeclareResource(RES_SCHEDULER);
+#define OS_TASK_PRIORITY_MIN 0
+#define OS_TASK_PRIORITY_MAX 31\r
\r
typedef struct OsDriver_s {\r
int OsGptChannelRef;\r
/*-------------------------------------------------------------------\r
* Counters\r
*-----------------------------------------------------------------*/\r
-typedef uint16 CounterType;\r
+typedef sint16 CounterType;
\r
typedef uint32 TickType;\r
typedef TickType *TickRefType;\r
StatusType ReceiveMessage( MessageType message_id, ApplicationDataRef dataRef );\r
\r
/*\r
- * ecore extensions\r
+ * ArcCore extensions\r
*/\r
TickType GetOsTick();\r
void OsTick(void);\r
void OsIdle(void);\r
\r
-/* The OS always have counter 0 */\r
-#define OS_TICK_COUNTER 0\r
-\r
// Generate conversion macro'\r
// Todo\r
#define OS_TICK2NS_OS_TICK_COUNTER(_x)\r
#elif defined(CFG_MPC5516) || defined(MPC5517)\r
#include "mpc5516.h"\r
#elif defined(CFG_MPC5567)\r
-#include "mpc5567.h"\r
+#include "mpc5567.h"
+#elif defined(CFG_MPC5633)
+#include "mpc563m.h"\r
#else\r
#error NO MCU SELECTED!!!!\r
#endif\r
# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple clean\r
#\r
\r
-\r
-\r
-#-include board_config.mk\r
-#export ARCH\r
-#export ARCH_FAM\r
-#export BOARDDIR\r
-\r
export UNAME:=$(shell uname)\r
\r
ifneq ($(findstring Darwin,$(UNAME)),)\r
export RELEASE = n\r
export PATH\r
\r
-#ifeq (${BDIR},)\r
-# -include saved_config.mk\r
-#endif\r
-\r
ifneq ($(filter clean_all,$(MAKECMDGOALS)),clean_all)\r
ifeq (${BOARDDIR},)\r
$(error BOARDDIR is empty) \r
export RELEASE_TREE=n\r
\r
override BDIR := system/kernel ${BDIR} \r
-#BDIR += system/kernel/testsystem\r
-\r
-# Misc\r
-#subdir-y += ecum\r
-# Drivers\r
-\r
\r
# Tools\r
# Ugly thing to make things work under cmd.exe \r
\r
export objdir = obj_$(BOARDDIR)\r
\r
-#comma = ,\r
-#empty = \r
-#space = $(empty) $(empty) \r
-\r
.PHONY: clean\r
.PHONY: release\r
\r
@echo " CROSS_COMPILE =$(CROSS_COMPILE)"\r
@echo ""\r
\r
-def-$(USE_T32_SIM) += USE_T32_SIM\r
def-$(USE_DBG_PRINTF) += USE_DBG_PRINTF\r
\r
\r
export MCU\r
export def-y+=$(CFG_ARCH_$(ARCH)) $(CFG_MCU) $(CFG_CPU)\r
\r
-BASEDIR = $(TOPDIR)/$(MOD)\r
-\r
# We descend into the object directories and build the. That way it's easier to build\r
# multi-arch support and we don't have to use objdir everywhere.\r
# ROOTDIR - The top-most directory\r
# SUBDIR - The current subdirectory it's building.\r
\r
-test:\r
- make embUnit/textui embunit/embUnit drivers/test all\r
-\r
comma:= ,\r
split = $(subst $(comma), ,$(1))\r
-\r
-\r
-#dir_cmd_goals := $(filter-out %_config config testa all install uninstall clean test save,$(MAKECMDGOALS))\r
dir_cmd_goals := $(call split,$(BDIR))\r
-\r
cmd_cmd_goals := $(filter clean all install,$(MAKECMDGOALS))\r
\r
-#$(error $(dir_cmd_goals) $(MAKECMDGOALS))\r
-\r
libs:\r
mkdir -p $@\r
\r
+@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
@chmod 777 $@/$(objdir)\r
$(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ $(cmd_cmd_goals)\r
-\r
-\r
-# --no-print-directory\r
-\r
.PHONY: test \r
\r
FORCE:\r
FLS_SST25XX_ERASE,\r
FLS_SST25XX_READ,\r
FLS_SST25XX_WRITE,\r
-} Fls_SST25xx_EcoreJobType;\r
+} Fls_SST25xx_Arc_JobType;\r
\r
/* Spi job state */\r
typedef enum {\r
Fls_AddressType flsAddr;\r
uint32 left;\r
Job_StateType state;\r
- Fls_SST25xx_EcoreJobType mainState;\r
+ Fls_SST25xx_Arc_JobType mainState;\r
Spi_SequenceType currSeq;\r
uint32 chunkSize;\r
} Fls_SST25xx_JobInfoType;\r
// Status of driver\r
MemIf_StatusType status;\r
MemIf_JobResultType jobResultType;\r
- Fls_SST25xx_EcoreJobType jobType;\r
+ Fls_SST25xx_Arc_JobType jobType;\r
\r
// Saved information from API calls.\r
Fls_AddressType flsAddr;\r
void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
{\r
#if defined(USE_CANIF)\r
- // Startup the CAN interafce; due to the missing COM manager\r
- CanIf_InitController(CAN_CTRL_A, 0);\r
- CanIf_SetControllerMode(CAN_CTRL_A, CANIF_CS_STARTED);\r
+ // Startup the CAN interface; due to the missing COM manager\r
+ CanIf_InitController(CANIF_CHANNEL_0, CANIF_CHANNEL_0_CONFIG_0);\r
+ CanIf_SetControllerMode(CANIF_CHANNEL_0, CANIF_CS_STARTED);\r
#endif\r
}\r
* The OsTick():\r
* 1. The Decrementer is setup by Frt_Start(period_ticks)\r
* 2. Frt_Init() setup INTC[7] to trigger OsTick\r
- * 3. OsTick() then increment counter 0\r
- * ( COUNTER_ID_OS_TICK = OS_TICK_COUNTER )\r
+ * 3. OsTick() then increment counter os_tick_counter if used
*/\r
\r
/*\r
* Non-Autosar stuff\r
*/\r
-\r
-void OsTick( void ) {\r
- counter_obj_t *c_p = Oil_GetCounter(OS_TICK_COUNTER);\r
-\r
- os_sys.tick++;\r
-\r
- IncCounter(c_p);\r
-\r
-// os_sys.tick = c_p->val;\r
-\r
- check_alarms(c_p);\r
- check_stbl(c_p);\r
+
+/* The id of the counter driven by the os tick, or -1 if not used.
+ * Using weak linking to set default value -1 if not set by config.
+ */
+CounterType Os_Arc_OsTickCounter __attribute__((weak)) = -1;
+\r
+void OsTick( void ) {
+ // if not used, os_tick_counter < 0
+ if (Os_Arc_OsTickCounter >= 0) {
+
+ counter_obj_t *c_p = Oil_GetCounter(Os_Arc_OsTickCounter);
+
+ os_sys.tick++;
+
+ IncCounter(c_p);
+
+ // os_sys.tick = c_p->val;
+
+ check_alarms(c_p);
+ check_stbl(c_p);
+ }
}\r
\r
#if 0\r
pcb_t *pcb = os_alloc_new_pcb();\r
strncpy(pcb->name,name,TASK_NAME_SIZE);\r
pcb->vector = -1;\r
- pcb->prio = prio;\r
+ pcb->prio = prio;
+ /* TODO: map to interrupt controller priority */
+ assert(prio<=OS_TASK_PRIORITY_MAX);\r
pcb->proc_type = PROC_ISR2;\r
pcb->state = ST_SUSPENDED;\r
pcb->entry = entry;\r
- pcb->stack.top = &stackTop;\r
+ pcb->stack.top = &stackTop;
+\r
\r
return os_add_task(pcb);\r
}\r
// TODO: Isn't this just EXTENED tasks ???
for( i=0; i < Oil_GetTaskCnt(); i++) {
tmp_pcb = os_get_pcb(i);
+ assert(tmp_pcb->prio<=OS_TASK_PRIORITY_MAX);
os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));
if( !(tmp_pcb->proc_type & PROC_ISR) ) {
os_pcb_make_virgin(tmp_pcb);
\r
\r
GEN_COUNTER_HEAD {\r
- GEN_COUNTER(COUNTER_ID_os_tick, "OS_TICK_COUNTER",COUNTER_TYPE_HARD,\r
+ GEN_COUNTER(COUNTER_ID_os_tick, "COUNTER_ID_OsTick",COUNTER_TYPE_HARD,\r
COUNTER_UNIT_NANO, 0xffff,1,1,0 ),\r
GEN_COUNTER(COUNTER_ID_soft_1, "counter_soft_1",COUNTER_TYPE_SOFT,\r
COUNTER_UNIT_NANO, 10,1,1,0),\r
GEN_COUNTER(COUNTER_ID_soft_2, "counter_soft_2",COUNTER_TYPE_SOFT,\r
COUNTER_UNIT_NANO, 100,1,1,0),\r
};\r
+
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;
\r
//-------------------------------------------------------------------\r
\r
#ifdef ALARM_USE\r
GEN_ALARM_HEAD {\r
{\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
.action =\r
{\r
.type = ALARM_ACTION_ACTIVATETASK,\r
},\r
{\r
/* Set EVENT_1 in etask_sup_m, driven by soft counter */\r
- .counter = &counter_list[OS_TICK_COUNTER],\r
- .counter_id = OS_TICK_COUNTER,\r
+ .counter = &counter_list[COUNTER_ID_OsTick],\r
+ .counter_id = COUNTER_ID_OsTick,\r
.action = {\r
.type = ALARM_ACTION_SETEVENT,\r
.task_id = TASK_ID_etask_sup_m,\r
#define RES_ID_INT_1 1\r
#define RES_ID_EXT_1 2\r
\r
-// OS_TICK_COUNTER located in Os.h\r
+#define COUNTER_ID_OsTick 0\r
// Driver all alarms\r
#define COUNTER_ID_soft_1 1\r
// Drives scheduletable 0\r
pos 1. 1. 14.\r
text "CPU:"\r
pos 1. 2. 10.\r
-CPU: PULLDOWN "mpc5516,mpc5554,CortexM3"\r
+CPU: PULLDOWN "mpc5516,mpc5554,mpc5633M,CortexM3"\r
(\r
)\r
HEADER "Project config"\r
save_close:\r
&cfg_cpu_g=dialog.string(CPU)\r
&cfg_project_path_g=dialog.string(P_PATH)\r
+ sys.cpu &cfg_cpu_g\r
do config save\r
win_close:\r
dialog.end\r
\r
\r
\r
+\r
\r
\r
\r
postload_MPC5516:\r
postload_MPC5554:\r
+postload_mpc5633M:\r
RETURN\r
\r
//-------------------------------------------------------------\r
\r
\r
\r
+\r
\r
\r
projects / arc.git / commitdiff