#endif\r
}\r
\r
-\r
-#if 0\r
-void Adc_ConfigureEQADCInterrupts (void)\r
-{\r
- Adc_GroupType group;\r
-\r
-#if defined(USE_KERNEL)\r
- TaskType tid;\r
- tid = Os_Arc_CreateIsr(Adc_EQADCError,EQADC_FISR_OVER_PRIORITY,"Adc_Err");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR_OVER);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group0ConversionComplete,EQADC_FIFO0_END_OF_QUEUE_PRIORITY,"Adc_Grp0");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR0_EOQF0);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group1ConversionComplete,EQADC_FIFO1_END_OF_QUEUE_PRIORITY,"Adc_Grp1");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR1_EOQF1);\r
-\r
-#else\r
- Irq_InstallVector (Adc_EQADCError,\r
- EQADC_FISR_OVER,\r
- EQADC_FISR_OVER_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group0ConversionComplete,\r
- EQADC_FISR0_EOQF0,\r
- EQADC_FIFO0_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group1ConversionComplete,\r
- EQADC_FISR1_EOQF1,\r
- EQADC_FIFO1_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
-#endif\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
- {\r
- /* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
- EQADC.FISR[group].B.RFOF = 1;\r
- EQADC.IDCR[group].B.RFOIE = 1;\r
-\r
- EQADC.FISR[group].B.CFUF = 1;\r
- EQADC.IDCR[group].B.CFUIE = 1;\r
-\r
- EQADC.FISR[group].B.TORF = 1;\r
- EQADC.IDCR[group].B.TORIE = 1;\r
-\r
- EQADC.FISR[group].B.EOQF = 1;\r
- EQADC.IDCR[group].B.EOQIE = 1;\r
- }\r
-}\r
-#endif\r
-\r
#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
void Adc_StartGroupConversion (Adc_GroupType group)\r
{\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.c\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief This file provides all the miscellaneous firmware functions (add-on\r
- * to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "misc.h"\r
-
-#define assert_param(expr) ((void)0)
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC \r
- * @brief MISC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup MISC_Private_Defines\r
- * @{\r
- */\r
-\r
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
- * 4 bits for subpriority\r
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
- * 0 bits for subpriority\r
- * @retval None\r
- */\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
- \r
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
-}\r
-\r
-/**\r
- * @brief Initializes the NVIC peripheral according to the specified\r
- * parameters in the NVIC_InitStruct.\r
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
- * the configuration information for the specified NVIC peripheral.\r
- * @retval None\r
- */\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
-{\r
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
- \r
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
- {\r
- /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
- tmppre = (0x4 - tmppriority);\r
- tmpsub = tmpsub >> tmppriority;\r
-\r
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
- tmppriority = tmppriority << 0x04;\r
- \r
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
- \r
- /* Enable the Selected IRQ Channels --------------------------------------*/\r
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
- else\r
- {\r
- /* Disable the Selected IRQ Channels -------------------------------------*/\r
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the vector table location and Offset.\r
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_VectTab_RAM\r
- * @arg NVIC_VectTab_FLASH\r
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
- * @retval None\r
- */\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
- assert_param(IS_NVIC_OFFSET(Offset)); \r
- \r
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
-}\r
-\r
-/**\r
- * @brief Selects the condition for the system to enter low power mode.\r
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_LP_SEVONPEND\r
- * @arg NVIC_LP_SLEEPDEEP\r
- * @arg NVIC_LP_SLEEPONEXIT\r
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_LP(LowPowerMode));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- SCB->SCR |= LowPowerMode;\r
- }\r
- else\r
- {\r
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the SysTick clock source.\r
- * @param SysTick_CLKSource: specifies the SysTick clock source.\r
- * This parameter can be one of the following values:\r
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
- * @retval None\r
- */\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
- {\r
- SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
- }\r
- else\r
- {\r
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-
-/**\r
- ******************************************************************************\r
- * @file misc.h\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief This file contains all the functions prototypes for the miscellaneous\r
- * firmware library functions (add-on to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MISC_H\r
-#define __MISC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup MISC\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief NVIC Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
- This parameter can be a value of @ref IRQn_Type \r
- (For the complete STM32 Devices IRQ Channels list, please\r
- refer to stm32f10x.h file) */\r
-\r
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
- specified in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
- in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
- will be enabled or disabled. \r
- This parameter can be set either to ENABLE or DISABLE */ \r
-} NVIC_InitTypeDef;\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup NVIC_Priority_Table \r
- * @{\r
- */\r
-\r
-/**\r
-@code \r
- The table below gives the allowed values of the pre-emption priority and subpriority according\r
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
- ============================================================================================================================\r
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
- ============================================================================================================================\r
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
- | | | 4 bits for subpriority\r
- ----------------------------------------------------------------------------------------------------------------------------\r
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
- | | | 3 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
- | | | 2 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
- | | | 1 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
- | | | 0 bits for subpriority \r
- ============================================================================================================================\r
-@endcode\r
-*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Vector_Table_Base \r
- * @{\r
- */\r
-\r
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
- ((VECTTAB) == NVIC_VectTab_FLASH))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup System_Low_Power \r
- * @{\r
- */\r
-\r
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
- ((LP) == NVIC_LP_SLEEPDEEP) || \\r
- ((LP) == NVIC_LP_SLEEPONEXIT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Preemption_Priority_Group \r
- * @{\r
- */\r
-\r
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
- 4 bits for subpriority */\r
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
- 3 bits for subpriority */\r
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
- 2 bits for subpriority */\r
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
- 1 bits for subpriority */\r
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
- 0 bits for subpriority */\r
-\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
- ((GROUP) == NVIC_PriorityGroup_1) || \\r
- ((GROUP) == NVIC_PriorityGroup_2) || \\r
- ((GROUP) == NVIC_PriorityGroup_3) || \\r
- ((GROUP) == NVIC_PriorityGroup_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SysTick_clock_source \r
- * @{\r
- */\r
-\r
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MISC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
#include "task_i.h"
#include "hooks.h"
#include "stm32f10x.h"
-#include "misc.h"
#include "irq.h"
#include "core_cm3.h"
extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+/*
+* PRIGROUP[2:0] Group prios Sub prios
+* 0b011 16 None
+* 0b100 8 2
+* 0b101 4 4
+* 0b110 2 8
+* 0b111 None 16
+*/
+#define AIRCR_VECTKEY ((uint32_t)0x05FA0000)
+
+/** Set NVIC prio group */
+static void NVIC_SetPrioGroup(uint32_t prioGroup)
+{
+ SCB->AIRCR = AIRCR_VECTKEY | (prioGroup<<8);
+}
+
void Irq_Init( void ) {
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
+ NVIC_SetPrioGroup(3); // No sub prioritys
}
void Irq_EOI( void ) {
return (SCB->ICSR & ICSR_VECTACTIVE);
}
+/**
+ * Init NVIC vector. We do not use subriority
+ *
+ */
+static void NVIC_InitVector(uint8_t vector, uint32_t prio)
+{
+ // Set prio
+ NVIC->IP[vector] = prio;
+
+ // Enable
+ NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
+}
+
/**
*
* @param stack_p Ptr to the current stack.
*/
void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
- // TODO: Use NVIC_Init here
- /*
- NVIC_InitTypeDef NVIC_InitStructure;
-
- // Enable and configure RCC global IRQ channel
- NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
- */
+ // TODO: Use NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio)); here
}
static inline int osPrioToCpuPio( uint8_t prio ) {
*/
void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
OsPcbType *pcb;
- NVIC_InitTypeDef irqInit;
pcb = os_find_task(tid);
Irq_VectorTable[vector+16] = (void *)pcb;
- irqInit.NVIC_IRQChannel = vector;
- irqInit.NVIC_IRQChannelPreemptionPriority = osPrioToCpuPio(pcb->prio);
- irqInit.NVIC_IRQChannelSubPriority = 0;
- irqInit.NVIC_IRQChannelCmd = ENABLE;
-
-
- // TODO: Same as for AttachIsr1
- NVIC_Init(&irqInit);
+ NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
}
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+.word _sidata\r
+.word _sdata\r
+.word _edata\r
+.word _sbss\r
+.word _ebss\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+* Vector table for a Cortex M3. Vectors start at addr 0x0.\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+ .extern Irq_Handler\r
+\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word Irq_Handler+1 /* SysTick */\r
+ .rept 83\r
+ .word Irq_Handler+1\r
+ .endr\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+\r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_cl.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR \r
- * address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word CAN1_TX_IRQHandler\r
- .word CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word OTG_FS_WKUP_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word TIM5_IRQHandler \r
- .word SPI3_IRQHandler \r
- .word UART4_IRQHandler \r
- .word UART5_IRQHandler \r
- .word TIM6_IRQHandler \r
- .word TIM7_IRQHandler \r
- .word DMA2_Channel1_IRQHandler \r
- .word DMA2_Channel2_IRQHandler \r
- .word DMA2_Channel3_IRQHandler \r
- .word DMA2_Channel4_IRQHandler \r
- .word DMA2_Channel5_IRQHandler \r
- .word ETH_IRQHandler \r
- .word ETH_WKUP_IRQHandler \r
- .word CAN2_TX_IRQHandler \r
- .word CAN2_RX0_IRQHandler \r
- .word CAN2_RX1_IRQHandler \r
- .word CAN2_SCE_IRQHandler \r
- .word OTG_FS_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x Connectivity line Devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_TX_IRQHandler\r
- .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX0_IRQHandler\r
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_WKUP_IRQHandler\r
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler \r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler \r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler \r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler \r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler \r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler \r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler \r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler \r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_IRQHandler \r
- .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel5_IRQHandler \r
- .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak ETH_IRQHandler \r
- .thumb_set ETH_IRQHandler,Default_Handler\r
-\r
- .weak ETH_WKUP_IRQHandler \r
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_TX_IRQHandler \r
- .thumb_set CAN2_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX0_IRQHandler \r
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX1_IRQHandler \r
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_SCE_IRQHandler \r
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_IRQHandler \r
- .thumb_set OTG_FS_IRQHandler ,Default_Handler\r
-#endif\r
- \r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_hd.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. \r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address,\r
- * - Configure external SRAM mounted on STM3210E-EVAL board\r
- * to be used as data memory (optional, to be enabled by user)\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
-\r
-.equ Initial_spTop, 0x20000400 \r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
- bl SystemInit_ExtMemCtl\r
-/* restore original stack pointer */ \r
- LDR r0, =_estack\r
- MSR msp, r0\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief Dummy SystemInit_ExtMemCtl function \r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits\r
-SystemInit_ExtMemCtl_Dummy:\r
- bx lr\r
- .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word Initial_spTop\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler\r
- .word TIM8_BRK_IRQHandler\r
- .word TIM8_UP_IRQHandler\r
- .word TIM8_TRG_COM_IRQHandler\r
- .word TIM8_CC_IRQHandler\r
- .word ADC3_IRQHandler\r
- .word FSMC_IRQHandler\r
- .word SDIO_IRQHandler\r
- .word TIM5_IRQHandler\r
- .word SPI3_IRQHandler\r
- .word UART4_IRQHandler\r
- .word UART5_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word DMA2_Channel1_IRQHandler\r
- .word DMA2_Channel2_IRQHandler\r
- .word DMA2_Channel3_IRQHandler\r
- .word DMA2_Channel4_5_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x High Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_BRK_IRQHandler\r
- .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_UP_IRQHandler\r
- .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_TRG_COM_IRQHandler\r
- .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_CC_IRQHandler\r
- .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
-\r
- .weak ADC3_IRQHandler\r
- .thumb_set ADC3_IRQHandler,Default_Handler\r
-\r
- .weak FSMC_IRQHandler\r
- .thumb_set FSMC_IRQHandler,Default_Handler\r
-\r
- .weak SDIO_IRQHandler\r
- .thumb_set SDIO_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler\r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler\r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler\r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler\r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler\r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler\r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_5_IRQHandler\r
- .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler\r
-\r
- .weak SystemInit_ExtMemCtl\r
- .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_ld.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- 0\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- 0\r
- 0\r
- .word SPI1_IRQHandler\r
- 0\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- 0\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Low Density devices.*/\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler \r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_md.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
-\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Medium Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
-#endif\r
vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel\r
obj-$(CFG_ARM_CM3) += system_stm32f10x.o\r
obj-$(CFG_ARM_CM3) += core_cm3.o\r
-\r
-obj-$(CFG_STM32_MD) += startup_stm32f10x_md.o\r
-obj-$(CFG_STM32_LD) += startup_stm32f10x_ld.o\r
-obj-$(CFG_STM32_HD) += startup_stm32f10x_hd.o\r
-obj-$(CFG_STM32_CL) += startup_stm32f10x_cl.o\r
+obj-$(CFG_ARM_CM3) += startup_stm32f10x.o\r
\r
#Ecu\r
#obj-y += EcuM_$(BOARDDIR).o\r
dep-y += asm_offset.h\r
dep-y += kernel_offset.h\r
dep-$(CFG_ARM_CM3) += arch_offset.h\r
-obj-$(CFG_ARM_CM3) += misc.o\r
\r
\r
# ARM assembler generates "define STACK_APA $12". The extra '$' we want to go.\r
projects / arc.git / commitdiff