/* MODULE : eDMA */\r
/****************************************************************************/\r
#include "ip_edma.h"\r
- CC_EXTENSION struct EDMA_tag {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t GRP3PRI:2;\r
- vuint32_t GRP2PRI:2;\r
- vuint32_t GRP1PRI:2;\r
- vuint32_t GRP0PRI:2;\r
- vuint32_t:4;\r
- vuint32_t ERGA:1;\r
- vuint32_t ERCA:1;\r
- vuint32_t EDBG:1;\r
- vuint32_t EBW:1;\r
- } B;\r
- } CR; /* Control Register */\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t VLD:1;\r
- vuint32_t:15;\r
- vuint32_t GPE:1;\r
- vuint32_t CPE:1;\r
- vuint32_t ERRCHN:6;\r
- vuint32_t SAE:1;\r
- vuint32_t SOE:1;\r
- vuint32_t DAE:1;\r
- vuint32_t DOE:1;\r
- vuint32_t NCE:1;\r
- vuint32_t SGE:1;\r
- vuint32_t SBE:1;\r
- vuint32_t DBE:1;\r
- } B;\r
- } ES; /* Error Status Register */\r
- uint32_t edma_reserved_erqrh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t ERQ31:1;\r
- vuint32_t ERQ30:1;\r
- vuint32_t ERQ29:1;\r
- vuint32_t ERQ28:1;\r
- vuint32_t ERQ27:1;\r
- vuint32_t ERQ26:1;\r
- vuint32_t ERQ25:1;\r
- vuint32_t ERQ24:1;\r
- vuint32_t ERQ23:1;\r
- vuint32_t ERQ22:1;\r
- vuint32_t ERQ21:1;\r
- vuint32_t ERQ20:1;\r
- vuint32_t ERQ19:1;\r
- vuint32_t ERQ18:1;\r
- vuint32_t ERQ17:1;\r
- vuint32_t ERQ16:1;\r
- vuint32_t ERQ15:1;\r
- vuint32_t ERQ14:1;\r
- vuint32_t ERQ13:1;\r
- vuint32_t ERQ12:1;\r
- vuint32_t ERQ11:1;\r
- vuint32_t ERQ10:1;\r
- vuint32_t ERQ09:1;\r
- vuint32_t ERQ08:1;\r
- vuint32_t ERQ07:1;\r
- vuint32_t ERQ06:1;\r
- vuint32_t ERQ05:1;\r
- vuint32_t ERQ04:1;\r
- vuint32_t ERQ03:1;\r
- vuint32_t ERQ02:1;\r
- vuint32_t ERQ01:1;\r
- vuint32_t ERQ00:1;\r
- } B;\r
- } ERQL; /* DMA Enable Request Register Low */\r
- uint32_t edma_reserved_eeirh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t EEI31:1;\r
- vuint32_t EEI30:1;\r
- vuint32_t EEI29:1;\r
- vuint32_t EEI28:1;\r
- vuint32_t EEI27:1;\r
- vuint32_t EEI26:1;\r
- vuint32_t EEI25:1;\r
- vuint32_t EEI24:1;\r
- vuint32_t EEI23:1;\r
- vuint32_t EEI22:1;\r
- vuint32_t EEI21:1;\r
- vuint32_t EEI20:1;\r
- vuint32_t EEI19:1;\r
- vuint32_t EEI18:1;\r
- vuint32_t EEI17:1;\r
- vuint32_t EEI16:1;\r
- vuint32_t EEI15:1;\r
- vuint32_t EEI14:1;\r
- vuint32_t EEI13:1;\r
- vuint32_t EEI12:1;\r
- vuint32_t EEI11:1;\r
- vuint32_t EEI10:1;\r
- vuint32_t EEI09:1;\r
- vuint32_t EEI08:1;\r
- vuint32_t EEI07:1;\r
- vuint32_t EEI06:1;\r
- vuint32_t EEI05:1;\r
- vuint32_t EEI04:1;\r
- vuint32_t EEI03:1;\r
- vuint32_t EEI02:1;\r
- vuint32_t EEI01:1;\r
- vuint32_t EEI00:1;\r
- } B;\r
- } EEIL; /* DMA Enable Error Interrupt Register Low */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SERQ; /* DMA Set Enable Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CERQ; /* DMA Clear Enable Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SEEI; /* DMA Set Enable Error Interrupt Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CEEI; /* DMA Clear Enable Error Interrupt Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CINT; /* DMA Clear Interrupt Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CERR; /* DMA Clear error Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SSRT; /* Set Start Bit Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CDNE; /* Clear Done Status Bit Register */\r
- uint32_t edma_reserved_irqrh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t INT31:1;\r
- vuint32_t INT30:1;\r
- vuint32_t INT29:1;\r
- vuint32_t INT28:1;\r
- vuint32_t INT27:1;\r
- vuint32_t INT26:1;\r
- vuint32_t INT25:1;\r
- vuint32_t INT24:1;\r
- vuint32_t INT23:1;\r
- vuint32_t INT22:1;\r
- vuint32_t INT21:1;\r
- vuint32_t INT20:1;\r
- vuint32_t INT19:1;\r
- vuint32_t INT18:1;\r
- vuint32_t INT17:1;\r
- vuint32_t INT16:1;\r
- vuint32_t INT15:1;\r
- vuint32_t INT14:1;\r
- vuint32_t INT13:1;\r
- vuint32_t INT12:1;\r
- vuint32_t INT11:1;\r
- vuint32_t INT10:1;\r
- vuint32_t INT09:1;\r
- vuint32_t INT08:1;\r
- vuint32_t INT07:1;\r
- vuint32_t INT06:1;\r
- vuint32_t INT05:1;\r
- vuint32_t INT04:1;\r
- vuint32_t INT03:1;\r
- vuint32_t INT02:1;\r
- vuint32_t INT01:1;\r
- vuint32_t INT00:1;\r
- } B;\r
- } INTL; /* DMA Interrupt Request Low */\r
- uint32_t edma_reserved_erh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t ERR31:1;\r
- vuint32_t ERR30:1;\r
- vuint32_t ERR29:1;\r
- vuint32_t ERR28:1;\r
- vuint32_t ERR27:1;\r
- vuint32_t ERR26:1;\r
- vuint32_t ERR25:1;\r
- vuint32_t ERR24:1;\r
- vuint32_t ERR23:1;\r
- vuint32_t ERR22:1;\r
- vuint32_t ERR21:1;\r
- vuint32_t ERR20:1;\r
- vuint32_t ERR19:1;\r
- vuint32_t ERR18:1;\r
- vuint32_t ERR17:1;\r
- vuint32_t ERR16:1;\r
- vuint32_t ERR15:1;\r
- vuint32_t ERR14:1;\r
- vuint32_t ERR13:1;\r
- vuint32_t ERR12:1;\r
- vuint32_t ERR11:1;\r
- vuint32_t ERR10:1;\r
- vuint32_t ERR09:1;\r
- vuint32_t ERR08:1;\r
- vuint32_t ERR07:1;\r
- vuint32_t ERR06:1;\r
- vuint32_t ERR05:1;\r
- vuint32_t ERR04:1;\r
- vuint32_t ERR03:1;\r
- vuint32_t ERR02:1;\r
- vuint32_t ERR01:1;\r
- vuint32_t ERR00:1;\r
- } B;\r
- } ERRL; /* DMA Error Low */\r
- uint32_t edma_reserved1[52];\r
-\r
- union {\r
- vuint8_t R;\r
- struct {\r
- vuint8_t ECP:1;\r
\r
- vuint8_t:1;\r
- vuint8_t GRPPRI:2;\r
- vuint8_t CHPRI:4;\r
-\r
- } B;\r
- } CPR[64]; /* Channel n Priority */\r
-\r
- uint32_t edma_reserved2[944];\r
-\r
-/****************************************************************************/\r
-/* DMA2 Transfer Control Descriptor */\r
-/****************************************************************************/\r
-\r
- CC_EXTENSION struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
- vuint32_t SADDR; /* source address */\r
-\r
- vuint16_t SMOD:5; /* source address modulo */\r
- vuint16_t SSIZE:3; /* source transfer size */\r
- vuint16_t DMOD:5; /* destination address modulo */\r
- vuint16_t DSIZE:3; /* destination transfer size */\r
- vint16_t SOFF; /* signed source address offset */\r
-\r
- vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
-\r
- vint32_t SLAST; /* last destination address adjustment, or\r
-\r
- scatter/gather address (if e_sg = 1) */\r
- vuint32_t DADDR; /* destination address */\r
-\r
- vuint16_t CITERE_LINK:1;\r
- vuint16_t CITER:15;\r
-\r
- vint16_t DOFF; /* signed destination address offset */\r
-\r
- vint32_t DLAST_SGA;\r
-\r
- vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
- vuint16_t BITER:15;\r
-\r
- vuint16_t BWC:2; /* bandwidth control */\r
- vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
- vuint16_t DONE:1; /* channel done */\r
- vuint16_t ACTIVE:1; /* channel active */\r
- vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
- vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
- vuint16_t D_REQ:1; /* disable ipd_req when done */\r
- vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
- vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
- vuint16_t START:1; /* explicit channel start */\r
- } TCD[64]; /* transfer_control_descriptor */\r
-\r
- };\r
-\r
- CC_EXTENSION struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
-\r
- struct tcd_alt1_t {\r
- vuint32_t SADDR; /* source address */\r
-\r
- vuint16_t SMOD:5; /* source address modulo */\r
- vuint16_t SSIZE:3; /* source transfer size */\r
- vuint16_t DMOD:5; /* destination address modulo */\r
- vuint16_t DSIZE:3; /* destination transfer size */\r
- vint16_t SOFF; /* signed source address offset */\r
-\r
- vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
-\r
- vint32_t SLAST; /* last destination address adjustment, or\r
-\r
- scatter/gather address (if e_sg = 1) */\r
- vuint32_t DADDR; /* destination address */\r
-\r
- vuint16_t CITERE_LINK:1;\r
- vuint16_t CITERLINKCH:6;\r
- vuint16_t CITER:9;\r
-\r
- vint16_t DOFF; /* signed destination address offset */\r
-\r
- vint32_t DLAST_SGA;\r
-\r
- vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
- vuint16_t BITERLINKCH:6;\r
- vuint16_t BITER:9;\r
-\r
- vuint16_t BWC:2; /* bandwidth control */\r
- vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
- vuint16_t DONE:1; /* channel done */\r
- vuint16_t ACTIVE:1; /* channel active */\r
- vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
- vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
- vuint16_t D_REQ:1; /* disable ipd_req when done */\r
- vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
- vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
- vuint16_t START:1; /* explicit channel start */\r
- } TCD[64]; /* transfer_control_descriptor */\r
- };\r
/****************************************************************************/\r
/* MODULE : INTC */\r
/****************************************************************************/\r
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