--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_MCBSTM32 \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_MD\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL=KERNEL MCU PWM ADC SIMPLE_PRINTF ARM_ITM_TERM RAMLOG DEM IOHWAB\r
+\r
+#\r
+# Modules needed by us\r
+#\r
+MOD_USE=KERNEL MCU\r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Use little heap\r
+def-y += HEAPSIZE=4000\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_MD\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+\r
+#include "Adc.h"\r
+#include "stm32f10x_adc.h"\r
+\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1,ADC_CH1,ADC_CH1,ADC_CH1\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ // NOT SUPPORTED .accessMode = ADC_ACCESS_MODE_SINGLE,\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ // NOT SUPPORTED .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ // NOT SUPPORTED .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ // NOT SUPPORTED .streamBufferMode = ADC_NO_STREAMING,\r
+ // NOT SUPPORTED .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0]},\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT,\r
+ ADC_TEST_BOARD_POT2,\r
+ ADC_TEST_BOARD_POT3,\r
+ ADC_TEST_BOARD_POT4,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Channel definitions, std container */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ // NOT SUPPORTED Adc_ResolutionType adcChannelResolution;\r
+ // NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;\r
+} Adc_ChannelConfigurationType;\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ // NOT SUPPORTED Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ // NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;\r
+ // NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ // NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;\r
+ // NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ // NOT SUPPORTED Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ // NOT SUPPORTED Dma_ChannelType dmaCommandChannel;\r
+ // NOT SUPPORTED Dma_ChannelType dmaResultChannel;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMACommands;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMAResults;\r
+} Adc_GroupDefType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 1,\r
+ .Pll2 = 104,\r
+ .Pll3 = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 3,\r
+ .Pll2 = 83,\r
+ .Pll3 = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+// .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+// .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+/*\r
+ * PWM003: The detection of development errors is configurable (STD_ON/STD_OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only STD_ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/*\r
+ * Setting to STD_ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE STD_ON\r
+\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/*\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == eemios channel id.\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_11 = 0, // TIM1 Channel 1\r
+ PWM_CHANNEL_12,\r
+ PWM_CHANNEL_13,\r
+ PWM_CHANNEL_14,\r
+ PWM_CHANNEL_21, // TIM2 Channel 1\r
+ PWM_CHANNEL_22,\r
+ PWM_CHANNEL_23,\r
+ PWM_CHANNEL_24,\r
+ PWM_CHANNEL_31, // TIM3 Channel 1\r
+ PWM_CHANNEL_32,\r
+ PWM_CHANNEL_33,\r
+ PWM_CHANNEL_34,\r
+ PWM_CHANNEL_41, // TIM4 Channel 1\r
+ PWM_CHANNEL_42,\r
+ PWM_CHANNEL_43,\r
+ PWM_CHANNEL_44,\r
+ PWM_TOTAL_NOF_CHANNELS,\r
+} Pwm_ChannelType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = PWM_CHANNEL_43, //PB8\r
+ PWM_CHANNEL_2 = PWM_CHANNEL_44, //PB9\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+\r
+/* NEW NEW */\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_PRESCALER_1=0,\r
+ PWM_CHANNEL_PRESCALER_2,\r
+ PWM_CHANNEL_PRESCALER_3,\r
+ PWM_CHANNEL_PRESCALER_4,\r
+} Pwm_ChannelPrescalerType;\r
+\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period\r
+\r
+typedef struct {\r
+ /* Number of duty ticks */\r
+ uint32_t duty:32;\r
+ /* Length of period, in ticks */\r
+ uint32_t period:32;\r
+ /* Counter */\r
+ uint32_t counter:32;\r
+ /* Enable freezing the channel when in debug mode */\r
+ uint32_t freezeEnable:1;\r
+ /* Disable output */\r
+ uint32_t outputDisable:1;\r
+ /* Select which bus disables the bus\r
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */\r
+ uint32_t outputDisableSelect:2;\r
+ /* Prescale the emios clock some more? */\r
+ Pwm_ChannelPrescalerType prescaler:2;\r
+ /* Prescale the emios clock some more? */\r
+ uint32_t usePrescaler:1;\r
+ /* Whether to use DMA. Currently unsupported */\r
+ uint32_t useDma:1;\r
+ uint32_t reserved_2:1;\r
+ /* Input filter. Ignored in output mode. */\r
+ uint32_t inputFilter:4;\r
+ /* Input filter clock source. Ignored in output mode */\r
+ uint32_t filterClockSelect:1;\r
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */\r
+ uint32_t flagEnable:1;\r
+ uint32_t reserved_3:3;\r
+ /* Trigger a match on channel A */\r
+ uint32_t forceMatchA:1;\r
+ /* Triggers a match on channel B */\r
+ uint32_t forceMatchB:1;\r
+ uint32_t reserved_4:1;\r
+ /* We can use different buses for the counter. Use the internal counter */\r
+ uint32_t busSelect:2;\r
+ /* What edges to flag on? */\r
+ uint32_t edgeSelect:1;\r
+ /* Polarity of the channel */\r
+ uint32_t edgePolarity:1;\r
+ /* EMIOS mode. 0x58 for buffered output PWM */\r
+ uint32_t mode:7;\r
+} Pwm_ChannelRegisterType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelRegisterType r;\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];\r
+#endif\r
+} Pwm_ConfigType;\r
+\r
+// Channel configuration macro.\r
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \\r
+ {\\r
+ .channel = _hwchannel,\\r
+ .r = {\\r
+ DUTY_AND_PERIOD(_duty, _period),\\r
+ .freezeEnable = 1,\\r
+ .outputDisable = 0,\\r
+ .usePrescaler = 1,\\r
+ .prescaler = _prescaler,\\r
+ .useDma = 0,\\r
+ .flagEnable = 0, /* See PWM052 */ \\r
+ .busSelect = 3, /* Use the internal counter bus */\\r
+ .edgePolarity = _polarity,\\r
+ .mode = 0\\r
+ }\\r
+ }\r
+\r
+#endif /*PWM_CFG_H_*/\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F103RB is an ARM 32-bit Cortex-M3 Microcontroller, \r
+\r
+ 72MHz\r
+ 128kB Flash \r
+ 20kB SRAM\r
+ 16-bit Timers with Input Capture, Output Compare and PWM, 16-bit 6-ch Advanced Timer \r
+ 2 16-bit Watchdog Timers \r
+ SysTick Timer \r
+ 2 SPI\r
+ 2 I2C \r
+ 3 USART \r
+ USB 2.0 Full Speed Interface \r
+ CAN 2.0B Active\r
+ 2 12-bit 16-ch A/D Converter \r
+ Fast I/O Ports\r
+ \r
+Memory Map\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_MCBSTM32 \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL=KERNEL MCU PWM ADC SIMPLE_PRINTF ARM_ITM_TERM RAMLOG DEM IOHWAB\r
+\r
+#\r
+# Modules needed by us\r
+#\r
+MOD_USE=KERNEL MCU\r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Use little heap\r
+def-y += HEAPSIZE=4000\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_CL\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 1,\r
+ .Pll2 = 104,\r
+ .Pll3 = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 3,\r
+ .Pll2 = 83,\r
+ .Pll3 = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+// .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+// .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F107VCT is an ARM 32-bit Cortex-M3 Microcontroller.\r
+Order info is STM3210C-EVAL.\r
+ \r
+Datasheets:\r
+ STM3210C-EVAL \r
+ http://www.st.com/stonline/products/literature/um/15082.pdf \r
+ \r
+ STM32F107VCT\r
+ http://www.st.com/stonline/products/literature/ds/15274.pdf\r
+ \r
+Info: \r
+ STM32F107VC\r
+ 72MHz\r
+ 256kB Flash \r
+ 64kB SRAM\r
+ 5 × USARTs,\r
+ 4 × 16-bit timers,\r
+ 2 × basic timers,\r
+ 3 × SPIs,\r
+ 2 × I2S,\r
+ 1 × I2C,\r
+ USB OTG FS,\r
+ 2 × CANs,\r
+ 1 × PWM timer,\r
+ 2 × ADCs,\r
+ 2 × DACs,\r
+ Ethernet\r
+ \r
+Memory Map:\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
projects / arc.git / commitdiff