\r
MEMORY\r
{\r
- flash(R) : ORIGIN = 0x08000000, LENGTH = 128K\r
- ram(RW) : ORIGIN = 0x20000000, LENGTH = 20K\r
+#include "memory.ldf"\r
}\r
\r
SECTIONS\r
/* Default linker script, for normal executables */\r
/* Linker script for 68HC12 executable (PROM). */\r
-OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12",\r
- "elf32-m68hc12")\r
+OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12", "elf32-m68hc12")\r
OUTPUT_ARCH(m68hc12)\r
ENTRY(_start)\r
\r
\r
MEMORY\r
{\r
- page0 (rwx) : ORIGIN = 0x0, LENGTH = 256\r
-\r
- /* RAM */\r
- data (rwx) : ORIGIN = 0x2000, LENGTH = 8k\r
-\r
- eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k\r
- text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
- \r
- /* high fixed bank, reserve 0x100 vectors and security. */\r
- text_h (rx) : ORIGIN = 0xc002, LENGTH = 16k-0x102\r
- vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
- \r
- /* Flash memory banks VMA:s */\r
- bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
- bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
- bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
- bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
- bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
- bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
- \r
- bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
- bank15 (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
- \r
- /* Flash memory banks LMA:s */\r
- /* iSystem winIDEA */\r
- bank8_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
- bank9_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
- bank10_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
- bank11_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
- bank12_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
- bank13_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
-\r
- bank14_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
- bank15_lma (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
- vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
- \r
- /* Freescale Codewarrior Hiwave (s19, TBDML)\r
- bank8_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
- bank9_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
- bank10_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
- bank11_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
- bank12_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
- bank13_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
-\r
- bank14_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
- bank15_lma (rx) : ORIGIN = 0x3f8002, LENGTH = 16k-0x102\r
- vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
- */\r
+#include "memory.ldf"\r
}\r
\r
/* Setup the stack on the top of the data memory bank. */\r
* Copyright (C) 2009 ArcCore AB <contact@arccore.com> \r
*/\r
\r
-/* For more info on sections check the E500 freescale doc: E500ABIUG.pdf\r
- *\r
- */\r
+/* Undef sections/keywords */ \r
+#undef PPC\r
+\r
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")\r
OUTPUT_ARCH(powerpc)\r
ENTRY(_start)\r
\r
\r
+\r
MEMORY\r
{\r
- /* MPC55xx Reset Control Word(RCW) */\r
- rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
- flash(R) : ORIGIN = 0x00000008, LENGTH = 0x100000\r
- /* 5516S, 48K\r
- * 5517S,5516G,5516E, 64K RAM\r
- * 5517G,E , 80K RAM\r
- */\r
- ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
+#include "memory.ldf"\r
}\r
\r
SECTIONS\r
--- /dev/null
+\r
+Elmicro Card12 HC12 Controller Module with MC912D60A / MC912DG128A\r
+\r
+ http://elmicro.com/en/card12.html\r
+\r
+MC912D60A Microcontroller Info:\r
+ MC912D60A MCU with LQFP112 package\r
+ 60 KB Flash\r
+ 1 KB EEPROM\r
+ 2 KB RAM\r
+ SPI\r
+ 2x SCI\r
+ Enhanced Capture Timer\r
+ 4 Channel PWM\r
+ 16 Channel 10 Bit A/D-Converter\r
+ up to 80 binary Inputs/Outputs!\r
+ \r
+Board Features:\r
+ 16 MHz Quarz Clock (8 MHz System Clock)\r
+ Two RS232 Ports with Transceiver MAX232A\r
+ PCA82C250 CAN Physical Interface\r
+ Special Reset Controller\r
+ Reset Switch\r
+ Operating Mode selectable via jumpers\r
+ BDM (Background Debug Mode) connector\r
+ All controller pins are available at two double row headers\r
+ 5V power supply\r
+ Credit card size: 86mm x 54mm\r
--- /dev/null
+\r
+\r
+/* The board Elmicro Card12 comes with MC912D60A or MC912DG128A.\r
+ * This memory mapping is for MC9S12DG128 but is also compatible \r
+ * with MC912D60A (which has more memory).\r
+ */\r
+ \r
+page0 (rwx) : ORIGIN = 0x0, LENGTH = 256\r
+\r
+/* RAM */\r
+data (rwx) : ORIGIN = 0x2000, LENGTH = 8k\r
+\r
+eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k\r
+text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
+ \r
+/* high fixed bank, reserve 0x100 vectors and security. */\r
+text_h (rx) : ORIGIN = 0xc002, LENGTH = 16k-0x102\r
+vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
+ \r
+/* Flash memory banks VMA:s */\r
+bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+ \r
+bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank15 (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+ \r
+/* Flash memory banks LMA:s */\r
+/* iSystem winIDEA */\r
+bank8_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank9_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank10_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank11_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank12_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank13_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+\r
+bank14_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank15_lma (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
+ \r
+/* Freescale Codewarrior Hiwave (s19, TBDML)\r
+bank8_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
+bank9_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
+bank10_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
+bank11_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
+bank12_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
+bank13_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
+\r
+bank14_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
+bank15_lma (rx) : ORIGIN = 0x3f8002, LENGTH = 16k-0x102\r
+vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
+*/
\ No newline at end of file
\r
\r
-Test board. \r
-=======================================================\r
\r
-The regression test board comes in different variants.\r
+The Freescale MPC5510 is an PowerPC process with a e200Z1+e200Z0 core. \r
\r
+Datasheets:\r
+ Eval board:\r
+ http://www.asyst.si/isystem/files/downloads/evaluation_boards/ITMPC5517_V10.pdf \r
\r
-This file supports:\r
-- EVB5516\r
+ MPC5516/7\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5510&webpageId=1067371573986721160325&nodeId=0162468rH3bTdG06C10325&fromPage=tax\r
\r
+Board:\r
+ 8Mhz external crystal\r
+ \r
+Info: \r
+ MPC5516/7 (I think that the board is always equipped with a MPC5517E now)\r
+ e200Z1 + e200Z0 (VLE only)\r
+ 48-66Mhz\r
+ 1.5MB Flash (MPC5516 1MB)\r
+ 80KB SRAM (MPC5516 64KB)\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 1M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+The Freescale MPC5510 is an PowerPC process with a e200Z1+e200Z0 core. \r
+The simulator environment ONLY supports one core.\r
+ \r
+Datasheets:\r
+ \r
+ MPC5516/7\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5510&webpageId=1067371573986721160325&nodeId=0162468rH3bTdG06C10325&fromPage=tax\r
+ \r
+Info: \r
+ MPC5516\r
+ 1.5MB Flash (MPC5516 1MB)\r
+ 80KB SRAM (MPC5516 64KB)\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 1M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+The Freescale MPC5554 is an PowerPC process with a e200Z6 core. \r
+The difference between this and the MPC551xsim is that this supports VLE.\r
+ \r
+Datasheets:\r
+ \r
+Info: \r
+ MPC5554\r
+ 2MB Flash\r
+ 64KB SRAM\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 2M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+\r
+The Freescale MPC5567 is an PowerPC process with a e200z6 core. \r
+The EVAL board used is the "ODEEP" concept. \r
+ \r
+Datasheets:\r
+ ODEEP \r
+ http://www.odeep.se/ \r
+ \r
+ MPC5567\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5567\r
+ \r
+Info: \r
+ MPC5567\r
+ 80-132Mhz\r
+ 2MB Flash \r
+ 80kB SRAM\r
+ 2 × SCI\r
+ 3 × DSPI\r
+ 5 × CAN\r
+ FlexRay\r
+ Ethernet\r
+ 24-ch PWM\r
+ 32-ch ETPU\r
+ 24-ch EMIOS\r
+ 2-ch × 20-ch, 12bit ADC\r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 2M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 0x100000\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F103RB is an ARM 32-bit Cortex-M3 Microcontroller, \r
+\r
+ 72MHz\r
+ 128kB Flash \r
+ 20kB SRAM\r
+ 16-bit Timers with Input Capture, Output Compare and PWM, 16-bit 6-ch Advanced Timer \r
+ 2 16-bit Watchdog Timers \r
+ SysTick Timer \r
+ 2 SPI\r
+ 2 I2C \r
+ 3 USART \r
+ USB 2.0 Full Speed Interface \r
+ CAN 2.0B Active\r
+ 2 12-bit 16-ch A/D Converter \r
+ Fast I/O Ports\r
+ \r
+Memory Map\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
--- /dev/null
+\r
+\r
+flash(R) : ORIGIN = 0x08000000, LENGTH = 128K\r
+ram(RW) : ORIGIN = 0x20000000, LENGTH = 20K\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F107VCT is an ARM 32-bit Cortex-M3 Microcontroller.\r
+Order info is STM3210C-EVAL.\r
+ \r
+Datasheets:\r
+ STM3210C-EVAL \r
+ http://www.st.com/stonline/products/literature/um/15082.pdf \r
+ \r
+ STM32F107VCT\r
+ http://www.st.com/stonline/products/literature/ds/15274.pdf\r
+ \r
+Info: \r
+ STM32F107VC\r
+ 72MHz\r
+ 256kB Flash \r
+ 64kB SRAM\r
+ 5 × USARTs,\r
+ 4 × 16-bit timers,\r
+ 2 × basic timers,\r
+ 3 × SPIs,\r
+ 2 × I2S,\r
+ 1 × I2C,\r
+ USB OTG FS,\r
+ 2 × CANs,\r
+ 1 × PWM timer,\r
+ 2 × ADCs,\r
+ 2 × DACs,\r
+ Ethernet\r
+ \r
+Memory Map:\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
--- /dev/null
+\r
+\r
+flash(R) : ORIGIN = 0x08000000, LENGTH = 256K\r
+ram(RW) : ORIGIN = 0x20000000, LENGTH = 64K\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = blinker_node.elf\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = pwm_node.elf\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = pwm_node2.elf\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = simple.elf\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = switch_node.elf\r
libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
#build-lib-y = tiny.a\r
$(Q)$(CPP) -x assembler-with-cpp -E -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
\r
\r
+# Board linker files are in the board directory \r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+\r
+# Preprocess linker files..\r
+%.ldp: %.ldf\r
+ @echo " >> CPP $<"\r
+ $(Q)$(CPP) -E -P -x assembler-with-cpp -o $@ $(addprefix -I ,$(inc-y)) $<\r
+\r
# @cat $@ \r
\r
.PHONY $(ROOTDIR)/libs:\r
/^\.bss/ { print " bss :" $$3+0 " bytes"; ram+=$$3}; \\r
END { print " ROM: ~" rom " bytes"; print " RAM: ~" ram " bytes"}' $(subst .elf,.map,$@)\r
endif\r
+ @echo\r
@echo " >>>>>>> DONE <<<<<<<<<"\r
+ @echo\r
\r
\r
$(size-exe-y): $(build-exe-y)\r
@echo TODO: Parse the file....\r
\r
.PHONY clean:\r
- @-rm -f *.o *.d *.h *.elf *.a\r
+ @-rm -f *.o *.d *.h *.elf *.a *.ldp\r
projects / arc.git / commitdiff