#include "Std_Types.h"\r
#include "Mcu.h"\r
-#include "Det.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"\r
+#endif
#include <assert.h>\r
#include "cpu.h"\r
#include <string.h>\r
#if 0\r
static void Mcu_LossOfLock( void ) {\r
-#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
- /* Should report MCU_E_CLOCK_FAILURE with DEM here.... but\r
- * we do the next best thing. Report with Det with API = 0\r
- */\r
- Det_ReportError(MODULE_ID_MCU,0,0,MCU_E_PLL_NOT_LOCKED);\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
#endif\r
\r
Mcu_Global.stats.lossOfLockCnt++;\r
#define SPR_PIR 286\r
#define SPR_PVR 287\r
\r
-#define CORE_PVR_E200Z1 0x81440000UL\r
-#define CORE_PVR_E200Z0 0x81710000UL\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL
+#define CORE_PVR_E200Z3 0x81120000UL\r
\r
\r
typedef struct {\r
{\r
.name = "MPC5516",\r
.pvr = CORE_PVR_E200Z0,\r
- },\r
+ },
+ {
+ .name = "MPC563X",
+ .pvr = CORE_PVR_E200Z3,
+ },
};\r
\r
core_info_t core_info_list[] = {\r
.name = "CORE_E200Z1",\r
.pvr = CORE_PVR_E200Z1,\r
},\r
+ {
+ .name = "CORE_E200Z3",
+ .pvr = CORE_PVR_E200Z3,
+ },
};\r
\r
// TODO: move\r
#include "Cpu.h"\r
#include "Mcu.h"\r
#include "CanIf_Cbk.h"\r
-#include "Det.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"\r
+#endif
#include <assert.h>\r
#include <stdlib.h>\r
#include <string.h>\r
#define VALIDATE_NO_RV(_exp,_api,_err )\r
#define DET_REPORTERROR(_x,_y,_z,_q)\r
#endif\r
-\r
+
+#if defined(USE_DEM)
+#define VALIDATE_DEM_NO_RV(_exp,_err ) \
+ if( !(_exp) ) { \
+ Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
+ return; \
+ }
+#else
+#define VALIDATE_DEM_NO_RV(_exp,_err )
+#endif
+
//-------------------------------------------------------------------\r
\r
// Message box status defines\r
tq2 = (config->CanControllerSeg2 + 1);\r
tq = 1 + tq1 + tq2;\r
\r
- // Check TQ limitations..\r
- VALIDATE_NO_RV(( (tq1>=4) && (tq1<=16)), 0x2, CAN_E_TIMEOUT ); // Actually should be sent to DEM\r
- VALIDATE_NO_RV(( (tq2>=2) && (tq2<=8)), 0x2, CAN_E_TIMEOUT ); // but this is the next best thing\r
- VALIDATE_NO_RV(( (tq>8) && (tq<25 )), 0x2, CAN_E_TIMEOUT );\r
+ // Check TQ limitations..
+ VALIDATE_DEM_NO_RV(( (tq1>=4) && (tq1<=16)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq2>=2) && (tq2<=8)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq>8) && (tq<25 )), CAN_E_TIMEOUT );\r
\r
// Assume we're using the peripheral clock instead of the crystal.\r
clock = McuE_GetPeripheralClock(config->CanCpuClockRef);\r
#include <assert.h>
#include <string.h>
#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"
+#endif
#include "h7f_types.h"
#include "Cpu.h"
#include "mpc55xx.h"
Fls_Global.jobResultType = MEMIF_JOB_FAILED;
Fls_Global.jobType = FLS_JOB_NONE;
Fls_Global.status = MEMIF_IDLE;
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_WRITE_FAILED, DEM_EVENT_STATUS_FAILED);
+#endif
FEE_JOB_ERROR_NOTIFICATION();
}
break;
Fls_Global.jobResultType = MEMIF_JOB_FAILED;
Fls_Global.jobType = FLS_JOB_NONE;
Fls_Global.status = MEMIF_IDLE;
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );
- FEE_JOB_ERROR_NOTIFICATION();
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_WRITE_FAILED, DEM_EVENT_STATUS_FAILED);
+#endif
+ FEE_JOB_ERROR_NOTIFICATION();
}
break;
#include <string.h>\r
#include "Std_Types.h"\r
#include "Mcu.h"\r
-#include "Det.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"
+#endif
#include "mpc55xx.h"\r
#include "Cpu.h"\r
#include "Ramlog.h"\r
//-------------------------------------------------------------------\r
\r
static void Mcu_LossOfLock( void ) {\r
-#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
- /* Should report MCU_E_CLOCK_FAILURE with DEM here.... but\r
- * we do the next best thing. Report with Det with API = 0\r
- */\r
- Det_ReportError(MODULE_ID_MCU,0,0,MCU_E_PLL_NOT_LOCKED);\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
#endif\r
\r
Mcu_Global.stats.lossOfLockCnt++;\r
#define SPR_PIR 286\r
#define SPR_PVR 287\r
\r
-#define CORE_PVR_E200Z1 0x81440000UL\r
-#define CORE_PVR_E200Z0 0x81710000UL\r
-#define CORE_PVR_E200Z6 0x81170000UL\r
+#define CORE_PVR_E200Z1 0x81440000UL\r
+#define CORE_PVR_E200Z0 0x81710000UL
+#define CORE_PVR_E200Z3 0x81120000UL\r
+#define CORE_PVR_E200Z6 0x81170000UL\r
\r
\r
typedef struct {\r
{\r
.name = "MPC5516",\r
.pvr = CORE_PVR_E200Z0,\r
- },\r
+ },
#elif defined(CFG_MPC5567)\r
{\r
.name = "MPC5567",\r
.pvr = CORE_PVR_E200Z6,\r
- }\r
+ }
+#elif defined(CFG_MPC5633)
+ {
+ .name = "MPC563X",
+ .pvr = CORE_PVR_E200Z3,
+ },
#endif\r
};\r
\r
{\r
.name = "CORE_E200Z6",\r
.pvr = CORE_PVR_E200Z6,\r
- }\r
+ }
+#elif defined(CFG_MPC5633)
+ {
+ .name = "CORE_E200Z3",
+ .pvr = CORE_PVR_E200Z3,
+ },\r
#endif\r
};\r
\r
* System clock calculation\r
*\r
* 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
- * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));\r
+ * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
+ * 563x - We run in legacy mode = 5567
*/\r
#if defined(CFG_MPC5516)\r
uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;\r
uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;\r
uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;\r
-#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
+#elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)\r
uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
uint32_t f_sys;\r
uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePoint;\r
\r
- f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+ f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
return f_sys;\r
}\r
\r
void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
{\r
- VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);
+ VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID);\r
//The pad configuration registers (SIU_PCR) in the SIU allow software control of the static electrical\r
//characteristics of external pins. The PCRs can select the multiplexed function of a pin, selection of pullup\r
//or pulldown devices, the slew rate of I/O signals, open drain mode for output pins, and hysteresis.\r
--- /dev/null
+/**************************************************************************/\r
+/* FILE NAME: mpc563m.h COPYRIGHT (c) Freescale 2008 */\r
+/* VERSION: 1.2 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC563m. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 1.0 G. Emerson 31/OCT/07 Initial version. */\r
+/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */\r
+/* Added ESYNCR1 ESYNCR2 SYNFMMR */\r
+/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */\r
+/* 8 channels in the middle of the range */\r
+/* do not exist */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC563M_H_\r
+#define _MPC563M_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:13;\r
+ } B;\r
+ } SYNCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYNSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EMODE:1;\r
+ vuint32_t CLKCFG:3;\r
+ vuint32_t:8;\r
+ vuint32_t EPREDIV:4;\r
+ vuint32_t:9;\r
+ vuint32_t EMFD:7;\r
+ } B;\r
+ } ESYNCR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:17;\r
+ vuint32_t ERFD:2;\r
+ } B;\r
+ } ESYNCR2;\r
+\r
+ int32_t FMPLL_reserved0[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MODEN:1;\r
+ vuint32_t MODSEL:1;\r
+ vuint32_t MODPERIOD:13;\r
+ vuint32_t:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } SYNFMMR;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct CAL_CS_tag {\r
+ union { /* Calibration Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Calibration Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+/* Calibration registers */\r
+ uint32_t EBI_reserved2[4];\r
+ struct CAL_CS_tag CAL_CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t PRD:1; /* Include PRD Field */\r
+\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t MLOCK:4;\r
+ vuint32_t LLOCK:16;\r
+ } B;\r
+ } LMLR;\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:3;\r
+ vuint32_t HBLOCK:28;\r
+ } B;\r
+ } HLR;\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t SMLOCK:4;\r
+ vuint32_t SLLOCK:16;\r
+ } B;\r
+ } SLMLR;\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t MSEL:4;\r
+ vuint32_t LSEL:16;\r
+ } B;\r
+ } LMSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t HBSEL:28;\r
+ } B;\r
+ } HSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } AR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:11;\r
+\r
+ vuint32_t:1;\r
+\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t DPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t IPFEN:1;\r
+\r
+ vuint32_t PFLIM:3;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } BIUCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:22;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } BIUAPR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LBCFG:2;\r
+ vuint32_t:30;\r
+ } B;\r
+ } BIUCR2;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t MASKNUM:16;\r
+ } B;\r
+ } MIDR;\r
+ int32_t SIU_reserved00;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS:1;\r
+ vuint32_t:8;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t SERF:1;\r
+ vuint32_t WKPCFG:1;\r
+ vuint32_t:12;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t RGF:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t SER:1;\r
+ vuint32_t:14;\r
+ vuint32_t CRE:1;\r
+ vuint32_t:15;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ int32_t SIU_reserved1[3];\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:3;\r
+ vuint16_t PA:3;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t DSC:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SRC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[512];\r
+\r
+ int16_t SIU_reserved_0[224];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[256];\r
+\r
+ int32_t SIU_reserved_3[64];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[256];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL5:2;\r
+ vuint32_t TSEL4:2;\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } ETISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } EIISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SINSELA:2;\r
+ vuint32_t SSSELA:2;\r
+ vuint32_t SCKSELA:2;\r
+ vuint32_t TRIGSELA:2;\r
+ vuint32_t SINSELB:2;\r
+ vuint32_t SSSELB:2;\r
+ vuint32_t SCKSELB:2;\r
+ vuint32_t TRIGSELB:2;\r
+ vuint32_t SINSELC:2;\r
+ vuint32_t SSSELC:2;\r
+ vuint32_t SCKSELC:2;\r
+ vuint32_t TRIGSELC:2;\r
+ vuint32_t SINSELD:2;\r
+ vuint32_t SSSELD:2;\r
+ vuint32_t SCKSELD:2;\r
+ vuint32_t TRIGSELD:2;\r
+ } B;\r
+ } DISR;\r
+\r
+ int32_t SIU_reserved2[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t ENGDIV:6;\r
+ vuint32_t:4;\r
+ vuint32_t EBTS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRL;\r
+\r
+ int32_t SIU_reserved3[2];\r
+\r
+ union { /* System Clock Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t BYPASS:1;\r
+ vuint32_t SYSCLKDIV:2;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYSDIV;\r
+\r
+ union {\r
+ vuint32_t R;\r
+\r
+ } HLT;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } HLTACK;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR; /* Output Update Disable Register */\r
+\r
+ uint32_t emios_reserved[5];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ } CADR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ } CBDR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ } CCNTR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR; /* Channel Status Register */\r
+ uint32_t emios_channel_reserved[3];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE :ETPU */\r
+/****************************************************************************/\r
+\r
+/***************************Configuration Registers**************************/\r
+\r
+ struct ETPU_tag {\r
+ union { /* MODULE CONFIGURATION REGISTER */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GEC:1; /* Global Exception Clear */\r
+ vuint32_t:3;\r
+ vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t:3;\r
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */\r
+ vuint32_t:5;\r
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */\r
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */\r
+ vuint32_t:2;\r
+ vuint32_t VIS:1; /* SCM Visability */\r
+ vuint32_t:5;\r
+ vuint32_t GTBE:1; /* Global Time Base Enable */\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* COHERENT DUAL-PARAMETER CONTROL */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STS:1; /* Start Status bit */\r
+ vuint32_t CTBASE:5; /* Channel Transfer Base */\r
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */\r
+ vuint32_t PWIDTH:1; /* Parameter Width */\r
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */\r
+ vuint32_t WR:1;\r
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */\r
+ } B;\r
+ } CDCR;\r
+\r
+ uint32_t etpu_reserved1;\r
+\r
+ union { /* MISC Compare Register */\r
+ vuint32_t R;\r
+ } MISCCMPR;\r
+\r
+ union { /* SCM off-range Date Register */\r
+ vuint32_t R;\r
+ } SCMOFFDATAR;\r
+\r
+ union { /* ETPU_A Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_A;\r
+ uint32_t etpu_reserved3; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved4;\r
+\r
+ union { /* ETPU_A Timebase Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ vuint32_t:1;\r
+ vuint32_t AM:1; /* Angle Mode */\r
+ vuint32_t:3;\r
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ vuint32_t:6;\r
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_A;\r
+\r
+ union { /* ETPU_A TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_A;\r
+\r
+ union { /* ETPU_A TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_A;\r
+\r
+ union { /* ETPU_A STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_A;\r
+\r
+ uint32_t etpu_reserved5[4];\r
+ uint32_t etpu_reserved6[4]; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved7[108];\r
+\r
+/*****************************Status and Control Registers**************************/\r
+\r
+ union { /* ETPU_A Channel Interrut Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */\r
+ } B;\r
+ } CISR_A;\r
+ uint32_t etpu_reserved8; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved9[2];\r
+\r
+ union { /* ETPU_A Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_A;\r
+ uint32_t etpu_reserved10; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved11[2];\r
+\r
+ union { /* ETPU_A Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_A;\r
+ uint32_t etpu_reserved12; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved13[2];\r
+\r
+ union { /* ETPU_A Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_A;\r
+ uint32_t etpu_reserved14; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved15[2];\r
+\r
+ union { /* ETPU_A Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_A;\r
+ uint32_t etpu_reserved16; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved17[2];\r
+\r
+ union { /* ETPU_A Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_A;\r
+ uint32_t etpu_reserved19; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20[10];\r
+ union { /* ETPU_A Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_A;\r
+ uint32_t etpu_reserved22; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20a[2];\r
+\r
+ union { /* ETPU_A Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_A;\r
+ uint32_t etpu_reserved22a; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved23[90];\r
+\r
+/*****************************Channels********************************/\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel Configuration Register */\r
+ struct {\r
+ vuint32_t CIE:1; /* Channel Interruput Enable */\r
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */\r
+ vuint32_t CPR:2; /* Channel Priority */\r
+ vuint32_t:3;\r
+ vuint32_t ETCS:1; /* Entry Table Condition Select */\r
+ vuint32_t:3;\r
+ vuint32_t CFS:5; /* Channel Function Select */\r
+ vuint32_t ODIS:1; /* Output disable */\r
+ vuint32_t OPOL:1; /* output polarity */\r
+ vuint32_t:3;\r
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */\r
+ } B;\r
+ } CR;\r
+ union {\r
+ vuint32_t R; /* Channel Status Control Register */\r
+ struct {\r
+ vuint32_t CIS:1; /* Channel Interruput Status */\r
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t DTRS:1; /* Data Transfer Status */\r
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t IPS:1; /* Input Pin State */\r
+ vuint32_t OPS:1; /* Output Pin State */\r
+ vuint32_t OBE:1; /* Output Buffer Enable */\r
+ vuint32_t:11;\r
+ vuint32_t FM1:1; /* Function mode */\r
+ vuint32_t FM0:1; /* Function mode */\r
+ } B;\r
+ } SCR;\r
+ union {\r
+ vuint32_t R; /* Channel Host Service Request Register */\r
+ struct {\r
+ vuint32_t:29; /* Host Service Request */\r
+ vuint32_t HSR:3;\r
+ } B;\r
+ } HSRR;\r
+ uint32_t etpu_reserved23;\r
+ } CHAN[127];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : XBAR CrossBar */\r
+/****************************************************************************/\r
+ struct XBAR_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR0; /* Master Priority Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR0; /* General Purpose Control Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved2[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR1; /* Master Priority Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR1; /* General Purpose Control Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved4[123];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR3; /* Master Priority Register for Slave Port 3 */\r
+\r
+ uint32_t xbar_reserved5[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR3; /* General Purpose Control Register for Slave Port 3 */\r
+ uint32_t xbar_reserved6[187];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR6; /* Master Priority Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved7[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR6; /* General Purpose Control Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved8[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR7; /* Master Priority Register for Slave Port 7 */\r
+\r
+ uint32_t xbar_reserved9[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR7; /* General Purpose Control Register for Slave Port 7 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+ struct ECSM_tag {\r
+\r
+ uint32_t ecsm_reserved1[5];\r
+\r
+ uint16_t ecsm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t ecsm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t ecsm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t ecsm_reserved5a[1];\r
+ uint32_t ecsm_reserved5b[1];\r
+\r
+ uint32_t ecsm_reserved5c[6];\r
+\r
+ uint8_t ecsm_reserved6[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t ecsm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t ecsm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEAR:32;\r
+ } B;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t ecsm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDH:32;\r
+ } B;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDL:32;\r
+ } B;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t ecsm_reserved12[2];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDH:32;\r
+ } B;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDL:32;\r
+ } B;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t GRP3PRI:2;\r
+ vuint32_t GRP2PRI:2;\r
+ vuint32_t GRP1PRI:2;\r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+ uint32_t edma_reserved_erqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ31:1;\r
+ vuint32_t ERQ30:1;\r
+ vuint32_t ERQ29:1;\r
+ vuint32_t ERQ28:1;\r
+ vuint32_t ERQ27:1;\r
+ vuint32_t ERQ26:1;\r
+ vuint32_t ERQ25:1;\r
+ vuint32_t ERQ24:1;\r
+ vuint32_t ERQ23:1;\r
+ vuint32_t ERQ22:1;\r
+ vuint32_t ERQ21:1;\r
+ vuint32_t ERQ20:1;\r
+ vuint32_t ERQ19:1;\r
+ vuint32_t ERQ18:1;\r
+ vuint32_t ERQ17:1;\r
+ vuint32_t ERQ16:1;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+ uint32_t edma_reserved_eeirh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI31:1;\r
+ vuint32_t EEI30:1;\r
+ vuint32_t EEI29:1;\r
+ vuint32_t EEI28:1;\r
+ vuint32_t EEI27:1;\r
+ vuint32_t EEI26:1;\r
+ vuint32_t EEI25:1;\r
+ vuint32_t EEI24:1;\r
+ vuint32_t EEI23:1;\r
+ vuint32_t EEI22:1;\r
+ vuint32_t EEI21:1;\r
+ vuint32_t EEI20:1;\r
+ vuint32_t EEI19:1;\r
+ vuint32_t EEI18:1;\r
+ vuint32_t EEI17:1;\r
+ vuint32_t EEI16:1;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+ uint32_t edma_reserved_irqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT31:1;\r
+ vuint32_t INT30:1;\r
+ vuint32_t INT29:1;\r
+ vuint32_t INT28:1;\r
+ vuint32_t INT27:1;\r
+ vuint32_t INT26:1;\r
+ vuint32_t INT25:1;\r
+ vuint32_t INT24:1;\r
+ vuint32_t INT23:1;\r
+ vuint32_t INT22:1;\r
+ vuint32_t INT21:1;\r
+ vuint32_t INT20:1;\r
+ vuint32_t INT19:1;\r
+ vuint32_t INT18:1;\r
+ vuint32_t INT17:1;\r
+ vuint32_t INT16:1;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+ uint32_t edma_reserved_erh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR31:1;\r
+ vuint32_t ERR30:1;\r
+ vuint32_t ERR29:1;\r
+ vuint32_t ERR28:1;\r
+ vuint32_t ERR27:1;\r
+ vuint32_t ERR26:1;\r
+ vuint32_t ERR25:1;\r
+ vuint32_t ERR24:1;\r
+ vuint32_t ERR23:1;\r
+ vuint32_t ERR22:1;\r
+ vuint32_t ERR21:1;\r
+ vuint32_t ERR20:1;\r
+ vuint32_t ERR19:1;\r
+ vuint32_t ERR18:1;\r
+ vuint32_t ERR17:1;\r
+ vuint32_t ERR16:1;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+\r
+ } B;\r
+ } CPR[64]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[944];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR; /* Current Priority Register */\r
+\r
+ uint32_t intc_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA:21;\r
+ vuint32_t INTVEC:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR; /* Interrupt Acknowledge Register */\r
+\r
+ uint32_t intc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR; /* End of Interrupt Register */\r
+\r
+ uint32_t intc_reserved3;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved4[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[358]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t ICEA0:1;\r
+ vuint32_t ICEA1:1;\r
+ vuint32_t:1;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t EQADC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:3;\r
+ vuint32_t TSBC:1;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t TSBCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t:4;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:4;\r
+ vuint32_t DPCS1_7:1;\r
+ vuint32_t DPCS1_6:1;\r
+ vuint32_t DPCS1_5:1;\r
+ vuint32_t DPCS1_4:1;\r
+ vuint32_t DPCS1_3:1;\r
+ vuint32_t DPCS1_2:1;\r
+ vuint32_t DPCS1_1:1;\r
+ vuint32_t DPCS1_0:1;\r
+ } B;\r
+ } DSICR1; /* DSI Configuration Register 1 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t SCISDOZ:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t M2:1;\r
+ vuint16_t INPOL:1;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_12_13_bit_tag {\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R12:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t ERR:1;\r
+ vuint16_t:1;\r
+ vuint16_t D:12;\r
+ } B;\r
+ } DR; /* Data Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN2_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t WRNEN:1;\r
+\r
+ vuint32_t MDISACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t MBFEN:1;\r
+ vuint32_t:10;\r
+\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t:2;\r
+\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+ int32_t FLEXCAN_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t flexcan2_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[32];\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Decimation Filter (DECFIL) */\r
+/****************************************************************************/\r
+ struct DECFIL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t SRES:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDEN:1;\r
+ vuint32_t ODEN:1;\r
+ vuint32_t ERREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FTYPE:2;\r
+ vuint32_t:1;\r
+ vuint32_t SCAL:2;\r
+ vuint32_t:1;\r
+ vuint32_t SAT:1;\r
+ vuint32_t ISEL:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_RATE:4;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BSY:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_COUNTER:4;\r
+ vuint32_t IDFC:1;\r
+ vuint32_t ODFC:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVFC:1;\r
+ vuint32_t OVRC:1;\r
+ vuint32_t IVRC:1;\r
+ vuint32_t:6;\r
+ vuint32_t IDF:1;\r
+ vuint32_t ODF:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVF:1;\r
+ vuint32_t OVR:1;\r
+ vuint32_t IVR:1;\r
+ } B;\r
+ } MSR; /* Status Register */\r
+\r
+ uint32_t decfil_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t PREFILL:1;\r
+ vuint32_t FLUSH:1;\r
+ vuint32_t INPBUF:16;\r
+ } B;\r
+ } IB;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t OUTTEG:4;\r
+ vuint32_t OUTBUF:16;\r
+ } B;\r
+ } OB;\r
+\r
+ uint32_t decfil_reserved2[2];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } COEF[9]; /* Filter Coefficient Registers */\r
+\r
+ uint32_t decfil_reserved3[13];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } TAP[8]; /* Filter TAP Registers */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Periodic Interval Timer (PIT) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:29;\r
+ vuint32_t MDIS_RTI:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } MCR; /* PIT Module Control Register */\r
+\r
+ uint32_t pit_reserved1[59];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } RTI; /* RTI Channel */\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } TIMER[4]; /* Timer Channels */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : System Timer Module (STM) */\r
+/****************************************************************************/\r
+ struct STM_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t:6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR; /* STM Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CNT; /* STM Counter Value */\r
+\r
+ uint32_t stm_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR0; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR0; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP0; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR1; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR1; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP1; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR2; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR2; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP2; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved4;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR3; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR3; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP3; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved5;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Software Watchdog Timer (SWT) */\r
+/****************************************************************************/\r
+ struct SWT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t:15;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WNO:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR; /* SWT Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR; /* SWT Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TO; /* SWT Time-out Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } WN; /* SWT Window Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR; /* SWT Service Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CO; /* Counter Output Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Power Management Controller (PMC) */\r
+/****************************************************************************/\r
+ struct PMC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LVIRR:1;\r
+ vuint32_t LVIHR:1;\r
+ vuint32_t LVI5R:1;\r
+ vuint32_t LVI3R:1;\r
+ vuint32_t LVI1R:1;\r
+ vuint32_t BRW:1;\r
+ vuint32_t BGS1:1;\r
+ vuint32_t BGS2:1;\r
+ vuint32_t LVIRE:1;\r
+ vuint32_t LVIHE:1;\r
+ vuint32_t LVI5E:1;\r
+ vuint32_t LVI3E:1;\r
+ vuint32_t LVI1E:1;\r
+ vuint32_t:2;\r
+ vuint32_t TLK:1;\r
+ vuint32_t LVIRC:1;\r
+ vuint32_t LVIHC:1;\r
+ vuint32_t LVI5C:1;\r
+ vuint32_t LVI3C:1;\r
+ vuint32_t LVI1C:1;\r
+ vuint32_t:3;\r
+ vuint32_t LVIRF:1;\r
+ vuint32_t LVIHF:1;\r
+ vuint32_t LVI5F:1;\r
+ vuint32_t LVI3F:1;\r
+ vuint32_t LVI1F:1;\r
+ vuint32_t:3;\r
+ } B;\r
+ } CFGR; /* Configuration and status register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t LVI50TRIM:4;\r
+ vuint32_t V33TRIM:4;\r
+ vuint32_t LVI33TRIM:4;\r
+ vuint32_t V12TRIM:4;\r
+ vuint32_t LVI12TRIM:4;\r
+ } B;\r
+ } TRIMR; /* Trimming register */\r
+ };\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0xC000\r
+#define SRAM_END 0x4000BFFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x100000\r
+#define FLASH_END 0xFFFFF\r
+\r
+/* Define instances of modules */\r
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)\r
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)\r
+#define FLASH (*( volatile struct FLASH_tag *) 0xC3F88000)\r
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)\r
+\r
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)\r
+#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)\r
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)\r
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)\r
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)\r
+#define ETPU_DATA_RAM_END 0xC3FC89FC\r
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)\r
+\r
+#define PBRIDGE (*( struct PBRIDGE_tag *) 0xFFF00000)\r
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)\r
+#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)\r
+#define STM (*( volatile struct STM_tag *) 0xFFF3C000)\r
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)\r
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)\r
+#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000)\r
+\r
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)\r
+\r
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006)\r
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)\r
+#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006)\r
+\r
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)\r
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC563M_H */\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
--- /dev/null
+/**************************************************************************\r
+ * FILE NAME: $RCSfile: mpc563m_vars.h,v $ COPYRIGHT (c) Freescale 2005 *\r
+ * DESCRIPTION: All Rights Reserved *\r
+ * Variables that define some features of the MPC563M. *\r
+ * !!!!This file must only be included once in every project!!!! *\r
+ *========================================================================*\r
+ * ORIGINAL AUTHOR: Geoff Emerson [r47354] *\r
+ * $Log: mpc563m_vars.h,v $\r
+ * Revision 1.1 2007/11/09 08:48:41 r47354\r
+ * *** empty log message ***\r
+ *\r
+\r
+ *\r
+ **************************************************************************/\r
+\r
+/* eTPU characteristics definition */\r
+struct eTPU_struct *eTPU = (struct eTPU_struct *)0xC3FC0000;\r
+\r
+uint32_t fs_etpu_code_start = 0xC3FD0000;\r
+uint32_t fs_etpu_data_ram_start = 0xC3FC8000;\r
+uint32_t fs_etpu_data_ram_end = 0xC3FC89FC;\r
+uint32_t fs_etpu_data_ram_ext = 0xC3FCC000;\r
+\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
+\r
+\r
inc-$(USE_COM) += $(ROOTDIR)/communication/PduR\r
vpath-$(USE_PDUR) += $(ROOTDIR)/communication/PduR\r
\r
+# IO Hardware Abstraction\r
+obj-$(USE_IOHWAB) += IoHwAb.o\r
+\r
+#Dem\r
+obj-$(USE_DEM) += Dem.o\r
+obj-$(USE_DEM) += Dem_LCfg.o\r
+inc-$(USE_DEM) += $(ROOTDIR)/diagnostic/Dem\r
+vpath-$(USE_DEM) += $(ROOTDIR)/diagnostic/Dem\r
+\r
+\r
#tests\r
#obj-y += RunTests.o\r
#obj-$(USE_CAN) += can_test.o\r
vpath-y += $(ROOTDIR)/diagnostic/Dem\r
vpath-y += $(ROOTDIR)/diagnostic/Det\r
\r
-\r
-VPATH += $(vpath-y)\r
-\r
-#$(error $(VPATH))\r
-\r
-# libs needed by us\r
-#build-lib-y += $(ROOTDIR)/libs/libboard_$(BOARDDIR).a\r
-\r
# include files need by us\r
inc-y += $(ROOTDIR)/include\r
inc-y += $(ROOTDIR)/kernel/test\r
# And last the generic board\r
#\r
inc-y += $(ROOTDIR)/boards/generic\r
+vpath-y += $(ROOTDIR)/boards/generic\r
+\r
+\r
+VPATH += $(vpath-y)\r
+#$(error $(VPATH))\r
\r
+# libs needed by us\r
+#build-lib-y += $(ROOTDIR)/libs/libboard_$(BOARDDIR).a\r
-
-# ARCH defines
-ARCH=arm_cm3
-ARCH_FAM=arm
-ARCH_MCU=arm_cm3
-
-# CFG (y/n) macros
-CFG=ARM ARM_CM3 BRD_ET_STM32_STAMP STM32_CL
-
-# What buildable modules does this board have,
-# default or private
-MOD_AVAIL=KERNEL MCU PWM ADC SIMPLE_PRINTF ARM_ITM_TERM RAMLOG
-#T32_TERM SIMPLE_PRINTF RAMLOG
-#
-
-# Needed by us
-MOD_USE=KERNEL MCU
-
-# Use little head
-def-y += HEAPSIZE=4000
-def-y += STM32F10X_CL
-
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+# CFG (y/n) macros\r
+CFG=ARM ARM_CM3 BRD_ET_STM32_STAMP STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL=KERNEL MCU PWM ADC SIMPLE_PRINTF ARM_ITM_TERM RAMLOG DEM IOHWAB\r
+#T32_TERM SIMPLE_PRINTF RAMLOG\r
+#\r
+\r
+# Needed by us\r
+MOD_USE=KERNEL MCU\r
+\r
+# Use little head\r
+def-y += HEAPSIZE=4000\r
+def-y += STM32F10X_CL\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_CFG_H_\r
+#define DEM_CFG_H_
+/*
+ * DEM General
+ */
+#define DEM_VERSION_INFO_API STD_ON // Activate/Deactivate ver info API.
+#define DEM_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.
+#define DEM_OBD_SUPPORT STD_OFF
+#define DEM_PTO_SUPPORT STD_OFF
+
+#define DEM_BSW_ERROR_BUFFER_SIZE 20 // Max nr of elements in BSW error buffer (0..255)
+#define DEM_FF_DID_LENGTH TBD // Length of DID & PID of FreezeFrames in Bytes.
+#define DEM_MAX_NUMBER_EVENT_ENTRY_MIR 0 // Max nr of events stored in mirror memory.
+#define DEM_MAX_NUMBER_EVENT_ENTRY_PER 0 // Max nr of events stored in permanent memory.
+#define DEM_MAX_NUMBER_EVENT_ENTRY_PRI 10 // Max nr of events stored in primary memory.
+#define DEM_MAX_NUMBER_EVENT_ENTRY_SEC 0 // Max nr of events stored in secondary memory.
+#define DEM_MAX_NUMBER_PRESTORED_FF 0 // Max nr of prestored FreezeFrames. 0=Not supported.
+
+/*
+ * Size limitations of the types derived from DemGeneral
+ */
+#define DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA 10 // 0..253 according to Autosar
+#define DEM_MAX_NR_OF_EVENT_DESTINATION 4 // 0..4 according to Autosar
+
+/*
+ * Size limitations of storage area
+ */
+#define DEM_MAX_SIZE_FF_DATA 10 // Max number of bytes in one freeze frame
+#define DEM_MAX_SIZE_EXT_DATA 10 // Max number of bytes in one extended data record
+#define DEM_MAX_NUMBER_EVENT 100 // Max number of events to keep status on
+
+#define DEM_MAX_NUMBER_EVENT_PRE_INIT 20 // Max number of events status to keep before init
+#define DEM_MAX_NUMBER_FF_DATA_PRE_INIT 20 // Max number of freeze frames to store before init
+#define DEM_MAX_NUMBER_EXT_DATA_PRE_INIT 20 // Max number of extended data to store before init
+
+#define DEM_MAX_NUMBER_EVENT_PRI_MEM (DEM_MAX_NUMBER_EVENT_ENTRY_PRI) // Max number of events status to store in primary memory
+#define DEM_MAX_NUMBER_FF_DATA_PRI_MEM 5 // Max number of freeze frames to store in primary memory
+#define DEM_MAX_NUMBER_EXT_DATA_PRI_MEM 5 // Max number of extended data to store in primary memory
+
+#endif /*DEM_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DEM_INTERRID_H_\r
+#define DEM_INTERRID_H_\r
+\r
+#endif /*DEM_INTERRID_H_*/\r
+/*
+ * Definition of event IDs used by BSW
+ * NB! Must be unique for each event!
+ */
+\r
+enum {
+ // Event IDs from DEM module
+ DEM_EVENT_ID_NULL = 0, // Do not change this entry!!!
+
+ // Event IDs from MCU
+ MCU_E_CLOCK_FAILURE,
+
+ // Event IDs from CAN
+ CANTRCV_E_NO_TRCV_CONTROL,
+ CANTP_E_OPER_NOT_SUPPORTED,
+ CANTP_E_COMM,
+ CANNM_E_CANIF_TRANSMIT_ERROR,
+ CANM_E_NETWORK_TIMEOUT,
+ CANIF_TRCV_E_TRANSCEIVER,
+ CANIF_E_INVALID_DLC,
+ CANIF_STOPPED,
+ CANIF_E_FULL_TX_BUFFER,
+ CAN_E_TIMEOUT,
+
+ // Event IDs from EEPROM
+ EEP_E_COM_FAILURE,
+
+ // Event IDs from flash
+ FLS_E_ERASED_FAILED,
+ FLS_E_WRITE_FAILED,
+ FLS_E_READ_FAILED,
+ FLS_E_COMPARE_FAILED,
+ FLS_E_UNEXPECTED_FLASH_ID,
+
+ // Event IDs from LIN
+ LIN_E_TIMEOUT,
+ LINIF_E_RESPONSE,
+ LINIF_E_NC_NO_RESPONSE,
+ LINIF_E_CHANNEL_X_SLAVE_Y,
+
+ // Event IDs from ECU
+ ECUM_E_RAM_CHECK_FAILED,
+ ECUM_E_ALL_RUN_REQUESTS_KILLED,
+ ECUM_E_CONFIGURATION_DATA_INCONSISTENT,
+
+ // Event IDs from COM
+// COMM_E_NET_START_IND_CHANNEL_<X>,
+
+ // Event IDs from PDUR
+ PDUR_E_PDU_INSTANCE_LOST,
+ PDUR_E_INIT_FAILED,
+
+ // DEM last event id for BSW
+ DEM_EVENT_ID_LAST_FOR_BSW
+};\r
#ifndef DEMINTEVTID_H_\r
-#define DEMINTEVTID_H_\r
+#define DEMINTEVTID_H_
+
+/*
+ * Definition of event IDs used by SW-C
+ * NB! Must be unique for each event!
+ */
+enum {
+ // NB! Event IDs below DEM_SWC_EVENT_ID_START not allowed!
+ DEM_EVENT_ID_SWC_START = DEM_EVENT_ID_LAST_FOR_BSW
+
+};
+\r
\r
#endif /*DEMINTEVTID_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dem.h"\r
+\r
+/*********************\r
+ * DEM Configuration *
+ *********************/
+
+
+/*
+ * Classes of extended data record
+ */
+
+
+/*
+ * Classes of extended data
+ */
+
+
+/*
+ * Classes of freeze frames
+ */
+
+
+/*
+ * Classes of PreDebounce algorithms
+ */
+
+
+/*
+ * Classes of event
+ */
+
+
+/*
+ * Event parameter list
+ */
+const Dem_EventParameterType EventParameter[] = {
+ {
+ .Arc_EOL = TRUE
+ }
+};
+
+
+/*
+ * DEM's config set
+ */
+const Dem_ConfigSetType DEM_ConfigSet = {
+ .EventParameter = EventParameter,
+// .DTCClassType = NULL, TODO: Add later
+// .GroupOfDtc = NULL, TODO: Add later
+// .OemIdClass = NULL TODO: Add later
+};
+\r
+/*
+ * DEM's config
+ */
+const Dem_ConfigType DEM_Config = {\r
+ .ConfigSet = &DEM_ConfigSet,
+};\r
-
-# ARCH defines
-ARCH=mpc55xx
-ARCH_FAM=ppc
-ARCH_MCU=mpc5516
-
-# CFG (y/n) macros
-CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC5516IT
-
-# What buildable modules does this board have,
-# default or private
-MOD_AVAIL+=KERNEL RAMLOG MCU GPT LIN CAN CANIF PORT DIO WDG WDGM T32_TERM PWM WINIDEA_TERM COM ADC DMA SIMPLE_PRINTF
-
-# Needed by us
-MOD_USE=KERNEL MCU
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5516\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC5516IT\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL+=KERNEL RAMLOG MCU GPT LIN CAN CANIF PORT DIO WDG WDGM T32_TERM PWM WINIDEA_TERM COM ADC DMA SIMPLE_PRINTF DEM PDUR IOHWAB\r
+\r
+# Needed by us\r
+MOD_USE=KERNEL MCU\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Adc ADC Driver
+ * @{ */
+
+/** @file Adc_Cfg.h
+ * Definitions of configuration parameters for ADC Driver.
+ */
+
#ifndef ADC_CFG_H_\r
#define ADC_CFG_H_\r
#include "Dma.h"
-\r
-#define ADC_PRIORITY_HW 0\r
-#define ADC_PRIORITY_HW_SW 1\r
+
+/** HW priority mechanism only. @see ADC_PRIORITY_IMPLEMENTATION */
+#define ADC_PRIORITY_HW 0
+/** HW and SW priority mechanism. @see ADC_PRIORITY_IMPLEMENTATION */
+#define ADC_PRIORITY_HW_SW 1
+/** No priority mechanism. @see ADC_PRIORITY_IMPLEMENTATION */
#define ADC_PRIORITY_NONE 2\r
-\r
-#define ADC_DEINIT_API STD_ON\r
-#define ADC_DEV_ERROR_DETECT STD_ON\r
-#define ADC_ENABLE_QUEUING STD_ON\r
-#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
-#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
-#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
-#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
-#define ADC_READ_GROUP_API STD_ON\r
-#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+
+/** Build DeInit API */
+#define ADC_DEINIT_API STD_ON
+/** Enable Development Error Trace */
+#define ADC_DEV_ERROR_DETECT STD_ON
+/** Not supported. */
+#define ADC_ENABLE_QUEUING STD_ON
+/** Build Start/Stop group API. */
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON
+/** Enable group conversion notification. */
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON
+/** Not supported. */
+#define ADC_HW_TRIGGER_API STD_OFF
+/** Implemented priority mechanism. */
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW
+/** Build Read group API */
+#define ADC_READ_GROUP_API STD_ON
+/** Build version info API (Not supported) */
+#define ADC_VERSION_API STD_ON
typedef uint16_t Adc_ValueGroupType;
-/* Non-standard type */
+/** HW specific data type. */
typedef union
{
vuint32_t R;
} B;
}Adc_CommandType;
-/* Std-type, supplier defined */
+/** Type of clock input for the conversion unit. */
typedef enum
{
ADC_SYSTEM_CLOCK
}Adc_ClockSourceType;
-/* Std-type, supplier defined */
+/** Clock prescaler factor. */
typedef enum
{
ADC_SYSTEM_CLOCK_DISABLED,
ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,
}Adc_PrescaleType;
-/* Non-standard type */
+/** Container for HW setup. */
typedef struct
{
Adc_ClockSourceType clockSource;
Adc_PrescaleType adcPrescale;
}Adc_HWConfigurationType;
-/* Std-type, supplier defined */
+/** Reference voltage source. */
typedef enum
{
ADC_REFERENCE_VOLTAGE_GROUND,
ADC_REFERENCE_VOLTAGE_5V,
}Adc_VoltageSourceType;
-/* Std-type, supplier defined */
+/** Duration of conversion. */
typedef enum
{
ADC_CONVERSION_TIME_2_CLOCKS,
ADC_CONVERSION_TIME_128_CLOCKS
}Adc_ConversionTimeType;
-/* Non-standard type */
+/** Enable/disable calibration. */
typedef enum
{
ADC_CALIBRATION_DISABLED,
ADC_CALIBRATION_ENABLED
}Adc_CalibrationType;
-/* Std-type, supplier defined */
+/** Channel resolution. */
typedef enum
{
ADC_RESOLUTION_12BITS
}Adc_ResolutionType;
-/* Non-standard type */
-/* Channel definitions. */
+/** Container for channel configuration. */
typedef struct
{
Adc_ConversionTimeType adcChannelConvTime;
/* TODO list timer sources here. */
-/* Std-type, supplier defined */
+/** Not supported. */
typedef enum
{
ADC_NO_TIMER,
}Adc_HwTriggerTimerType;
-/* Std-type, supplier defined */
+/** Not supported. */
typedef uint16_t Adc_StreamNumSampleType;
-/* Std-type, supplier defined */
+/** Channel conversion mode. */
typedef enum
{
ADC_CONV_MODE_DISABLED,
- ADC_CONV_MODE_ONESHOT = 1,
- ADC_CONV_MODE_CONTINOUS = 9,
+ ADC_CONV_MODE_ONESHOT = 1, /**< A single conversion. */
+ ADC_CONV_MODE_CONTINOUS = 9, /**< Conversions performed continuously. */
}Adc_GroupConvModeType;
-/* Impl. specific */
+/** Container for module initialization parameters. */
typedef struct
{
const Adc_HWConfigurationType* hwConfigPtr;
extern const Adc_ConfigType AdcConfig [];
-/* Used ?? */
+/** Container for groups status info. */
typedef struct
{
uint8 notifictionEnable;
Adc_StatusType groupStatus;
}Adc_GroupStatus;
-/* Implementation specific */
+/** Container for group setup. */
typedef struct
{
Adc_GroupAccessModeType accessMode;
}Adc_GroupDefType;
\r
/* Group definitions. */\r
-\r
+
+/** ID of group */
typedef enum\r
{\r
ADC_GROUP0,\r
ADC_GROUP3,\r
ADC_NBR_OF_GROUPS\r
}Adc_GroupType;\r
-\r
+
+/** ID of channel */
typedef enum\r
{\r
ADC_CH0,\r
ADC_GROUP3_CH2,\r
ADC_NBR_OF_GROUP3_CHANNELS,\r
}Adc_Group3Signals;\r
-\r
-extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+
+/** HW specific command configarations. */
+extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];
+/** HW specific result buffer configarations. */
extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
\r
#endif /*ADC_CFG_H_*/\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup CanIf CAN Interface
+ * @{ */
-
-
-
-
-
+/** @file CanIf_Cfg.h
+ * Definitions of configuration parameters for CAN Interface.
+ */
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
\r
#include "Can.h"\r
-// Identifiers for the elements in CanIfControllerConfig[]
-// This is the ConfigurationIndex in CanIf_InitController()
+/** Identifiers for the elements in CanIfControllerConfig[].
+ * This is the ConfigurationIndex in CanIf_InitController(). */
typedef enum {
CANIF_CHANNEL_0_CONFIG_0 = 0,
CANIF_CHANNEL_CONFIGURATION_CNT
} CanIf_Arc_ConfigurationIndexType;
+/** Channel id's */
typedef enum {
CANIF_CHANNEL_0,
CANIF_CHANNEL_1,
CANIF_CHANNEL_CNT,
} CanIf_Arc_ChannelIdType;
-\r
+
+/** Software filtering type */
typedef enum {\r
- CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
- CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
- CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
- CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
- CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, /**< Not supported */
+ CANIF_SOFTFILTER_TYPE_INDEX, /**< Not supported */
+ CANIF_SOFTFILTER_TYPE_LINEAR, /**< Not supported */
+ CANIF_SOFTFILTER_TYPE_TABLE, /**< Not supported */
+ CANIF_SOFTFILTER_TYPE_MASK, /**< CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering */
} CanIf_SoftwareFilterTypeType;\r
-\r
+
+/** Type of the upper layer interfacing this module */
typedef enum {\r
CANIF_USER_TYPE_CAN_NM,\r
CANIF_USER_TYPE_CAN_TP,\r
CANIF_USER_TYPE_CAN_SPECIAL,\r
} CanIf_UserTypeType;\r
\r
-\r
-\r
+/** Notification function for CANIF_USER_TYPE_CAN_SPECIAL */
typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
-\r
+
+/** Defines if PDU Can id can be changed at runtime. */
typedef enum {\r
CANIF_PDU_TYPE_STATIC = 0,\r
- CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+ CANIF_PDU_TYPE_DYNAMIC /**< Not supported */
} CanIf_PduTypeType;\r
-\r
+
+/** PDU Can id type */
typedef enum {\r
CANIF_CAN_ID_TYPE_29 = 0,\r
CANIF_CAN_ID_TYPE_11\r
/*\r
* Public container\r
*/\r
-#define CANIF_VERSION_INFO_API STD_ON\r
-#define CANIF_DEV_ERROR_DETECT STD_ON\r
-#define CANIF_DLC_CHECK STD_ON\r
-#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
-#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
-#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
-#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
-#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
-#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
-#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
-#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+#define CANIF_VERSION_INFO_API STD_ON /**< Build version info API */
+#define CANIF_DEV_ERROR_DETECT STD_ON /**< Enable Development Error Trace */
+#define CANIF_DLC_CHECK STD_ON /**< Enable/disable DLC checking. */
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF /**< Not supported */
+#define CANIF_READRXPDU_DATA_API STD_OFF /**< Not supported */
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF /**< Not supported */
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF /**< Not supported */
+#define CANIF_SETDYNAMICTXID_API STD_OFF /**< Not supported */
+#define CANIF_WAKEUP_EVENT_API STD_OFF /**< Not supported */
+#define CANIF_TRANSCEIVER_API STD_OFF /**< Not supported */
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF /**< Not supported */
\r
//-------------------------------------------------------------------\r
\r
\r
\r
//-------------------------------------------------------------------\r
-/*\r
- * CanIfHrhRangeConfig container\r
- */\r
\r
+/** Parameters for configuring Can id ranges. Not supported. */
typedef struct {\r
- // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
- // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
- // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ /** Lower CAN Identifier of a receive CAN L-PDU for identifier range
+ * definition, in which all CAN Ids shall pass the software filtering. Range: 11
+ * Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer */
uint32 CanIfRxPduLowerCanId;\r
\r
- // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
- // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
- // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ /** Upper CAN Identifier of a receive CAN L-PDU for identifier range
+ * definition, in which all CAN Ids shall pass the software filtering. Range: 11
+ * Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer */
uint32 CanIfRxPduUpperCanId;\r
} CanIf_HrhRangeConfigType;\r
\r
\r
-\r
//-------------------------------------------------------------------\r
/*\r
* CanIfInitHrhConfig container\r
- */\r
+ */
+/** Definition of Hardware Receive Handle */
typedef struct {\r
- // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
- // configured, software filtering is enabled.\r
+ /** Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is
+ * configured, software filtering is enabled. */
Can_Arc_HohType CanIfHrhType;\r
\r
- // Selects the hardware receive objects by using the HRH range/list from\r
- // CAN Driver configuration to define, for which HRH a software filtering has\r
- // to be performed at during receive processing. True: Software filtering is\r
- // enabled False: Software filtering is disabled\r
+ /** Selects the hardware receive objects by using the HRH range/list from
+ * CAN Driver configuration to define, for which HRH a software filtering has
+ * to be performed at during receive processing. True: Software filtering is
+ * enabled False: Software filtering is disabled */
boolean CanIfSoftwareFilterHrh;\r
\r
- // Reference to controller Id to which the HRH belongs to. A controller can\r
- // contain one or more HRHs.\r
+ /** Reference to controller Id to which the HRH belongs to. A controller can
+ * contain one or more HRHs. */
CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
\r
- // The parameter refers to a particular HRH object in the CAN Driver Module\r
- // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
- // are defined in the CAN Driver Module and hence it is derived from CAN\r
- // Driver Configuration.\r
+ /** The parameter refers to a particular HRH object in the CAN Driver Module
+ * configuration. The HRH id is unique in a given CAN Driver. The HRH Ids
+ * are defined in the CAN Driver Module and hence it is derived from CAN
+ * Driver Configuration. */
Can_Arc_HRHType CanIfHrhIdSymRef ;\r
\r
- // Defines the parameters required for configuraing multiple\r
- // CANID ranges for a given same HRH.\r
+ /** Defines the parameters required for configuraing multiple
+ * CANID ranges for a given same HRH. */
const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
\r
- // End Of List. Set to TRUE is this is the last object in the list.\r
+ /** End Of List. Set to TRUE if this is the last object in the list. */
boolean CanIf_Arc_EOL;\r
} CanIf_HrhConfigType;\r
\r
/*\r
* CanIfInitHthConfig container\r
*/\r
-\r
+/** Definition of Hardware Transmit Handle */
typedef struct {\r
- // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ /** Defines the HTH type i.e, whether its a BasicCan or FullCan. */
Can_Arc_HohType CanIfHthType;\r
\r
- // Reference to controller Id to which the HTH belongs to. A controller\r
- // can contain one or more HTHs\r
+ /** Reference to controller Id to which the HTH belongs to. A controller
+ * can contain one or more HTHs */
CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
\r
- // The parameter refers to a particular HTH object in the CAN Driver Module\r
- // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
- // are defined in the CAN Driver Module and hence it is derived from CAN\r
- // Driver Configuration.\r
+ /** The parameter refers to a particular HTH object in the CAN Driver Module
+ * configuration. The HTH id is unique in a given CAN Driver. The HTH Ids
+ * are defined in the CAN Driver Module and hence it is derived from CAN
+ * Driver Configuration. */
Can_Arc_HTHType CanIfHthIdSymRef ;\r
\r
- // End Of List. Set to TRUE is this is the last object in the list.\r
+ /** End Of List. Set to TRUE if this is the last object in the list. */
boolean CanIf_Arc_EOL;\r
} CanIf_HthConfigType;\r
\r
//-------------------------------------------------------------------\r
/*\r
* CanIfInitHohConfig container\r
- */\r
+ */
+/** Definition of Hardware Object Handle. */
typedef struct {\r
- // Selects the CAN interface specific configuration setup. This type of external\r
- // data structure shall contain the post build initialization data for the\r
- // CAN interface for all underlying CAN Drivers.\r
+ /** Reference to the CAN Driver controller config. */
const Can_ConfigSetType *CanConfigSet;\r
\r
- // This container contains contiguration parameters for each hardware receive object.\r
+ /** This container contains contiguration parameters for each hardware receive object. */
const CanIf_HrhConfigType *CanIfHrhConfig;\r
\r
- // This container contains parameters releated to each HTH\r
+ /** This container contains parameters releated to each HTH */
const CanIf_HthConfigType *CanIfHthConfig;\r
\r
- // End Of List. Set to TRUE is this is the last object in the list.\r
+ /** End Of List. Set to TRUE if this is the last object in the list. */
boolean CanIf_Arc_EOL;\r
} CanIf_InitHohConfigType;\r
\r
* CanIfTxPduConfig container\r
*/\r
\r
-// This container contains the configuration (parameters) of each transmit\r
-// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
-// represents the symolic name of Transmit L-PDU.\r
+/** Definition of Tx PDU (Protocol Data Unit). */
typedef struct {\r
- // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
- // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
- // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ /** ECU wide unique, symbolic handle for transmit CAN L-PDU. The
+ * CanIfCanTxPduId is configurable at pre-compile and post-built time.
+ * Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId; */
PduIdType CanIfTxPduId;\r
\r
- // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
- // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
- // Extended CAN identifier\r
+ /** CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-
+ * PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For
+ * Extended CAN identifier */
uint32 CanIfCanTxPduIdCanId;\r
\r
- // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
- // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
- // can have a range from 0 to 8 bytes.\r
+ /** Data length code (in bytes) of transmit CAN L-PDUs used by the CAN
+ * Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu
+ * can have a range from 0 to 8 bytes. */
uint8 CanIfCanTxPduIdDlc;\r
\r
- // Defines the type of each transmit CAN L-PDU.\r
- // DYNAMIC CAN ID is defined at runtime.\r
- // STATIC CAN ID is defined at compile-time.\r
+ /** Defines the type of each transmit CAN L-PDU.
+ * DYNAMIC CAN ID is defined at runtime.
+ * STATIC CAN ID is defined at compile-time. */
CanIf_PduTypeType CanIfCanTxPduType;\r
\r
#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
- // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
- // for reading its notification status. True: Enabled False: Disabled\r
+ /** Enables and disables transmit confirmation for each transmit CAN L-PDU
+ * for reading its notification status. True: Enabled False: Disabled */
boolean CanIfReadTxPduNotifyStatus;\r
#endif\r
\r
- // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
- // PDU transmission.\r
- // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
- // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ /** CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-
+ * PDU transmission.
+ * EXTENDED_CAN The CANID is of type Extended (29 bits).
+ * STANDARD_CAN The CANID is of type Standard (11 bits). */
CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
\r
- // Name of target confirmation services to target upper layers (PduR, CanNm\r
- // and CanTp. If parameter is not configured then no call-out function is\r
- // provided by the upper layer for this Tx L-PDU.\r
+ /** Name of target confirmation services to target upper layers (PduR, CanNm
+ * and CanTp. If parameter is not configured then no call-out function is
+ * provided by the upper layer for this Tx L-PDU. */
void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
\r
- // Handle, that defines the hardware object or the pool of hardware objects\r
- // configured for transmission. The parameter refers HTH Id, to which the L-\r
- // PDU belongs to.\r
+ /** Handle, that defines the hardware object or the pool of hardware objects
+ * configured for transmission. The parameter refers HTH Id, to which the L-
+ * PDU belongs to. */
const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
\r
- // Reference to the "global" Pdu structure to allow harmonization of handle\r
- // IDs in the COM-Stack. ..\r
+ /** Reference to the "global" Pdu structure to allow harmonization of handle
+ * IDs in the COM-Stack. */
void *PduIdRef;\r
} CanIf_TxPduConfigType;\r
\r
*/\r
\r
\r
-// This container contains the configuration (parameters) of each receive\r
-// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
-// represents the symolic name of Receive L-PDU.\r
-\r
+/** Definition of Rx PDU (Protocol Data Unit). */
typedef struct {\r
- // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
- // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
- // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
- // of defined CanRxPduIds\r
+ /** ECU wide unique, symbolic handle for receive CAN L-PDU. The
+ * CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill
+ * ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number
+ * of defined CanRxPduIds */
PduIdType CanIfCanRxPduId;\r
\r
- // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
- // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
- // Extended CAN identifier\r
+ /** CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:
+ * Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For
+ * Extended CAN identifier */
uint32 CanIfCanRxPduCanId;\r
\r
- // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
- // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
- // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ /** Data Length code of received CAN L-PDUs used by the CAN Interface.
+ * Exa: DLC check. The data area size of a CAN L-PDU can have a range
+ * from 0 to 8 bytes. uint8 CanIfCanRxPduDlc; */
uint8 CanIfCanRxPduDlc;\r
\r
#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
- // Enables and disables the Rx buffering for reading of received L-PDU data.\r
- // True: Enabled False: Disabled\r
+ /** Enables and disables the Rx buffering for reading of received L-PDU data.
+ * True: Enabled False: Disabled */
boolean CanIfReadRxPduData;\r
#endif\r
\r
#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
- // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
- // Enables and disables receive indication for each receive CAN L-PDU for\r
- // reading its' notification status. True: Enabled False: Disabled\r
+ /** CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}
+ * Enables and disables receive indication for each receive CAN L-PDU for
+ * reading its' notification status. True: Enabled False: Disabled */
boolean CanIfReadRxPduNotifyStatus;\r
#endif\r
\r
- // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
- // PDU transmission.\r
- // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
- // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ /** CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-
+ * PDU transmission.
+ * EXTENDED_CAN The CANID is of type Extended (29 bits)
+ * STANDARD_CAN The CANID is of type Standard (11 bits) */
CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
\r
- // This parameter defines the type of the receive indication call-outs called to\r
- // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ /** This parameter defines the type of the receive indication call-outs called to
+ * the corresponding upper layer the used TargetRxPduId belongs to. */
CanIf_UserTypeType CanIfRxUserType;\r
\r
- // Name of target indication services to target upper layers (PduRouter,\r
- // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
- // function is configured.\r
+ /** Name of target indication services to target upper layers (PduRouter,
+ * CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out
+ * function is configured. */
void *CanIfUserRxIndication;\r
\r
- // The HRH to which Rx L-PDU belongs to, is referred through this\r
- // parameter.\r
+ /** The HRH to which Rx L-PDU belongs to, is referred through this
+ * parameter. */
const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
\r
- // Reference to the "global" Pdu structure to allow harmonization of handle\r
- // IDs in the COM-Stack.\r
+ /** Reference to the "global" Pdu structure to allow harmonization of handle
+ * IDs in the COM-Stack. */
void *PduIdRef;\r
\r
- // Defines the type of software filtering that should be used\r
- // for this receive object.\r
+ /** Defines the type of software filtering that should be used
+ * for this receive object. */
CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
\r
- // Acceptance filters, 1 - care, 0 - don't care.\r
- // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
- // ArcCore exension\r
+ /** Acceptance filters, 1 - care, 0 - don't care.
+ * Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType
+ * ArcCore exension */
uint32 CanIfCanRxPduCanIdMask;\r
\r
} CanIf_RxPduConfigType;\r
/*\r
* CanIfControllerConfig container\r
*/\r
-\r
+/** Not supported. */
typedef enum {\r
CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
} CanIf_WakeupSupportType;\r
\r
\r
-// This is the type supplied to CanIf_InitController()\r
-typedef struct {\r
- CanIf_WakeupSupportType WakeupSupport; // Not used\r
+/** Container used to create channel init configurations.
+ * @see CanIf_Arc_ConfigurationIndexType
+ * @see CanIf_Arc_ChannelIdType */
+typedef struct {
+ /** Not used */
+ CanIf_WakeupSupportType WakeupSupport;
- // CanIf-specific id of the controller\r
+ /** CanIf-specific id of the controller */
CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
-\r
- const char CanIfDriverNameRef[8]; // Not used\r
-\r
+
+ /** Not used */
+ const char CanIfDriverNameRef[8];
+
+ /** Reference to */
const Can_ControllerConfigType *CanIfInitControllerRef;\r
} CanIf_ControllerConfigType;\r
\r
uint32 todo;\r
} CanIf_TransceiverConfigType;\r
\r
-// Callout functions with respect to the upper layers. This callout functions\r
-// defined in this container are common to all configured underlying CAN\r
-// Drivers / CAN Transceiver Drivers.\r
+/** Callout functions with respect to the upper layers. This callout functions
+ * defined in this container are common to all configured underlying CAN
+ * Drivers / CAN Transceiver Drivers. */
typedef struct {\r
- // Name of target BusOff notification services to target upper layers\r
- // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
- // Multiplicity: 1\r
+ /** Name of target BusOff notification services to target upper layers
+ * (PduRouter, CanNm, CanTp and ComplexDeviceDrivers). */
void (*CanIfBusOffNotification)(uint8 Controller);\r
\r
- // Name of target wakeup notification services to target upper layers\r
- // e.g Ecu_StateManager. If parameter is 0\r
- // no call-out function is configured.\r
- // Multiplicity: 0..1\r
+ /** Name of target wakeup notification services to target upper layers
+ * e.g Ecu_StateManager. If parameter is 0
+ * no call-out function is configured. */
void (*CanIfWakeUpNotification)();\r
\r
- // Name of target wakeup validation notification services to target upper\r
- // layers (ECU State Manager). If parameter is 0 no call-out function is\r
- // configured.\r
- // Multiplicity: 0..1\r
+ /** Name of target wakeup validation notification services to target upper
+ * layers (ECU State Manager). If parameter is 0 no call-out function is
+ * configured. */
void (*CanIfWakeupValidNotification)();\r
\r
- // ArcCore ext.\r
+ /** ArcCore ext. */
void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
\r
} CanIf_DispatchConfigType;\r
\r
-// This container contains the references to the configuration setup of each\r
-// underlying CAN driver.\r
-\r
+/** This container contains the references to the configuration setup of each
+ * underlying CAN driver. */
typedef struct {\r
- // Selects the CAN Interface specific configuration setup. This type of the\r
- // external data structure shall contain the post build initialization data for the\r
- // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ /** Not used. */
uint32 CanIfConfigSet;\r
-\r
- uint32 CanIfNumberOfCanRxPduIds;\r
- uint32 CanIfNumberOfCanTXPduIds;\r
+
+ /** Size of Rx PDU list. */
+ uint32 CanIfNumberOfCanRxPduIds;
+ /** Size of Tx PDU list. */
+ uint32 CanIfNumberOfCanTXPduIds;
+ /** Not used */
uint32 CanIfNumberOfDynamicCanTXPduIds;\r
\r
//\r
// Containers\r
//\r
\r
- // This container contains the reference to the configuration\r
- // setup of each underlying CAN driver.\r
- // Multiplicity: 0..*\r
+ /** Hardware Object Handle list */
const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
\r
- // This container contains the configuration (parameters) of each\r
- // receive CAN L-PDU. The SHORT-NAME of\r
- // "CanIfRxPduConfig" container itself represents the symolic\r
- // name of Receive L-PDU.\r
- // Multiplicity: 0..*\r
+ /** Rx PDU's list */
const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
-\r
- // This container contains the configuration (parameters) of each\r
- // transmit CAN L-PDU. The SHORT-NAME of\r
- // "CanIfTxPduConfig" container represents the symolic name of\r
- // Transmit L-PDU.\r
- // Multiplicity: 0..*\r
+
+ /** Tx PDU's list */
const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
\r
} CanIf_InitConfigType;\r
\r
-\r
+/** Top level config container. */
typedef struct {\r
- // This container contains the configuration (parameters) of all\r
- // addressed CAN controllers by each underlying CAN driver.\r
- // Multiplicity: 1..*\r
+ /** Reference to the list of channel init configurations. */
const CanIf_ControllerConfigType *ControllerConfig;\r
\r
- // Callout functions with respect to the upper layers. This callout\r
- // functions defined in this container are common to all\r
- // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ /** Callout functions with respect to the upper layers. This callout
+ * functions defined in this container are common to all
+ * configured underlying CAN Drivers / CAN Transceiver Drivers */
const CanIf_DispatchConfigType *DispatchConfig;\r
\r
- // This container contains the init parameters of the CAN\r
- // Interface.\r
- // Multiplicity: 1..*\r
+ /** This container contains the init parameters of the CAN Interface. */
const CanIf_InitConfigType *InitConfig;\r
\r
- // This container contains the configuration (parameters) of all\r
- // addressed CAN transceivers by each underlying CAN\r
- // Transceiver Driver.\r
- // Multiplicity: 1..*\r
+ /** Not used */
const CanIf_TransceiverConfigType *TransceiverConfig;
- // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers
+ /** ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers */
const CanControllerIdType *Arc_ChannelToControllerMap;\r
} CanIf_ConfigType;\r
\r
-\r
+/** Instance of the top level container. */
extern CanIf_ConfigType CanIf_Config;\r
\r
#endif\r
-\r
+/** @} */
\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Can CAN Driver
+ * @{ */
-
-
-
-
-
+/** @file Can_Cfg.h
+ * Definitions of configuration parameters for CAN Driver.
+ */
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
-// Number of controller configs\r
+/** Number of controller configs. */
#define CAN_ARC_CTRL_CONFIG_CNT 2\r
-\r
-#define CAN_DEV_ERROR_DETECT STD_ON\r
-#define CAN_VERSION_INFO_API STD_ON\r
-#define CAN_MULTIPLEXED_TRANSMISSION STD_ON // Makes no differens in the code\r
-#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
-#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
-\r
-// loop cnt.. very strange timeout\r
+
+/** Enable Development Error Trace. */
+#define CAN_DEV_ERROR_DETECT STD_ON
+/** Build version info API. */
+#define CAN_VERSION_INFO_API STD_ON
+/** Not supported. */
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF
+/** Not supported. */
+#define CAN_WAKEUP_SUPPORT STD_OFF
+/** Not supported. */
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF
+/** Not supported. */
#define CAN_TIMEOUT_DURATION 100\r
\r
#define INTERRUPT 0\r
#define POLLING 1\r
\r
-// Can controller\r
-#define CAN_BUSOFF_PROCESSING INTERRUPT // INTERRUPT/POLLING\r
-#define CAN_CONTROLLER_ACTIVATION OFF\r
-#define CAN_CONTROLLER_BAUD_RATE 125000\r
-#define CAN_DRIVER_CONTROLLER_ID 0\r
-#define CAN_CONTROLLER_PROP_SEG 4\r
-#define CAN_CONTROLLER_PHASE1_SEG 4\r
-#define CAN_CONTROLLER_PHASE2_SEG 4\r
-#define CAN_CONTROLLER_TIME_QUANTA 4\r
-#define CAN_RX_PROCESSING INTERRUPT\r
-#define CAN_TX_PROCESSING INTERRUPT\r
+// Can controller
+/** Bus off handling. Polling not supported */
+#define CAN_BUSOFF_PROCESSING INTERRUPT // INTERRUPT/POLLING
+/** Not supported. */
+#define CAN_CONTROLLER_ACTIVATION OFF
+/** Not used. @see Can_ControllerConfigType */
+#define CAN_CONTROLLER_BAUD_RATE 125000
+/** Not used. @see CanControllerIdType */
+#define CAN_DRIVER_CONTROLLER_ID 0
+/** Not used. @see Can_ControllerConfigType */
+#define CAN_CONTROLLER_PROP_SEG 4
+/** Not used. @see Can_ControllerConfigType */
+#define CAN_CONTROLLER_PHASE1_SEG 4
+/** Not used. @see Can_ControllerConfigType */
+#define CAN_CONTROLLER_PHASE2_SEG 4
+/** Not used. @see Can_ControllerConfigType */
+#define CAN_CONTROLLER_TIME_QUANTA 4
+/** Rx handling. Polling not supported. */
+#define CAN_RX_PROCESSING INTERRUPT
+/** Tx handling. Polling not supported. */
+#define CAN_TX_PROCESSING INTERRUPT
+/** Wakeup handling. Polling not supported. */
#define CAN_WAKEUP_PROCESSING INTERRUPT\r
-\r
+
+/** Available HW controllers. */
typedef enum {\r
CAN_CTRL_A = 0,\r
CAN_CTRL_B,\r
CAN_CTRL_F,\r
CAN_CONTROLLER_CNT \r
}CanControllerIdType;\r
-\r
+
+/** CAN id types. */
typedef enum {\r
CAN_ID_TYPE_EXTENDED,\r
CAN_ID_TYPE_MIXED,\r
CAN_ID_TYPE_STANDARD,\r
} Can_IdTypeType;\r
-\r
+
+/** CAN HW object types. */
typedef enum {\r
CAN_OBJECT_TYPE_RECEIVE,\r
CAN_OBJECT_TYPE_TRANSMIT,\r
} Can_ObjectTypeType;\r
-\r
+
+/** HW object Can type. Full not supported. */
typedef enum {\r
CAN_ARC_HANDLE_TYPE_BASIC,\r
CAN_ARC_HANDLE_TYPE_FULL\r
} Can_Arc_HohType;\r
\r
// HTH definitions\r
-// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration
+/** Transmit object id:s */
typedef enum {\r
CAN_HTH_A_1 = 0,\r
CAN_HTH_C_1,\r
} Can_Arc_HTHType;\r
\r
// HRH definitions\r
-// Due to effiency: Start with index 0 and don't use any holes in the enumeration\r
+// Due to effiency: Start with index 0 and don't use any holes in the enumeration
+/** Receive object id:s */
typedef enum {\r
CAN_HRH_A_1 = 0,\r
CAN_HRH_C_1,\r
NUM_OF_HRHS\r
} Can_Arc_HRHType;\r
\r
-// Non-standard type\r
+// Non-standard type
+/** Container for callback configuration. */
typedef struct {\r
- void (*CancelTxConfirmation)( const Can_PduType *);\r
- void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
- void (*ControllerBusOff)(uint8);\r
- void (*TxConfirmation)(PduIdType);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+ void (*CancelTxConfirmation)( const Can_PduType *); /**< Not supported. */
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * ); /**< Called on successful reception of a PDU. */
+ void (*ControllerBusOff)(uint8); /**< Called on BusOff. */
+ void (*TxConfirmation)(PduIdType); /**< Called on successful transmission of a PDU. */
+ void (*ControllerWakeup)(uint8); /**< Not supported. */
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType); /**< Called on HW error. */
} Can_CallbackType;\r
\r
/*\r
* CanGeneral Container\r
*/\r
\r
-// This container contains the parameters related each CAN Driver Unit.\r
+/** Container for parameters related to the CAN Driver. */
typedef struct {\r
- // Specifies the InstanceId of this module instance. If only one instance is\r
- // present it shall have the Id 0\r
+ /** Specifies the InstanceId of this module instance. If only one instance is
+ * present it shall have the Id 0 */
int CanIndex;\r
\r
#if 0 // This is only used by the config tool\r
} Can_GeneralType;\r
\r
\r
-/*\r
- * CanFilterMask container\r
- */\r
+/** Type for Can id filter mask */
typedef uint32 Can_FilterMaskType;\r
\r
/*\r
* CanHardwareObject container\r
- */\r
-\r
-//This container contains the configuration (parameters) of CAN Hardware\r
-//Objects.\r
+ */
+
+/** Container for CAN Hardware Object parameters */
typedef struct Can_HardwareObjectStruct {\r
- // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ /** Specifies the type (Full-CAN or Basic-CAN) of a hardware object. */
Can_Arc_HohType CanHandleType;\r
\r
- // Specifies whether the IdValue is of type - standard identifier - extended\r
- // identifier - mixed mode ImplementationType: Can_IdType\r
+ /** Specifies whether the IdValue is of type - standard identifier - extended
+ * identifier - mixed mode */
Can_IdTypeType CanIdType;\r
\r
- // Specifies (together with the filter mask) the identifiers range that passes\r
- // the hardware filter.\r
+ /** Specifies (together with the filter mask) the identifiers range that passes
+ * the hardware filter. */
uint32 CanIdValue;\r
\r
- // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
- // in a given CAN Driver, and it should start with 0 and continue without any\r
- // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
- // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ /** Holds the handle ID of HRH or HTH. The value of this parameter is unique
+ * in a given CAN Driver, and it should start with 0 and continue without any
+ * gaps. The HRH and HTH Ids are defined under two different name-spaces.
+ * Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3 */
uint32 CanObjectId;\r
\r
- // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ /** Specifies if the HardwareObject is used as Transmit or as Receive object */
Can_ObjectTypeType CanObjectType;\r
\r
- // Reference to the filter mask that is used for hardware filtering togerther\r
- // with the CAN_ID_VALUE\r
+ /** Reference to the filter mask that is used for hardware filtering togerther
+ * with the CAN_ID_VALUE */
Can_FilterMaskType *CanFilterMaskRef;\r
\r
- // A "1" in this mask tells the driver that that HW Message Box should be\r
- // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ /** A "1" in this mask tells the driver that that HW Message Box should be
+ * occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW. */
uint32 Can_Arc_MbMask;\r
\r
- // End Of List. Set to TRUE is this is the last object in the list.\r
+ /** End Of List. Set to TRUE if this is the last object in the list. */
boolean Can_Arc_EOL;\r
\r
} Can_HardwareObjectType;\r
CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
CAN_ARC_PROCESS_TYPE_POLLING,\r
} Can_Arc_ProcessType;\r
-\r
+
+/** Container for configuration of a controller. */
typedef struct {\r
\r
- // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
- // events in polling mode.\r
- // INTERRUPT or POLLING\r
+ /** Enables / disables API Can_MainFunction_BusOff() for handling busoff
+ * events in polling mode. Polling not supported. */
Can_Arc_ProcessType CanBusOffProcessing;\r
\r
- // Defines if a CAN controller is used in the configuration.\r
+ /** Defines if a CAN controller is used in the configuration. */
boolean CanControllerActivation;\r
\r
- // Specifies the buadrate of the controller in kbps.\r
+ /** Specifies the buadrate of the controller in kbps. */
uint32 CanControllerBaudRate;\r
\r
- // This parameter provides the controller ID which is unique in a given CAN\r
- // Driver. The value for this parameter starts with 0 and continue without any\r
- // gaps.\r
+ /** This parameter provides the controller ID which is unique in a given CAN
+ * Driver. The value for this parameter starts with 0 and continue without any
+ * gaps. */
CanControllerIdType CanControllerId;\r
\r
- // Specifies propagation delay in time quantas.\r
+ /** Specifies propagation delay in time quantas. */
uint32 CanControllerPropSeg;\r
\r
- // Specifies phase segment 1 in time quantas.\r
+ /** Specifies phase segment 1 in time quantas. */
uint32 CanControllerSeg1;\r
\r
- // Specifies phase segment 2 in time quantas.\r
+ /** Specifies phase segment 2 in time quantas. */
uint32 CanControllerSeg2;\r
\r
- // Specifies the time quanta for the controller. The calculation of the resulting\r
- // prescaler value depending on module clocking and time quanta shall be\r
- // done offline Hardware specific.\r
+ /** Specifies the time quanta for the controller. The calculation of the resulting
+ * prescaler value depending on module clocking and time quanta shall be
+ * done offline Hardware specific. */
uint32 CanControllerTimeQuanta;\r
\r
- // Enables / disables API Can_MainFunction_Read() for handling PDU\r
- // reception events in polling mode.\r
+ /** Enables / disables API Can_MainFunction_Read() for handling PDU
+ * reception events in polling mode. Polling not supported. */
Can_Arc_ProcessType CanRxProcessing;\r
\r
- // Enables / disables API Can_MainFunction_Write() for handling PDU\r
- // transmission events in polling mode.\r
+ /** Enables / disables API Can_MainFunction_Write() for handling PDU
+ * transmission events in polling mode. Polling not supported. */
Can_Arc_ProcessType CanTxProcessing;\r
\r
- // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
- // events in polling mode.\r
+ /** Enables / disables API Can_MainFunction_Wakeup() for handling wakeup
+ * events in polling mode. Polling not supported. */
Can_Arc_ProcessType CanWakeupProcessing;\r
\r
- // Reference to the CPU clock configuration, which is set in the MCU driver\r
- // configuration\r
+ /** Reference to the CPU clock configuration, which is set in the MCU driver
+ * configuration */
uint32 CanCpuClockRef;\r
\r
- // This parameter contains a reference to the Wakeup Source for this\r
- // controller as defined in the ECU State Manager. Implementation Type:\r
- // reference to EcuM_WakeupSourceType\r
+ /** This parameter contains a reference to the Wakeup Source for this
+ * controller as defined in the ECU State Manager. Implementation Type:
+ * reference to EcuM_WakeupSourceType. Not supported. */
uint32 CanWakeupSourceRef;\r
\r
//\r
// ArcCore stuff\r
//\r
\r
- // List of Hoh id's that belong to this controller\r
+ /** List of Hardware Object id's that belong to this controller. */
const Can_HardwareObjectType *Can_Arc_Hoh;\r
-\r
+
+ /** Enable controller self reception. */
boolean Can_Arc_Loopback;\r
\r
- // Set this to use the fifo\r
+ /** Set this to use the fifo */
boolean Can_Arc_Fifo;\r
\r
} Can_ControllerConfigType;\r
\r
\r
\r
-/*\r
- * CanConfigSet container\r
- */\r
+/** Container for controller parameters. */
typedef struct {\r
const Can_ControllerConfigType *CanController;\r
\r
const Can_CallbackType *CanCallbacks;\r
} Can_ConfigSetType;\r
\r
-\r
-typedef struct {\r
- // This is the multiple configuration set container for CAN Driver\r
- // Multiplicity 1..*\r
- const Can_ConfigSetType *CanConfigSet;\r
- // This container contains the parameters related each CAN\r
- // Driver Unit.\r
- // Multiplicity 1..*\r
+/** Top level container for parameters. */
+typedef struct {
+ /** Controller parameters. */
+ const Can_ConfigSetType *CanConfigSet;
+ /** Driver parameters. */
const Can_GeneralType *CanGeneral;\r
\r
-\r
} Can_ConfigType;\r
\r
-\r
-extern const Can_ConfigType CanConfigData;\r
+/** Top level container for parameters. */
+extern const Can_ConfigType CanConfigData;
+/** For direct access to controller list */
extern const Can_ControllerConfigType CanControllerConfigData[];\r
+/** Container for controller parameters. */
extern const Can_ConfigSetType Can_ConfigSet;\r
\r
\r
#endif /*CAN_CFG_H_*/\r
+/** @} */
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Com COM module
+ * @{ */
-
-
-
+/** @file Com_Cfg.h
+ * Definitions of configuration parameters for the COM module.
+ */
#ifndef COM_CFG_H_\r
\r
#define COM_DEV_ERROR_DETECT\r
\r
-\r
-#define COM_MAX_NR_IPDU 30\r
-#define COM_MAX_NR_SIGNAL 30\r
+/** Max number of I-PDUs allowed in the configuration. */
+#define COM_MAX_NR_IPDU 30
+/** Max number of signals allowed in the configuration. */
+#define COM_MAX_NR_SIGNAL 30
+/** Max number of group signals allowed in the configuration. */
#define COM_MAX_NR_GROUPSIGNAL 30\r
-\r
-#define COM_MAX_NR_SIGNALS_PER_IPDU 10\r
-#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 10\r
+
+/** Max number of signals allowed per I-PDU. */
+#define COM_MAX_NR_SIGNALS_PER_IPDU 10
+/** Max number of signal groups allowed per I-PDU. */
+#define COM_MAX_NR_SIGNALGROUPS_PER_IPDU 10
+/** Max number of group signals allowd per signal group. */
#define COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP 10\r
\r
\r
\r
#define CPU_ENDIANESS BIG_ENDIAN\r
\r
-/*\r
- * ComGeneral pre-compile time configuration parameters.
- */\r
+
#define ComConfigurationTimeBase\r
#define ComConfigurationUseDet\r
#define ComVersionInfoApi\r
\r
\r
-\r
-\r
-\r
-#endif /*COM_CFG_H_*/\r
+#endif /*COM_CFG_H_*/
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Det DET
+ * @{ */
+/** @file Det_Cfg.h
+ * Definitions of configuration parameters for DET.
+ * Specification: Autosar v2.0.1, Final
+ */
-
-
-
-
-
-/*\r
- * Development Error Tracer driver\r
- *\r
- * Specification: Autosar v2.0.1, Final\r
- *\r
- */\r
#ifndef _DET_CFG_H_\r
#define _DET_CFG_H_\r
\r
-#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
-#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
-#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
-#define DET_USE_STDERR STD_ON // Enable to get DET errors on stderr\r
+#define DET_ENABLE_CALLBACKS STD_ON /**< Enable to use callback on errors */
+#define DET_USE_RAMLOG STD_ON /**< Enable to log DET errors to ramlog */
+#define DET_WRAP_RAMLOG STD_ON /**< The ramlog wraps around when reaching the end */
+#define DET_USE_STDERR STD_ON /**< Enable to get DET errors on stderr */
\r
-#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
+#define DET_DEINIT_API STD_ON /**< Enable/Disable the Det_DeInit function */
\r
-#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
-#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+#define DET_RAMLOG_SIZE (32) /**< Number of entries in ramlog */
+#define DET_NUMBER_OF_CALLBACKS (5) /**< Number of callbacks */
\r
#endif /*_DET_CFG_H_*/\r
+/** @} */
+/** @addtogroup Dio DIO Driver
+ * @{ */
-
-
-
-
+/** @file Dio_Cfg.h
+ * Definitions of configuration parameters for the DIO Driver.
+ */
#ifndef DIO_CFG_H_\r
#define DIO_CFG_H_\r
\r
#define DIO_DEV_ERROR_DETECT STD_ON\r
#define DIO_END_OF_LIST -1\r
\r
-// MPC5516 physical\r
+/** HW specific DIO port definitions. */
typedef enum\r
{\r
DIO_PORT_A = 0,\r
DIO_PORT_H,\r
DIO_PORT_J,\r
DIO_PORT_K\r
-} Dio_PortTypesType;\r
-\r
-// Pin Name GPIO(PCR)Num\r
+} Dio_PortTypesType;
+
+/** @name DIO channels
+ * HW specific dio channels.
+ */
+// Pin Name GPIO(PCR)Num
+//@{
#define DIO_CHANNEL_A0 0\r
#define DIO_CHANNEL_A1 1\r
#define DIO_CHANNEL_A2 2\r
#define DIO_CHANNEL_J15 143\r
\r
#define DIO_CHANNEL_K0 144\r
-#define DIO_CHANNEL_K1 145\r
+#define DIO_CHANNEL_K1 145
+//@}
\r
// Channels \r
extern const Dio_ChannelType DioChannelConfigData[];\r
#ifndef DMA_CFG_H_\r
#define DMA_CFG_H_\r
-\r
+
+/** Channel id's. HW specific. */
typedef enum\r
{\r
DMA_ADC_GROUP0_RESULT_CHANNEL,\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup EcuM ECU State Manager
+ * @{ */
-
-
-
-
-
+/** @file EcuM_Cfg.h
+ * Definitions of configuration parameters for ECU State Manager.
+ * Initialization sequences are defined in EcuM_Callout_template.c
+ */
#ifndef ECUM_CFG_H_\r
#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
+
+/** Build version info API */
+#define ECUM_VERSION_INFO_API STD_ON
+/** Using NVRAM Manager */
+#define ECUM_INCLUDE_NVRAM_MGR STD_OFF
+/** Enable Development Error Trace */
#define ECUM_DEV_ERROR_DETECT STD_ON\r
\r
#include "EcuM_Generated_Types.h"\r
\r
#endif /*ECUM_CFG_H_*/\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Fls Flash Driver
+ * @{ */
-
-
-
-
-
+/** @file Fls_Cfg.h
+ * Definitions of configuration parameters for Flash Driver.
+ */
#ifndef FLS_CFG_H_
#define FLS_CFG_H_
#include "MemIf_Types.h"
-/* Indicate that we are building Post Build, NOT Pre-Compile */
+/** Indicate that we are building Post Build, NOT Pre-Compile */
#define FLS_VARIANT_PB STD_ON
/*
* Fls General container
*/
-// The flash driver shall load the flash access code to RAM whenever an
-// erase or write job is started and unload (overwrite) it after that job has
-// been finished or canceled. true: Flash access code loaded on job start /
-// unloaded on job end or error. false: Flash access code not loaded to /
-// unloaded from RAM at all.
+/** The flash driver shall load the flash access code to RAM whenever an
+ * erase or write job is started and unload (overwrite) it after that job has
+ * been finished or canceled. true: Flash access code loaded on job start /
+ * unloaded on job end or error. false: Flash access code not loaded to /
+ * unloaded from RAM at all. */
#define FLS_AC_LOAD_ON_JOB_START STD_OFF
-// The flash memory start address (see also FLS118).
-// FLS169: This parameter defines the lower boundary for read / write /
-// erase and compare jobs.
+/** The flash memory start address (see also FLS118).
+ * FLS169: This parameter defines the lower boundary for read / write /
+ * erase and compare jobs. */
#define FLS_BASE_ADDRESS 0x00000000
-// Compile switch to enable and disable the Fls_Cancel function. true: API
-// supported / function provided. false: API not supported / function not pro-
-// vided
+/** Compile switch to enable and disable the Fls_Cancel function. true: API
+ * supported / function provided. false: API not supported / function not pro-
+ * vided */
#define FLS_CANCEL_API STD_OFF
-// Compile switch to enable and disable the Fls_Compare function. true: API
-// supported / function provided. false: API not supported / function not pro-
-// vided
+/** Compile switch to enable and disable the Fls_Compare function. true: API
+ * supported / function provided. false: API not supported / function not pro-
+ * vided */
#define FLS_COMPARE_API STD_ON
-// Pre-processor switch for enabling the development error detection and
-// reporting (see FLS077).
-
+/** Pre-processor switch for enabling the development error detection and
+ * reporting (see FLS077). */
#define FLS_DEV_ERROR_DETECT STD_ON
-// Index of the driver, used by FEE.
+/** Index of the driver, used by FEE. */
#define FLS_DRIVER_INDEX 100
-// Compile switch to enable and disable the Fls_GetJobResult function. true:
-// API supported / function provided. false: API not supported / function not
-// provided
+/** Compile switch to enable and disable the Fls_GetJobResult function. true:
+ * API supported / function provided. false: API not supported / function not
+ * provided */
#define FLS_GET_JOB_RESULT_API STD_ON
-// Compile switch to enable and disable the Fls_GetStatus function. true: API
-// supported / function provided. false: API not supported / function not pro-
-// vided
+/** Compile switch to enable and disable the Fls_GetStatus function. true: API
+ * supported / function provided. false: API not supported / function not pro-
+ * vided */
#define FLS_GET_STATUS_API STD_ON
-// Compile switch to enable and disable the Fls_SetMode function. true: API
-// supported / function provided. false: API not supported / function not pro-
-// vided
+/** Compile switch to enable and disable the Fls_SetMode function. true: API
+ * supported / function provided. false: API not supported / function not pro-
+ * vided */
#define FLS_SET_MODE_API STD_OFF
-// The total amount of flash memory in bytes (see also FLS118).
-// FLS170: This parameter in conjunction with FLS_BASE_ADDRESS
-// defines the upper boundary for read / write / erase and compare jobs
+/** The total amount of flash memory in bytes (see also FLS118).
+ * FLS170: This parameter in conjunction with FLS_BASE_ADDRESS
+ * defines the upper boundary for read / write / erase and compare jobs */
#define FLS_TOTAL_SIZE 0x180000 // from addr 0x0000_0000 to 0x0018_0000
-#define FLS_READ_PAGE_SIZE 0x8 // Read page size of 128 bits (4 words) (8 bytes)
+/** Read page size of 128 bits (4 words) (8 bytes) */
+#define FLS_READ_PAGE_SIZE 0x8
// Job processing triggered by hardware interrupt. true: Job processing trig-
// gered by interrupt (hardware controlled). false: Job processing not trig-
// gered by interrupt (software controlled)
-// NOT supported by Freescale hardware
+/** NOT supported by Freescale hardware */
#define FLS_USE_INTERRUPTS STD_OFF
#define FLS_VERSION_INFO_API STD_ON
extern char __FLS_SIZE__;
#endif
-// Configuration description of a flashable sector
+/** Configuration description of a flashable sector */
typedef struct {
- // Number of continuous sectors with the above characteristics.
+ /** Number of continuous sectors with the above characteristics. */
Fls_LengthType FlsNumberOfSectors;
- // Size of one page of this sector. Implementation Type: Fls_LengthType.
+ /** Size of one page of this sector. Implementation Type: Fls_LengthType. */
Fls_LengthType FlsPageSize;
- // Size of this sector. Implementation Type: Fls_LengthTyp
+ /** Size of this sector. Implementation Type: Fls_LengthTyp */
Fls_LengthType FlsSectorSize;
- // Start address of this sector
+ /** Start address of this sector */
Fls_AddressType FlsSectorStartaddress;
} Fls_SectorType;
-// Container for runtime configuration parameters of the flash driver. Imple-
-// mentation Type: Fls_ConfigType.
+/** Container for runtime configuration parameters of the flash driver.
+ * Implementation Type: Fls_ConfigType. */
typedef struct {
- // Address offset in RAM to which the erase flash access code shall be
- // loaded. Used as function pointer to access the erase flash access code.
+ /** Address offset in RAM to which the erase flash access code shall be
+ * loaded. Used as function pointer to access the erase flash access code. */
void (*FlsAcErase)();
- // Address offset in RAM to which the write flash access code shall be
- // loaded. Used as function pointer to access the write flash access code.
+ /** Address offset in RAM to which the write flash access code shall be
+ * loaded. Used as function pointer to access the write flash access code. */
void (*FlsAcWrite)();
//#if 0
// // Cycle time of calls of the flash driver's main function.
// float FlsCallCycle;
//#endif
- // Mapped to the job end notification routine provided by some upper layer
- // module, typically the Fee module.
+ /** Mapped to the job end notification routine provided by some upper layer
+ * module, typically the Fee module. */
void (*FlsJobEndNotification)();
- // Mapped to the job error notification routine provided by some upper layer
- // module, typically the Fee module.
+ /** Mapped to the job error notification routine provided by some upper layer
+ * module, typically the Fee module. */
void (*FlsJobErrorNotification)();
- // The maximum number of bytes to read or compare in one cycle of the
- // flash driver's job processing function in fast mode.
+ /** The maximum number of bytes to read or compare in one cycle of the
+ * flash driver's job processing function in fast mode. */
uint32 FlsMaxReadFastMode;
- // The maximum number of bytes to read or compare in one cycle of the
- // flash driver's job processing function in normal mode.
+ /** The maximum number of bytes to read or compare in one cycle of the
+ * flash driver's job processing function in normal mode. */
uint32 FlsMaxReadNormalMode;
- // The maximum number of bytes to write in one cycle of the flash driver's job
- // processing function in fast mode.
+ /** The maximum number of bytes to write in one cycle of the flash driver's job
+ * processing function in fast mode. */
uint32 FlsMaxWriteFastMode;
- // The maximum number of bytes to write in one cycle of the flash driver's job
- // processing function in normal mode.
+ /** The maximum number of bytes to write in one cycle of the flash driver's job
+ * processing function in normal mode. */
uint32 FlsMaxWriteNormalMode;
- // Erase/write protection settings. Only relevant if supported by hardware.
+ /** Erase/write protection settings. Only relevant if supported by hardware. */
uint32 FlsProtection;
- // List of flash:able sectors and pages
+ /** List of flash:able sectors and pages */
const Fls_SectorType *FlsSectorList;
- // Size of List of the FlsSectorList
+ /** Size of List of the FlsSectorList */
const uint32 FlsSectorListSize;
uint8 *FlsBlockToPartitionMap;
extern const Fls_ConfigType FlsConfigSet[];
#if 0
-/* N/A since PPC have PIC */
+/** N/A since PPC have PIC */
#define FLS_AC_LOCATION_ERASE
#define FLS_AC_LOCATION_WRITE
-/* N/A since we have internal flash */
+/** N/A since we have internal flash */
#define FLS_EXPECTED_HW_ID
#endif
#endif /*FLS_CFG_H_*/
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Gpt GPT Driver
+ * @{ */
-
-
-
-
-
+/** @file Gpt_Cfg.h
+ * Definitions of configuration parameters for GPT Driver.
+ */
#ifndef GPT_CFG_H_\r
#define GPT_CFG_H_\r
#include "Std_Types.h"\r
\r
\r
-// Pre-compile only\r
+/** Configuration is pre-compile only. Not supported. */
#define GPT_VARIANT_PC STD_OFF\r
-// Mix of pre-compile and post-build\r
+/** Configuration is a mix of pre-compile and post-build */
#define GPT_VARIANT_PB STD_ON\r
\r
//#define DEC_TEST\r
//#define GPT_TEST\r
\r
-/* Std PIT channels */\r
+/** HW PIT channels */
#define GPT_CHANNEL_RTI 0\r
#define GPT_CHANNEL_PIT_0 GPT_CHANNEL_RTI\r
#define GPT_CHANNEL_PIT_1 1\r
\r
#define GPT_PIT_CNT (GPT_CHANNEL_PIT_8 + 1)\r
\r
-/* Mcu channels */\r
+/** Decrementer */
#define GPT_CHANNEL_DEC 9\r
\r
#define GPT_CHANNEL_CNT (GPT_CHANNEL_DEC+1)\r
// Illegal channel\r
#define GPT_CHANNEL_ILL 31\r
\r
-\r
+/** Enable Development Error Trace */
#define GPT_DEV_ERROR_DETECT STD_ON\r
-// Enables/Disables wakeup source reporting\r
+/** Enables/Disables wakeup source reporting. Not supported. */
#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
-\r
-#define GPT_DEINIT_API STD_ON\r
-#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
-#define GPT_TIME_REMAINING_API STD_ON\r
-#define GPT_TIME_ELAPSED_API STD_ON\r
+/** Build DeInit API */
+#define GPT_DEINIT_API STD_ON
+/** Build notification API */
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON
+/** Build time remaining API */
+#define GPT_TIME_REMAINING_API STD_ON
+/** Build time elapsed API */
+#define GPT_TIME_ELAPSED_API STD_ON
+/** Build version info API */
#define GPT_VERSION_INFO_API STD_ON\r
-// TODO: EcuM things missing to get this API working properly\r
+/** Build wakeup API. Not supported */
#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
\r
\r
-// This container contains the channel-wide configuration (parameters) of the\r
-// GPT Driver\r
+/** This container contains the channel-wide configuration (parameters) of the
+ * GPT Driver */
typedef struct {\r
- // GPT187: The GPT module specific clock input for the timer unit can\r
- // statically be configured and allows to select different clock sources\r
- // (external clock, internal GPT specific clock) per channel\r
+ /** GPT187: The GPT module specific clock input for the timer unit can
+ * statically be configured and allows to select different clock sources
+ * (external clock, internal GPT specific clock) per channel */
uint32 GptChannelClkSrc;\r
\r
- // Channel Id of the GPT channel. This value will be assigned to the symbolic\r
- // name derived of the GptChannelConfiguration container short name.\r
+ /** Channel Id of the GPT channel. */
Gpt_ChannelType GptChannelId;\r
\r
- // Specifies the behaviour of the timerchannel after the timeout has expired\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */
Gpt_ChannelMode GptChannelMode;\r
\r
- // Function pointer to callback function\r
+ /** Function pointer to callback function */
void (*GptNotification)();\r
\r
- // GPT module specific prescaler factor per channel\r
+ /** GPT module specific prescaler factor per channel */
uint32 GptChannelPrescale;\r
\r
- // GPT188: Enables wakeup capability of CPU for a channel when timeout\r
- // period expires. This might be different to enabling the notification\r
- // depending on hardware capabilities\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout
+ * period expires. This might be different to enabling the notification
+ * depending on hardware capabilities. Not supported. */
boolean GptEnableWakeup;\r
} Gpt_ConfigType;\r
-\r
+
+/** The list of channel configurations */
extern const Gpt_ConfigType GptConfigData[];\r
\r
-#endif /*GPT_CFG_H_*/\r
+#endif /*GPT_CFG_H_*/
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup LinIf LIN Interface
+ * @{ */
-
-
-
-
-
+/** @file LinIf_Cfg.h
+ * Definitions of configuration parameters for LIN Interface.
+ */
#ifndef LINIF_CFG_H_\r
#define LINIF_CFG_H_\r
PDU_MSG_LIN_RX_2,\r
};\r
\r
-/* Switches the Development Error Detection and Notification\r
+/** Switches the Development Error Detection and Notification
ON or OFF. */\r
#define LINIF_DEV_ERROR_DETECT STD_ON\r
\r
-/* States if multiple drivers are included in the LIN Interface or not. The\r
- * reason for this parameter is to reduce the size of LIN Interface if multiple\r
- * drivers are not used. */\r
+/** States if multiple drivers are included in the LIN Interface or not. The
+ * reason for this parameter is to reduce the size of LIN Interface if multiple
+ * drivers are not used. */
#define LINIF_MULTIPLE_DRIVER_SUPPORT STD_OFF\r
\r
-/* States if the node configuration commands Assign NAD and Conditional\r
- * Change NAD are supported. */\r
+/** States if the node configuration commands Assign NAD and Conditional
+ * Change NAD are supported. */
#define LINIF_OPTIONAL_REQUEST_SUPPORTED STD_OFF\r
\r
-/* States if the TP is included in the LIN Interface or not. The reason for this\r
- * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+/** States if the TP is included in the LIN Interface or not. The reason for this
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */
#define LINIF_TP_SUPPORTED STD_OFF\r
\r
-/* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+/** Switches the LinIf_GetVersionInfo function ON or OFF. */
#define LINIF_VERSION_INFO_API STD_ON\r
\r
typedef struct {\r
- /* Switches the Development Error Detection and Notification\r
- ON or OFF. */\r
+ /** Switches the Development Error Detection and Notification
+ * ON or OFF. */
boolean LinIfDevErrorDetect;\r
- /* States if multiple drivers are included in the LIN Interface or not. The\r
- * reason for this parameter is to reduce the size of LIN Interface if multiple\r
- * drivers are not used. */\r
+ /** States if multiple drivers are included in the LIN Interface or not. The
+ * reason for this parameter is to reduce the size of LIN Interface if multiple
+ * drivers are not used. */
boolean LinIfMultipleDriversSupported;\r
- /* States if the node configuration commands Assign NAD and Conditional\r
- * Change NAD are supported. */\r
+ /** States if the node configuration commands Assign NAD and Conditional
+ * Change NAD are supported. */
boolean LinIfNcOptionalRequestSupported;\r
- /* States if the TP is included in the LIN Interface or not. The reason for this\r
- * parameter is to reduce the size of LIN Interface if the TP is not used. */\r
+ /** States if the TP is included in the LIN Interface or not. The reason for this
+ * parameter is to reduce the size of LIN Interface if the TP is not used. */
boolean LinIfTpSupported;\r
- /* Switches the LinIf_GetVersionInfo function ON or OFF. */\r
+ /** Switches the LinIf_GetVersionInfo function ON or OFF. */
boolean LinIfVersionInfoApi;\r
}LinIf_GeneralType;\r
\r
#define LINIF_SCH_CNT 2\r
\r
#endif /*LINIF_CFG_H_*/\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Lin LIN Driver
+ * @{ */
-
-
-
-
-
+/** @file Lin_Cfg.h
+ * Definitions of configuration parameters for LIN Driver.
+ */
#ifndef LIN_CFG_H_\r
#define LIN_CFG_H_\r
\r
#include "Std_Types.h"\r
\r
-/* Switches the Development Error Detection and Notification\r
+/** Switches the Development Error Detection and Notification
ON or OFF. */\r
#define LIN_DEV_ERROR_DETECT STD_ON\r
\r
-/* Specifies the InstanceId of this module instance. If only one\r
+/** Specifies the InstanceId of this module instance. If only one
instance is present it shall have the Id 0. */\r
#define LIN_INDEX 0\r
\r
-/* Specifies the maximum number of loops for blocking function\r
- * until a timeout is raised in short term wait loops */\r
+/** Specifies the maximum number of loops for blocking function
+ * until a timeout is raised in short term wait loops */
#define LIN_TIMEOUT_DURATION 10\r
\r
-/* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+/** Switches the Lin_GetVersionInfo function ON or OFF. */
#define LIN_VERSION_INFO_API STD_ON\r
-\r
+
+/** HW specific controller id's */
typedef enum {\r
LIN_CTRL_A = 0,\r
LIN_CTRL_B,\r
LIN_CTRL_H,\r
LIN_CONTROLLER_CNT\r
}LinControllerIdType;\r
-\r
+
+/** Not used */
typedef struct {\r
- /* Switches the Development Error Detection and Notification\r
+ /** Switches the Development Error Detection and Notification
ON or OFF. */\r
boolean LinDevErrorDetect;\r
- /* Specifies the InstanceId of this module instance. If only one\r
+ /** Specifies the InstanceId of this module instance. If only one
instance is present it shall have the Id 0. */\r
uint8 LinIndex;\r
- /* Specifies the maximum number of loops for blocking function\r
+ /** Specifies the maximum number of loops for blocking function
* until a timeout is raised in short term wait loops */\r
uint16 LinTimeoutDuration;\r
- /* Switches the Lin_GetVersionInfo function ON or OFF. */\r
+ /** Switches the Lin_GetVersionInfo function ON or OFF. */
boolean LinVersionInfoApi;\r
}Lin_GeneralType;\r
-\r
+
+/** Container for channel settings */
typedef struct {\r
- /* Specifies the baud rate of the LIN channel */\r
+ /** Specifies the baud rate of the LIN channel */
uint16 LinChannelBaudRate;\r
- /* Identifies the LIN channel.*/\r
+ /** Identifies the LIN channel.*/
uint8 LinChannelId;\r
- /* Specifies if the LIN hardware channel supports wake up functionality */\r
+ /** Specifies if the LIN hardware channel supports wake up functionality */
boolean LinChannelWakeUpSupport;\r
- /* This parameter contains a reference to the Wakeup Source\r
- * for this controller as defined in the ECU State Manager.\r
- * Implementation Type: reference to EcuM_WakeupSourceType */\r
+ /** This parameter contains a reference to the Wakeup Source
+ * for this controller as defined in the ECU State Manager.
+ * Implementation Type: reference to EcuM_WakeupSourceType */
uint32 LinChannelEcuMWakeUpSource;\r
- /* Reference to the LIN clock source configuration, which is set\r
+ /** Reference to the LIN clock source configuration, which is set
* in the MCU driver configuration.*/\r
uint32 LinClockRef;\r
} Lin_ChannelConfigType;\r
\r
\r
#endif /*LIN_CFG_H_*/\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Mcu MCU Driver
+ * @{ */
-
-
-
-
-
+/** @file Mcu_Cfg.h
+ * Definitions of configuration parameters for MCU Driver.
+ */
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
#include "mpc55xx.h"\r
-\r
+
+/** Enable Development Error Trace */
#define MCU_DEV_ERROR_DETECT STD_ON\r
-// Preprocessor switch to enable / disable the use of the function\r
-// Mcu_PerformReset()\r
+/** Enable/disable the use of the function Mcu_PerformReset() */
#define MCU_PERFORM_RESET_API STD_ON\r
-\r
+/** Build version info API */
#define MCU_VERSION_INFO_API STD_ON\r
\r
#include "Std_Types.h"\r
\r
/* FMPLL modes( atleast in 5553/5554 ) */\r
-\r
+
+/** HW specific PLL modes */
typedef enum {\r
MCU_FMPLL_BYPASS = 0,\r
MCU_FMPLL_EXTERNAL_REF,\r
MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
} Mcu_FMPLLmode_t;\r
-\r
+
+/** Symbolic names for clock settings */
typedef enum {\r
MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
//MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
} Mcu_ClockType;\r
\r
-\r
+/** Defines clock settings */
typedef struct {\r
- // This container defines a reference point in the Mcu Clock tree\r
- // It defines the frequency which then can be used by other modules\r
- // as an input value. Lower multiplicity is 1, as even in the\r
- // simplest case (only one frequency is used), there is one\r
- // frequency to be defined.\r
+ /** PLL input frequency for this clock setting. */
uint32 McuClockReferencePoint;\r
\r
- // Phase locked loop configuration parameters for MPC551x.\r
- uint8 PllEprediv;\r
- uint8 PllEmfd;\r
+ /** PLL configuration parameter for MPC551x. */
+ uint8 PllEprediv;
+ /** PLL configuration parameter for MPC551x. */
+ uint8 PllEmfd;
+ /** PLL configuration parameter for MPC551x. */
uint8 PllErfd;\r
} Mcu_ClockSettingConfigType;\r
-\r
+
+/** Not used */
typedef struct {\r
- // The parameter represents the MCU Mode settings\r
+ /** The parameter represents the MCU Mode settings */
uint32 McuMode;\r
} Mcu_ModeSettingConfigType;\r
-\r
+
+/** Not used */
typedef struct {\r
- // This parameter shall represent the Data pre-setting to be initialized\r
+ /** This parameter shall represent the Data pre-setting to be initialized */
uint32 McuRamDefaultValue;\r
\r
- // This parameter shall represent the MCU RAM section base address\r
+ /** This parameter shall represent the MCU RAM section base address */
uint32 McuRamSectionBaseAddress;\r
\r
- // This parameter shall represent the MCU RAM Section size\r
+ /** This parameter shall represent the MCU RAM Section size */
uint32 McuRamSectionSize;\r
\r
} Mcu_RamSectorSettingConfigType;\r
\r
\r
-// This container defines a reference point in the Mcu Clock tree. It defines\r
-// the frequency which then can be used by other modules as an input value.\r
-// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
-// used), there is one frequency to be defined.\r
+/** Not used */
typedef struct {\r
\r
- // This is the frequency for the specific instance of the McuClockReference-\r
- // Point container. It shall be givn in Hz.\r
+ /** This is the frequency for the specific instance of the McuClockReference-
+ * Point container. It shall be given in Hz. */
uint32 McuClockReferencePointFrequency;\r
\r
} Mcu_ClockReferencePointType;\r
-\r
+
+/** Top level configuration container */
typedef struct {\r
- // Enables/Disables clock failure notification. In case this feature is not supported\r
- // by HW the setting should be disabled.\r
+ /** Enables/Disables clock failure notification. In case this feature is not supported
+ * by HW the setting should be disabled. */
uint8 McuClockSrcFailureNotification;\r
\r
- // This parameter shall represent the number of Modes available for the\r
- // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ /** This parameter shall represent the number of Modes available for the
+ * MCU. calculationFormula = Number of configured McuModeSettingConf */
uint8 McuNumberOfMcuModes;\r
\r
- // This parameter shall represent the number of RAM sectors available for\r
- // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
- // tingConf\r
+ /** This parameter shall represent the number of RAM sectors available for
+ * the MCU. calculationFormula = Number of configured McuRamSectorSet-
+ * tingConf */
uint8 McuRamSectors;\r
\r
- // This parameter shall represent the number of clock setting available for\r
- // the MCU.\r
+ /** This parameter shall represent the number of clock setting available for
+ * the MCU. */
uint8 McuClockSettings;\r
\r
- // This parameter defines the default clock settings that should be used\r
- // It is an index into the McuClockSettingsConfig\r
+ /** This parameter defines the default clock settings that should be used
+ * It is an index into the McuClockSettingsConfig */
Mcu_ClockType McuDefaultClockSettings;\r
\r
- // This parameter relates to the MCU specific reset configuration. This ap-\r
- // plies to the function Mcu_PerformReset, which performs a microcontroller\r
- // reset using the hardware feature of the microcontroller.\r
+ /** This parameter relates to the MCU specific reset configuration. This ap-
+ * plies to the function Mcu_PerformReset, which performs a microcontroller
+ * reset using the hardware feature of the microcontroller. */
uint32 McuResetSetting;\r
\r
- // This container contains the configuration (parameters) for the\r
- // Clock settings of the MCU. Please see MCU031 for more in-\r
- // formation on the MCU clock settings.\r
+ /** This container contains the configuration (parameters) for the
+ * Clock settings of the MCU. Please see MCU031 for more in-
+ * formation on the MCU clock settings. */
Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
\r
- // This container contains the configuration (parameters) for the\r
- // Mode setting of the MCU. Please see MCU035 for more information\r
- // on the MCU mode settings.\r
+ /** This container contains the configuration (parameters) for the
+ * Mode setting of the MCU. Please see MCU035 for more information
+ * on the MCU mode settings. */
Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
\r
- // This container contains the configuration (parameters) for the\r
- // RAM Sector setting. Please see MCU030 for more information\r
- // on RAM sec-tor settings.\r
+ /** This container contains the configuration (parameters) for the
+ * RAM Sector setting. Please see MCU030 for more information
+ * on RAM sector settings. */
Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
\r
} Mcu_ConfigType;\r
#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
\r
#endif /*MCU_CFG_H_*/\r
+/** @} */
-\r
-#define PDUR_MODULE_ID 51\r
-#define PDUR_INSTANCE_ID 0\r
-\r
-#define MUST_BE_OFF 0\r
-\r
-/* Turns on/off debug print statements in the PDU router code. */\r
-//#define PDUR_PRINT_DEBUG_STATEMENTS\r
-\r
-/* Turns on/off reentrancy checks */\r
-#define PDUR_REENTRANCY_CHECK\r
-\r
-\r
-#define PDUR_DEV_ERROR_DETECT 1 // Should this be enables in DASA configuration?\r
-\r
-#define PDUR_VERSION_INFO_API\r
-\r
-#ifdef CFG_DASA\r
-#define PDUR_ZERO_COST_OPERATION\r
-#endif\r
-\r
-#ifdef PDUR_ZERO_COST_OPERATION\r
- // CanIf, FrIf, LinIf\r
- #define PDUR_SINGLE_IF CAN_IF\r
- // CanTp, FrTp, LinTp\r
- //#define PDUR_SINGLE_TP CanTp\r
- #define PDUR_MULTICAST_TOIF_SUPPORT MUST_BE_OFF\r
- #define PDUR_MULTICAST_FROMIF_SUPPORT MUST_BE_OFF\r
- #define PDUR_MULTICAST_TOTP_SUPPORT MUST_BE_OFF\r
- #define PDUR_MULTICAST_FROMTP_SUPPORT MUST_BE_OFF\r
-\r
-#else\r
- #define PDUR_GATEWAY_OPERATION\r
- #ifdef PDUR_GATEWAY_OPERATION\r
- #define PDUR_MEMORY_SIZE\r
- //#define PDUR_SB_TX_BUFFER_SUPPORT\r
- #define PDUR_FIFO_TX_BUFFER_SUPPORT\r
- #define PDUR_MAX_TX_BUFFER_NUMBER 10\r
- #endif\r
-\r
- //#define PDUR_IPDUM_SUPPORT\r
-\r
- // NOTE: Support for minimum routing not implemented yet.\r
- /*\r
- #define PDUR_MINIMUM_ROUTING_UP_MODULE COM\r
- #define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF\r
- #define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)\r
- #define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)\r
- #define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)\r
- #define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)\r
- */\r
-#endif\r
-\r
-// Interfaces\r
-#define PDUR_CANIF_SUPPORT\r
-//#define PDUR_CANTP_SUPPORT\r
-//#define PDUR_FRIF_SUPPORT\r
-//#define PDUR_FRTP_SUPPORT\r
-#define PDUR_LINIF_SUPPORT\r
-//#define PDUR_LINTP_SUPPORT\r
-#define PDUR_COM_SUPPORT\r
-#define PDUR_DCM_SUPPORT\r
-\r
-\r
-//#define PDUR_MAX_TX_BUFFER_NUMBER\r
-\r
-// ERROR TYPES\r
-#define PDUR_E_CONFIG_PTR_INVALID 0x06\r
-#define PDUR_E_INVALID_REQUEST 0x01\r
-#define PDUR_E_PDU_ID_INVALID 0x02\r
-#define PDUR_E_TP_TX_REQ_REJECTED 0x03\r
-#define PDUR_E_DATA_PTR_INVALID 0x05\r
-#define PDUR_E_PDU_INSTANCE_LOST 0x10\r
+
+#define PDUR_MODULE_ID 51
+#define PDUR_INSTANCE_ID 0
+
+#define MUST_BE_OFF 0
+
+/* Turns on/off debug print statements in the PDU router code. */
+//#define PDUR_PRINT_DEBUG_STATEMENTS
+
+/* Turns on/off reentrancy checks */
+#define PDUR_REENTRANCY_CHECK
+
+
+#define PDUR_DEV_ERROR_DETECT 1 // Should this be enables in DASA configuration?
+
+#define PDUR_VERSION_INFO_API
+
+#ifdef PDUR_ZERO_COST_OPERATION
+ // CanIf, FrIf, LinIf
+ #define PDUR_SINGLE_IF CAN_IF
+ // CanTp, FrTp, LinTp
+ //#define PDUR_SINGLE_TP CanTp
+ #define PDUR_MULTICAST_TOIF_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_FROMIF_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_TOTP_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_FROMTP_SUPPORT MUST_BE_OFF
+
+#else
+ #define PDUR_GATEWAY_OPERATION
+ #ifdef PDUR_GATEWAY_OPERATION
+ #define PDUR_MEMORY_SIZE
+ //#define PDUR_SB_TX_BUFFER_SUPPORT
+ #define PDUR_FIFO_TX_BUFFER_SUPPORT
+ #define PDUR_MAX_TX_BUFFER_NUMBER 10
+ #endif
+
+ //#define PDUR_IPDUM_SUPPORT
+
+ // NOTE: Support for minimum routing not implemented yet.
+ /*
+ #define PDUR_MINIMUM_ROUTING_UP_MODULE COM
+ #define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF
+ #define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)
+ #define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)
+ #define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)
+ #define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)
+ */
+#endif
+
+// Interfaces
+#define PDUR_CANIF_SUPPORT
+//#define PDUR_CANTP_SUPPORT
+//#define PDUR_FRIF_SUPPORT
+//#define PDUR_FRTP_SUPPORT
+#define PDUR_LINIF_SUPPORT
+//#define PDUR_LINTP_SUPPORT
+#define PDUR_COM_SUPPORT
+#define PDUR_DCM_SUPPORT
+
+
+//#define PDUR_MAX_TX_BUFFER_NUMBER
+
+// ERROR TYPES
+#define PDUR_E_CONFIG_PTR_INVALID 0x06
+#define PDUR_E_INVALID_REQUEST 0x01
+#define PDUR_E_PDU_ID_INVALID 0x02
+#define PDUR_E_TP_TX_REQ_REJECTED 0x03
+#define PDUR_E_DATA_PTR_INVALID 0x05
+#define PDUR_E_PDU_INSTANCE_LOST 0x10
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Port Port Driver
+ * @{ */
-
-
-
-
-
+/** @file Port_Cfg.h
+ * Definitions of configuration parameters for Port Driver.
+ */
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
#include "Std_Types.h"\r
-\r
-#define PORT_VERSION_INFO_API STD_ON\r
-#define PORT_DEV_ERROR_DETECT STD_ON\r
+
+/** Build version info API */
+#define PORT_VERSION_INFO_API STD_ON
+/** Enable Development Error Trace */
+#define PORT_DEV_ERROR_DETECT STD_ON
+/** Build change pin direction API */
#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
-\r
+
+/** HW specific symbolic names of pins */
typedef enum\r
{\r
PA0,\r
PK0,\r
PK1\r
} Port_PinType;\r
-\r
+
+/** @name HW specific register bits. */
+//@{
#define BIT0 (1<<15)\r
#define BIT1 (1<<14)\r
#define BIT2 (1<<13)\r
// Should be this out of reset\r
#define PCR_RESET (0)\r
#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
-\r
+//@}
\r
#define EVB_TEST_CONFIG (&PortConfigData)\r
\r
-\r
+/** Top level configuration container */
typedef struct\r
-{\r
- uint16_t padCnt;\r
- const uint16_t *padConfig;\r
- uint16_t outCnt;\r
+{
+ /** Total number of pins */
+ uint16_t padCnt;
+ /** List of pin configurations */
+ const uint16_t *padConfig;
+ /** Total number of pin default levels */
+ uint16_t outCnt;
+ /** List of pin default levels */
const uint8_t *outConfig;\r
// uint16_t inCnt;\r
// const uint8_t *inConfig;\r
} Port_ConfigType;\r
-\r
+
+/** Instance of the top level configuration container */
extern const Port_ConfigType PortConfigData;\r
\r
#endif /*PORT_CFG_H_*/\r
+/** @} */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * Pwm_Cfg.c
+ *
+ * Created on: 2009-jul-09
+ * Author: nian
+ */
+
+#include "Pwm.h"
+#include "Pwm_Cfg.h"
+
+extern void MyPwmNotificationRoutine(void);
+
+const Pwm_ConfigType PwmConfig = {
+ .Channels = {
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 3000, 0x6000, PWM_CHANNEL_PRESCALER_4, PWM_HIGH),
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 2000, 0x2000, PWM_CHANNEL_PRESCALER_2, PWM_LOW)
+ },
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON
+ .NotificationHandlers = {
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1
+ NULL // PWM_CHANNEL_2
+ }
+#endif
+};
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Pwm PWM Driver
+ * @{ */
+
+/** @file Pwm_Cfg.h
+ * Definitions of configuration parameters for PWM Driver.
+ */
+
+#ifndef PWM_CFG_H_
+#define PWM_CFG_H_
+
+/*
+ * PwmGeneral
+ */
+
+/*
+ * PWM003: The detection of development errors is configurable (ON/OFF) at
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable
+ * the detection of all development errors
+ */
+/** Enable Development Error Trace */
+#define PWM_DEV_EROR_DETECT STD_ON
+/** Build GetOutputState() */
+#define PWM_GET_OUTPUT_STATE STD_ON
+/** Determines if module is configurable at runtime */
+#define PWM_STATICALLY_CONFIGURED STD_OFF
+/** Use notifications */
+#define PWM_NOTIFICATION_SUPPORTED STD_ON
+/** Build period and duty API */
+#define PWM_SET_PERIOD_AND_DUTY STD_ON
+
+/**
+ * PWM106: This is implementation specific but not all values may be valid
+ * within the type. This shall be chosen in order to have the most efficient
+ * implementation on a specific microcontroller platform.
+ *
+ * PWM106 => Pwm_ChannelType == eemios channel id.
+ */
+typedef uint8 Pwm_ChannelType;
+
+/**
+ * PWM070: All time units used within the API services of the PWM module shall
+ * be of the unit ticks.
+ */
+typedef uint16 Pwm_PeriodType;
+
+
+/**
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end
+ * of the current period.
+ *
+ * Note: Currently only ON mode is supported.
+ */
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON
+
+/****************************************************************************
+ * Not defined in AUTOSAR.
+ */
+#define PWM_ISR_PRIORITY 1
+#define PWM_PRESCALER 64
+/**
+ * Setting to ON freezes the current output state of a PWM channel when in
+ * debug mode.
+ */
+#define PWM_FREEZE_ENABLE STD_ON
+
+/****************************************************************************
+ * Enumeration of channels
+ * Maps a symbolic name to a hardware channel
+ */
+typedef enum {
+#if defined(CFG_BRD_MPC5516IT)
+ PWM_CHANNEL_1 = 13, /* Emios channel 13 and 12 map to the */
+ PWM_CHANNEL_2 = 12, /* LEDs LD4 and LD5 of MPC5516IT */
+
+#elif defined(CFG_BRD_MPC5567QRTECH)
+ PWM_CHANNEL_1 = 10, /* Emios channel 10 maps to PCR189 which
+ * is available on pin 54 of the
+ * ERNI 154822 connector
+ */
+ PWM_CHANNEL_2 = 12, /* Channel 12 goes to PCR191, also
+ * available on the ERNI 154822 connector
+ */
+#else
+#warning "Unknown board or CFG_BRD_* undefined"
+#endif
+ PWM_NUMBER_OF_CHANNELS = 2
+} Pwm_NamedChannelsType;
+
+typedef enum {
+ PWM_CHANNEL_PRESCALER_1=0,
+ PWM_CHANNEL_PRESCALER_2,
+ PWM_CHANNEL_PRESCALER_3,
+ PWM_CHANNEL_PRESCALER_4,
+} Pwm_ChannelPrescalerType;
+
+/**
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,
+ * the following macro can be used to convert between that format and the
+ * mpc5516 format.
+ */
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period
+
+#if defined(CFG_MPC5516)
+ /** Mode is buffered PWM output (OPWM)
+ * Mode is buffered Output PW and frequency modulation mode */
+#define PWM_EMIOS_OPWM 0x5A
+#elif defined(CFG_MPC5567)
+ /** Mode is buffered OPWM with frequency modulation (allows change of
+ * period) */
+#define PWM_EMIOS_OPWM 0x19
+#endif
+
+
+typedef struct {
+ /** Number of duty ticks */
+ uint32_t duty:32;
+ /** Length of period, in ticks */
+ uint32_t period:32;
+ /** Counter */
+ uint32_t counter:32;
+ /** Enable freezing the channel when in debug mode */
+ uint32_t freezeEnable:1;
+ /** Disable output */
+ uint32_t outputDisable:1;
+ /** Select which bus disables the bus
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */
+ uint32_t outputDisableSelect:2;
+ /** Prescale the emios clock some more? */
+ Pwm_ChannelPrescalerType prescaler:2;
+ /** Prescale the emios clock some more? */
+ uint32_t usePrescaler:1;
+ /** Whether to use DMA. Currently unsupported */
+ uint32_t useDma:1;
+ uint32_t reserved_2:1;
+ /** Input filter. Ignored in output mode. */
+ uint32_t inputFilter:4;
+ /** Input filter clock source. Ignored in output mode */
+ uint32_t filterClockSelect:1;
+ /** Enable interrupts/flags on this channel? Required for DMA as well. */
+ uint32_t flagEnable:1;
+ uint32_t reserved_3:3;
+ /** Trigger a match on channel A */
+ uint32_t forceMatchA:1;
+ /** Triggers a match on channel B */
+ uint32_t forceMatchB:1;
+ uint32_t reserved_4:1;
+ /** We can use different buses for the counter. Use the internal counter */
+ uint32_t busSelect:2;
+ /** What edges to flag on? */
+ uint32_t edgeSelect:1;
+ /** Polarity of the channel */
+ uint32_t edgePolarity:1;
+ /** EMIOS mode. 0x58 for buffered output PWM */
+ uint32_t mode:7;
+} Pwm_ChannelRegisterType;
+
+typedef struct {
+ Pwm_ChannelRegisterType r;
+ Pwm_ChannelType channel;
+} Pwm_ChannelConfigurationType;
+
+
+typedef struct {
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];
+#endif
+} Pwm_ConfigType;
+
+/** Channel configuration macro. */
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \
+ {\
+ .channel = _hwchannel,\
+ .r = {\
+ DUTY_AND_PERIOD(_duty, _period),\
+ .freezeEnable = 1,\
+ .outputDisable = 0,\
+ .usePrescaler = 1,\
+ .prescaler = _prescaler,\
+ .useDma = 0,\
+ .flagEnable = 0, /* See PWM052 */ \
+ .busSelect = 3, /* Use the internal counter bus */\
+ .edgePolarity = _polarity,\
+ .mode = PWM_EMIOS_OPWM\
+ }\
+ }
+
+#endif /* PWM_CFG_H_ */
+/** @} */
-
-# ARCH defines
-ARCH=mpc55xx
-ARCH_FAM=ppc
-ARCH_MCU=mpc5516
-
-# CFG (y/n) macros
-CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC551XSIM SIMULATOR
-
-# What buildable modules does this board have,
-# default or private
-MOD_AVAIL=KERNEL RAMLOG MCU GPT LIN CAN WDG WDGM T32_TERM WINIDEA_TERM SIMPLE_PRINTF
-
-# Needed by us
-MOD_USE=KERNEL MCU
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5516\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC BOOKE E200Z1 MPC55XX MPC5516 BRD_MPC551XSIM SIMULATOR\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL=KERNEL RAMLOG MCU GPT LIN CAN WDG WDGM T32_TERM WINIDEA_TERM SIMPLE_PRINTF DEM IOHWAB\r
+\r
+# Needed by us\r
+MOD_USE=KERNEL MCU\r
// Mcu_GetResetReason();\r
#if 0\r
Det_Init();\r
+#if defined(USE_DEM)
Dem_PreInit();\r
+#endif
EcuM_AL_DriverInitOne();\r
#endif\r
\r
NvM_WriteAll();\r
NvM_CancelWriteAll();\r
\r
+#if defined(USE_DEM)
Dem_PreInit();\r
Dem_Init();\r
{\r
Dem_EventStatusType status = 0;\r
Dem_ReportErrorStatus(id,status);\r
}\r
+#endif
Rte_Start();\r
Rte_Stop();\r
#endif\r
-
-# ARCH defines
-ARCH=mpc55xx
-ARCH_FAM=ppc
-ARCH_MCU=mpc5554
-
-# CFG (y/n) macros
-CFG=PPC BOOKE SPE E200Z6 MPC55XX MPC5554 BRD_MPC5554SIM SIMULATOR
-
-# What buildable modules does this board have,
-# default or private
-MOD_AVAIL+=KERNEL RAMLOG MCU GPT LIN CAN COM WDG WDGM T32_TERM WINIDEA_TERM SIMPLE_PRINTF
-
-# Needed by kernel
-MOD_USE+=KERNEL MCU
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5554\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC BOOKE SPE E200Z6 MPC55XX MPC5554 BRD_MPC5554SIM SIMULATOR\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL+=KERNEL RAMLOG MCU GPT LIN CAN COM WDG WDGM T32_TERM WINIDEA_TERM SIMPLE_PRINTF DEM IOHWAB\r
+\r
+# Needed by kernel\r
+MOD_USE+=KERNEL MCU\r
-
-# ARCH defines
-ARCH=mpc55xx
-ARCH_FAM=ppc
-ARCH_MCU=mpc5567
-
-# CFG (y/n) macros
-CFG=PPC BOOKE E200Z6 MPC55XX MPC5567 BRD_MPC5567QRTECH SPE
-
-# What buildable modules does this board have,
-# default or private
-MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM T32_TERM WINIDEA_TERM PWM CAN CANIF COM ADC DMA SIMPLE_PRINTF
-
-# Needed by us
-MOD_USE=KERNEL MCU
-
-
+\r
+# ARCH defines\r
+ARCH=mpc55xx\r
+ARCH_FAM=ppc\r
+ARCH_MCU=mpc5567\r
+\r
+# CFG (y/n) macros\r
+CFG=PPC BOOKE E200Z6 MPC55XX MPC5567 BRD_MPC5567QRTECH SPE\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM T32_TERM WINIDEA_TERM PWM CAN CANIF COM ADC DMA SIMPLE_PRINTF DEM PDUR IOHWAB\r
+\r
+# Needed by us\r
+MOD_USE=KERNEL MCU\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+
+#define PDUR_MODULE_ID 51
+#define PDUR_INSTANCE_ID 0
+
+#define MUST_BE_OFF 0
+
+/* Turns on/off debug print statements in the PDU router code. */
+//#define PDUR_PRINT_DEBUG_STATEMENTS
+
+/* Turns on/off reentrancy checks */
+#define PDUR_REENTRANCY_CHECK
+
+
+#define PDUR_DEV_ERROR_DETECT 1 // Should this be enables in DASA configuration?
+
+#define PDUR_VERSION_INFO_API
+
+#ifdef PDUR_ZERO_COST_OPERATION
+ // CanIf, FrIf, LinIf
+ #define PDUR_SINGLE_IF CAN_IF
+ // CanTp, FrTp, LinTp
+ //#define PDUR_SINGLE_TP CanTp
+ #define PDUR_MULTICAST_TOIF_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_FROMIF_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_TOTP_SUPPORT MUST_BE_OFF
+ #define PDUR_MULTICAST_FROMTP_SUPPORT MUST_BE_OFF
+
+#else
+ #define PDUR_GATEWAY_OPERATION
+ #ifdef PDUR_GATEWAY_OPERATION
+ #define PDUR_MEMORY_SIZE
+ //#define PDUR_SB_TX_BUFFER_SUPPORT
+ #define PDUR_FIFO_TX_BUFFER_SUPPORT
+ #define PDUR_MAX_TX_BUFFER_NUMBER 10
+ #endif
+
+ //#define PDUR_IPDUM_SUPPORT
+
+ // NOTE: Support for minimum routing not implemented yet.
+ /*
+ #define PDUR_MINIMUM_ROUTING_UP_MODULE COM
+ #define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF
+ #define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)
+ #define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)
+ #define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)
+ #define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)
+ */
+#endif
+
+// Interfaces
+#define PDUR_CANIF_SUPPORT
+//#define PDUR_CANTP_SUPPORT
+//#define PDUR_FRIF_SUPPORT
+//#define PDUR_FRTP_SUPPORT
+#define PDUR_LINIF_SUPPORT
+//#define PDUR_LINTP_SUPPORT
+#define PDUR_COM_SUPPORT
+#define PDUR_DCM_SUPPORT
+
+
+//#define PDUR_MAX_TX_BUFFER_NUMBER
+
+// ERROR TYPES
+#define PDUR_E_CONFIG_PTR_INVALID 0x06
+#define PDUR_E_INVALID_REQUEST 0x01
+#define PDUR_E_PDU_ID_INVALID 0x02
+#define PDUR_E_TP_TX_REQ_REJECTED 0x03
+#define PDUR_E_DATA_PTR_INVALID 0x05
+#define PDUR_E_PDU_INSTANCE_LOST 0x10
--- /dev/null
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5633
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE
+
+# What buildable modules does this board have,
+# default or private
+MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM T32_TERM WINIDEA_TERM PWM CAN CANIF COM ADC DMA SIMPLE_PRINTF
+
+# Needed by us
+MOD_USE=KERNEL MCU
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePoint = 8000000UL,\r
+ .PllEprediv = 1,\r
+ .PllEmfd = 104,\r
+ .PllErfd = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePoint = 40000000UL,\r
+ .PllEprediv = 3,\r
+ .PllEmfd = 83,\r
+ .PllErfd = 5,\r
+ }\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+ .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+// Preprocessor switch to enable / disable the use of the function\r
+// Mcu_PerformReset()\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+\r
+/* FMPLL modes( atleast in 5553/5554 ) */\r
+\r
+typedef enum {\r
+ MCU_FMPLL_BYPASS = 0,\r
+ MCU_FMPLL_EXTERNAL_REF,\r
+ MCU_FMPLL_EXTERNAL_REF_NO_FM,\r
+ MCU_FMPLL_DUAL_CONTROLLER_MODE,\r
+} Mcu_FMPLLmode_t;\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
+ MCU_NBR_OF_CLOCKS,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF,\r
+ //MCU_CLOCKTYPE_EXTERNAL_REF_NO_FM,\r
+ //MCU_CLOCKTYPE_DUAL_CONTROLLER_MODE,\r
+} Mcu_ClockType;\r
+\r
+typedef struct {\r
+ // This container defines a reference point in the Mcu Clock tree\r
+ // It defines the frequency which then can be used by other modules\r
+ // as an input value. Lower multiplicity is 1, as even in the\r
+ // simplest case (only one frequency is used), there is one\r
+ // frequency to be defined.\r
+ uint32 McuClockReferencePoint;\r
+\r
+ // Phase locked loop configuration parameters for MPC551x.\r
+ uint8 PllEprediv;\r
+ uint8 PllEmfd;\r
+ uint8 PllErfd;\r
+} Mcu_ClockSettingConfigType;\r
+\r
+typedef struct {\r
+ // The parameter represents the MCU Mode settings\r
+ uint32 McuMode;\r
+} Mcu_ModeSettingConfigType;\r
+\r
+typedef struct {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ uint32 McuRamDefaultValue;\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ uint32 McuRamSectionBaseAddress;\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ uint32 McuRamSectionSize;\r
+\r
+} Mcu_RamSectorSettingConfigType;\r
+\r
+\r
+// This container defines a reference point in the Mcu Clock tree. It defines\r
+// the frequency which then can be used by other modules as an input value.\r
+// Lower multiplicity is 1, as even in the simplest case (only one frequency is\r
+// used), there is one frequency to be defined.\r
+typedef struct {\r
+\r
+ // This is the frequency for the specific instance of the McuClockReference-\r
+ // Point container. It shall be givn in Hz.\r
+ uint32 McuClockReferencePointFrequency;\r
+\r
+} Mcu_ClockReferencePointType;\r
+\r
+typedef struct {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ uint8 McuClockSrcFailureNotification;\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+ uint8 McuNumberOfMcuModes;\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ uint8 McuRamSectors;\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ uint8 McuClockSettings;\r
+\r
+ // This parameter defines the default clock settings that should be used\r
+ // It is an index into the McuClockSettingsConfig\r
+ Mcu_ClockType McuDefaultClockSettings;\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+ uint32 McuResetSetting;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ Mcu_ClockSettingConfigType * McuClockSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more information\r
+ // on the MCU mode settings.\r
+ Mcu_ModeSettingConfigType *McuModeSettingConfig;\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ Mcu_RamSectorSettingConfigType *McuRamSectorSettingConfig;\r
+\r
+} Mcu_ConfigType;\r
+\r
+extern const Mcu_ConfigType McuConfigData[];\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
#include "Lin.h"\r
#include "LinSM_Cbk.h"\r
#include "PduR_LinIf.h"\r
-#include "Det.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"
+#endif\r
\r
/* Development error macros. */\r
#if ( LINIF_DEV_ERROR_DETECT == STD_ON )\r
if(ptrFrame->LinIfPduDirection == LinIfRxPdu){\r
if(Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr) == LIN_RX_OK){\r
PduR_LinIfRxIndication(ptrFrame->LinIfTxTargetPduId,Lin_SduPtr);\r
- }else{// RX_ERROR or BUSY\r
- Det_ReportError(MODULE_ID_LINIF,0,LINIF_MAINFUNCTION_SERVICE_ID,LINIF_E_RESPONSE);\r
+ }else{// RX_ERROR or BUSY
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(LINIF_E_RESPONSE, DEM_EVENT_STATUS_FAILED);
+#endif\r
}\r
} else if(ptrFrame->LinIfPduDirection == LinIfTxPdu){\r
Lin_StatusType status = Lin_GetStatus(LinIfChannelCfg[chIndex].LinIfChannelId, &Lin_SduPtr);\r
if(status == LIN_TX_OK){\r
PduR_LinIfTxConfirmation(ptrFrame->LinIfTxTargetPduId);\r
}else{// TX_ERROR or BUSY\r
- Det_ReportError(MODULE_ID_LINIF,0,LINIF_MAINFUNCTION_SERVICE_ID,LINIF_E_RESPONSE);\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(LINIF_E_RESPONSE, DEM_EVENT_STATUS_FAILED);
+#endif
}\r
}\r
// Update index after getting status of last frame\r
#include <string.h>\r
\r
\r
-#include "Det.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"\r
+#endif
#include "PduR.h"\r
#include "PduR_Com.h"\r
#include "PduR_CanIf.h"\r
\r
if (PduR_BufferIsFull(Buffer)) { // Buffer is full\r
PduR_BufferFlush(Buffer);\r
- DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_PDU_INSTANCE_LOST);\r
-\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(PDUR_E_PDU_INSTANCE_LOST, DEM_EVENT_STATUS_FAILED);\r
+#endif\r
\r
} else {\r
// Copy data to last place in buffer\r
#else\r
#include "LinIf.h"\r
#endif\r
-\r
-\r
+
+#include "Com.h"
\r
PduR_FctPtrType PduR_StdLinFctPtrs = {\r
.TargetIndicationFctPtr = Com_RxIndication,\r
.TargetTransmitFctPtr = LinIf_Transmit,\r
.TargetConfirmationFctPtr = Com_TxConfirmation,\r
.TargetTriggerTransmitFctPtr = Com_TriggerTransmit,\r
-};\r
+};
+
+
\r
PduR_FctPtrType PduR_StdCanFctPtrs = {\r
.TargetIndicationFctPtr = Com_RxIndication,\r
.TargetConfirmationFctPtr = Com_TxConfirmation,\r
.TargetTriggerTransmitFctPtr = Com_TriggerTransmit,\r
};\r
-\r
+
if (route->PduRDestPdu.TxBufferRef->TxConfP) { // Transfer confirmation pending.\r
// Enqueue the new I-PDU. This will flush the buffer if it is full according to the buffer specification.\r
PduR_BufferQueue(route->PduRDestPdu.TxBufferRef, SduPtr);\r
- // TODO report PDUR_E_INSTANCE_LOST to DEM if needed.\r
+ // TODO report PDUR_E_PDU_INSTANCE_LOST to DEM if needed.\r
}\r
\r
if (!route->PduRDestPdu.TxBufferRef->TxConfP) { // No transfer confirmation pending (anymore).\r
if (route->PduRDestPdu.TxBufferRef->TxConfP) { // Transfer confirmation pending.\r
DEBUG(DEBUG_LOW,"\tTransfer confirmation pending.\n");\r
PduR_BufferQueue(route->PduRDestPdu.TxBufferRef, SduPtr);\r
- // TODO report PDUR_E_INSTANCE_LOST to DEM if needed.\r
+ // TODO report PDUR_E_PDU_INSTANCE_LOST to DEM if needed.\r
\r
}\r
\r
\r
\r
} else {\r
- // TODO report PDUR_E_INSTANCE_LOST to DEM.\r
- //Dem_ReportErrorStatus(PDUR_E_INSTANCE_LOST, 0);\r
- DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, 0x00, PDUR_E_PDU_INSTANCE_LOST);\r
- DEBUG(DEBUG_LOW,"\tTransmission failed. PDUR_E_INSTANCE_LOST\n");\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(PDUR_E_PDU_INSTANCE_LOST, DEM_EVENT_STATUS_FAILED);\r
+#endif
+ DEBUG(DEBUG_LOW,"\tTransmission failed. PDUR_E_PDU_INSTANCE_LOST\n");\r
}\r
}\r
}\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup PduR PDU Router
+ * @{ */
-
-
-
-
-
+/** @file PduR_Types.h
+ * Type definitions for PDU Router.
+ */
#ifndef _PDUR_TYPES_H\r
#define _PDUR_TYPES_H\r
\r
#include "ComStack_Types.h"\r
\r
-/* PduR_StateType defines the states of which the PDU router can be in */\r
+/** PduR_StateType defines the states of which the PDU router can be in */
typedef enum {\r
- PDUR_UNINIT, // PDU Router is not initialized.\r
- PDUR_ONLINE, // PDU Router initialized successfully.\r
- PDUR_REDUCED // PDU Router initialization did not succeed. Only minimum routing is provided.\r
+ PDUR_UNINIT, /**< PDU Router is not initialized. */
+ PDUR_ONLINE, /**< PDU Router initialized successfully. */
+ PDUR_REDUCED /**< PDU Router initialization did not succeed. Only minimum routing is provided. */
} PduR_StateType;\r
\r
typedef enum {\r
- PDU_CNLDO, // Cancel transfer since data is outdated.\r
- PDU_CNLNB, // Cancel transfer since buffer is full.\r
- PDU_CNLOR // Cancel transfer of another reason.\r
+ PDU_CNLDO, /**< Cancel transfer since data is outdated. */
+ PDU_CNLNB, /**< Cancel transfer since buffer is full. */
+ PDU_CNLOR /**< Cancel transfer of another reason. */
} PduR_CancelReasonType;\r
\r
typedef uint8 PduR_ParameterValueType;\r
\r
typedef enum {\r
- PDUR_NO_PROVISION, // No data provision.\r
- PDUR_TRIGGER_TRANSMIT, // Trigger transmit type.\r
- PDUR_DIRECT // Data provision type.\r
+ PDUR_NO_PROVISION, /**< No data provision. */
+ PDUR_TRIGGER_TRANSMIT, /**< Trigger transmit type. */
+ PDUR_DIRECT /**< Data provision type. */
} PduR_DataProvisionType;\r
\r
\r
\r
/* ################ NEW DEFINITIONS ################### */\r
typedef struct {\r
- Std_ReturnType (*TargetIndicationFctPtr)(PduIdType, const uint8*); // Pointer to target function in layer above PDU router.\r
- Std_ReturnType (*TargetTransmitFctPtr)(PduIdType, const PduInfoType*); // Pointer to target function below PDU router.\r
+ Std_ReturnType (*TargetIndicationFctPtr)(PduIdType, const uint8*); /**< Pointer to target function in layer above PDU router. */
+ Std_ReturnType (*TargetTransmitFctPtr)(PduIdType, const PduInfoType*); /**< Pointer to target function below PDU router. */
\r
\r
void (*TargetConfirmationFctPtr)(PduIdType);\r
\r
- /*\r
+ /**
* Target function for trigger transmit requests from the interface modules, e.g. Com_TriggerTransmit. Only\r
* needed if gateway mode is not used, that is, if .DataProvision is set to PDUR_NO_PROVISION.\r
*/\r
// uint8 TxIdx; // This is the same as First, hence left out.\r
uint8 *Buffer;\r
\r
- /*\r
+ /**
* Depth of buffer
*/\r
uint8 Depth;\r
\r
- /*\r
+ /**
* Length of buffer
*/\r
uint8 Length;\r
} PduRTxBuffer_type;\r
\r
typedef struct {\r
- /*\r
+ /**
* The maximum numbers of Tx buffers.
*/\r
uint16 PduRMaxTxBufferNumber; // ???\r
} PduRTxBufferTable_type;\r
\r
typedef struct {\r
- /*\r
+ /**
* PDU identifier assigned by the PDU router.
*/\r
uint16 HandleId;\r
\r
- /*\r
+ /**
* Reference to unique PDU identifier.
*/\r
// SrcPduRef\r
\r
typedef struct {\r
\r
- /*\r
+ /**
* Data provision mode for this PDU.
*/\r
PduR_DataProvisionType DataProvision;\r
\r
- /*\r
+ /**
* Reference to unique PDU identifier which shall\r
* be used by the PDU router instead of the source identifier.
*/\r
// For the moment replaced by this\r
uint16 DestPduId;\r
\r
- /*\r
+ /**
* Reference to the assigned Tx buffer.\r
*\r
* Comment: Only required for non-TP gateway PDUs.
} PduRDefaultValue_type;\r
\r
typedef struct {\r
- /*\r
+ /**
* Not part of standard
*/\r
PduR_FctPtrType *FctPtrs;\r
uint8 PduR_Arc_EOL;\r
uint8 PduR_GatewayMode;\r
\r
- /*\r
+ /**
* Length of PDU data.\r
*\r
* Comment: Only required if a TX buffer is configured.
*/\r
uint8 SduLength;\r
\r
- /*\r
+ /**
* Chunk size for routing on the fly.\r
*\r
* Comment: Only required for TP gateway PDUs.
*/\r
uint16 TpChunkSize;\r
\r
- /*\r
+ /**
* Specifies the default value of the PDU.\r
*\r
* Comment: Only require for gateway operation.
*/\r
PduRDefaultValue_type PduRDefaultValue;\r
\r
- /*\r
+ /**
* Specifies the source of the PDU to be routed.
*/\r
PduRSrcPdu_type PduRSrcPdu;\r
\r
- /*\r
+ /**
* Specifies the destination(s) of the PDU to be routed.\r
*\r
* Comment: Multicast (many destinations) is not supported in this implementation.\r
*/\r
uint16 NRoutingPaths;\r
\r
- /*\r
+ /**
* References to the routing paths defined for this configuration.
*/\r
PduRRoutingPath_type PduRRoutingPath[];\r
\r
\r
typedef struct {\r
- /*\r
+ /**
* Unique configuration identifier.
*/\r
uint8 PduRConfigurationId;\r
\r
- /*\r
+ /**
* The routing table of this PDU router configuration.
*/\r
PduRRoutingTable_type *PduRRoutingTable;\r
\r
\r
- /*\r
+ /**
* The buffers used for TP gateway operation.\r
*\r
* Comment: Not implemented in this version.
*/\r
//PduRTpBufferTable_type PduRTpBufferTable;\r
\r
- /*\r
+ /**
* The buffers used for non-TP gateway operation.
*/\r
PduRTxBufferTable_type *PduRTxBufferTable;\r
} PduR_PBConfigType;\r
\r
#endif\r
+/** @} */
+#include <string.h>
+#include "Dem.h"
+#include "Det.h"
+//#include "Fim.h"
+//#include "Nvm.h"
+//#include "SchM_Dem.h"
+#include "MemMap.h"
+#include "Mcu.h"
+
+/*
+ * Local types
+ */
+
+typedef uint16 ChecksumType;
+
+// For keeping track of the events status
+typedef struct {
+ Dem_EventIdType eventId;
+ uint16 occurrence;
+ Dem_EventStatusType eventStatus;
+ boolean eventStatusChanged;
+ Dem_OperationCycleIdType operationCycleId;
+ Dem_EventStatusExtendedType eventStatusExtended;
+} EventStatusRecType;
+
+
+// Types for storing different event data on event memory
+typedef struct {
+ Dem_EventIdType eventId;
+ uint16 occurrence;
+ ChecksumType checksum;
+} EventRecType;
+
+typedef struct {
+ Dem_EventIdType eventId;
+ uint16 occurrence;
+ uint16 dataSize;
+ sint8 data[DEM_MAX_SIZE_FF_DATA];
+ ChecksumType checksum;
+} FreezeFrameRecType;
+
+typedef struct {
+ Dem_EventIdType eventId;
+ uint16 dataSize;
+ uint8 data[DEM_MAX_SIZE_EXT_DATA];
+ ChecksumType checksum;
+} ExtDataRecType;
+
+
+// State variable
+typedef enum
+{
+ DEM_UNINITIALIZED = 0,
+ DEM_PREINITIALIZED,
+ DEM_INITIALIZED
+} Dem_StateType;
+
+static Dem_StateType demState = DEM_UNINITIALIZED;
+
+// Help pointer to configuration set
+static const Dem_ConfigSetType *configSet;
+
+#if (DEM_VERSION_INFO_API == STD_ON)
+static Std_VersionInfoType _Dem_VersionInfo =
+{
+ .vendorID = (uint16)1,
+ .moduleID = (uint16)1,
+ .instanceID = (uint8)1,
+ .sw_major_version = (uint8)DEM_SW_MAJOR_VERSION,
+ .sw_minor_version = (uint8)DEM_SW_MINOR_VERSION,
+ .sw_patch_version = (uint8)DEM_SW_PATCH_VERSION,
+ .ar_major_version = (uint8)DEM_AR_MAJOR_VERSION,
+ .ar_minor_version = (uint8)DEM_AR_MINOR_VERSION,
+ .ar_patch_version = (uint8)DEM_AR_PATCH_VERSION,
+};
+#endif /* DEM_VERSION_INFO_API */
+
+/*
+ * Allocation of operation cycle state list
+ */
+
+static Dem_OperationCycleStateType operationCycleStateList[DEM_OPERATION_CYCLE_ID_ENDMARK];
+/*
+ * Allocation of local event status buffer
+ */
+static EventStatusRecType eventStatusBuffer[DEM_MAX_NUMBER_EVENT];
+
+/*
+ * Allocation of pre-init event memory (used between pre-init and init)
+ */
+static FreezeFrameRecType preInitFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRE_INIT];
+static ExtDataRecType preInitExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRE_INIT];
+
+/*
+ * Allocation of primary event memory ramlog (after init)
+ */
+static EventRecType priMemEventBuffer[DEM_MAX_NUMBER_EVENT_PRI_MEM];
+static FreezeFrameRecType priMemFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRI_MEM];
+static ExtDataRecType priMemExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRI_MEM];
+
+
+/*
+ * Procedure: setZero
+ * Description: Fill the *ptr to *(ptr+nrOfBytes-1) area with zeroes
+ */
+void setZero(void *ptr, uint16 nrOfBytes)
+{
+ uint8 *clrPtr = (uint8*)ptr;
+
+ if (nrOfBytes > 0)
+ {
+ *clrPtr = 0x00;
+ memcpy(clrPtr+1, clrPtr, nrOfBytes-1);
+ }
+}
+
+/*
+ * Procedure: zeroPriMemBuffers
+ * Description: Fill the primary buffers with zeroes
+ */
+void zeroPriMemBuffers(void)
+{
+ setZero(priMemEventBuffer, sizeof(priMemEventBuffer));
+ setZero(priMemFreezeFrameBuffer, sizeof(priMemFreezeFrameBuffer));
+ setZero(priMemExtDataBuffer, sizeof(priMemExtDataBuffer));
+}
+
+/*
+ * Procedure: calcChecksum
+ * Description: Calculate checksum over *data to *(data+nrOfBytes-1) area
+ */
+ChecksumType calcChecksum(void *data, uint16 nrOfBytes)
+{
+ uint16 i;
+ uint8 *ptr = (uint8*)data;
+ ChecksumType sum = 0;
+
+ for (i = 0; i < nrOfBytes; i++)
+ sum += *ptr++;
+ sum ^= 0xaaaa;
+ return sum;
+}
+
+/*
+ * Procedure: updateEventStatusRec
+ * Description: Update the status of "eventId", if not exist and "createIfNotExist" is
+ * true a new record is created
+ */
+void updateEventStatusRec(const Dem_EventParameterType *eventParam, Dem_EventStatusType eventStatus, boolean createIfNotExist, EventStatusRecType *eventStatusRec)
+{
+ uint16 i;
+ imask_t state = McuE_EnterCriticalSection();
+
+ // Lookup event ID
+ for (i = 0; (eventStatusBuffer[i].eventId != eventParam->EventID) && (i < DEM_MAX_NUMBER_EVENT); i++);
+
+ if ((i == DEM_MAX_NUMBER_EVENT) && (createIfNotExist)) {
+ // Search for free position
+ for (i = 0; (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EVENT); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT) {
+ // Create new event record
+ eventStatusBuffer[i].eventId = eventParam->EventID;
+ eventStatusBuffer[i].occurrence = 0;
+ eventStatusBuffer[i].eventStatus = DEM_EVENT_STATUS_PASSED;
+ eventStatusBuffer[i].eventStatusChanged = FALSE;
+ eventStatusBuffer[i].operationCycleId = eventParam->EventClass->OperationCycleRef;
+ eventStatusBuffer[i].eventStatusExtended = DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE;
+ }
+ else {
+ // Error: Event status buffer full
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);
+ }
+ }
+
+ if (i < DEM_MAX_NUMBER_EVENT) {
+ // Update event record
+ eventStatusBuffer[i].eventStatusExtended &= ~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE);
+
+ if (eventStatus == DEM_EVENT_STATUS_FAILED) {
+ eventStatusBuffer[i].eventStatusExtended |= (DEM_TEST_FAILED | DEM_TEST_FAILED_THIS_OPERATION_CYCLE | DEM_TEST_FAILED_SINCE_LAST_CLEAR);
+ if (eventStatusBuffer[i].eventStatus != eventStatus) {
+ eventStatusBuffer[i].occurrence++;
+ }
+ }
+
+ if (eventStatus == DEM_EVENT_STATUS_PASSED) {
+ eventStatusBuffer[i].eventStatusExtended &= ~DEM_TEST_FAILED;
+ }
+
+ if (eventStatusBuffer[i].eventStatus != eventStatus) {
+ eventStatusBuffer[i].eventStatus = eventStatus;
+ eventStatusBuffer[i].eventStatusChanged = TRUE;
+ }
+ else {
+ eventStatusBuffer[i].eventStatusChanged = FALSE;
+ }
+
+ // Copy the record
+ memcpy(eventStatusRec, &eventStatusBuffer[i], sizeof(EventStatusRecType));
+ }
+ else {
+ // Copy an empty record to return data
+ eventStatusRec->eventId = DEM_EVENT_ID_NULL;
+ eventStatusRec->eventStatus = DEM_EVENT_STATUS_PASSED;
+ eventStatusRec->occurrence = 0;
+ eventStatusBuffer[i].eventStatusChanged = FALSE;
+ eventStatusBuffer[i].eventStatusExtended = DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR;
+ }
+
+
+ McuE_ExitCriticalSection(state);
+}
+
+
+/*
+ * Procedure: mergeEventStatusRec
+ * Description: Update the occurrence counter of status, if not exist a new record is created
+ */
+void mergeEventStatusRec(EventRecType *eventRec)
+{
+ uint16 i;
+ imask_t state = McuE_EnterCriticalSection();
+
+ // Lookup event ID
+ for (i = 0; (eventStatusBuffer[i].eventId != eventRec->eventId) && (i < DEM_MAX_NUMBER_EVENT); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT) {
+ // Update occurrence counter, rest of pre init state is kept.
+ eventStatusBuffer[i].occurrence += eventRec->occurrence;
+
+ }
+ else {
+ // Search for free position
+ for (i = 0; (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EVENT); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT) {
+ // Create new event, from stored event
+ eventStatusBuffer[i].eventId = eventRec->eventId;
+ eventStatusBuffer[i].occurrence = eventRec->occurrence;
+ eventStatusBuffer[i].eventStatus = DEM_EVENT_STATUS_PASSED;
+ eventStatusBuffer[i].eventStatusChanged = FALSE;
+ }
+ else {
+ // Error: Event status buffer full
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_MERGE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);
+ }
+ }
+
+ McuE_ExitCriticalSection(state);
+}
+
+/*
+ * Procedure: getEventStatusRec
+ * Description: Returns the status record of "eventId" in "eventStatusRec"
+ */
+void getEventStatusRec(Dem_EventIdType eventId, EventStatusRecType *eventStatusRec)
+{
+ uint16 i;
+ // Lookup event ID
+ for (i = 0; (eventStatusBuffer[i].eventId != eventId) && (i < DEM_MAX_NUMBER_EVENT); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT) {
+ // Copy the record
+ memcpy(eventStatusRec, &eventStatusBuffer[i], sizeof(EventStatusRecType));
+ }
+ else {
+ eventStatusRec->eventId = DEM_EVENT_ID_NULL;
+ eventStatusRec->eventStatus = DEM_EVENT_STATUS_PASSED;
+ eventStatusRec->occurrence = 0;
+ }
+}
+
+
+/*
+ * Procedure: lookupEventIdParameter
+ * Description: Returns the pointer to event id parameters of "eventId" in "*eventIdParam",
+ * if not found NULL is returned.
+ */
+void lookupEventIdParameter(Dem_EventIdType eventId, const Dem_EventParameterType **const eventIdParam)
+{
+ uint16 i;
+ *eventIdParam = NULL;
+
+ // Lookup the correct event id parameters
+ for (i = 0; !configSet->EventParameter[i].Arc_EOL; i++) {
+ if (configSet->EventParameter[i].EventID == eventId) {
+ *eventIdParam = &configSet->EventParameter[i];
+ return;
+ }
+ }
+ // Id not found return with NULL pointer
+}
+
+
+void getFreezeFrameData(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)
+{
+ // TODO: Fill out
+}
+
+
+void storeFreezeFrameDataPreInit(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)
+{
+ // TODO: Fill out
+}
+
+
+void updateFreezeFrameOccurrencePreInit(EventRecType *EventBuffer)
+{
+ // TODO: Fill out
+}
+
+/*
+ * Procedure: getExtendedData
+ * Description: Collects the extended data according to "eventParam" and return it in "extData",
+ * if not found eventId is set to DEM_EVENT_ID_NULL.
+ */
+void getExtendedData(const Dem_EventParameterType *eventParam, ExtDataRecType *extData)
+{
+ Std_ReturnType callbackReturnCode;
+ uint16 i;
+ uint16 storeIndex = 0;
+ uint16 recordSize;
+
+ // Clear ext data record
+ setZero(extData, sizeof(ExtDataRecType));
+
+ // Check if any pointer to extended data class
+ if (eventParam->ExtendedDataClassRef != NULL) {
+ // Request extended data and copy it to the buffer
+ for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL); i++) {
+ recordSize = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->DataSize;
+ if ((storeIndex + recordSize) <= DEM_MAX_SIZE_EXT_DATA) {
+ callbackReturnCode = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->CallbackGetExtDataRecord(&extData->data[storeIndex]);
+ if (callbackReturnCode != E_OK) {
+ // Callback data currently not available, clear space.
+ setZero(&extData->data[storeIndex], recordSize);
+ }
+ storeIndex += recordSize;
+ }
+ else {
+ // Error: Size of extended data record is bigger than reserved space.
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GET_EXTENDED_DATA_ID, DEM_E_EXT_DATA_TO_BIG);
+ break; // Break the loop
+ }
+ }
+ }
+
+ // Check if any data has been stored
+ if (storeIndex != 0) {
+ extData->eventId = eventParam->EventID;
+ extData->dataSize = storeIndex;
+ extData->checksum = calcChecksum(extData, sizeof(ExtDataRecType)-sizeof(ChecksumType));
+ }
+ else {
+ extData->eventId = DEM_EVENT_ID_NULL;
+ extData->dataSize = storeIndex;
+ extData->checksum = 0;
+ }
+}
+
+
+/*
+ * Procedure: storeExtendedDataPreInit
+ * Description: Store the extended data pointed by "extendedData" to the "preInitExtDataBuffer"
+ */
+void storeExtendedDataPreInit(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)
+{
+ uint16 i;
+ imask_t state = McuE_EnterCriticalSection();
+
+ // Lookup first free position
+ for (i = 0; (preInitExtDataBuffer[i].eventId !=0) && (i<DEM_MAX_NUMBER_EXT_DATA_PRE_INIT); i++);
+
+ if (i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT) {
+ memcpy(&preInitExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));
+ }
+ else {
+ // Error: Pre init extended data buffer full
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRE_INIT_ID, DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL);
+ }
+
+ McuE_ExitCriticalSection(state);
+}
+
+
+/*
+ * Procedure: storeEventPriMem
+ * Description: Store the event data of "eventStatus->eventId" in "priMemEventBuffer",
+ * if non existent a new entry is created.
+ */
+void storeEventPriMem(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatus)
+{
+ uint16 i;
+ imask_t state = McuE_EnterCriticalSection();
+
+
+ // Lookup event ID
+ for (i = 0; (priMemEventBuffer[i].eventId != eventStatus->eventId) && (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) {
+ // Update event found
+ priMemEventBuffer[i].occurrence = eventStatus->occurrence;
+ priMemEventBuffer[i].checksum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));
+ }
+ else {
+ // Search for free position
+ for (i=0; (priMemEventBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI); i++);
+
+ if (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) {
+ priMemEventBuffer[i].eventId = eventStatus->eventId;
+ priMemEventBuffer[i].occurrence = eventStatus->occurrence;
+ priMemEventBuffer[i].checksum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));
+ }
+ else {
+ // Error: Pri mem event buffer full
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EVENT_PRI_MEM_ID, DEM_E_PRI_MEM_EVENT_BUFF_FULL);
+ }
+ }
+
+ McuE_ExitCriticalSection(state);
+}
+
+
+/*
+ * Procedure: storeEventEvtMem
+ * Description: Store the event data of "eventStatus->eventId" in event memory according to
+ * "eventParam" destination option.
+ */
+void storeEventEvtMem(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatus)
+{
+ uint16 i;
+
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {
+ switch (eventParam->EventClass->EventDestination[i])
+ {
+ case DEM_DTC_ORIGIN_PRIMARY_MEMORY:
+ storeEventPriMem(eventParam, eventStatus);
+ break;
+
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:
+ case DEM_DTC_ORIGIN_PERMANENT_MEMORY:
+ case DEM_DTC_ORIGIN_MIRROR_MEMORY:
+ // Not yet supported
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+/*
+ * Procedure: storeExtendedDataPriMem
+ * Description: Creates new an extended data record in "priMemExtDataBuffer".
+ */
+void storeExtendedDataPriMem(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)
+{
+ uint16 i;
+ imask_t state = McuE_EnterCriticalSection();
+
+ // Lookup first free position
+ for (i = 0; (priMemExtDataBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM); i++);
+ if (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) {
+ memcpy(&priMemExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));
+ }
+ else {
+ // Error: Pri mem extended data buffer full
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRI_MEM_ID, DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL);
+ }
+
+ McuE_ExitCriticalSection(state);
+}
+
+
+/*
+ * Procedure: storeExtendedDataEvtMem
+ * Description: Store the extended data in event memory according to
+ * "eventParam" destination option
+ */
+void storeExtendedDataEvtMem(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)
+{
+ uint16 i;
+
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {
+ switch (eventParam->EventClass->EventDestination[i])
+ {
+ case DEM_DTC_ORIGIN_PRIMARY_MEMORY:
+ storeExtendedDataPriMem(eventParam, extendedData);
+ break;
+
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:
+ case DEM_DTC_ORIGIN_PERMANENT_MEMORY:
+ case DEM_DTC_ORIGIN_MIRROR_MEMORY:
+ // Not yet supported
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+void storeFreezeFrameDataPriMem(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)
+{
+ // TODO: Fill out
+}
+
+
+/*
+ * Procedure: storeFreezeFrameDataEvtMem
+ * Description: Store the freeze frame data in event memory according to
+ * "eventParam" destination option
+ */
+void storeFreezeFrameDataEvtMem(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)
+{
+ uint16 i;
+
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {
+ switch (eventParam->EventClass->EventDestination[i])
+ {
+ case DEM_DTC_ORIGIN_PRIMARY_MEMORY:
+ storeFreezeFrameDataPriMem(eventParam, freezeFrame);
+ break;
+
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:
+ case DEM_DTC_ORIGIN_PERMANENT_MEMORY:
+ case DEM_DTC_ORIGIN_MIRROR_MEMORY:
+ // Not yet supported
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+/*
+ * Procedure: handlePreInitEvent
+ * Description: Handle the updating of event status and storing of
+ * event related data in preInit buffers.
+ */
+void handlePreInitEvent(Dem_EventIdType eventId, Dem_EventStatusType eventStatus)
+{
+ const Dem_EventParameterType *eventParam;
+ EventStatusRecType eventStatusLocal;
+ FreezeFrameRecType freezeFrameLocal;
+ ExtDataRecType extendedDataLocal;
+
+ // Find configuration for this event
+ lookupEventIdParameter(eventId, &eventParam);
+ if (eventParam != NULL) {
+ if (eventParam->EventClass->OperationCycleRef < DEM_OPERATION_CYCLE_ID_ENDMARK) {
+ if (operationCycleStateList[eventParam->EventClass->OperationCycleRef] == DEM_CYCLE_STATE_START) {
+ if (eventStatus == DEM_EVENT_STATUS_PASSED) {
+ updateEventStatusRec(eventParam, eventStatus, FALSE, &eventStatusLocal);
+ }
+ else {
+ updateEventStatusRec(eventParam, eventStatus, TRUE, &eventStatusLocal);
+ }
+
+ if (eventStatusLocal.eventStatusChanged) {
+
+ if (eventStatusLocal.eventStatus == DEM_EVENT_STATUS_FAILED) {
+ // Collect freeze frame data
+ getFreezeFrameData(eventParam, &freezeFrameLocal);
+ storeFreezeFrameDataPreInit(eventParam, &freezeFrameLocal);
+
+ // Check if first time -> store extended data
+ if (eventStatusLocal.occurrence == 1) {
+ // Collect extended data
+ getExtendedData(eventParam, &extendedDataLocal);
+ if (extendedDataLocal.eventId != DEM_EVENT_ID_NULL)
+ {
+ storeExtendedDataPreInit(eventParam, &extendedDataLocal);
+ }
+ }
+ }
+ }
+ }
+ else {
+ // Operation cycle not started
+ // TODO: Report error?
+ }
+ }
+ else {
+ // Operation cycle not set
+ // TODO: Report error?
+ }
+ }
+ else {
+ // Event ID not configured
+ // TODO: Report error?
+ }
+}
+
+
+/*
+ * Procedure: handleEvent
+ * Description: Handle the updating of event status and storing of
+ * event related data in event memory.
+ */
+Std_ReturnType handleEvent(Dem_EventIdType eventId, Dem_EventStatusType eventStatus)
+{
+ Std_ReturnType returnCode = E_OK;
+ const Dem_EventParameterType *eventParam;
+ EventStatusRecType eventStatusLocal;
+ FreezeFrameRecType freezeFrameLocal;
+ ExtDataRecType extendedDataLocal;
+
+ // Find configuration for this event
+ lookupEventIdParameter(eventId, &eventParam);
+ if (eventParam != NULL) {
+ if (eventParam->EventClass->OperationCycleRef < DEM_OPERATION_CYCLE_ID_ENDMARK) {
+ if (operationCycleStateList[eventParam->EventClass->OperationCycleRef] == DEM_CYCLE_STATE_START) {
+ updateEventStatusRec(eventParam, eventStatus, TRUE, &eventStatusLocal);
+
+ if (eventStatusLocal.eventStatusChanged) {
+
+ if (eventStatusLocal.eventStatus == DEM_EVENT_STATUS_FAILED) {
+ storeEventEvtMem(eventParam, &eventStatusLocal);
+ // Collect freeze frame data
+ getFreezeFrameData(eventParam, &freezeFrameLocal);
+ storeFreezeFrameDataEvtMem(eventParam, &freezeFrameLocal);
+
+ // Check if first time -> store extended data
+ if (eventStatusLocal.occurrence == 1) {
+ // Collect extended data
+ getExtendedData(eventParam, &extendedDataLocal);
+ if (extendedDataLocal.eventId != DEM_EVENT_ID_NULL)
+ {
+ storeExtendedDataEvtMem(eventParam, &extendedDataLocal);
+ }
+ }
+ }
+ }
+ }
+ else {
+ // Operation cycle not started
+ returnCode = E_NOT_OK;
+ }
+ }
+ else {
+ // Operation cycle not set
+ returnCode = E_NOT_OK;
+ }
+ }
+ else {
+ // Event ID not configured
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+/*
+ * Procedure: getEventStatus
+ * Description: Returns the extended event status bitmask of eventId in "eventStatusExtended".
+ */
+void getEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended)
+{
+ EventStatusRecType eventStatusLocal;
+
+ // Get recorded status
+ getEventStatusRec(eventId, &eventStatusLocal);
+ if (eventStatusLocal.eventId == eventId) {
+ *eventStatusExtended = eventStatusLocal.eventStatusExtended;
+ }
+ else {
+ // Event Id not found, no report received.
+ *eventStatusExtended = DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR;
+ }
+}
+
+/*
+ * Procedure: getEventFailed
+ * Description: Returns the TRUE or FALSE of "eventId" in "eventFailed" depending on current status.
+ */
+void getEventFailed(Dem_EventIdType eventId, boolean *eventFailed)
+{
+ EventStatusRecType eventStatusLocal;
+
+ // Get recorded status
+ getEventStatusRec(eventId, &eventStatusLocal);
+ if (eventStatusLocal.eventId == eventId) {
+ if (eventStatusLocal.eventStatusExtended & DEM_TEST_FAILED) {
+ *eventFailed = TRUE;
+ }
+ else {
+ *eventFailed = FALSE;
+ }
+ }
+ else {
+ // Event Id not found, assume ok.
+ *eventFailed = FALSE;
+ }
+}
+
+/*
+ * Procedure: getEventTested
+ * Description: Returns the TRUE or FALSE of "eventId" in "eventTested" depending on
+ * current status the "test not completed this operation cycle" bit.
+ */
+void getEventTested(Dem_EventIdType eventId, boolean *eventTested)
+{
+ EventStatusRecType eventStatusLocal;
+
+ // Get recorded status
+ getEventStatusRec(eventId, &eventStatusLocal);
+ if (eventStatusLocal.eventId == eventId) {
+ if ( !(eventStatusLocal.eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) {
+ *eventTested = TRUE;
+ }
+ else {
+ *eventTested = FALSE;
+ }
+ }
+ else {
+ // Event Id not found, not tested.
+ *eventTested = FALSE;
+ }
+}
+
+/*
+ * Procedure: getFaultDetectionCounter
+ * Description: Returns pre debounce counter of "eventId" in "counter" and return value E_OK if
+ * the counter was available else E_NOT_OK.
+ */
+Std_ReturnType getFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter)
+{
+ Std_ReturnType returnCode = E_NOT_OK;
+ const Dem_EventParameterType *eventParam;
+
+ lookupEventIdParameter(eventId, &eventParam);
+ if (eventParam != NULL) {
+ if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) {
+ switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName)
+ {
+ case DEM_NO_PRE_DEBOUNCE:
+ if (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal != NULL) {
+ returnCode = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCnt(counter);
+ }
+ break;
+
+ case DEM_PRE_DEBOUNCE_COUNTER_BASED:
+ case DEM_PRE_DEBOUNCE_FREQUENCY_BASED:
+ case DEM_PRE_DEBOUNCE_TIME_BASED:
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_NOT_IMPLEMENTED_YET);
+#endif
+ break;
+
+ default:
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_PARAM_DATA);
+#endif
+ break;
+ }
+ }
+ }
+
+ return returnCode;
+}
+
+/*
+ * Procedure: setOperationCycleState
+ * Description: Change the operation state of "operationCycleId" to "cycleState" and updates stored
+ * event connected to this cycle id.
+ * Returns E_OK if operation was successful else E_NOT_OK.
+ */
+Std_ReturnType setOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState)
+{
+ uint16 i;
+ Std_ReturnType returnCode = E_OK;
+
+ if (operationCycleId < DEM_OPERATION_CYCLE_ID_ENDMARK) {
+ switch (cycleState)
+ {
+ case DEM_CYCLE_STATE_START:
+ operationCycleStateList[operationCycleId] = cycleState;
+ // Lookup event ID
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {
+ if ((eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (eventStatusBuffer[i].operationCycleId == operationCycleId)) {
+ eventStatusBuffer[i].eventStatusExtended &= ~DEM_TEST_FAILED_THIS_OPERATION_CYCLE;
+ eventStatusBuffer[i].eventStatusExtended |= DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE;
+ }
+ }
+ break;
+
+ case DEM_CYCLE_STATE_END:
+ operationCycleStateList[operationCycleId] = cycleState;
+ break;
+ default:
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);
+#endif
+ returnCode = E_NOT_OK;
+ break;
+ }
+ }
+ else {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+//==============================================================================//
+// //
+// E X T E R N A L F U N C T I O N S //
+// //
+//==============================================================================//
+
+/*********************************************
+ * Interface for upper layer modules (8.3.1) *
+ *********************************************/
+
+/*
+ * Procedure: Dem_GetVersionInfo
+ * Reentrant: Yes
+ */
+#if (DEM_VERSION_INFO_API == STD_ON)
+void Dem_GetVersionInfo(Std_VersionInfoType *versionInfo) {
+ memcpy(versionInfo, &_Dem_VersionInfo, sizeof(Std_VersionInfoType));
+}
+#endif /* DEM_VERSION_INFO_API */
+
+
+/***********************************************
+ * Interface ECU State Manager <-> DEM (8.3.2) *
+ ***********************************************/
+
+/*
+ * Procedure: Dem_PreInit
+ * Reentrant: No
+ */
+void Dem_PreInit(void)
+{
+ int i, j;
+
+ if (DEM_Config.ConfigSet == NULL) {
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_PREINIT_ID, DEM_E_CONFIG_PTR_INVALID);
+ return;
+ } else {
+ configSet = DEM_Config.ConfigSet;
+ }
+
+ // Initializion of operation cycle states.
+ for (i = 0; i < DEM_OPERATION_CYCLE_ID_ENDMARK; i++) {
+ operationCycleStateList[i] = DEM_CYCLE_STATE_END;
+ }
+
+ // Initialize the event status buffer
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {
+ eventStatusBuffer[i].eventId = DEM_EVENT_ID_NULL;
+ eventStatusBuffer[i].occurrence = 0;
+ eventStatusBuffer[i].eventStatusExtended = DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR;
+ eventStatusBuffer[i].eventStatus = DEM_EVENT_STATUS_PASSED;
+ eventStatusBuffer[i].eventStatusChanged = FALSE;
+ }
+
+ for (i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; i++) {
+ preInitFreezeFrameBuffer[i].checksum = 0;
+ preInitFreezeFrameBuffer[i].eventId = DEM_EVENT_ID_NULL;
+ preInitFreezeFrameBuffer[i].occurrence = 0;
+ preInitFreezeFrameBuffer[i].dataSize = 0;
+ for (j = 0; j < DEM_MAX_SIZE_FF_DATA;j++)
+ preInitFreezeFrameBuffer[i].data[j] = 0;
+ }
+
+ for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++) {
+ preInitExtDataBuffer[i].checksum = 0;
+ preInitExtDataBuffer[i].eventId = DEM_EVENT_ID_NULL;
+ preInitExtDataBuffer[i].dataSize = 0;
+ for (j = 0; j < DEM_MAX_SIZE_EXT_DATA;j++)
+ preInitExtDataBuffer[i].data[j] = 0;
+ }
+
+ setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_START);
+
+ demState = DEM_PREINITIALIZED;
+}
+
+
+/*
+ * Procedure: Dem_Init
+ * Reentrant: No
+ */
+void Dem_Init(void)
+{
+ uint16 i;
+ ChecksumType cSum;
+ EventStatusRecType eventStatusLocal;
+ const Dem_EventParameterType *eventParam;
+
+ /*
+ * Validate and read out saved error log from non volatile memory
+ */
+
+ // Validate event records stored in primary memory
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT_PRI_MEM; i++) {
+ cSum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));
+ if ((cSum != priMemEventBuffer[i].checksum) || priMemEventBuffer[i].eventId == DEM_EVENT_ID_NULL) {
+ // Not valid, clear the record
+ setZero(&priMemEventBuffer[i], sizeof(EventRecType));
+ }
+ else {
+ // Valid, update current status
+ mergeEventStatusRec(&priMemEventBuffer[i]);
+
+ // Update occurrence counter on pre init stored freeze frames
+ updateFreezeFrameOccurrencePreInit(&priMemEventBuffer[i]);
+ }
+ }
+
+ // Validate extended data records stored in primary memory
+ for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; i++) {
+ cSum = calcChecksum(&priMemExtDataBuffer[i], sizeof(ExtDataRecType)-sizeof(ChecksumType));
+ if ((cSum != priMemExtDataBuffer[i].checksum) || priMemExtDataBuffer[i].eventId == DEM_EVENT_ID_NULL) {
+ // Unlegal record, clear the record
+ setZero(&priMemExtDataBuffer[i], sizeof(ExtDataRecType));
+ }
+ }
+
+ // Validate freeze frame records stored in primary memory
+ for (i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRI_MEM; i++) {
+ cSum = calcChecksum(&priMemFreezeFrameBuffer[i], sizeof(FreezeFrameRecType)-sizeof(ChecksumType));
+ if ((cSum != priMemFreezeFrameBuffer[i].checksum) || (priMemFreezeFrameBuffer[i].eventId == DEM_EVENT_ID_NULL)) {
+ // Wrong checksum, clear the record
+ setZero(&priMemFreezeFrameBuffer[i], sizeof(FreezeFrameRecType));
+ }
+ }
+
+ /*
+ * Handle errors stored in temporary buffer (if any)
+ */
+
+ // Transfer updated event data to event memory
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {
+ if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) {
+ // Update the event memory
+ lookupEventIdParameter(eventStatusBuffer[i].eventId, &eventParam);
+ storeEventEvtMem(eventParam, &eventStatusBuffer[i]);
+ }
+ }
+
+ // Transfer extended data to event memory if necessary
+ for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++) {
+ if (preInitExtDataBuffer[i].eventId != DEM_EVENT_ID_NULL) {
+ getEventStatusRec(preInitExtDataBuffer[i].eventId, &eventStatusLocal);
+ // Check if new or old error event
+ if (eventStatusLocal.occurrence == 1) {
+ // It has not been stored before so store it.
+ lookupEventIdParameter(preInitExtDataBuffer[i].eventId, &eventParam);
+ storeExtendedDataEvtMem(eventParam, &preInitExtDataBuffer[i]);
+ }
+ }
+ }
+
+ // Transfer freeze frames to event memory
+ for (i = 0; i < DEM_MAX_NUMBER_FF_DATA_PRE_INIT; i++) {
+ if (preInitFreezeFrameBuffer[i].eventId != DEM_EVENT_ID_NULL) {
+ lookupEventIdParameter(preInitFreezeFrameBuffer[i].eventId, &eventParam);
+ storeFreezeFrameDataEvtMem(eventParam, &preInitFreezeFrameBuffer[i]);
+ }
+ }
+
+ demState = DEM_INITIALIZED;
+}
+
+
+/*
+ * Procedure: Dem_shutdown
+ * Reentrant: No
+ */
+void Dem_Shutdown(void)
+{
+ setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_END);
+
+ demState = DEM_UNINITIALIZED;
+}
+
+
+/*
+ * Interface for basic software scheduler
+ */
+void Dem_MainFunction(void)
+{
+
+}
+
+
+/***************************************************
+ * Interface SW-Components via RTE <-> DEM (8.3.3) *
+ ***************************************************/
+
+/*
+ * Procedure: Dem_SetEventStatus
+ * Reentrant: Yes
+ */
+Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, Dem_EventStatusType eventStatus)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ returnCode = handleEvent(eventId, eventStatus);
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_SETEVENTSTATUS_ID, DEM_E_UNINIT);
+ returnCode = E_NOT_OK;
+#endif
+ }
+
+ return returnCode;
+}
+
+
+/*
+ * Procedure: Dem_ResetEventStatus
+ * Reentrant: Yes
+ */
+Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId)
+{
+ const Dem_EventParameterType *eventParam;
+ EventStatusRecType eventStatusLocal;
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ lookupEventIdParameter(eventId, &eventParam);
+ if (eventParam != NULL) {
+ updateEventStatusRec(eventParam, DEM_EVENT_STATUS_PASSED, FALSE, &eventStatusLocal);
+ }
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_RESETEVENTSTATUS_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ getEventStatus(eventId, eventStatusExtended);
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTSTATUS_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ getEventFailed(eventId, eventFailed);
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTFAILED_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ getEventTested(eventId, eventTested);
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTTESTED_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ returnCode = getFaultDetectionCounter(eventId, counter);
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState)
+{
+ Std_ReturnType returnCode = E_OK;
+
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started
+ {
+ returnCode = setOperationCycleState(operationCycleId, cycleState);
+
+ }
+ else
+ {
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_UNINIT);
+#endif
+ returnCode = E_NOT_OK;
+ }
+
+ return returnCode;
+}
+
+
+/********************************************
+ * Interface BSW-Components <-> DEM (8.3.4) *
+ ********************************************/
+
+/*
+ * Procedure: Dem_ReportErrorStatus
+ * Reentrant: Yes
+ */
+void Dem_ReportErrorStatus( Dem_EventIdType eventId, Dem_EventStatusType eventStatus )
+{
+
+ switch (demState) {
+ case DEM_PREINITIALIZED:
+ // Update status and check if is to be stored
+ if ((eventStatus == DEM_EVENT_STATUS_PASSED) || (eventStatus == DEM_EVENT_STATUS_FAILED)) {
+ handlePreInitEvent(eventId, eventStatus);
+ }
+ break;
+
+ case DEM_INITIALIZED:
+ // Handle report
+ if ((eventStatus == DEM_EVENT_STATUS_PASSED) || (eventStatus == DEM_EVENT_STATUS_FAILED)) {
+ (void)handleEvent(eventId, eventStatus);
+ }
+ break;
+
+ case DEM_UNINITIALIZED:
+ default:
+ // Uninitialized can not do anything
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+ Det_ReportError(MODULE_ID_DEM, 0, DEM_REPORTERRORSTATUS_ID, DEM_E_UNINIT);
+#endif
+ break;
+
+ } // switch (demState)
+}
+
+/*********************************
+ * Interface DCM <-> DEM (8.3.5) *
+ *********************************/
+
+/***********************************
+ * OBD-specific Interfaces (8.3.6) *
+ ***********************************/
-\r
-#include "Std_Types.h"\r
-#include "Rte.h"\r
-#include "Dem.h"\r
-#include "Dem_Lcfg.h"\r
-#include "Dem_PBcfg.h"\r
-//#include "NvM.h"\r
-// #include "Fim.h"\r
-// #include "Rte_Dem.h"\r
-#include "Dem_IntEvtId.h"\r
-#include "Dem_IntErrId.h"\r
-#include "Os.h"\r
-\r
-void Dem_PreInit( void ) {\r
- \r
-}\r
-void Dem_Init( void ) {\r
- \r
-}\r
-\r
-Std_ReturnType Dem_ReportErrorStatus( Dem_EventIdType id ,Dem_EventStatusType type ) {\r
- (void )id;\r
- (void )type;\r
- return RTE_E_OK;\r
-}\r
#ifndef DEM_LCFG_H_\r
-#define DEM_LCFG_H_\r
+#define DEM_LCFG_H_
+
+#include "Dem_Types.h"
+
+
+/*
+ * Callback function prototypes
+ */
+
+// InitMonitorForEvent
+typedef Std_ReturnType (*Dem_CallbackInitMonitorForEventFncType)(Dem_InitMonitorKindType InitMonitorKind);
+
+// InitMonitorForFunction
+typedef Std_ReturnType (*Dem_CallbackInitMonitorForFunctionFncType)(void);
+
+// EventStatusChanged
+typedef Std_ReturnType (*Dem_CallbackEventStatusChangedFncType)(Dem_EventStatusExtendedType EventStatusOld, Dem_EventStatusExtendedType EventStatusNew);
+
+// DTCStatusChanged
+typedef Std_ReturnType (*Dem_CallbackDTCStatusChangedFncType)(uint8 DTCStatusOld, uint8 DTCStatusNew);
+
+// DIDServices
+#if 1 // Until DCM is available
+typedef uint8 Dcm_NegativeResponseCodeType;
+#endif
+typedef Std_ReturnType (*Dem_CallbackConditionCheckReadFncType)(Dcm_NegativeResponseCodeType *Nrc);
+typedef Std_ReturnType (*Dem_CallbackReadDataFncType)(uint8 *Data);
+typedef Std_ReturnType (*Dem_CallbackReadDataLength)(uint16 *DidLength);
+
+// GetExtendedDataRecord
+typedef Std_ReturnType (*Dem_CallbackGetExtDataRecordFncType)(uint8 *ExtendedDataRecord);
+
+// GetFaultDetectionCounter
+typedef Std_ReturnType (*Dem_CallbackGetFaultDetectionCounterFncType)(sint8 *EventIdFaultDetectionCounter);
+
+// GetPIDValue
+typedef Std_ReturnType (*Dem_CallbackGetPIDValueFncType)(uint8 *DataValueBuffer);
+
+/*
+ * DemGeneral types
+ */
+
+// 10.2.25 DemEnableCondition
+typedef struct {
+ boolean EnableConditionStatus; //
+ // uint16 EnableConditionID; // Optional
+} Dem_EnableConditionType;
+
+// 10.2.30 DemExtendedDataRecordClass
+typedef struct {
+ uint16 RecordNumber; // (1)
+ uint16 DataSize; // (1)
+ Dem_CallbackGetExtDataRecordFncType CallbackGetExtDataRecord;// (1)
+} Dem_ExtendedDataRecordClassType;
+
+// 10.2.13 DemExtendedDataClass
+typedef struct {
+ const Dem_ExtendedDataRecordClassType *const ExtendedDataRecordClassRef[DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA+1]; // (1..253)
+} Dem_ExtendedDataClassType;
+
+// 10.2.8 DemPidOrDid
+typedef struct {
+ boolean PidOrDidUsePort; // (1)
+ uint8 PidOrDidSize; // (1)
+ uint16 DidIdentifier; // (0..1)
+ Dem_CallbackConditionCheckReadFncType DidConditionCheckReadFnc; // (0..1)
+ Dem_CallbackReadDataLength DidReadDataLengthFnc; // (0..1)
+ Dem_CallbackReadDataFncType DidReadFnc; // (0..1)
+ uint8 PidIndentifier; // (0..1)
+ Dem_CallbackGetPIDValueFncType PidReadFnc; // (0..1)
+} Dem_PidOrDidType;
+
+// 10.2.18 DemFreezeFrameClass
+typedef struct {
+ Dem_FreezeFrameKindType FFKind; // (1)
+// uint8 FFRecordNumber; // (1) Optional
+// const Dem_PidOrDidType *FFIdClassRef; // (1..255) Optional?
+} Dem_FreezeFrameClassType;
+
+// 10.2.4 DemIndicator
+typedef struct {
+ uint16 Indicator; // (1)
+} Dem_IndicatorType;
+
+// 10.2.28 DemNvramBlockId
+typedef struct {
+ // TODO: Fill out
+} Dem_NvramBlockIdType;
+
+/*
+ * DemConfigSetType types
+ */
+
+// 10.2.6 DemCallbackDTCStatusChanged
+typedef struct {
+ Dem_CallbackDTCStatusChangedFncType CallbackDTCStatusChangedFnc; // (0..1)
+} Dem_CallbackDTCStatusChangedType;
+
+// 10.2.26 DemCallbackInitMForF
+typedef struct {
+ Dem_CallbackInitMonitorForFunctionFncType CallbackInitMForF; // (0..1)
+} Dem_CallbackInitMForFType;
+
+// 10.2.17 DemDTCClass
+typedef struct {
+ uint32 DTC; // (1)
+ uint8 DTCFunctionUnit; // (1)
+ Dem_DTCKindType DTCKind; // (1)
+ const Dem_CallbackDTCStatusChangedType *CallbackDTCStatusChanged; // (0..*)
+ const Dem_CallbackInitMForFType *CallbackInitMForF; // (0..*)
+ // Dem_DTCSeverityType DTCSeverity // (0..1) Optional
+} Dem_DTCClassType;
+
+// 10.2.5 DemCallbackEventStatusChanged
+typedef struct {
+ Dem_CallbackEventStatusChangedFncType CallbackEventStatusChangedFnc; // (0..1)
+} Dem_CallbackEventStatusChangedType;
+
+// 10.2.27 DemCallbackInitMForE
+typedef struct {
+ Dem_CallbackInitMonitorForEventFncType CallbackInitMForEFnc; // (0..1)
+} Dem_CallbackInitMforEType;
+
+typedef struct {
+ Dem_IndicatorStatusType IndicatorBehaviour; // (1)
+ Dem_IndicatorType *LinkedIndicator; // (1)
+} Dem_IndicatorAttributeType;
+
+typedef struct {
+ Dem_CallbackGetFaultDetectionCounterFncType CallbackGetFDCnt; // (1)
+} Dem_PreDebounceMonitorInternalType;
+
+typedef struct {
+ // TODO: Fill out
+} Dem_PreDebounceCounterBasedType;
+
+typedef struct {
+ // TODO: Fill out
+} Dem_PreDebounceFrequencyBasedType;
+
+typedef struct {
+ // TODO: Fill out
+} Dem_PreDebounceTimeBasedType;
+
+typedef struct {
+ Dem_PreDebounceNameType PreDebounceName; // (1)
+ union {
+ const Dem_PreDebounceMonitorInternalType *PreDebounceMonitorInternal; // (0..1)
+ const Dem_PreDebounceCounterBasedType *PreDebounceCouterBased; // (0..1)
+ const Dem_PreDebounceFrequencyBasedType *PreDebounceFrequencyBased; // (0..1)
+ const Dem_PreDebounceTimeBasedType *PreDebounceTimeBased; // (0..1)
+ } PreDebounceAlgorithm;
+} Dem_PreDebounceAlgorithmClassType;
+
+// 10.2.14 DemEventClass
+typedef struct {
+ boolean ConsiderPtoStatus; // (1)
+ const Dem_DTCOriginType EventDestination[DEM_MAX_NR_OF_EVENT_DESTINATION+1];// (0..4)
+ uint8 EventPriority; // (1)
+ boolean FFPrestorageSupported; // (1)
+ boolean HealingAllowed; // (1)
+ Dem_OperationCycleIdType OperationCycleRef; // (1)
+// uint8 HealingCycleCounter; // (0..1) Optional
+// const Dem_EnableConditionType *EnableConditionRef; // (0..*) Optional
+// const Dem_OperationCycleTgtType *HealingCycleRef; // (0..1) Optional
+ const Dem_PreDebounceAlgorithmClassType *PreDebounceAlgorithmClass; // (0..255) (Only one supported)
+ const Dem_IndicatorAttributeType *IndicatorAttribute; // (0..255)
+// Dem_OEMSPecific
+
+} Dem_EventClassType;
+
+// 10.2.12 DemEventParameter
+typedef struct {
+ uint16 EventID; // (1)
+ Dem_EventKindType EventKind; // (1)
+ const Dem_EventClassType *EventClass; // (1)
+ const Dem_ExtendedDataClassType *ExtendedDataClassRef; // (0..1)
+ const Dem_FreezeFrameClassType *FreezeFrameClassRef; // (0..255)
+ const Dem_CallbackInitMforEType *CallbackInitMforE; // (0..1)
+ const Dem_CallbackEventStatusChangedType *CallbackEventStatusChanged;// (0..*)
+ const Dem_DTCClassType *DTCClass; // (0..1)
+ boolean Arc_EOL;
+} Dem_EventParameterType;
+
+// 10.2.19 DemGroupOfDTC
+typedef struct {
+ // TODO: Fill out
+} Dem_GroupOfDtcType;
+
+// 10.2.10 DemOemIdClass
+typedef struct {
+ uint8 OemID; // (Pre+Post)
+} Dem_OemIdClassType;
+
+// 10.2.9 DemConfigSet
+typedef struct {
+ const Dem_EventParameterType *EventParameter; // (0..65535)
+ const Dem_DTCClassType *DTCClass; // (1..16777214)
+ const Dem_GroupOfDtcType *GroupOfDtc; // (1.16777214)
+ const Dem_OemIdClassType *OemIdClass; // (0..*)
+} Dem_ConfigSetType;
+
+// 10.2.2 Dem
+typedef struct {
+ const Dem_ConfigSetType *ConfigSet; // (1)
+} Dem_ConfigType;
+
+
+/*
+ * Make the DEM_Config visible for others.
+ */
+extern const Dem_ConfigType DEM_Config;
+\r
\r
#endif /*DEM_LCFG_H_*/\r
#ifndef DEM_TYPES_H_\r
-#define DEM_TYPES_H_\r
-\r
+#define DEM_TYPES_H_
+#include "Std_Types.h"\r
+
+/*
+ * Dem_EventIdType
+ */
+typedef uint16 Dem_EventIdType;
+
+/*
+ * DemDTCKindType
+ */
+typedef uint8 Dem_DTCKindType;
+#define DEM_DTC_KIND_ALL_DTCS 0x01
+#define DEM_DTC_KIND_EMISSON_REL_DTCS 0x02
+
+/*
+ * DemDTCOriginType
+ */
+typedef uint8 Dem_DTCOriginType;
+#define DEM_DTC_ORIGIN_MIRROR_MEMORY 0x04
+#define DEM_DTC_ORIGIN_PERMANENT_MEMORY 0x03
+#define DEM_DTC_ORIGIN_PRIMARY_MEMORY 0x02
+#define DEM_DTC_ORIGIN_SECONDARY_MEMORY 0x01
+
+/*
+ * DemEventStatusExtendedType
+ */
+typedef uint8 Dem_EventStatusExtendedType;
+#define DEM_TEST_FAILED 0x01
+#define DEM_TEST_FAILED_THIS_OPERATION_CYCLE 0x02
+#define DEM_PENDING_DTC 0x04
+#define DEM_CONFIRMED_DTC 0x08
+#define DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR 0x10
+#define DEM_TEST_FAILED_SINCE_LAST_CLEAR 0x20
+#define DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE 0x40
+#define DEM_WARNING_INDICATOR_REQUESTED 0x80
+
+/*
+ * DemOperationCycleType
+ */
+typedef uint8 Dem_OperationCycleIdType; // TODO: Check type and values
+enum {
+ DEM_ACTIVE, // Started by DEM on Dem_PreInit and stopped on Dem_Shutdown
+
+ DEM_POWER, // Power ON/OFF Cycle
+ DEM_IGNITION, // Ignition ON/OF Cycle
+ DEM_WARMUP, // OBD Warm up Cycle
+ DEM_OBD_DCY, // OBD Driving Cycle
+
+ DEM_OPERATION_CYCLE_ID_ENDMARK
+};
+
+/*
+ * Dem_OperationCycleStateType
+ */
+typedef uint8 Dem_OperationCycleStateType;
+#define DEM_CYCLE_STATE_START 1
+#define DEM_CYCLE_STATE_END 2
+
+/*
+ * DemFreezeFrameKindType
+ */
+typedef uint8 Dem_FreezeFrameKindType; // TODO: Check type and values
+#define DEM_FREEZE_FRAME_NON_OBD 0x01
+#define DEM_FREEZE_FRAME_OBD 0x02
+
+/*
+ * DemEventKindType
+ */
+typedef uint8 Dem_EventKindType; // TODO: Check type and values
+#define DEM_EVENT_KIND_BSW 0x01
+#define DEM_EVENT_KIND_SWC 0x02
+
+/*
+ * Dem_EventStatusType
+ */
+typedef uint8 Dem_EventStatusType;
+#define DEM_EVENT_STATUS_PASSED 0
+#define DEM_EVENT_STATUS_FAILED 1
+#define DEM_EVENT_STATUS_PREPASSED 2
+#define DEM_EVENT_STATUS_PREFAILED 3
+
+/*
+ * Dem_DTCType
+ */
+typedef uint32 Dem_DTCType;
+
+/*
+ * Dem_InitMonitorKindType
+ */
+typedef uint8 Dem_InitMonitorKindType;
+#define DEM_INIT_MONITOR_CLEAR 1
+#define DEM_INIT_MONITOR_RESTART 2
+
+/*
+ * Dem_IndicatorStatusType
+ */
+typedef uint8 Dem_IndicatorStatusType;
+#define DEM_INDICATOR_OFF 0
+#define DEM_INDICATOR_CONTINUOUS 1
+#define DEM_INDICATOR_BLINKING 2
+#define DEM_INDICATOR_BLINK_CONT 3
+
+/*
+ * Dem_FaultDetectionCpunterType
+ */
+typedef sint8 Dem_FaultDetectionCounterType;
+
+/*
+ * Dem_PreDebounceNameType
+ */
+typedef uint8 Dem_PreDebounceNameType;
+enum {
+ DEM_NO_PRE_DEBOUNCE,
+ DEM_PRE_DEBOUNCE_COUNTER_BASED,
+ DEM_PRE_DEBOUNCE_FREQUENCY_BASED,
+ DEM_PRE_DEBOUNCE_TIME_BASED
+};
+
+
#endif /*DEM_TYPES_H_*/\r
#include <assert.h>\r
#include "Trace.h"\r
#include "Com.h"\r
-#include "Adc.h"\r
#include "pwm_node2_helpers.h"
\r
void OsIdle( void ) {\r
Com_MainFunctionTx();\r
Com_MainFunctionRx();\r
\r
- can_node_receive();\r
+ pwm_node2_receive();\r
}\r
\r
/*\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Adc ADC Driver
+ * @{ */
+
+/** @file Adc.h
+ * API and type definitions for ADC Driver.
+ */
+
#ifndef ADC_H_\r
#define ADC_H_\r
\r
#define ADC_SW_MINOR_VERSION 0
#define ADC_SW_PATCH_VERSION 0
\r
-/* Std-type */\r
+/** Group status. */
typedef enum\r
{\r
ADC_IDLE,\r
}Adc_StatusType;\r
\r
\r
-/* Det error that the adc can produce. */\r
+/* DET errors that the ADC can produce. */
typedef enum\r
{\r
ADC_E_UNINIT = 0x0A,\r
ADC_E_BUFFER_UNINIT = 0x19\r
}Adc_DetErrorType;\r
\r
-/* API service ID's */\r
+/** API service ID's */
typedef enum\r
{\r
ADC_INIT_ID = 0x00,\r
* Std-types
*
*/
+/** Access mode to group conversion results (Not supported). */
typedef enum
{
ADC_ACCESS_MODE_SINGLE,
ADC_ACCESS_MODE_STREAMING
}Adc_GroupAccessModeType;
+/** Group trigger source (Not supported). */
typedef enum
{
ADC_TRIGG_SRC_HW,
ADC_TRIGG_SRC_SW,
}Adc_TriggerSourceType;
-
+/** HW trigger edge (Not supported). */
typedef enum
{
ADC_NO_HW_TRIG,
ADC_HW_TRIG_RISING_EDGE,
}Adc_HwTriggerSignalType;
+/** Stream buffer type (Not supported). */
typedef enum
{
ADC_NO_STREAMING,
#include "Adc_Cfg.h"
\r
-/* Function interface. */\r
+/* Function interface. */
+/** Initializes the ADC hardware units and driver. */
Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr);\r
-#if (ADC_DEINIT_API == STD_ON)\r
+#if (ADC_DEINIT_API == STD_ON)
+/** Returns all ADC HW Units to a state comparable to their power on reset state. */
Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr);\r
-#endif\r
+#endif
+/** Sets up the result buffer for a group. */
Std_ReturnType Adc_SetupResultBuffer (Adc_GroupType group, Adc_ValueGroupType *bufferPtr);\r
-#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)
+/** Starts the conversion of all channels of the requested ADC Channel group. */
void Adc_StartGroupConversion (Adc_GroupType group);\r
//void Adc_StopGroupConversion (Adc_GroupType group);\r
#endif\r
-#if (ADC_READ_GROUP_API == STD_ON)\r
+#if (ADC_READ_GROUP_API == STD_ON)
+/** Reads results from last conversion into buffer */
Std_ReturnType Adc_ReadGroup (Adc_GroupType group, Adc_ValueGroupType *dataBufferPtr);\r
#endif\r
-#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
-void Adc_EnableGroupNotification (Adc_GroupType group);\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)
+/** Enables the notification mechanism for the requested ADC Channel group. */
+void Adc_EnableGroupNotification (Adc_GroupType group);
+/** Disables the notification mechanism for the requested ADC Channel group. */
void Adc_DisableGroupNotification (Adc_GroupType group);\r
-#endif\r
+#endif
+/** Returns the conversion status of the requested ADC Channel group. */
Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group);\r
\r
-#endif /*ADC_H_*/\r
+#endif /*ADC_H_*/
+
+/** @} */
+
// Init transition for current mode\r
#define CAN_E_TRANSITION 0x06\r
\r
-#define CAN_E_TIMEOUT 0x10 // Should be defined by DEM\r
-\r
\r
#include "Std_Types.h"\r
#include "CanIf_Types.h"\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup CanIf CAN Interface
+ * @{ */
-
-
-
-
-
+/** @file CanIf_Types.h
+ * Definitions of configuration parameters for CAN Interface.
+ */
#ifndef CANIF_TYPES_H_
#define CANIF_TYPES_H_
#include "ComStack_Types.h"
// API service with wrong parameter
+/** @name Error Codes */
+//@{
#define CANIF_E_PARAM_CANID 10
#define CANIF_E_PARAM_DLC 11
#define CANIF_E_PARAM_HRH 12
#define CANIF_TRCV_E_TRCV_NOT_NORMAL 70
#define CANIF_E_INVALID_TXPDUID 80
#define CANIF_E_INVALID_RXPDUID 90
+//@}
typedef enum {
- // UNINIT mode. Default mode of the CAN driver and all
- // CAN controllers connected to one CAN network after
- // power on.
+ /** UNINIT mode. Default mode of the CAN driver and all
+ * CAN controllers connected to one CAN network after
+ * power on. */
CANIF_CS_UNINIT = 0,
- // STOPPED mode. At least one of all CAN controllers
- // connected to one CAN network are halted and does
- // not operate on the bus.
+ /** STOPPED mode. At least one of all CAN controllers
+ * connected to one CAN network are halted and does
+ * not operate on the bus. */
CANIF_CS_STOPPED,
- // STARTED mode. All CAN controllers connected to
- // one CAN network are started by the CAN driver and
- // in full-operational mode.
+ /** STARTED mode. All CAN controllers connected to
+ * one CAN network are started by the CAN driver and
+ * in full-operational mode. */
CANIF_CS_STARTED,
- // SLEEP mode. At least one of all CAN controllers
- // connected to one CAN network are set into the
- // SLEEP mode and can be woken up by request of the
- // CAN driver or by a network event (must be supported
- // by CAN hardware)
+ /** SLEEP mode. At least one of all CAN controllers
+ * connected to one CAN network are set into the
+ * SLEEP mode and can be woken up by request of the
+ * CAN driver or by a network event (must be supported
+ * by CAN hardware) */
CANIF_CS_SLEEP,
} CanIf_ControllerModeType;
-// Status of the PDU channel group. Current mode of the channel defines its
-// transmit or receive activity. Communication direction (transmission and/or
-// reception) of the channel can be controlled separately or together by upper
-// layers.
+/** Status of the PDU channel group. Current mode of the channel defines its
+ * transmit or receive activity. Communication direction (transmission and/or
+ * reception) of the channel can be controlled separately or together by upper
+ * layers. */
typedef enum {
- // Channel shall be set to the offline mode
- // => no transmission and reception
+ /** Channel shall be set to the offline mode
+ * => no transmission and reception */
CANIF_SET_OFFLINE = 0,
- // Receive path of the corresponding channel
- // shall be disabled
+ /** Receive path of the corresponding channel
+ * shall be disabled */
CANIF_SET_RX_OFFLINE,
- // Receive path of the corresponding channel
- // shall be enabled
+ /** Receive path of the corresponding channel
+ * shall be enabled */
CANIF_SET_RX_ONLINE,
- // Transmit path of the corresponding channel
- // shall be disabled
+ /** Transmit path of the corresponding channel
+ * shall be disabled */
CANIF_SET_TX_OFFLINE,
- // Transmit path of the corresponding channel
- // shall be enabled
+ /** Transmit path of the corresponding channel
+ * shall be enabled */
CANIF_SET_TX_ONLINE,
- // Channel shall be set to online mode
- // => full operation mode
+ /** Channel shall be set to online mode
+ * => full operation mode */
CANIF_SET_ONLINE,
- // Transmit path of the corresponding channel
- // shall be set to the offline active mode
- // => notifications are processed but transmit
- // requests are blocked.
+ /** Transmit path of the corresponding channel
+ * shall be set to the offline active mode
+ * => notifications are processed but transmit
+ * requests are blocked. */
CANIF_SET_TX_OFFLINE_ACTIVE,
} CanIf_ChannelSetModeType;
typedef enum {
- // Channel is in the offline mode ==> no transmission or reception
+ /** Channel is in the offline mode ==> no transmission or reception */
CANIF_GET_OFFLINE = 0,
- // Receive path of the corresponding channel is enabled and
- // transmit path is disabled
+ /** Receive path of the corresponding channel is enabled and
+ * transmit path is disabled */
CANIF_GET_RX_ONLINE,
- // Transmit path of the corresponding channel is enabled and
- // receive path is disabled
+ /** Transmit path of the corresponding channel is enabled and
+ * receive path is disabled */
CANIF_GET_TX_ONLINE,
- // Channel is in the online mode ==> full operation mode
+ /** Channel is in the online mode ==> full operation mode */
CANIF_GET_ONLINE,
- // Transmit path of the corresponding channel is in
- // the offline mode ==> transmit notifications are processed but
- // transmit requests are blocked. The receiver path is disabled.
+ /** Transmit path of the corresponding channel is in
+ * the offline mode ==> transmit notifications are processed but
+ * transmit requests are blocked. The receiver path is disabled. */
CANIF_GET_OFFLINE_ACTIVE,
- // Transmit path of the corresponding channel is in the offline
- // active mode ==> transmit notifications are processed but transmit
- // requests are blocked. The receive path is enabled.
+ /** Transmit path of the corresponding channel is in the offline
+ * active mode ==> transmit notifications are processed but transmit
+ * requests are blocked. The receive path is enabled. */
CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE
} CanIf_ChannelGetModeType;
typedef enum {
- // No transmit or receive event occurred for
- // the requested L-PDU.
+ /** No transmit or receive event occurred for
+ * the requested L-PDU. */
CANIF_NO_NOTIFICATION = 0,
- // The requested Rx/Tx CAN L-PDU was
- // successfully transmitted or received.
+ /** The requested Rx/Tx CAN L-PDU was
+ * successfully transmitted or received. */
CANIF_TX_RX_NOTIFICATION,
} CanIf_NotifStatusType;
typedef enum {
- // Transceiver mode NORMAL
+ /** Transceiver mode NORMAL */
CANIF_TRCV_MODE_NORMAL = 0,
- // Transceiver mode STANDBY
+ /** Transceiver mode STANDBY */
CANIF_TRCV_MODE_STANDBY,
- //Transceiver mode SLEEP
+ /** Transceiver mode SLEEP */
CANIF_TRCV_MODE_SLEEP
} CanIf_TransceiverModeType;
typedef enum {
- // Due to an error wake up reason was not detected.
- // This value may only be reported when error was
- // reported to DEM before.
+ /** Due to an error wake up reason was not detected.
+ * This value may only be reported when error was
+ * reported to DEM before. */
CANIF_TRCV_WU_ERROR = 0,
- // The transceiver does not support any information
- // for the wakeup reason.
+ /** The transceiver does not support any information
+ * for the wakeup reason. */
CANIF_TRCV_WU_NOT_SUPPORTED,
- // The transceiver has detected, that the network has
- // caused the wake up of the ECU
+ /** The transceiver has detected, that the network has
+ * caused the wake up of the ECU */
CANIF_TRCV_WU_BY_BUS,
- // The transceiver detected, that the network has woken
- // the ECU via a request to NORMAL mode
+ /** The transceiver detected, that the network has woken
+ * the ECU via a request to NORMAL mode */
CANIF_TRCV_WU_INTERNALLY,
- // The transceiver has detected, that the "wake up"
- // is due to an ECU reset
+ /** The transceiver has detected, that the "wake up"
+ * is due to an ECU reset */
CANIF_TRCV_WU_RESET,
- // The transceiver has detected, that the "wake up"
- // is due to an ECU reset after power on.
+ /** The transceiver has detected, that the "wake up"
+ * is due to an ECU reset after power on. */
CANIF_TRCV_WU_POWER_ON
} CanIf_TrcvWakeupReasonType;
typedef enum {
- // The notification for wakeup events is enabled
- // on the addressed network.
+ /** The notification for wakeup events is enabled
+ * on the addressed network. */
CANIF_TRCV_WU_ENABLE = 0,
- // The notification for wakeup events is disabled
- // on the addressed network.
+ /** The notification for wakeup events is disabled
+ * on the addressed network. */
CANIF_TRCV_WU_DISABLE,
- // A stored wakeup event is cleared on the addressed network
+ /** A stored wakeup event is cleared on the addressed network */
CANIF_TRCV_WU_CLEAR
} CanIf_TrcvWakeupModeType;
#endif /*CANIF_TYPES_H_*/
+/** @} */
+/** @addtogroup Com COM module
+ * @{ */
-
-
+/** @file Com_Types.h
+ * Definitions of configuration types and parameters for the COM module.
+ */
#ifndef COM_TYPES_H_\r
type == SINT16 ? sizeof(sint16) : \\r
type == SINT32 ? sizeof(sint32) : sizeof(boolean)) \\r
\r
-\r
-typedef struct {\r
- ComFilterAlgorithm_type ComFilterAlgorithm;\r
- uint32 ComFilterMask;\r
- uint32 ComFilterMax;\r
- uint32 ComFilterMin;\r
+/** Filter configuration type.
+ * NOT SUPPORTED
+ */
+typedef struct {
+ /** The algorithm that this filter uses. */
+ ComFilterAlgorithm_type ComFilterAlgorithm;
+ /** Filter mask. */
+ uint32 ComFilterMask;
+ /** Max value for filter. */
+ uint32 ComFilterMax;
+ /** Min value for filter. */
+ uint32 ComFilterMin;
+ /** Offset for filter. */
uint32 ComFilterOffset;\r
uint32 ComFilterPeriodFactor;\r
uint32 ComFilterX;\r
-\r
-\r
uint32 ComFilterArcN;\r
uint32 ComFilterArcNewValue;\r
uint32 ComFilterArcOldValue;\r
\r
} ComFilter_type;\r
\r
-\r
+/** Configuration structure for group signals */
typedef struct {\r
- /* Starting position (bit) of the signal within the IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Range 0 to 63.\r
+ /** Starting position (bit) of the signal within the IPDU.
+ * Range 0 to 63.
*/\r
const uint8 ComBitPosition;\r
\r
- /* The size of the signal in bits.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Range 0 to 64.\r
+ /** The size of the signal in bits.
+ * Range 0 to 64.
*/\r
const uint8 ComBitSize;\r
\r
- /* Identifier for the signal.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Should be the same value as the index in the COM signal array.\r
+ /** Identifier for the signal.
+ * Should be the same value as the index in the COM signal array.
*/\r
const uint8 ComHandleId;\r
\r
- /* Callback function used when an invalid signal is received.\r
- *\r
- * Context:\r
- * - Receive.\r
- * - Not required.\r
- */\r
- // ComInvalidNotification;\r
-\r
- /*\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.\r
- */\r
- //uint8 ComSignalDataInvalidValue;\r
-\r
- /* Defines the endianess of the signal's network representation.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- */\r
+ /** Defines the endianess of the signal's network representation. */
const ComSignalEndianess_type ComSignalEndianess;\r
\r
- /*\r
- * Value used to initialized this signal.\r
- *\r
- * Context:\r
- * - Send\r
- * - Required\r
- */\r
+ /** Value used to initialize this signal. */
const uint32 ComSignalInitValue;\r
\r
- /* The number of bytes if the signal has type UINT8_N;\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required if type of signal is UINT8_N\r
- *\r
- * Comment: Range 1 to 8.\r
+ /** The number of bytes if the signal has type UINT8_N;
+ * Range 1 to 8.
*/\r
const uint8 ComSignalLength;\r
\r
- /* Defines the type of the signal\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- */\r
+ /** Defines the type of the signal. */
const Com_SignalType ComSignalType;\r
\r
\r
- /* Filter for this signal\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required.\r
+ /** Filter for this signal.
+ * NOT SUPPORTED
*/\r
const ComFilter_type ComFilter;\r
\r
/* Pointer to the shadow buffer of the signal group that this group signal is contained in.\r
*\r
- * Comment: This is initialized by Com_Init() and should not be configured.\r
+ * This is initialized by Com_Init() and should not be configured.
*/\r
//void *Com_Arc_ShadowBuffer;\r
-\r
+
+ /* Callback function used when an invalid signal is received. */
+ // ComInvalidNotification;
+ //uint8 ComSignalDataInvalidValue;
\r
/* IPDU id of the IPDU that this signal belongs to.\r
*\r
- * Comment: This is initialized by Com_Init() and should not be configured.\r
+ * This is initialized by Com_Init() and should not be configured.
*/\r
\r
//const uint8 ComIPduHandleId;\r
//const uint8 ComSignalUpdated;\r
-\r
+
+ /** Marks the end of list for the configuration array. */
const uint8 Com_Arc_EOL;\r
} ComGroupSignal_type;\r
-\r
+
+
+/** Configuration structure for signals and signal groups. */
typedef struct {\r
\r
- /* Starting position (bit) of the signal within the IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Range 0 to 63.
+ /** Starting position (bit) of the signal within the IPDU.
+ * Range 0 to 63.
*/\r
const uint8 ComBitPosition;\r
\r
- /* The size of the signal in bits.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Range 0 to 64.
+ /** The size of the signal in bits.
+ * Range 0 to 63.
*/\r
const uint8 ComBitSize;\r
\r
-\r
- /* Action to be taken if an invalid signal is received.\r
- *\r
- * Context:\r
- * -
- */\r
- // ComDataInvalidAction;\r
-\r
- /* Notification function for error notification.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Not required.\r
- *
- */\r
+ /** Notification function for error notification. */
void (*ComErrorNotification) (void);\r
\r
- /* First timeout period for deadline monitoring.\r
- *\r
- * Context:\r
- * - Receive\r
- * - Not required.
- */\r
+ /** First timeout period for deadline monitoring. */
const uint32 ComFirstTimeoutFactor;\r
\r
- /* Identifier for the signal.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment: Should be the same value as the index in the COM signal array.
+ /** Identifier for the signal.
+ * Should be the same value as the index in the COM signal array.
*/\r
const uint8 ComHandleId;\r
\r
- /* Callback function used when an invalid signal is received.\r
- *\r
- * Context:\r
- * - Receive.\r
- * - Not required.
- */\r
- // ComInvalidNotification;\r
-\r
- /* Tx and Rx notification function.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.
- */\r
+ /** Tx and Rx notification function. */
void (*ComNotification) (void);\r
\r
- /* Action to be performed when a reception timeout occurs.\r
- *\r
- * Context:\r
- * - Receive.\r
- * - Required.
- */\r
+ /** Action to be performed when a reception timeout occurs. */
const ComRxDataTimeoutAction_type ComRxDataTimeoutAction;\r
\r
- /*\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.
- */\r
- //uint8 ComSignalDataInvalidValue;\r
-\r
- /* Defines the endianess of the signal's network representation.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.
- */\r
+ /** Defines the endianess of the signal's network representation. */
const ComSignalEndianess_type ComSignalEndianess;\r
\r
- /*\r
- * Value used to initialized this signal.\r
- *\r
- * Context:\r
- * - Send\r
- * - Required
- */\r
+ /** Value used to initialized this signal. */
const uint32 ComSignalInitValue;\r
\r
- /* The number of bytes if the signal has type UINT8_N;\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required if type of signal is UINT8_N\r
- *\r
- * Comment: Range 1 to 8.
+ /** The number of bytes if the signal has type UINT8_N;
+ * Range 1 to 8.
*/\r
const uint8 ComSignalLength;\r
\r
- /* Defines the type of the signal\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.
- */\r
+ /** Defines the type of the signal. */
const Com_SignalType ComSignalType;\r
\r
- /* Timeout period for deadline monitoring.\r
- *\r
- * Context:\r
- * - Receive\r
- * - Not required.\r
- */\r
- //const uint32 Com_Arc_DeadlineCounter;\r
+ /** Timeout period for deadline monitoring. */
const uint32 ComTimeoutFactor;\r
\r
- /* Timeout notification function\r
- *\r
- * Context:\r
- * - Receive and send\r
- * - Not required.\r
- */\r
+ /** Timeout notification function. */
void (*ComTimeoutNotification) (void);\r
\r
const ComTransferProperty_type ComTransferProperty;\r
\r
- /*\r
- * The bit position in the PDU for this signals update bit.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.\r
- *\r
- * Comment: Range 0 to 63. If update bit is used for this signal, then the corresponding parameter ComSignalArcUseUpdateBit\r
- * needs to be set to one.
+ /** The bit position in the PDU for this signal's update bit.
+ * Range 0 to 63.
+ * Only applicable if an update bit is used. NULL otherwise.
*/\r
- const uint8 ComUpdateBitPosition;\r
+ const uint8 ComUpdateBitPosition;
+
+ /** Marks if this signal uses an update bit.
+ * Should be set to one if an update bit is used.
+ */
const uint8 ComSignalArcUseUpdateBit;\r
\r
- /* Filter for this signal\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required.
+ /** Filter for this signal.
+ * NOT SUPPORTED.
*/\r
const ComFilter_type ComFilter;\r
\r
-\r
- /**** SIGNAL GROUP DATA ****/\r
- const uint8 Com_Arc_IsSignalGroup;\r
+ /** Marks if this signal is a signal group.
+ * Should be set to 1 if the signal is a signal group.
+ */
+ const uint8 Com_Arc_IsSignalGroup;
+
+ /** Array of group signals.
+ * Only applicable if this signal is a signal group.
+ */
const ComGroupSignal_type *ComGroupSignal[COM_MAX_NR_SIGNALS_PER_SIGNAL_GROUP];\r
+
+
//void *Com_Arc_ShadowBuffer;\r
//void *Com_Arc_IPduDataPtr;\r
\r
-\r
/* Pointer to the data storage of this signals IPDU.\r
- *\r
- * Comment: This is initialized by Com_Init() and should not be configured.
+ * This is initialized by Com_Init() and should not be configured.
*/\r
//const void *ComIPduDataPtr;\r
\r
/* IPDU id of the IPDU that this signal belongs to.\r
- *\r
- * Comment: This is initialized by Com_Init() and should not be configured.\r
+ * This is initialized by Com_Init() and should not be configured.
*/\r
\r
//const uint8 ComIPduHandleId;\r
//const uint8 ComSignalUpdated;\r
-\r
-\r
+
+ /* Callback function used when an invalid signal is received.
+ */
+ // ComInvalidNotification;
+
+ //uint8 ComSignalDataInvalidValue;
+
+ /* Action to be taken if an invalid signal is received.
+ */
+ // ComDataInvalidAction;
+
+ /** Marks the end of list for the signal configuration array. */
const uint8 Com_Arc_EOL;\r
} ComSignal_type;\r
+
+
\r
+/** Configuration structure for Tx-mode for I-PDUs. */
+typedef struct {
\r
-typedef struct {\r
- /* Transmission mode for this IPdu.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required.
- */\r
+ /** Transmission mode for this IPdu. */
const ComTxModeMode_type ComTxModeMode;\r
\r
- /* Defines the number of times this IPdu will be sent in each IPdu cycle.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required for transmission modes DIRECT/N-times and MIXED.\r
- *\r
- * Comment: Should be set to 0 for DIRECT transmission mode and >0 for DIRECT/N-times mode.
+ /** Defines the number of times this IPdu will be sent in each IPdu cycle.
+ * Should be set to 0 for DIRECT transmission mode and >0 for DIRECT/N-times mode.
*/\r
const uint8 ComTxModeNumberOfRepetitions;\r
\r
- /* Defines the period of the transmissions in DIRECT/N-times and MIXED\r
- * transmission modes.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required for DIRECT/N-times and MIXED transmission modes.
- */\r
+ /** Defines the period of the transmissions in DIRECT/N-times and MIXED transmission modes. */
const uint32 ComTxModeRepetitionPeriodFactor;\r
\r
- /* Time before first transmission of this IPDU. (i.e. between the ipdu group start\r
- * and this IPDU is sent for the first time.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required for all transmission modes except NONE.
- */\r
+ /** Time before first transmission of this IPDU. (i.e. between the ipdu group start and this IPDU is sent for the first time. */
const uint32 ComTxModeTimeOffsetFactor;\r
\r
- /* Period of cyclic transmission.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required for CYCLIC and MIXED transmission mode.
- */\r
+ /** Period of cyclic transmission. */
const uint32 ComTxModeTimePeriodFactor;\r
} ComTxMode_type;\r
\r
-\r
+/** Extra configuration structure for Tx I-PDUs. */
typedef struct {\r
\r
- /* Minimum delay between successive transmissions of the IPdu.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Not required.
- */\r
+ /** Minimum delay between successive transmissions of the IPdu. */
const uint32 ComTxIPduMinimumDelayFactor;\r
\r
- /* COM will fill unused areas within an IPdu with this bit patter.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Required.
+ /** COM will fill unused areas within an IPdu with this bit patter.
*/\r
const uint8 ComTxIPduUnusedAreasDefault;\r
\r
- /* Transmission modes for this IPdu.\r
- *\r
- * Context:\r
- * - Send.\r
- * - Not required.\r
- *\r
- * Comment: TMS is not implemented so only one static transmission\r
- * mode is supported.
+ /** Transmission modes for the IPdu.
+ * TMS is not implemented so only one static transmission mode is supported.
*/\r
const ComTxMode_type ComTxModeTrue;\r
+
//ComTxMode_type ComTxModeFalse;\r
+} ComTxIPdu_type;
+
\r
-} ComTxIPdu_type;\r
-\r
-/*\r
-typedef struct {\r
- uint8 ComTxIPduNumberOfRepetitionsLeft;\r
- uint32 ComTxModeRepetitionPeriodTimer;\r
- uint32 ComTxIPduMinimumDelayTimer;\r
- uint32 ComTxModeTimePeriodTimer;\r
-} ComTxIPduTimer_type;\r
-*/\r
-\r
+/** Configuration structure for I-PDU groups */
typedef struct ComIPduGroup_type {\r
- // ID of this group. 0-31.\r
+ /** ID of this group.
+ * Range 0 to 31.
+ */
const uint8 ComIPduGroupHandleId;\r
\r
// reference to the group that this group possibly belongs to.\r
//struct ComIPduGroup_type *ComIPduGroupRef;\r
-\r
+
+ /** Marks the end of list for the I-PDU group configuration array. */
const uint8 Com_Arc_EOL;\r
} ComIPduGroup_type;\r
\r
-\r
+
+/** Configuration structure for an I-PDU. */
typedef struct {\r
\r
- /* Callout function of this IPDU.\r
+ /** Callout function of this IPDU.
* The callout function is an optional function used both on sender and receiver side.\r
* If configured, it determines whether an IPdu is considered for further processing. If\r
* the callout return false the IPdu will not be received/sent.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.
*/\r
boolean (*ComIPduCallout)(PduIdType PduId, const uint8 *IPduData);\r
\r
\r
- /* The ID of this IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.\r
- *\r
- * Comment:
- */\r
+ /** The ID of this IPDU. */
const uint8 ComIPduRxHandleId;\r
\r
- /* Signal processing mode for this IPDU.\r
- *\r
- * Context:\r
- * - Receive.\r
- * - Required.
- */\r
+ /** Signal processing mode for this IPDU. */
const Com_IPduSignalProcessingMode ComIPduSignalProcessing;\r
\r
- /* Size of the IPDU in bytes. 0-8 for CAN and LIN and 0-256 for FlexRay.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.
+ /** Size of the IPDU in bytes.
+ * Range 0-8 for CAN and LIN and 0-256 for FlexRay.
*/\r
const uint8 ComIPduSize;\r
\r
- /* The direction of the IPDU. Receive or Send.\r
- *\r
- * Context:\r
- * - Receive or send.\r
- * - Required.
- */\r
+ /** The direction of the IPDU. Receive or Send. */
const Com_IPduDirection ComIPduDirection;\r
\r
- /* Reference to the IPDU group that this IPDU belongs to.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Required.
- */\r
+ /** Reference to the IPDU group that this IPDU belongs to. */
const uint8 ComIPduGroupRef;\r
\r
- /* Reference to global PDU structure. ???\r
- *\r
- * No global PDU structure defined so this variable is left out.
- */\r
- // PduIdRef\r
-\r
- /* Container of transmission related parameters.\r
- *\r
- * Context:\r
- * - Send\r
- * - Required.
- */\r
+ /** Container of transmission related parameters. */
const ComTxIPdu_type ComTxIPdu;\r
\r
- /* Transmission related timers and parameters.\r
- *\r
- * Context:\r
- * - Send\r
- * - Not required.\r
- * - Not part of the AUTOSAR standard.\r
- *\r
- * Comment: These are internal variables and should not be configured.
- */\r
- //ComTxIPduTimer_type Com_Arc_TxIPduTimers;\r
-\r
- /* Pointer to data storage of this IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- *\r
- * Comment: this memory will be initialized dynamically in Com_Init();
+ /** References to all signal groups contained in this IPDU.
+ * It probably makes little sense not to define at least one signal or signal group for each IPDU.
*/\r
- //void *ComIPduDataPtr;\r
-\r
- /* References to all signals contained in this IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.\r
- *\r
- * Comment: It probably makes little sense not to define at least one signal for each IPDU.\r
- */\r
- //const uint8 Com_Arc_NIPduSignalGroupRef;\r
const ComSignal_type *ComIPduSignalGroupRef[COM_MAX_NR_SIGNALS_PER_IPDU];\r
\r
\r
- /* References to all signals contained in this IPDU.\r
- *\r
- * Context:\r
- * - Send and receive.\r
- * - Not required.\r
- *\r
- * Comment: It probably makes little sense not to define at least one signal for each IPDU.\r
+ /** References to all signals contained in this IPDU.
+ * It probably makes little sense not to define at least one signal or signal group for each IPDU.
*/\r
//const uint8 NComIPduSignalRef;\r
const ComSignal_type *ComIPduSignalRef[COM_MAX_NR_SIGNALS_PER_IPDU];\r
* The following two variables are used to control the per I-PDU based Rx/Tx-deadline monitoring.\r
*/\r
//const uint32 Com_Arc_DeadlineCounter;\r
- //const uint32 Com_Arc_TimeoutFactor;\r
+ //const uint32 Com_Arc_TimeoutFactor;
+
+ /* Transmission related timers and parameters.
+ * These are internal variables and should not be configured.
+ */
+ //ComTxIPduTimer_type Com_Arc_TxIPduTimers;
+
+ /* Pointer to data storage of this IPDU.
+ */
+ //void *ComIPduDataPtr;
\r
+
+ /** Marks the end of list for this configuration array. */
const uint8 Com_Arc_EOL;\r
\r
} ComIPdu_type;\r
\r
\r
-// Contains configuration specific configuration parameters. Exists once per configuration.\r
+/** Top-level configuration container for COM. Exists once per configuration. */
typedef struct {\r
\r
- // The ID of this configuration. This is returned by Com_GetConfigurationId();\r
+ /** The ID of this configuration. This is returned by Com_GetConfigurationId(); */
const uint8 ComConfigurationId;\r
\r
/*\r
ComGwMapping_type ComGwMapping[];\r
*/\r
\r
- // IPDU definitions. At least one\r
+ /** IPDU definitions */
const ComIPdu_type *ComIPdu;\r
\r
//uint16 Com_Arc_NIPdu;\r
\r
- // IPDU group definitions\r
+ /** IPDU group definitions */
const ComIPduGroup_type *ComIPduGroup;\r
\r
- // Signal definitions\r
+ /** Signal definitions */
const ComSignal_type *ComSignal;\r
\r
// Signal group definitions\r
//ComSignalGroup_type *ComSignalGroup;\r
\r
- // Group signal definitions\r
+ /** Group signal definitions */
const ComGroupSignal_type *ComGroupSignal;\r
\r
} Com_ConfigType;\r
\r
-#endif /*COM_TYPES_H_*/\r
+#endif /*COM_TYPES_H_*/
+/** @} */
#ifndef DEM_H_\r
#define DEM_H_\r
-\r
-#include "Std_Types.h"\r
-#include "Dem_Types.h"\r
-#include "Dem_IntErrId.h"\r
-\r
-typedef uint16 Dem_EventIdType;\r
-typedef uint8 Dem_EventStatusType;\r
-\r
-void Dem_PreInit( void );\r
-void Dem_Init( void );\r
-Std_ReturnType Dem_ReportErrorStatus( Dem_EventIdType,Dem_EventStatusType);\r
-\r
-\r
+
+#define DEM_SW_MAJOR_VERSION 1
+#define DEM_SW_MINOR_VERSION 0
+#define DEM_SW_PATCH_VERSION 0
+#define DEM_AR_MAJOR_VERSION 3
+#define DEM_AR_MINOR_VERSION 0
+#define DEM_AR_PATCH_VERSION 1
+
+#include "Dem_Types.h"
+#include "Dem_Cfg.h"
+#include "Dem_Lcfg.h"\r
+#include "Dem_IntErrId.h"
+#include "Dem_IntEvtId.h"
+// #include "Rte_Dem.h"
+
+
+#if (DEM_DEV_ERROR_DETECT == STD_ON)
+// Error codes produced by this module
+#define DEM_E_CONFIG_PTR_INVALID 0x01
+#define DEM_E_PARAM_CONFIG 0x10
+#define DEM_E_PARAM_ADDRESS 0x11
+#define DEM_E_PARAM_DATA 0x12
+#define DEM_E_PARAM_LENGTH 0x13
+#define DEM_E_UNINIT 0x20
+#define DEM_E_NODATAAVAILABLE 0x30
+
+#define DEM_E_EVENT_STATUS_BUFF_FULL 0x40
+#define DEM_E_EXT_DATA_TO_BIG 0x41
+#define DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL 0x42
+#define DEM_E_PRI_MEM_EVENT_BUFF_FULL 0x43
+#define DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL 0x44
+
+#define DEM_E_NOT_IMPLEMENTED_YET 0xff
+
+// Service ID in this module
+#define DEM_PREINIT_ID 0x01
+#define DEM_INIT_ID 0x02
+#define DEM_SETEVENTSTATUS_ID 0x10
+#define DEM_RESETEVENTSTATUS_ID 0x11
+#define DEM_GETEVENTSTATUS_ID 0x12
+#define DEM_GETEVENTFAILED_ID 0x13
+#define DEM_GETEVENTTESTED_ID 0x14
+#define DEM_GETFAULTDETECTIONCOUNTER_ID 0x15
+#define DEM_SETOPERATIONCYCLESTATE_ID 0x16
+#define DEM_REPORTERRORSTATUS_ID 0x20
+
+#define DEM_UPDATE_EVENT_STATUS_ID 0x40
+#define DEM_MERGE_EVENT_STATUS_ID 0x41
+#define DEM_GET_EXTENDED_DATA_ID 0x42
+#define DEM_STORE_EXT_DATA_PRE_INIT_ID 0x43
+#define DEM_STORE_EVENT_PRI_MEM_ID 0x44
+#define DEM_STORE_EXT_DATA_PRI_MEM_ID 0x45
+
+#define DEM_GLOBAL_ID 0xff
+
+#endif
+
+
+/*
+ * Interface for upper layer modules (8.3.1)
+ */
+
+#if (DEM_VERSION_INFO_API == STD_ON)
+void Dem_GetVersionInfo(Std_VersionInfoType *versionInfo);
+#endif /* DEM_VERSION_INFO_API */
+
+/*
+ * Interface ECU State Manager <-> DEM (8.3.2)
+ */
+void Dem_PreInit( void );
+void Dem_Init( void );
+void Dem_Shutdown( void );
+
+
+/*
+ * Interface for basic software scheduler
+ */
+void Dem_MainFunction( void );
+
+
+/*
+ * Interface SW-Components via RTE <-> DEM (8.3.3)
+ */
+Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, uint8 eventStatus);
+Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId);
+Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended);
+Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed);
+Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested);
+Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter);
+Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType OperationCycleId, Dem_OperationCycleStateType CycleState);
+
+
+/*
+ * Interface BSW-Components <-> DEM (8.3.4)
+ */
+void Dem_ReportErrorStatus(Dem_EventIdType eventId ,uint8 eventStatus);
+
+
+/*
+ * Interface DCM <-> DEM (8.3.5)
+ */
+
+
+/*
+ * OBD-specific Interfaces (8.3.6)
+ */
+
#endif /*DEM_H_*/\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup EcuM ECU State Manager
+ * @{ */
-
-
-
-
-
+/** @file EcuM.h
+ * API and type definitions for ECU State Manager.
+ */
#ifndef ECUM_H_\r
#define ECUM_H_\r
#include "ComStack_Types.h"\r
#endif\r
\r
-// Error codes produced by this module\r
+/** @name Error Codes */
+//@{
#define ECUM_E_NOT_INITIATED (0x10)\r
#define ECUM_E_SERVICE_DISABLED (0x11)\r
#define ECUM_E_NULL_POINTER (0x12)\r
#define ECUM_E_MISMATCHED_RUN_RELEASE (0x15)\r
#define ECUM_E_STATE_PAR_OUT_OF_RANGE (0x16)\r
#define ECUM_E_UNKNOWN_WAKEUP_SOURCE (0x17)\r
-\r
-// Service ID in this module\r
+//@}
+
+/** @name Service id's */
+//@{
#define ECUM_GETSTATE_ID (0x07)\r
#define ECUM_SELECTAPPMODE_ID (0x0f)\r
#define ECUM_GETAPPMODE_ID (0x11)\r
#define ECUM_SELECT_BOOTARGET_ID (0x12)\r
#define ECUM_GET_BOOTARGET_ID (0x13)\r
#define ECUM_MAINFUNCTION_ID (0x18)\r
-\r
+
+/** Possible states */
typedef enum {\r
ECUM_STATE_APP_RUN = 0x32,\r
ECUM_STATE_SHUTDOWN = 0x40,\r
typedef uint8 EcuM_UserType;\r
\r
enum {\r
- // Internal reset of µC (bit 2)\r
- // The internal reset typically only resets the µC\r
- // core but not peripherals or memory\r
- // controllers. The exact behavior is hardware\r
- // specific.\r
- // This source may also indicate an unhandled\r
- // exception.\r
+ /** Internal reset of µC (bit 2).
+ * The internal reset typically only resets the µC
+ * core but not peripherals or memory
+ * controllers. The exact behavior is hardware
+ * specific.
+ * This source may also indicate an unhandled
+ * exception. */
ECUM_WKSOURCE_INTERNAL_RESET = 0x04,\r
\r
- // Reset by external watchdog (bit 4), if\r
- // detection supported by hardware\r
+ /** Reset by external watchdog (bit 4), if
+ * detection supported by hardware */
ECUM_WKSOURCE_EXTERNAL_WDG = 0x10,\r
\r
- // Reset by internal watchdog (bit 3)\r
+ /** Reset by internal watchdog (bit 3) */
ECUM_WKSOURCE_INTERNAL_WDG = 0x08,\r
\r
- // Power cycle (bit 0)\r
+ /** Power cycle (bit 0) */
ECUM_WKSOURCE_POWER = 0x01,\r
\r
- // ~0 to the power of 29\r
+ /** ~0 to the power of 29 */
ECUM_WKSOURCE_ALL_SOURCES = 0x3FFFFFFF,\r
\r
- // Hardware reset (bit 1).\r
- // If hardware cannot distinguish between a\r
- // power cycle and a reset reason, then this\r
- // shall be the default wakeup source\r
+ /** Hardware reset (bit 1).
+ * If hardware cannot distinguish between a
+ * power cycle and a reset reason, then this
+ * shall be the default wakeup source */
ECUM_WKSOURCE_RESET = 0x02,\r
};\r
\r
\r
typedef enum\r
{\r
- ECUM_WKSTATUS_NONE = 0, // No pending wakeup event was detected\r
- ECUM_WKSTATUS_PENDING = 1, // The wakeup event was detected but not yet validated\r
- ECUM_WKSTATUS_VALIDATED = 2, // The wakeup event is valid\r
- ECUM_WKSTATUS_EXPIRED = 3, // The wakeup event has not been validated and has expired therefore\r
+ ECUM_WKSTATUS_NONE = 0, /**< No pending wakeup event was detected */
+ ECUM_WKSTATUS_PENDING = 1, /**< The wakeup event was detected but not yet validated */
+ ECUM_WKSTATUS_VALIDATED = 2, /**< The wakeup event is valid */
+ ECUM_WKSTATUS_EXPIRED = 3, /**< The wakeup event has not been validated and has expired therefore */
} EcuM_WakeupStatusType;\r
\r
typedef enum\r
{\r
- ECUM_WWKACT_RUN = 0, // Initialization into RUN state\r
- ECUM_WKACT_TTII = 2, // Execute time triggered increased inoperation protocol and shutdown\r
- ECUM_WKACT_SHUTDOWN = 3, // Immediate shutdown\r
+ ECUM_WWKACT_RUN = 0, /**< Initialization into RUN state */
+ ECUM_WKACT_TTII = 2, /**< Execute time triggered increased inoperation protocol and shutdown */
+ ECUM_WKACT_SHUTDOWN = 3, /**< Immediate shutdown */
} EcuM_WakeupReactionType;\r
\r
typedef enum\r
{\r
- ECUM_BOOT_TARGET_APP = 0, // The Ecu will boot into the application\r
- ECUM_BOOT_TARGET_BOOTLOADER = 1, // The Ecu will boot into the bootloader\r
+ ECUM_BOOT_TARGET_APP = 0, /**< The Ecu will boot into the application */
+ ECUM_BOOT_TARGET_BOOTLOADER = 1, /**< The Ecu will boot into the bootloader */
} EcuM_BootTargetType;\r
void EcuM_AL_SwitchOff( void );\r
\r
#endif /*ECUM_H_*/\r
+/** @} */
#include "Std_Types.h"
#include "Det.h"
//#include "MemIf_Types.h"
-// TODO: not yet #include "Dem.h"
-
+#if defined(USE_DEM)
+#include "Dem.h"
+#endif
// SW ans Autosar spec versions
#define FLS_SW_MAJOR_VERSION 1
#define FLS_SW_MINOR_VERSION 0
// Write verification (compare) failed
#define FLS_E_VERIFY_WRITE_FAILED 0x08
-// These should be assigned by the DEM module
-#define FLS_E_ERASED_FAILED 0x09
-#define FLS_E_WRITE_FAILED 0x0A
-#define FLS_E_READ_FAILED 0x0B
-#define FLS_E_COMPARE_FAILED 0x0C
-#define FLS_E_UNEXPECTED_FLASH_ID 0x0D
-
// Service id's for fls functions
#define FLS_INIT_ID 0x00
#define FLS_ERASE_ID 0x01
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Gpt GPT Driver
+ * @{ */
-
-
-
-
-
+/** @file Gpt.h
+ * API and type definitions for GPT Driver.
+ */
#ifndef GPT_H_
#define GPT_H_
#include "Std_Types.h"
//#include "EcuM.h" mahi: What for ???
-/* ERROR CODES */
+/** @name Error Codes */
+//@{
#define GPT_E_UNINIT 0x0a
#define GPT_E_BUSY 0x0b
#define GPT_E_NOT_STARTED 0x0c
#define GPT_E_PARAM_VALUE 0x15
#define GPT_E_PARAM_MODE 0x1f
#define GPT_E_PARAM_CONFIG 0x0e // TODO: Not in spec. Find real value
+//@}
-/* SERVICE_ID's */
+/** @name Service id's */
+//@{
#define GPT_INIT_SERVICE_ID 0x01
#define GPT_DEINIT_SERVICE_ID 0x02
#define GPT_GETTIMEELAPSED_SERVICE_ID 0x03
#define GPT_DISABLEWAKEUP_SERVICE_ID 0x0a
#define GPT_ENABLEWAKEUP_SERVICE_ID 0x0b
#define GPT_CBK_CHECKWAKEUP_SERVICE_ID 0x0c
+//@}
+/** Channel id type */
typedef uint8_t Gpt_ChannelType;
+/** Channel time value type */
typedef uint32_t Gpt_ValueType;
+/** Channel behavior */
typedef enum
{
GPT_MODE_ONESHOT=0,
#endif
#endif /*GPT_H_*/
+/** @} */
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-#ifndef DEM_INTERRID_H_\r
-#define DEM_INTERRID_H_\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
-#endif /*DEM_INTERRID_H_*/\r
\r
-/* Added by Mattias Ekberg 2008-10-20 while implementing the PDU router. The value of PDUR_E_INSTANCE_LOST can\r
- be changed without affecting the PDU router.*/\r
-#define PDUR_E_INSTANCE_LOST 0\r
+/*\r
+ * ----------------------------------------------------------------------------\r
+ * NOTE: This file is a stub only. ECU software needs to provide a generated IO\r
+ * hardware abstraction module that overrides this file.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Lin LIN Driver
+ * @{ */
-
-
-
-
-
+/** @file Lin.h
+ * API and type definitions for LIN Driver.
+ */
#ifndef LIN_H_\r
#define LIN_H_\r
typedef struct {\r
} Lin_ConfigType;\r
\r
-/* Represents all valid protected Identifier used by Lin_SendHeader(). */\r
+/** Represents all valid protected Identifier used by Lin_SendHeader(). */
typedef uint8 Lin_FramePidType;\r
\r
-/* This type is used to specify the Checksum model to be used for the LIN Frame. */\r
+/** This type is used to specify the Checksum model to be used for the LIN Frame. */
typedef enum {\r
LIN_ENHANCED_CS,\r
LIN_CLASSIC_CS,\r
} Lin_FrameCsModelType;\r
\r
-// This type is used to specify whether the frame processor is required to transmit the\r
-// response part of the LIN frame.\r
+/** This type is used to specify whether the frame processor is required to transmit the
+ * response part of the LIN frame. */
typedef enum {\r
- // Response is generated from this (master) node\r
+ /** Response is generated from this (master) node */
LIN_MASTER_RESPONSE=0,\r
- // Response is generated from a remote slave node\r
+ /** Response is generated from a remote slave node */
LIN_SLAVE_RESPONSE,\r
- // Response is generated from one slave to another slave,\r
- // for the master the response will be anonymous, it does not\r
- // have to receive the response.\r
+ /** Response is generated from one slave to another slave,
+ * for the master the response will be anonymous, it does not
+ * have to receive the response. */
IN_SLAVE_TO_SLAVE,\r
\r
} Lin_FrameResponseType;\r
\r
-// This type is used to specify the number of SDU data bytes to copy.\r
+/** This type is used to specify the number of SDU data bytes to copy. */
typedef uint8 Lin_FrameDIType;\r
\r
-// This Type is used to provide PID, checksum model, data length and SDU pointer\r
-// from the LIN Interface to the LIN driver.\r
+/** This Type is used to provide PID, checksum model, data length and SDU pointer
+ * from the LIN Interface to the LIN driver. */
typedef struct {\r
Lin_FrameCsModelType Cs;\r
Lin_FramePidType Pid;\r
}Lin_DriverStatusType;\r
\r
typedef enum {\r
- // LIN frame operation return value.\r
- // Development or production error occurred\r
+ /** LIN frame operation return value.
+ * Development or production error occurred */
LIN_NOT_OK,\r
\r
- // LIN frame operation return value.\r
- // Successful transmission.\r
+ /** LIN frame operation return value.
+ * Successful transmission. */
LIN_TX_OK,\r
\r
- // LIN frame operation return value.\r
- // Ongoing transmission (Header or Response).\r
+ /** LIN frame operation return value.
+ * Ongoing transmission (Header or Response). */
LIN_TX_BUSY,\r
\r
- // LIN frame operation return value.\r
- // Erroneous header transmission such as:\r
- // - Mismatch between sent and read back data\r
- // - Identifier parity error or\r
- // - Physical bus error\r
+ /** LIN frame operation return value.
+ * Erroneous header transmission such as:
+ * - Mismatch between sent and read back data
+ * - Identifier parity error or
+ * - Physical bus error */
LIN_TX_HEADER_ERRORLIN,\r
\r
- // LIN frame operation return value.\r
- // Erroneous response transmission such as:\r
- // - Mismatch between sent and read back data\r
- // - Physical bus error\r
+ /** LIN frame operation return value.
+ * Erroneous response transmission such as:
+ * - Mismatch between sent and read back data
+ * - Physical bus error */
LIN_TX_ERROR,\r
\r
- // LIN frame operation return value.\r
- // Reception of correct response.\r
+ /** LIN frame operation return value.
+ * Reception of correct response. */
LIN_RX_OK,\r
\r
- // LIN frame operation return value. Ongoing reception: at\r
- // least one response byte has been received, but the\r
- // checksum byte has not been received.\r
+ /** LIN frame operation return value. Ongoing reception: at
+ * least one response byte has been received, but the
+ * checksum byte has not been received. */
LIN_RX_BUSY,\r
\r
- // LIN frame operation return value.\r
- // Erroneous response reception such as:\r
- // - Framing error\r
- // - Overrun error\r
- // - Checksum error or\r
- // - Short response\r
+ /** LIN frame operation return value.
+ * Erroneous response reception such as:
+ * - Framing error
+ * - Overrun error
+ * - Checksum error or
+ * - Short response */
LIN_RX_ERROR,\r
\r
\r
- // LIN frame operation return value.\r
- // No response byte has been received so far.\r
+ /** LIN frame operation return value.
+ * No response byte has been received so far. */
LIN_RX_NO_RESPONSE,\r
\r
- // LIN channel state return value.\r
- // LIN channel not initialized.\r
+ /** LIN channel state return value.
+ * LIN channel not initialized. */
LIN_CH_UNINIT,\r
\r
- // LIN channel state return value.\r
- // Normal operation; the related LIN channel is ready to\r
- // transmit next header. No data from previous frame\r
- // available (e.g. after initialization)\r
+ /** LIN channel state return value.
+ * Normal operation; the related LIN channel is ready to
+ * transmit next header. No data from previous frame
+ * available (e.g. after initialization) */
LIN_CH_OPERATIONAL,\r
\r
- // LIN channel state return value.\r
- // Sleep mode operation; in this mode wake-up detection\r
- // from slave nodes is enabled.\r
+ /** LIN channel state return value.
+ * Sleep mode operation; in this mode wake-up detection
+ * from slave nodes is enabled. */
LIN_CH_SLEEP\r
\r
} Lin_StatusType;\r
\r
-/* --- Service IDs --- */\r
+/** @name Service id's */
+//@{
#define LIN_INIT_SERVICE_ID 0x00\r
#define LIN_GETVERSIONINFO_SERVICE_ID 0x01\r
#define LIN_WAKEUPVALIDATION_SERVICE_ID 0x0A\r
#define LIN_WAKE_UP_SERVICE_ID 0x07\r
#define LIN_GETSTATUS_SERVICE_ID 0x08\r
#define LIN_GO_TO_SLEEP_INTERNAL_SERVICE_ID 0x09\r
-\r
-/* --- Error codes --- */\r
+//@}
+
+/** @name Error Codes */
+//@{\r
#define LIN_E_UNINIT 0x00\r
#define LIN_E_CHANNEL_UNINIT 0x01\r
#define LIN_E_INVALID_CHANNEL 0x02\r
#define LIN_E_INVALID_POINTER 0x03\r
#define LIN_E_STATE_TRANSITION 0x04\r
-#define LIN_E_TIMEOUT 0x05 //TODO Assigned by DEM\r
+//@}
\r
void Lin_Init( const Lin_ConfigType* Config );\r
\r
Lin_StatusType Lin_GetStatus( uint8 Channel, uint8** Lin_SduPtr );\r
\r
#endif\r
-\r
+/** @} */
\r
\r
\r
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup LinIf LIN Interface
+ * @{ */
-
-
-
-
-
+/** @file LinIf.h
+ * API and type definitions for LIN Interface.
+ */
#ifndef LINIF_H_\r
#define LINIF_H_\r
#include "ComM_Types.h"\r
\r
\r
-\r
-\r
-/* --- Service IDs --- */\r
+/** @name Service id's */
+//@{
#define LINIF_INIT_SERVICE_ID 0x00\r
#define LINIF_GETVERSIONINFO_SERVICE_ID 0x03\r
#define LINIF_SCHEDULEREQUEST_SERVICE_ID 0x05\r
#define LINIF_GOTOSLEEP_SERVICE_ID 0x06\r
#define LINIF_WAKEUP_SERVICE_ID 0x07\r
#define LINIF_MAINFUNCTION_SERVICE_ID 0x80\r
-\r
-/* --- Error codes --- */\r
+//@}
+
+/** @name Error Codes */
+//@{
#define LINIF_E_UNINIT 0x00\r
#define LINIF_E_ALREADY_INITIALIZED 0x10\r
#define LINIF_E_NONEXISTENT_CHANNEL 0x20\r
#define LINIF_E_PARAMETER_POINTER 0x40\r
#define LINIF_E_SCHEDULE_OVERFLOW 0x50\r
#define LINIF_E_SCHEDULE_REQUEST_ERROR 0x51\r
-#define LINIF_E_RESPONSE 0x52 //Assigned\r
-#define LINIF_E_NC_NO_RESPONSE 0x53 //Assigned by DEM\r
-#define LINIF_E_CHANNEL_X_SLAVE_Y 0x54 //Assigned by DEM\r
+//@}
#if (LINIF_VERSION_INFO_API == STD_ON)\r
void LinIf_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
void LinIf_MainFunction();\r
\r
#endif\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Mcu MCU Driver
+ * @{ */
-
-
-
-
-
+/** @file Mcu.h
+ * API and type definitions for MCU Driver.
+ */
#ifndef MCU_H_\r
#define MCU_H_\r
#include "irq_types.h"\r
//#include "mpc55xx_aos.h"\r
\r
-/* Service ID's */\r
+/** @name Service id's */
+//@{
#define MCU_INIT_SERVICE_ID 0x00\r
#define MCU_INITRAMSECTION_SERVICE_ID 0x01\r
#define MCU_INITCLOCK_SERVICE_ID 0x02\r
#define MCU_SETMODE_SERVICE_ID 0x08\r
#define MCU_GETVERSIONINFO_SERVICE_ID 0x09\r
#define MCU_INTCVECTORINSTALL_SERVICE_ID 0x0A // Not in spec but follows pattern\r
-\r
-/* Development error codes */\r
+//@}
+
+/** @name Error Codes */
+//@{
#define MCU_E_PARAM_CONFIG 0x0A\r
#define MCU_E_PARAM_CLOCK 0x0B\r
#define MCU_E_PARAM_MODE 0x0C\r
#define MCU_E_PARAM_RAMSECTION 0x0D\r
#define MCU_E_PLL_NOT_LOCKED 0x0E\r
#define MCU_E_UNINIT 0x0F\r
+//@}
\r
/* Specific return values */\r
-#define MCU_GETRESETRAWVALUE_NORESETREG_RV 0x00 // MCU006\r
-#define MCU_GETRESETRAWVALUE_UNINIT_RV 0xffffffff // MCU135\r
+#define MCU_GETRESETRAWVALUE_NORESETREG_RV 0x00 /**< MCU006 */
+#define MCU_GETRESETRAWVALUE_UNINIT_RV 0xffffffff /**< MCU135 */
\r
typedef enum {\r
MCU_PLL_LOCKED,\r
\r
\r
#endif /*MCU_H_*/\r
+/** @} */
#ifndef OS_H_\r
#define OS_H_\r
\r
-#define OS_SW_MAJOR_VERSION 1
+#define OS_SW_MAJOR_VERSION 2
#define OS_SW_MINOR_VERSION 0
#define OS_SW_PATCH_VERSION 0\r
-#ifndef _PDUR_H_\r
-#define _PDUR_H_\r
-\r
-#define PDUR_VENDOR_ID 1\r
-#define PDUR_AR_MAJOR_VERSION 2\r
-#define PDUR_AR_MINOR_VERSION 2\r
-#define PDUR_AR_PATCH_VERSION 2\r
-#define PDUR_SW_MAJOR_VERSION 3\r
-#define PDUR_SW_MINOR_VERSION 0\r
-#define PDUR_SW_PATCH_VERSION 2\r
-\r
-#include "PduR_Cfg.h"\r
-#include "PduR_Types.h"\r
-\r
-#ifndef PDUR_ZERO_COST_OPERATION\r
-#include "PduR_PbCfg.h"\r
-#endif\r
-\r
-#include "PduR_Com.h"\r
-#include "PduR_CanIf.h"\r
-#include "PduR_LinIf.h"\r
-\r
-/* Contain the current state of the PDU router. The router is uninitialized\r
- * until PduR_Init has been run.\r
- */\r
-PduR_StateType PduRState;\r
-\r
-extern const PduR_PBConfigType *PduRConfig;\r
-\r
-#ifdef PDUR_PRINT_DEBUG_STATEMENTS\r
-/* A simple debug macro to be used instead of printf(). This way all print\r
- * statements are turned off if PDUR_PRINT_DEBUG_STATEMENTS is undefined.\r
- */\r
-//#include <stdio.h>\r
-#define debug(...) simple_printf(__VA_ARGS__)\r
-\r
-#else\r
-#define debug(...)\r
-\r
-#endif\r
-\r
-#ifdef PDUR_REENTRANCY_CHECK\r
-/*\r
- * The macros Enter and Exit performs the ReEntrancy check of the PDU router functions.\r
- * Enter shall be called at the beginning of the function with the current PduId and the wanted\r
- * return value (possibly nothing for void methods).\r
- * Exit should be called at the end of the function where reentrancy is desirable.\r
- */\r
-#define Enter(PduId,...) \\r
- static uint8 entered;\\r
- static PduIdType enteredId;\\r
- if (entered && enteredId == PduId) { \\r
- debug("Function already entered. EnteredId: %d, CurrentId: %d. Exiting.\n", enteredId, PduId); \\r
- return __VA_ARGS__; \\r
- } else { \\r
- entered = 1; \\r
- enteredId = PduId; \\r
- } \\r
-\r
-\r
-#define Exit() \\r
- entered = 0; \\r
-\r
-#else\r
-#define Enter(...)\r
-#define Exit()\r
-#endif\r
-\r
-#ifdef PDUR_DEV_ERROR_DETECT\r
-\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
-\r
-// Define macro for state, parameter and data pointer checks.\r
-// TODO Implement data range check if needed.\r
-#define DevCheck(PduId,PduPtr,ApiId,...) \\r
- if (PduRState == PDUR_UNINIT || PduRState == PDUR_REDUCED) { \\r
- DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \\r
- DEBUG(DEBUG_LOW,"PDU Router not initialized. Routing request ignored.\n"); \\r
- Exit(); \\r
- return __VA_ARGS__; \\r
- } \\r
- if (PduPtr == 0 && PDUR_DEV_ERROR_DETECT) { \\r
- DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_DATA_PTR_INVALID); \\r
- Exit(); \\r
- return __VA_ARGS__; \\r
- } \\r
- if ((PduId >= PduRConfig->PduRRoutingTable->NRoutingPaths) && PDUR_DEV_ERROR_DETECT) { \\r
- DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_PDU_ID_INVALID); \\r
- Exit(); \\r
- return __VA_ARGS__; \\r
- } \\r
-\r
-\r
-#else\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q)\r
-#define DevCheck(...)\r
-\r
-#endif\r
-\r
-Std_ReturnType PduR_CancelTransmitRequest(\r
- PduR_CancelReasonType PduCancelReason, PduIdType PduId);\r
-void PduR_ChangeParameterRequest(PduR_ParameterValueType PduParameterValue,\r
- PduIdType PduId);\r
-\r
-/* Zero Cost Operation function definitions\r
- * These macros replaces the original functions if zero cost\r
- * operation is desired. */\r
-#ifdef PDUR_ZERO_COST_OPERATION\r
-\r
-#define PduR_Init(...)\r
-#define PduR_GetVersionInfo(...)\r
-#define PduR_GetConfigurationId(...) 0\r
-\r
-#else // Not zero cost operation\r
-void PduR_Init(const PduR_PBConfigType* ConfigPtr);\r
-void PduR_GetVersionInfo(Std_VersionInfoType* versionInfo);\r
-uint32 PduR_GetConfigurationId();\r
-\r
-void PduR_BufferQueue(PduRTxBuffer_type *Buffer, const uint8 * SduPtr);\r
-void PduR_BufferDeQueue(PduRTxBuffer_type *Buffer, uint8 *SduPtr);\r
-void PduR_BufferFlush(PduRTxBuffer_type *Buffer);\r
-uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer);\r
-\r
-/*\r
- * Macros\r
- */\r
-#define setTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 1\r
-#define clearTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 0\r
-\r
-#endif\r
-\r
-extern PduR_FctPtrType PduR_StdCanFctPtrs;\r
-extern PduR_FctPtrType PduR_StdLinFctPtrs;\r
-\r
-#endif /* _PDUR_H_ */\r
+#ifndef _PDUR_H_
+#define _PDUR_H_
+
+#define PDUR_VENDOR_ID 1
+#define PDUR_AR_MAJOR_VERSION 2
+#define PDUR_AR_MINOR_VERSION 2
+#define PDUR_AR_PATCH_VERSION 2
+#define PDUR_SW_MAJOR_VERSION 3
+#define PDUR_SW_MINOR_VERSION 0
+#define PDUR_SW_PATCH_VERSION 2
+
+#include "Trace.h"
+
+#include "PduR_Cfg.h"
+#include "PduR_Types.h"
+
+#ifndef PDUR_ZERO_COST_OPERATION
+#include "PduR_PbCfg.h"
+#endif
+
+#include "PduR_Com.h"
+#include "PduR_CanIf.h"
+#include "PduR_LinIf.h"
+
+/* Contain the current state of the PDU router. The router is uninitialized
+ * until PduR_Init has been run.
+ */
+PduR_StateType PduRState;
+
+extern const PduR_PBConfigType *PduRConfig;
+
+
+#ifdef PDUR_PRINT_DEBUG_STATEMENTS
+/* A simple debug macro to be used instead of printf(). This way all print
+ * statements are turned off if PDUR_PRINT_DEBUG_STATEMENTS is undefined.
+ */
+//#include <stdio.h>
+#define debug(...) simple_printf(__VA_ARGS__)
+
+#else
+#define debug(...)
+
+#endif
+
+#ifdef PDUR_REENTRANCY_CHECK
+/*
+ * The macros Enter and Exit performs the ReEntrancy check of the PDU router functions.
+ * Enter shall be called at the beginning of the function with the current PduId and the wanted
+ * return value (possibly nothing for void methods).
+ * Exit should be called at the end of the function where reentrancy is desirable.
+ */
+#define Enter(PduId,...) \
+ static uint8 entered;\
+ static PduIdType enteredId;\
+ if (entered && enteredId == PduId) { \
+ debug("Function already entered. EnteredId: %d, CurrentId: %d. Exiting.\n", enteredId, PduId); \
+ return __VA_ARGS__; \
+ } else { \
+ entered = 1; \
+ enteredId = PduId; \
+ } \
+
+
+#define Exit() \
+ entered = 0; \
+
+#else
+#define Enter(...)
+#define Exit()
+#endif
+
+#ifdef PDUR_DEV_ERROR_DETECT
+
+#undef DET_REPORTERROR
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)
+
+// Define macro for state, parameter and data pointer checks.
+// TODO Implement data range check if needed.
+#define DevCheck(PduId,PduPtr,ApiId,...) \
+ if (PduRState == PDUR_UNINIT || PduRState == PDUR_REDUCED) { \
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \
+ DEBUG(DEBUG_LOW,"PDU Router not initialized. Routing request ignored.\n"); \
+ Exit(); \
+ return __VA_ARGS__; \
+ } \
+ if (PduPtr == 0 && PDUR_DEV_ERROR_DETECT) { \
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_DATA_PTR_INVALID); \
+ Exit(); \
+ return __VA_ARGS__; \
+ } \
+ if ((PduId >= PduRConfig->PduRRoutingTable->NRoutingPaths) && PDUR_DEV_ERROR_DETECT) { \
+ DET_REPORTERROR(PDUR_MODULE_ID, PDUR_INSTANCE_ID, ApiId, PDUR_E_PDU_ID_INVALID); \
+ Exit(); \
+ return __VA_ARGS__; \
+ } \
+
+
+#else
+#undef DET_REPORTERROR
+#define DET_REPORTERROR(_x,_y,_z,_q)
+#define DevCheck(...)
+
+#endif
+
+Std_ReturnType PduR_CancelTransmitRequest(
+ PduR_CancelReasonType PduCancelReason, PduIdType PduId);
+void PduR_ChangeParameterRequest(PduR_ParameterValueType PduParameterValue,
+ PduIdType PduId);
+
+/* Zero Cost Operation function definitions
+ * These macros replaces the original functions if zero cost
+ * operation is desired. */
+#ifdef PDUR_ZERO_COST_OPERATION
+#define PduR_Init(...)
+#define PduR_GetVersionInfo(...)
+#define PduR_GetConfigurationId(...) 0
+
+#else // Not zero cost operation
+void PduR_Init(const PduR_PBConfigType* ConfigPtr);
+void PduR_GetVersionInfo(Std_VersionInfoType* versionInfo);
+uint32 PduR_GetConfigurationId();
+
+void PduR_BufferQueue(PduRTxBuffer_type *Buffer, const uint8 * SduPtr);
+void PduR_BufferDeQueue(PduRTxBuffer_type *Buffer, uint8 *SduPtr);
+void PduR_BufferFlush(PduRTxBuffer_type *Buffer);
+uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer);
+
+/*
+ * Macros
+ */
+#define setTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 1
+#define clearTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 0
+
+#endif
+
+extern PduR_FctPtrType PduR_StdCanFctPtrs;
+extern PduR_FctPtrType PduR_StdLinFctPtrs;
+
+#endif /* _PDUR_H_ */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup General General
+ * @{ */
-
-
-
-
-
+/** @file Platform_Types.h
+ * General platform type definitions.
+ */
#ifndef _PLATFORM_TYPES_H_\r
#define _PLATFORM_TYPES_H_\r
typedef double float64; \r
\r
#endif\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Port Port Driver
+ * @{ */
-
-
-
-
-
+/** @file Port.h
+ * API and type definitions for Port Driver.
+ */
#ifndef PORT_H_\r
#define PORT_H_\r
#if PORT_VERSION_INFO_API == STD_ON\r
void Port_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
#endif \r
-\r
+
+/** @name Error Codes */
+//@{
#define PORT_E_PARAM_PIN 0x0a\r
#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b\r
#define PORT_E_PARAM_CONFIG 0x0c\r
#define PORT_E_PARAM_INVALID_MODE 0x0d\r
#define PORT_E_MODE_UNCHANGEABLE 0x0e\r
#define PORT_E_UNINIT 0x0f\r
-\r
+//@}
+
+/** @name Service id's */
+//@{
#define PORT_INIT_ID 0x00\r
#define PORT_SET_PIN_DIRECTION_ID 0x01\r
#define PORT_REFRESH_PORT_DIRECTION_ID 0x02\r
#define PORT_GET_VERSION_INFO_ID 0x03\r
#define PORT_SET_PIN_MODE_ID 0x04\r
+//@}
\r
-/*\r
+/**
* PORT046: The type Port_PinDirectionType is a type for defining the direction of a Port Pin. \r
* PORT_PIN_IN Sets port pin as input. \r
* PORT_PIN_OUT Sets port pin as output. \r
void Port_SetPinMode( Port_PinType Pin, Port_PinModeType Mode );\r
\r
#endif /*PORT_H_*/\r
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+/** @addtogroup Pwm PWM Driver
+ * @{ */
+
+/** @file Pwm.h
+ * API and type definitions for PWM Driver.
+ */
+
#ifndef PWM_H_
#define PWM_H_
/**************************************************************
* Type definitions
**************************************************************/
-// PWM002: Development error values are of type uint8
+/** PWM002: Development error values are of type uint8 */
typedef uint8 Pwm_ErrorType;
-/*
+/**
* PWM058: The width of the duty cycle parameter is 16 bits
*
* PWM059: The PWM module shall comply with the following scaling scheme
/*
* Constants
*****************/
-
-/* Pwm_Init called with the wrong parameter */
+/** @name Error Codes */
+//@{
+/** Pwm_Init called with the wrong parameter */
//const Pwm_ErrorType PWM_E_PARAM_CONFIG = 0x10;
#define PWM_E_PARAM_CONFIG 0x10
-/* PWM is not initialized yet */
+/** PWM is not initialized yet */
//const Pwm_ErrorType PWM_E_UNINIT = 0x11;
#define PWM_E_UNINIT 0x11
-/* Invalid PWM channel identifier */
+/** Invalid PWM channel identifier */
//const Pwm_ErrorType PWM_E_PARAM_CHANNEL = 0x12;
#define PWM_E_PARAM_CHANNEL 0x12
-/* Use of unauthorized service on PWM channel configured fixed period */
+/** Use of unauthorized service on PWM channel configured fixed period */
//const Pwm_ErrorType PWM_E_PERIOD_UNCHANGEABLE = 0x13;
#define PWM_E_PERIOD_UNCHANGEABLE 0x13
-/* Pwm_Init called when already initialized */
+/** Pwm_Init called when already initialized */
//const Pwm_ErrorType PWM_E_ALREADY_INITIALIZED = 0x14;
#define PWM_E_ALREADY_INITIALIZED 0x14
+//@}
/*
* Implemented functions
#endif
#endif /* PWM_H_ */
+/** @} */
* for more details.
* -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup General General
+ * @{ */
+
+/** @file Std_Types.h
+ * Definitions of General types.
+ */
\r
#ifndef _STD_TYPES_H\r
#define _STD_TYPES_H\r
uint16 vendorID;\r
uint16 moduleID;\r
uint8 instanceID;\r
- /* Vendor numbers */\r
- uint8 sw_major_version;\r
- uint8 sw_minor_version;\r
- uint8 sw_patch_version;\r
- /* Autosar spec. numbers */\r
- uint8 ar_major_version;\r
- uint8 ar_minor_version;\r
- uint8 ar_patch_version;\r
+
+ uint8 sw_major_version; /**< Vendor numbers */
+ uint8 sw_minor_version; /**< Vendor numbers */
+ uint8 sw_patch_version; /**< Vendor numbers */
+
+ uint8 ar_major_version; /**< Autosar spec. numbers */
+ uint8 ar_minor_version; /**< Autosar spec. numbers */
+ uint8 ar_patch_version; /**< Autosar spec. numbers */
} Std_VersionInfoType;\r
\r
-/* make compare number... #if blabla > 10203 ( 1.2.3 ) */\r
+/** make compare number... #if version > 10203 ( 1.2.3 ) */
#define STD_GET_VERSION (_major,_minor,_patch) (_major * 10000 + _minor * 100 + _patch)\r
\r
-/* Non-standard macro */\r
+/** Create Std_VersionInfoType */
#define STD_GET_VERSION_INFO(_vi,_module) \\r
((_vi)->vendorID = _module ## _VENDOR_ID);\\r
((_vi)->moduleID = _module ## _MODULE_ID);\\r
#define STATUSTYPEDEFINED\r
typedef enum {\r
E_OK = 0,\r
- /* STD OSEK */\r
- E_OS_ACCESS = 1,\r
- E_OS_CALLEVEL = 2,\r
- E_OS_ID = 3,\r
- E_OS_LIMIT = 4,\r
- E_OS_NOFUNC = 5,\r
- E_OS_RESOURCE = 6,\r
- E_OS_STATE = 7,\r
- E_OS_VALUE = 8,\r
-\r
- /* AUTOSAR, see 7.10 */\r
- E_OS_SERVICEID,\r
- E_OS_RATE ,\r
- E_OS_ILLEGAL_ADDRESS ,\r
- E_OS_MISSINGEND ,\r
- E_OS_DISABLEDINT ,\r
- E_OS_STACKFAULT ,\r
- E_OS_PROTECTION_MEMORY ,\r
- E_OS_PROTECTION_TIME ,\r
- E_OS_PROTECTION_LOCKED ,\r
- E_OS_PROTECTION_EXCEPTION ,\r
- E_OS_PROTECTION_RATE,\r
+ E_OS_ACCESS = 1, /**< STD OSEK */
+ E_OS_CALLEVEL = 2, /**< STD OSEK */
+ E_OS_ID = 3, /**< STD OSEK */
+ E_OS_LIMIT = 4, /**< STD OSEK */
+ E_OS_NOFUNC = 5, /**< STD OSEK */
+ E_OS_RESOURCE = 6, /**< STD OSEK */
+ E_OS_STATE = 7, /**< STD OSEK */
+ E_OS_VALUE = 8, /**< STD OSEK */
+\r
+ E_OS_SERVICEID, /**< AUTOSAR, see 7.10 */
+ E_OS_RATE , /**< AUTOSAR, see 7.10 */
+ E_OS_ILLEGAL_ADDRESS , /**< AUTOSAR, see 7.10 */
+ E_OS_MISSINGEND , /**< AUTOSAR, see 7.10 */
+ E_OS_DISABLEDINT , /**< AUTOSAR, see 7.10 */
+ E_OS_STACKFAULT , /**< AUTOSAR, see 7.10 */
+ E_OS_PROTECTION_MEMORY , /**< AUTOSAR, see 7.10 */
+ E_OS_PROTECTION_TIME , /**< AUTOSAR, see 7.10 */
+ E_OS_PROTECTION_LOCKED , /**< AUTOSAR, see 7.10 */
+ E_OS_PROTECTION_EXCEPTION , /**< AUTOSAR, see 7.10 */
+ E_OS_PROTECTION_RATE, /**< AUTOSAR, see 7.10 */
\r
/* COM.. TODO: move ?? */\r
E_COM_ID,\r
\r
\r
- /* Implementation specific */\r
+ /** Implementation specific */
E_OS_SYS_APA,\r
\r
E_NOT_OK,\r
\r
\r
#endif\r
+/** @} */
#elif defined(CFG_MPC5516) || defined(MPC5517)\r
#include "mpc5516.h"\r
#elif defined(CFG_MPC5567)\r
-#include "mpc5567.h"\r
+#include "mpc5567.h"
+#elif defined(CFG_MPC5633)
+#include "mpc563m.h"\r
#else\r
#error NO MCU SELECTED!!!!\r
#endif\r
#include "NvM.h"
#include "Rte.h"
+#if defined(USE_DEM)
#include "Dem.h"
+#endif
//#include "Crc.h"
void NvM_Init( void ){
#include "Fls.h"\r
#include "Fls_SST25xx.h"\r
#include "Spi.h"\r
-//#include "Dem.h"\r
#include "Det.h"\r
+#if defined(USE_DEM)
+#include "Dem.h"
+#endif
#include <stdlib.h>\r
#include <assert.h>\r
//#include <stdio.h>\r
} else if( jobResult == SPI_SEQ_OK ) {\r
\r
if( memcmp(Fls_SST25xx_CompareBuffer,gJob->targetAddr, readSize) != 0 ) {\r
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_COMPARE_FAILED );\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_COMPARE_FAILED, DEM_EVENT_STATUS_FAILED);\r
+#endif
FEE_JOB_ERROR_NOTIFICATION();\r
return;\r
}\r
Fls_SST25xx_Global.jobType = FLS_SST25XX_NONE;\r
Fls_SST25xx_Global.status = MEMIF_IDLE;\r
\r
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_COMPARE_FAILED );\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_COMPARE_FAILED, DEM_EVENT_STATUS_FAILED);
+#endif
FEE_JOB_ERROR_NOTIFICATION();\r
}\r
}\r
\r
switch(Fls_SST25xx_Global.jobType) {\r
case FLS_SST25XX_ERASE:\r
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_ERASED_FAILED );\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_ERASED_FAILED, DEM_EVENT_STATUS_FAILED);\r
+#endif
break;\r
case FLS_SST25XX_READ:\r
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_READ_FAILED );\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_READ_FAILED, DEM_EVENT_STATUS_FAILED);\r
+#endif
break;\r
case FLS_SST25XX_WRITE:\r
- DET_REPORTERROR(MODULE_ID_FLS,0, 0x6, FLS_E_WRITE_FAILED );\r
+#if defined(USE_DEM)
+ Dem_ReportErrorStatus(FLS_E_WRITE_FAILED, DEM_EVENT_STATUS_FAILED);\r
+#endif
break;\r
default:\r
assert(0);\r
--- /dev/null
+\r
+inc: all\r
+\r
+clean: all\r
+\r
+all:\r
+ @echo ""\r
+ @echo "***"\r
+ @echo "* You are building Arctic Core using the Empty Toolchain."\r
+ @echo "* This toolchain is designed to produce nothing, but to integrate well with Arctic Studio."\r
+ @echo "* "\r
+ @echo "* You are probably seeing this message for one of the following reasons:"\r
+ @echo "* 1. You are using the Arctic Studio 'Build All' command."\r
+ @echo "* There is no harm in this. However, if you don't want to see this message, you can build just your own project"\r
+ @echo "* by marking your project in the Project Explorer and using the 'Build Project' command instead."\r
+ @echo "* "\r
+ @echo "* 2. You have 'Build automatically' activated."\r
+ @echo "* There is no harm in this either. Just deselect it in the Project menu to stop rebuilding on every save."\r
+ @echo "* "\r
+ @echo "* 3. Your workspace setup is wrong."\r
+ @echo "* If you are developing an application for Arctic Core you should put all your code in a separate C-project."\r
+ @echo "* This project should then reference the Arctic Core source code project. Please refer to"\r
+ @echo "* http://arccore.com/wiki/Quick-start_Tutorial for instructions on setting up your workspace."\r
+ @echo "* "\r
+ @echo "* Arctic Studio keeps a separate console for each of the projects in the workspace. To view the log for another project"\r
+ @echo "* simply select that project in the Project Explorer."\r
+ @echo "* "\r
+ @echo "*** DONE"\r
+\r
\ No newline at end of file
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
// This file is just examples of implementation for the stubs needed by\r
// the EcuM. Every Autocore application should use an own version of this\r
// file to implement the setup and tear down of the system.\r
\r
#include "EcuM.h"\r
#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
#if defined(USE_MCU)\r
#include "Mcu.h"\r
#endif\r
#if defined(USE_PWM)\r
#include "Pwm.h"\r
#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
\r
void EcuM_AL_DriverInitZero()\r
{\r
Det_Init();\r
Det_Start();\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
}\r
\r
EcuM_ConfigType* EcuM_DeterminePbConfiguration()\r
// Setup COM layer\r
Com_Init(ConfigPtr->ComConfig);\r
#endif\r
+ \r
+#if defined(USE_IOHWAB)\r
+ // Setup IO Hardware Abstraction\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Initialize DEM\r
+ Dem_Init();\r
+#endif\r
\r
}\r
\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-// Struct generated by the code generator depends on the\r
-// included modules\r
-\r
-#ifndef _ECUM_GENERATED_TYPES_H_\r
-#define _ECUM_GENERATED_TYPES_H_\r
-\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_PORT)\r
-#include "Port.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-\r
-typedef struct\r
-{\r
- EcuM_StateType EcuMDefaultShutdownTarget;\r
- uint8 EcuMDefaultShutdownMode;\r
- AppModeType EcuMDefaultAppMode;\r
-\r
-#if defined(USE_MCU)\r
- const Mcu_ConfigType* McuConfig;\r
-#endif\r
-#if defined(USE_PORT)\r
- const Port_ConfigType* PortConfig;\r
-#endif\r
-#if defined(USE_CAN)\r
- const Can_ConfigType* CanConfig;\r
-#endif\r
-#if defined(USE_CANIF)\r
- const CanIf_ConfigType* CanIfConfig;\r
-#endif\r
-#if defined(USE_COM)\r
- const Com_ConfigType* ComConfig;\r
-#endif\r
-#if defined(USE_PWM)\r
- const Pwm_ConfigType* PwmConfig;\r
-#endif\r
-} EcuM_ConfigType;\r
-\r
-#endif /*_ECUM_GENERATED_TYPES_H_*/\r
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-#ifndef DEM_PBCFG_H_\r
-#define DEM_PBCFG_H_\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
-#endif /*DEM_PBCFG_H_*/\r
+\r
+/*\r
+ * ----------------------------------------------------------------------------\r
+ * NOTE: This file is a stub only. ECU software needs to provide a generated IO\r
+ * hardware abstraction module that overrides this file.\r
+ * ----------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+#include "IoHwAb.h"\r
+\r
+\r
+void IoHwAb_Init() {\r
+\r
+}\r
pos 1. 1. 14.\r
text "CPU:"\r
pos 1. 2. 10.\r
-CPU: PULLDOWN "mpc5516,mpc5554,CortexM3"\r
+CPU: PULLDOWN "mpc5516,mpc5554,mpc5633M,CortexM3"\r
(\r
)\r
HEADER "Project config"\r
save_close:\r
&cfg_cpu_g=dialog.string(CPU)\r
&cfg_project_path_g=dialog.string(P_PATH)\r
+ sys.cpu &cfg_cpu_g\r
do config save\r
win_close:\r
dialog.end\r
\r
\r
\r
+\r
\r
\r
projects / arc.git / commitdiff