\r
\r
/* ----------------------------[includes]------------------------------------*/\r
-\r
#include "Can.h"\r
-\r
-//#include "ip_flexcan.h"\r
#include <stdio.h>\r
#include "mpc55xx.h"\r
#include "Cpu.h"\r
Can_InitController(cfgCtrlPtr->CanControllerId,unitPtr->cfgCtrlPtr);\r
\r
switch (cfgCtrlPtr->CanControllerId) {\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC5606S) || defined(CFG_MPC5604B)\r
case CAN_CTRL_A:\r
ISR_INSTALL_ISR2( "Can", Can_A_BusOff, FLEXCAN_0_ESR_BOFF_INT, 2, 0);\r
ISR_INSTALL_ISR2( "Can", Can_A_Err, FLEXCAN_0_ESR_ERR_INT, 2, 0 );\r
ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_1_BUF_16_31, 2, 0 );\r
ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_1_BUF_32_63, 2, 0 );\r
break;\r
-#elif defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567) || defined(CFG_MPC5604B)\r
+#endif\r
+#if defined(CFG_MPC5604B)\r
+ case CAN_CTRL_C:\r
+ ISR_INSTALL_ISR2( "Can", Can_C_BusOff, FLEXCAN_2_ESR_BOFF_INT, 2, 0);\r
+ ISR_INSTALL_ISR2( "Can", Can_C_Err, FLEXCAN_2_ESR_ERR_INT, 2, 0 );\r
+ INSTALL_HANDLER4( "Can", Can_C_Isr, FLEXCAN_2_BUF_00_03, 2, 0 ); /* 0-3, 4-7, 8-11, 12-15 */\r
+ ISR_INSTALL_ISR2( "Can", Can_C_Isr, FLEXCAN_2_BUF_16_31, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Can", Can_C_Isr, FLEXCAN_2_BUF_32_63, 2, 0 );\r
+ break;\r
+ case CAN_CTRL_D:\r
+ ISR_INSTALL_ISR2( "Can", Can_D_BusOff, FLEXCAN_3_ESR_BOFF_INT, 2, 0);\r
+ ISR_INSTALL_ISR2( "Can", Can_D_Err, FLEXCAN_3_ESR_ERR_INT, 2, 0 );\r
+ INSTALL_HANDLER4( "Can", Can_D_Isr, FLEXCAN_3_BUF_00_03, 2, 0 ); /* 0-3, 4-7, 8-11, 12-15 */\r
+ ISR_INSTALL_ISR2( "Can", Can_D_Isr, FLEXCAN_3_BUF_16_31, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Can", Can_D_Isr, FLEXCAN_3_BUF_32_63, 2, 0 );\r
+ break;\r
+ case CAN_CTRL_E:\r
+ ISR_INSTALL_ISR2( "Can", Can_E_BusOff, FLEXCAN_4_ESR_BOFF_INT, 2, 0);\r
+ ISR_INSTALL_ISR2( "Can", Can_E_Err, FLEXCAN_4_ESR_ERR_INT, 2, 0 );\r
+ INSTALL_HANDLER4( "Can", Can_E_Isr, FLEXCAN_4_BUF_00_03, 2, 0 ); /* 0-3, 4-7, 8-11, 12-15 */\r
+ ISR_INSTALL_ISR2( "Can", Can_E_Isr, FLEXCAN_4_BUF_16_31, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Can", Can_E_Isr, FLEXCAN_4_BUF_32_63, 2, 0 );\r
+ break;\r
+ case CAN_CTRL_E:\r
+ ISR_INSTALL_ISR2( "Can", Can_F_BusOff, FLEXCAN_5_ESR_BOFF_INT, 2, 0);\r
+ ISR_INSTALL_ISR2( "Can", Can_F_Err, FLEXCAN_5_ESR_ERR_INT, 2, 0 );\r
+ INSTALL_HANDLER4( "Can", Can_F_Isr, FLEXCAN_5_BUF_00_03, 2, 0 ); /* 0-3, 4-7, 8-11, 12-15 */\r
+ ISR_INSTALL_ISR2( "Can", Can_F_Isr, FLEXCAN_5_BUF_16_31, 2, 0 );\r
+ ISR_INSTALL_ISR2( "Can", Can_F_Isr, FLEXCAN_5_BUF_32_63, 2, 0 );\r
+ break;\r
+#endif\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5567)\r
case CAN_CTRL_A:\r
ISR_INSTALL_ISR2( "Can", Can_A_BusOff, FLEXCAN_A_ESR_BOFF_INT, 2, 0);\r
ISR_INSTALL_ISR2( "Can", Can_A_Err, FLEXCAN_A_ESR_ERR_INT, 2, 0 );\r
ISR_INSTALL_ISR2( "Can", Can_A_Isr, FLEXCAN_E_IFLAG1_BUF63_32I, 2, 0 );\r
break;\r
#endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5604B)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
case CAN_CTRL_F:\r
ISR_INSTALL_ISR2( "Can", Can_F_BusOff, FLEXCAN_F_ESR_BOFF_INT, 2, 0 );\r
ISR_INSTALL_ISR2( "Can", Can_F_Err, FLEXCAN_F_ESR_ERR_INT, 2, 0 );\r
/****************************************************************************/\r
/* MODULE : FlexCAN */\r
/****************************************************************************/\r
- CC_EXTENSION struct FLEXCAN2_tag {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t MDIS:1;\r
- vuint32_t FRZ:1;\r
- vuint32_t:1;\r
- vuint32_t HALT:1;\r
- vuint32_t NOTRDY:1;\r
- vuint32_t:1;\r
- vuint32_t SOFTRST:1;\r
- vuint32_t FRZACK:1;\r
- vuint32_t:1;\r
- vuint32_t:1;\r
-\r
- vuint32_t WRNEN:1;\r
-\r
- vuint32_t MDISACK:1;\r
- vuint32_t:1;\r
- vuint32_t:1;\r
-\r
- vuint32_t SRXDIS:1;\r
- vuint32_t MBFEN:1;\r
- vuint32_t:10;\r
-\r
- vuint32_t MAXMB:6;\r
- } B;\r
- } MCR; /* Module Configuration Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t PRESDIV:8;\r
- vuint32_t RJW:2;\r
- vuint32_t PSEG1:3;\r
- vuint32_t PSEG2:3;\r
- vuint32_t BOFFMSK:1;\r
- vuint32_t ERRMSK:1;\r
- vuint32_t CLKSRC:1;\r
- vuint32_t LPB:1;\r
-\r
- vuint32_t TWRNMSK:1;\r
- vuint32_t RWRNMSK:1;\r
- vuint32_t:2;\r
-\r
- vuint32_t SMP:1;\r
- vuint32_t BOFFREC:1;\r
- vuint32_t TSYN:1;\r
- vuint32_t LBUF:1;\r
- vuint32_t LOM:1;\r
- vuint32_t PROPSEG:3;\r
- } B;\r
- } CR; /* Control Register */\r
-\r
- union {\r
- vuint32_t R;\r
- } TIMER; /* Free Running Timer */\r
- int32_t FLEXCAN_reserved00;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RXGMASK; /* RX Global Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RX14MASK; /* RX 14 Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RX15MASK; /* RX 15 Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t RXECNT:8;\r
- vuint32_t TXECNT:8;\r
- } B;\r
- } ECR; /* Error Counter Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:14;\r
-\r
- vuint32_t TWRNINT:1;\r
- vuint32_t RWRNINT:1;\r
-\r
- vuint32_t BIT1ERR:1;\r
- vuint32_t BIT0ERR:1;\r
- vuint32_t ACKERR:1;\r
- vuint32_t CRCERR:1;\r
- vuint32_t FRMERR:1;\r
- vuint32_t STFERR:1;\r
- vuint32_t TXWRN:1;\r
- vuint32_t RXWRN:1;\r
- vuint32_t IDLE:1;\r
- vuint32_t TXRX:1;\r
- vuint32_t FLTCONF:2;\r
- vuint32_t:1;\r
- vuint32_t BOFFINT:1;\r
- vuint32_t ERRINT:1;\r
- vuint32_t:1;\r
- } B;\r
- } ESR; /* Error and Status Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF63M:1;\r
- vuint32_t BUF62M:1;\r
- vuint32_t BUF61M:1;\r
- vuint32_t BUF60M:1;\r
- vuint32_t BUF59M:1;\r
- vuint32_t BUF58M:1;\r
- vuint32_t BUF57M:1;\r
- vuint32_t BUF56M:1;\r
- vuint32_t BUF55M:1;\r
- vuint32_t BUF54M:1;\r
- vuint32_t BUF53M:1;\r
- vuint32_t BUF52M:1;\r
- vuint32_t BUF51M:1;\r
- vuint32_t BUF50M:1;\r
- vuint32_t BUF49M:1;\r
- vuint32_t BUF48M:1;\r
- vuint32_t BUF47M:1;\r
- vuint32_t BUF46M:1;\r
- vuint32_t BUF45M:1;\r
- vuint32_t BUF44M:1;\r
- vuint32_t BUF43M:1;\r
- vuint32_t BUF42M:1;\r
- vuint32_t BUF41M:1;\r
- vuint32_t BUF40M:1;\r
- vuint32_t BUF39M:1;\r
- vuint32_t BUF38M:1;\r
- vuint32_t BUF37M:1;\r
- vuint32_t BUF36M:1;\r
- vuint32_t BUF35M:1;\r
- vuint32_t BUF34M:1;\r
- vuint32_t BUF33M:1;\r
- vuint32_t BUF32M:1;\r
- } B;\r
- } IMRH; /* Interruput Masks Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF31M:1;\r
- vuint32_t BUF30M:1;\r
- vuint32_t BUF29M:1;\r
- vuint32_t BUF28M:1;\r
- vuint32_t BUF27M:1;\r
- vuint32_t BUF26M:1;\r
- vuint32_t BUF25M:1;\r
- vuint32_t BUF24M:1;\r
- vuint32_t BUF23M:1;\r
- vuint32_t BUF22M:1;\r
- vuint32_t BUF21M:1;\r
- vuint32_t BUF20M:1;\r
- vuint32_t BUF19M:1;\r
- vuint32_t BUF18M:1;\r
- vuint32_t BUF17M:1;\r
- vuint32_t BUF16M:1;\r
- vuint32_t BUF15M:1;\r
- vuint32_t BUF14M:1;\r
- vuint32_t BUF13M:1;\r
- vuint32_t BUF12M:1;\r
- vuint32_t BUF11M:1;\r
- vuint32_t BUF10M:1;\r
- vuint32_t BUF09M:1;\r
- vuint32_t BUF08M:1;\r
- vuint32_t BUF07M:1;\r
- vuint32_t BUF06M:1;\r
- vuint32_t BUF05M:1;\r
- vuint32_t BUF04M:1;\r
- vuint32_t BUF03M:1;\r
- vuint32_t BUF02M:1;\r
- vuint32_t BUF01M:1;\r
- vuint32_t BUF00M:1;\r
- } B;\r
- } IMRL; /* Interruput Masks Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF63I:1;\r
- vuint32_t BUF62I:1;\r
- vuint32_t BUF61I:1;\r
- vuint32_t BUF60I:1;\r
- vuint32_t BUF59I:1;\r
- vuint32_t BUF58I:1;\r
- vuint32_t BUF57I:1;\r
- vuint32_t BUF56I:1;\r
- vuint32_t BUF55I:1;\r
- vuint32_t BUF54I:1;\r
- vuint32_t BUF53I:1;\r
- vuint32_t BUF52I:1;\r
- vuint32_t BUF51I:1;\r
- vuint32_t BUF50I:1;\r
- vuint32_t BUF49I:1;\r
- vuint32_t BUF48I:1;\r
- vuint32_t BUF47I:1;\r
- vuint32_t BUF46I:1;\r
- vuint32_t BUF45I:1;\r
- vuint32_t BUF44I:1;\r
- vuint32_t BUF43I:1;\r
- vuint32_t BUF42I:1;\r
- vuint32_t BUF41I:1;\r
- vuint32_t BUF40I:1;\r
- vuint32_t BUF39I:1;\r
- vuint32_t BUF38I:1;\r
- vuint32_t BUF37I:1;\r
- vuint32_t BUF36I:1;\r
- vuint32_t BUF35I:1;\r
- vuint32_t BUF34I:1;\r
- vuint32_t BUF33I:1;\r
- vuint32_t BUF32I:1;\r
- } B;\r
- } IFRH; /* Interruput Flag Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF31I:1;\r
- vuint32_t BUF30I:1;\r
- vuint32_t BUF29I:1;\r
- vuint32_t BUF28I:1;\r
- vuint32_t BUF27I:1;\r
- vuint32_t BUF26I:1;\r
- vuint32_t BUF25I:1;\r
- vuint32_t BUF24I:1;\r
- vuint32_t BUF23I:1;\r
- vuint32_t BUF22I:1;\r
- vuint32_t BUF21I:1;\r
- vuint32_t BUF20I:1;\r
- vuint32_t BUF19I:1;\r
- vuint32_t BUF18I:1;\r
- vuint32_t BUF17I:1;\r
- vuint32_t BUF16I:1;\r
- vuint32_t BUF15I:1;\r
- vuint32_t BUF14I:1;\r
- vuint32_t BUF13I:1;\r
- vuint32_t BUF12I:1;\r
- vuint32_t BUF11I:1;\r
- vuint32_t BUF10I:1;\r
- vuint32_t BUF09I:1;\r
- vuint32_t BUF08I:1;\r
- vuint32_t BUF07I:1;\r
- vuint32_t BUF06I:1;\r
- vuint32_t BUF05I:1;\r
- vuint32_t BUF04I:1;\r
- vuint32_t BUF03I:1;\r
- vuint32_t BUF02I:1;\r
- vuint32_t BUF01I:1;\r
- vuint32_t BUF00I:1;\r
- } B;\r
- } IFRL; /* Interruput Flag Register */\r
-\r
- uint32_t flexcan2_reserved2[19];\r
-\r
- struct canbuf_t {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:4;\r
- vuint32_t CODE:4;\r
- vuint32_t:1;\r
- vuint32_t SRR:1;\r
- vuint32_t IDE:1;\r
- vuint32_t RTR:1;\r
- vuint32_t LENGTH:4;\r
- vuint32_t TIMESTAMP:16;\r
- } B;\r
- } CS;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t STD_ID:11;\r
- vuint32_t EXT_ID:18;\r
- } B;\r
- } ID;\r
-\r
- union {\r
- vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
- vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
- vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
- vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
- } DATA;\r
-\r
- } BUF[64];\r
-\r
- uint32_t flexcan2_reserved3[256];\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RXIMR[64]; /* RX Individual Mask Registers */\r
-\r
- };\r
+#include "ip_flexcan.h"\r
/****************************************************************************/\r
/* MODULE : FEC */\r
/****************************************************************************/\r
projects / arc.git / commitdiff