--- /dev/null
+/**************************************************************************/\r
+/* FILE NAME: mpc563m.h COPYRIGHT (c) Freescale 2008 */\r
+/* VERSION: 1.2 All Rights Reserved */\r
+/* */\r
+/* DESCRIPTION: */\r
+/* This file contain all of the register and bit field definitions for */\r
+/* MPC563m. */\r
+/*========================================================================*/\r
+/* UPDATE HISTORY */\r
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */\r
+/* --- ----------- --------- --------------------- */\r
+/* 1.0 G. Emerson 31/OCT/07 Initial version. */\r
+/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */\r
+/* Added ESYNCR1 ESYNCR2 SYNFMMR */\r
+/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */\r
+/* 8 channels in the middle of the range */\r
+/* do not exist */\r
+/**************************************************************************/\r
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/\r
+\r
+#ifndef _MPC563M_H_\r
+#define _MPC563M_H_\r
+\r
+#include "typedefs.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#ifdef __MWERKS__\r
+#pragma push\r
+#pragma ANSI_strict off\r
+#endif\r
+\r
+/****************************************************************************/\r
+/* MODULE : PBRIDGE Peripheral Bridge */\r
+/****************************************************************************/\r
+ struct PBRIDGE_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MBW0:1;\r
+ vuint32_t MTR0:1;\r
+ vuint32_t MTW0:1;\r
+ vuint32_t MPL0:1;\r
+ vuint32_t MBW1:1;\r
+ vuint32_t MTR1:1;\r
+ vuint32_t MTW1:1;\r
+ vuint32_t MPL1:1;\r
+ vuint32_t MBW2:1;\r
+ vuint32_t MTR2:1;\r
+ vuint32_t MTW2:1;\r
+ vuint32_t MPL2:1;\r
+ vuint32_t MBW3:1;\r
+ vuint32_t MTR3:1;\r
+ vuint32_t MTW3:1;\r
+ vuint32_t MPL3:1;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+ } B;\r
+ } MPCR; /* Master Privilege Control Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FMPLL */\r
+/****************************************************************************/\r
+ struct FMPLL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t PREDIV:3;\r
+ vuint32_t MFD:5;\r
+ vuint32_t:1;\r
+ vuint32_t RFD:3;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:13;\r
+ } B;\r
+ } SYNCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:22;\r
+ vuint32_t LOLF:1;\r
+ vuint32_t LOC:1;\r
+ vuint32_t MODE:1;\r
+ vuint32_t PLLSEL:1;\r
+ vuint32_t PLLREF:1;\r
+ vuint32_t LOCKS:1;\r
+ vuint32_t LOCK:1;\r
+ vuint32_t LOCF:1;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYNSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EMODE:1;\r
+ vuint32_t CLKCFG:3;\r
+ vuint32_t:8;\r
+ vuint32_t EPREDIV:4;\r
+ vuint32_t:9;\r
+ vuint32_t EMFD:7;\r
+ } B;\r
+ } ESYNCR1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t LOCEN:1;\r
+ vuint32_t LOLRE:1;\r
+ vuint32_t LOCRE:1;\r
+ vuint32_t LOLIRQ:1;\r
+ vuint32_t LOCIRQ:1;\r
+ vuint32_t:17;\r
+ vuint32_t ERFD:2;\r
+ } B;\r
+ } ESYNCR2;\r
+\r
+ int32_t FMPLL_reserved0[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MODEN:1;\r
+ vuint32_t MODSEL:1;\r
+ vuint32_t MODPERIOD:13;\r
+ vuint32_t:1;\r
+ vuint32_t INC_STEP:15;\r
+ } B;\r
+ } SYNFMMR;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : External Bus Interface (EBI) */\r
+/****************************************************************************/\r
+ struct CS_tag {\r
+ union { /* Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct CAL_CS_tag {\r
+ union { /* Calibration Base Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BA:17;\r
+ vuint32_t:3;\r
+ vuint32_t PS:1;\r
+ vuint32_t:4;\r
+ vuint32_t BL:1;\r
+ vuint32_t WEBS:1;\r
+ vuint32_t TBDIP:1;\r
+ vuint32_t:2;\r
+ vuint32_t BI:1;\r
+ vuint32_t V:1;\r
+ } B;\r
+ } BR;\r
+\r
+ union { /* Calibration Option Register Bank */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t AM:17;\r
+ vuint32_t:7;\r
+ vuint32_t SCY:4;\r
+ vuint32_t:1;\r
+ vuint32_t BSCY:2;\r
+ vuint32_t:1;\r
+ } B;\r
+ } OR;\r
+ };\r
+\r
+ struct EBI_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:5;\r
+ vuint32_t SIZEEN:1;\r
+ vuint32_t SIZE:2;\r
+ vuint32_t:8;\r
+ vuint32_t ACGE:1;\r
+ vuint32_t EXTM:1;\r
+ vuint32_t EARB:1;\r
+ vuint32_t EARP:2;\r
+ vuint32_t:4;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t:5;\r
+ vuint32_t DBM:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ uint32_t EBI_reserved1;\r
+\r
+ union { /* Transfer Error Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TEAF:1;\r
+ vuint32_t BMTF:1;\r
+ } B;\r
+ } TESR;\r
+\r
+ union { /* Bus Monitor Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t BMT:8;\r
+ vuint32_t BME:1;\r
+ vuint32_t:7;\r
+ } B;\r
+ } BMCR;\r
+\r
+ struct CS_tag CS[4];\r
+\r
+/* Calibration registers */\r
+ uint32_t EBI_reserved2[4];\r
+ struct CAL_CS_tag CAL_CS[4];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FLASH */\r
+/****************************************************************************/\r
+ struct FLASH_tag {\r
+ union { /* Module Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t SIZE:4;\r
+ vuint32_t:1;\r
+ vuint32_t LAS:3;\r
+ vuint32_t:3;\r
+ vuint32_t MAS:1;\r
+ vuint32_t EER:1;\r
+ vuint32_t RWE:1;\r
+ vuint32_t BBEPE:1;\r
+ vuint32_t EPE:1;\r
+ vuint32_t PEAS:1;\r
+ vuint32_t DONE:1;\r
+ vuint32_t PEG:1;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t PRD:1; /* Include PRD Field */\r
+\r
+ vuint32_t STOP:1;\r
+ vuint32_t:1;\r
+ vuint32_t PGM:1;\r
+ vuint32_t PSUS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t ESUS:1;\r
+ vuint32_t EHV:1;\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* LML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LME:1;\r
+ vuint32_t:10;\r
+ vuint32_t SLOCK:1;\r
+ vuint32_t MLOCK:4;\r
+ vuint32_t LLOCK:16;\r
+ } B;\r
+ } LMLR;\r
+\r
+ union { /* HL Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t HBE:1;\r
+ vuint32_t:3;\r
+ vuint32_t HBLOCK:28;\r
+ } B;\r
+ } HLR;\r
+\r
+ union { /* SLML Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SLE:1;\r
+ vuint32_t:10;\r
+ vuint32_t SSLOCK:1;\r
+ vuint32_t SMLOCK:4;\r
+ vuint32_t SLLOCK:16;\r
+ } B;\r
+ } SLMLR;\r
+\r
+ union { /* LMS Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t MSEL:4;\r
+ vuint32_t LSEL:16;\r
+ } B;\r
+ } LMSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t HBSEL:28;\r
+ } B;\r
+ } HSR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:10;\r
+ vuint32_t ADDR:19;\r
+ vuint32_t:3;\r
+ } B;\r
+ } AR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:11;\r
+\r
+ vuint32_t:1;\r
+\r
+ vuint32_t M3PFE:1;\r
+ vuint32_t M2PFE:1;\r
+ vuint32_t M1PFE:1;\r
+ vuint32_t M0PFE:1;\r
+ vuint32_t APC:3;\r
+ vuint32_t WWSC:2;\r
+ vuint32_t RWSC:3;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t DPFEN:1;\r
+ vuint32_t:1;\r
+ vuint32_t IPFEN:1;\r
+\r
+ vuint32_t PFLIM:3;\r
+ vuint32_t BFEN:1;\r
+ } B;\r
+ } BIUCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+\r
+ vuint32_t:22;\r
+\r
+ vuint32_t:2;\r
+\r
+ vuint32_t M3AP:2;\r
+ vuint32_t M2AP:2;\r
+ vuint32_t M1AP:2;\r
+ vuint32_t M0AP:2;\r
+ } B;\r
+ } BIUAPR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LBCFG:2;\r
+ vuint32_t:30;\r
+ } B;\r
+ } BIUCR2;\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : SIU */\r
+/****************************************************************************/\r
+ struct SIU_tag {\r
+ int32_t SIU_reserved0;\r
+\r
+ union { /* MCU ID Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PARTNUM:16;\r
+ vuint32_t MASKNUM:16;\r
+ } B;\r
+ } MIDR;\r
+ int32_t SIU_reserved00;\r
+\r
+ union { /* Reset Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PORS:1;\r
+ vuint32_t ERS:1;\r
+ vuint32_t LLRS:1;\r
+ vuint32_t LCRS:1;\r
+ vuint32_t WDRS:1;\r
+ vuint32_t CRS:1;\r
+ vuint32_t:8;\r
+ vuint32_t SSRS:1;\r
+ vuint32_t SERF:1;\r
+ vuint32_t WKPCFG:1;\r
+ vuint32_t:12;\r
+ vuint32_t BOOTCFG:2;\r
+ vuint32_t RGF:1;\r
+ } B;\r
+ } RSR;\r
+\r
+ union { /* System Reset Control Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SSR:1;\r
+ vuint32_t SER:1;\r
+ vuint32_t:14;\r
+ vuint32_t CRE:1;\r
+ vuint32_t:15;\r
+ } B;\r
+ } SRCR;\r
+\r
+ union { /* External Interrupt Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIF15:1;\r
+ vuint32_t EIF14:1;\r
+ vuint32_t EIF13:1;\r
+ vuint32_t EIF12:1;\r
+ vuint32_t EIF11:1;\r
+ vuint32_t EIF10:1;\r
+ vuint32_t EIF9:1;\r
+ vuint32_t EIF8:1;\r
+ vuint32_t EIF7:1;\r
+ vuint32_t EIF6:1;\r
+ vuint32_t EIF5:1;\r
+ vuint32_t EIF4:1;\r
+ vuint32_t EIF3:1;\r
+ vuint32_t EIF2:1;\r
+ vuint32_t EIF1:1;\r
+ vuint32_t EIF0:1;\r
+ } B;\r
+ } EISR;\r
+\r
+ union { /* DMA/Interrupt Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t EIRE15:1;\r
+ vuint32_t EIRE14:1;\r
+ vuint32_t EIRE13:1;\r
+ vuint32_t EIRE12:1;\r
+ vuint32_t EIRE11:1;\r
+ vuint32_t EIRE10:1;\r
+ vuint32_t EIRE9:1;\r
+ vuint32_t EIRE8:1;\r
+ vuint32_t EIRE7:1;\r
+ vuint32_t EIRE6:1;\r
+ vuint32_t EIRE5:1;\r
+ vuint32_t EIRE4:1;\r
+ vuint32_t EIRE3:1;\r
+ vuint32_t EIRE2:1;\r
+ vuint32_t EIRE1:1;\r
+ vuint32_t EIRE0:1;\r
+ } B;\r
+ } DIRER;\r
+\r
+ union { /* DMA/Interrupt Select Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DIRS3:1;\r
+ vuint32_t DIRS2:1;\r
+ vuint32_t DIRS1:1;\r
+ vuint32_t DIRS0:1;\r
+ } B;\r
+ } DIRSR;\r
+\r
+ union { /* Overrun Status Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t OVF15:1;\r
+ vuint32_t OVF14:1;\r
+ vuint32_t OVF13:1;\r
+ vuint32_t OVF12:1;\r
+ vuint32_t OVF11:1;\r
+ vuint32_t OVF10:1;\r
+ vuint32_t OVF9:1;\r
+ vuint32_t OVF8:1;\r
+ vuint32_t OVF7:1;\r
+ vuint32_t OVF6:1;\r
+ vuint32_t OVF5:1;\r
+ vuint32_t OVF4:1;\r
+ vuint32_t OVF3:1;\r
+ vuint32_t OVF2:1;\r
+ vuint32_t OVF1:1;\r
+ vuint32_t OVF0:1;\r
+ } B;\r
+ } OSR;\r
+\r
+ union { /* Overrun Request Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ORE15:1;\r
+ vuint32_t ORE14:1;\r
+ vuint32_t ORE13:1;\r
+ vuint32_t ORE12:1;\r
+ vuint32_t ORE11:1;\r
+ vuint32_t ORE10:1;\r
+ vuint32_t ORE9:1;\r
+ vuint32_t ORE8:1;\r
+ vuint32_t ORE7:1;\r
+ vuint32_t ORE6:1;\r
+ vuint32_t ORE5:1;\r
+ vuint32_t ORE4:1;\r
+ vuint32_t ORE3:1;\r
+ vuint32_t ORE2:1;\r
+ vuint32_t ORE1:1;\r
+ vuint32_t ORE0:1;\r
+ } B;\r
+ } ORER;\r
+\r
+ union { /* External IRQ Rising-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IREE15:1;\r
+ vuint32_t IREE14:1;\r
+ vuint32_t IREE13:1;\r
+ vuint32_t IREE12:1;\r
+ vuint32_t IREE11:1;\r
+ vuint32_t IREE10:1;\r
+ vuint32_t IREE9:1;\r
+ vuint32_t IREE8:1;\r
+ vuint32_t IREE7:1;\r
+ vuint32_t IREE6:1;\r
+ vuint32_t IREE5:1;\r
+ vuint32_t IREE4:1;\r
+ vuint32_t IREE3:1;\r
+ vuint32_t IREE2:1;\r
+ vuint32_t IREE1:1;\r
+ vuint32_t IREE0:1;\r
+ } B;\r
+ } IREER;\r
+\r
+ union { /* External IRQ Falling-Edge Event Enable Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t IFEE15:1;\r
+ vuint32_t IFEE14:1;\r
+ vuint32_t IFEE13:1;\r
+ vuint32_t IFEE12:1;\r
+ vuint32_t IFEE11:1;\r
+ vuint32_t IFEE10:1;\r
+ vuint32_t IFEE9:1;\r
+ vuint32_t IFEE8:1;\r
+ vuint32_t IFEE7:1;\r
+ vuint32_t IFEE6:1;\r
+ vuint32_t IFEE5:1;\r
+ vuint32_t IFEE4:1;\r
+ vuint32_t IFEE3:1;\r
+ vuint32_t IFEE2:1;\r
+ vuint32_t IFEE1:1;\r
+ vuint32_t IFEE0:1;\r
+ } B;\r
+ } IFEER;\r
+\r
+ union { /* External IRQ Digital Filter Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } IDFR;\r
+\r
+ int32_t SIU_reserved1[3];\r
+\r
+ union { /* Pad Configuration Registers */\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:3;\r
+ vuint16_t PA:3;\r
+ vuint16_t OBE:1;\r
+ vuint16_t IBE:1;\r
+ vuint16_t DSC:2;\r
+ vuint16_t ODE:1;\r
+ vuint16_t HYS:1;\r
+ vuint16_t SRC:2;\r
+ vuint16_t WPE:1;\r
+ vuint16_t WPS:1;\r
+ } B;\r
+ } PCR[512];\r
+\r
+ int16_t SIU_reserved_0[224];\r
+\r
+ union { /* GPIO Pin Data Output Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDO:1;\r
+ } B;\r
+ } GPDO[256];\r
+\r
+ int32_t SIU_reserved_3[64];\r
+\r
+ union { /* GPIO Pin Data Input Registers */\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:7;\r
+ vuint8_t PDI:1;\r
+ } B;\r
+ } GPDI[256];\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TSEL5:2;\r
+ vuint32_t TSEL4:2;\r
+ vuint32_t TSEL3:2;\r
+ vuint32_t TSEL2:2;\r
+ vuint32_t TSEL1:2;\r
+ vuint32_t TSEL0:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } ETISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ESEL15:2;\r
+ vuint32_t ESEL14:2;\r
+ vuint32_t ESEL13:2;\r
+ vuint32_t ESEL12:2;\r
+ vuint32_t ESEL11:2;\r
+ vuint32_t ESEL10:2;\r
+ vuint32_t ESEL9:2;\r
+ vuint32_t ESEL8:2;\r
+ vuint32_t ESEL7:2;\r
+ vuint32_t ESEL6:2;\r
+ vuint32_t ESEL5:2;\r
+ vuint32_t ESEL4:2;\r
+ vuint32_t ESEL3:2;\r
+ vuint32_t ESEL2:2;\r
+ vuint32_t ESEL1:2;\r
+ vuint32_t ESEL0:2;\r
+ } B;\r
+ } EIISR;\r
+\r
+ union { /* IMUX Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SINSELA:2;\r
+ vuint32_t SSSELA:2;\r
+ vuint32_t SCKSELA:2;\r
+ vuint32_t TRIGSELA:2;\r
+ vuint32_t SINSELB:2;\r
+ vuint32_t SSSELB:2;\r
+ vuint32_t SCKSELB:2;\r
+ vuint32_t TRIGSELB:2;\r
+ vuint32_t SINSELC:2;\r
+ vuint32_t SSSELC:2;\r
+ vuint32_t SCKSELC:2;\r
+ vuint32_t TRIGSELC:2;\r
+ vuint32_t SINSELD:2;\r
+ vuint32_t SSSELD:2;\r
+ vuint32_t SCKSELD:2;\r
+ vuint32_t TRIGSELD:2;\r
+ } B;\r
+ } DISR;\r
+\r
+ int32_t SIU_reserved2[29];\r
+\r
+ union { /* Chip Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t MATCH:1;\r
+ vuint32_t DISNEX:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } CCR;\r
+\r
+ union { /* External Clock Configuration Register Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:18;\r
+ vuint32_t ENGDIV:6;\r
+ vuint32_t:4;\r
+ vuint32_t EBTS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EBDF:2;\r
+ } B;\r
+ } ECCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CARL;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRH;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CBRL;\r
+\r
+ int32_t SIU_reserved3[2];\r
+\r
+ union { /* System Clock Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:27;\r
+ vuint32_t BYPASS:1;\r
+ vuint32_t SYSCLKDIV:2;\r
+ vuint32_t:2;\r
+ } B;\r
+ } SYSDIV;\r
+\r
+ union {\r
+ vuint32_t R;\r
+\r
+ } HLT;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } HLTACK;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EMIOS */\r
+/****************************************************************************/\r
+ struct EMIOS_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t GTBE:1;\r
+ vuint32_t ETB:1;\r
+ vuint32_t GPREN:1;\r
+ vuint32_t:6;\r
+ vuint32_t SRV:4;\r
+ vuint32_t GPRE:8;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t F23:1;\r
+ vuint32_t F22:1;\r
+ vuint32_t F21:1;\r
+ vuint32_t F20:1;\r
+ vuint32_t F19:1;\r
+ vuint32_t F18:1;\r
+ vuint32_t F17:1;\r
+ vuint32_t F16:1;\r
+ vuint32_t F15:1;\r
+ vuint32_t F14:1;\r
+ vuint32_t F13:1;\r
+ vuint32_t F12:1;\r
+ vuint32_t F11:1;\r
+ vuint32_t F10:1;\r
+ vuint32_t F9:1;\r
+ vuint32_t F8:1;\r
+ vuint32_t F7:1;\r
+ vuint32_t F6:1;\r
+ vuint32_t F5:1;\r
+ vuint32_t F4:1;\r
+ vuint32_t F3:1;\r
+ vuint32_t F2:1;\r
+ vuint32_t F1:1;\r
+ vuint32_t F0:1;\r
+ } B;\r
+ } GFR; /* Global FLAG Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t OU23:1;\r
+ vuint32_t OU22:1;\r
+ vuint32_t OU21:1;\r
+ vuint32_t OU20:1;\r
+ vuint32_t OU19:1;\r
+ vuint32_t OU18:1;\r
+ vuint32_t OU17:1;\r
+ vuint32_t OU16:1;\r
+ vuint32_t OU15:1;\r
+ vuint32_t OU14:1;\r
+ vuint32_t OU13:1;\r
+ vuint32_t OU12:1;\r
+ vuint32_t OU11:1;\r
+ vuint32_t OU10:1;\r
+ vuint32_t OU9:1;\r
+ vuint32_t OU8:1;\r
+ vuint32_t OU7:1;\r
+ vuint32_t OU6:1;\r
+ vuint32_t OU5:1;\r
+ vuint32_t OU4:1;\r
+ vuint32_t OU3:1;\r
+ vuint32_t OU2:1;\r
+ vuint32_t OU1:1;\r
+ vuint32_t OU0:1;\r
+ } B;\r
+ } OUDR; /* Output Update Disable Register */\r
+\r
+ uint32_t emios_reserved[5];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel A Data Register */\r
+ } CADR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel B Data Register */\r
+ } CBDR;\r
+\r
+ union {\r
+ vuint32_t R; /* Channel Counter Register */\r
+ } CCNTR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FREN:1;\r
+ vuint32_t ODIS:1;\r
+ vuint32_t ODISSL:2;\r
+ vuint32_t UCPRE:2;\r
+ vuint32_t UCPREN:1;\r
+ vuint32_t DMA:1;\r
+ vuint32_t:1;\r
+ vuint32_t IF:4;\r
+ vuint32_t FCK:1;\r
+ vuint32_t FEN:1;\r
+ vuint32_t:3;\r
+ vuint32_t FORCMA:1;\r
+ vuint32_t FORCMB:1;\r
+ vuint32_t:1;\r
+ vuint32_t BSL:2;\r
+ vuint32_t EDSEL:1;\r
+ vuint32_t EDPOL:1;\r
+ vuint32_t MODE:7;\r
+ } B;\r
+ } CCR; /* Channel Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t OVR:1;\r
+ vuint32_t:15;\r
+ vuint32_t OVFL:1;\r
+ vuint32_t:12;\r
+ vuint32_t UCIN:1;\r
+ vuint32_t UCOUT:1;\r
+ vuint32_t FLAG:1;\r
+ } B;\r
+ } CSR; /* Channel Status Register */\r
+ uint32_t emios_channel_reserved[3];\r
+\r
+ } CH[24];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE :ETPU */\r
+/****************************************************************************/\r
+\r
+/***************************Configuration Registers**************************/\r
+\r
+ struct ETPU_tag {\r
+ union { /* MODULE CONFIGURATION REGISTER */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t GEC:1; /* Global Exception Clear */\r
+ vuint32_t:3;\r
+ vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */\r
+\r
+ vuint32_t:1; /* For single ETPU implementations */\r
+\r
+ vuint32_t:3;\r
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */\r
+ vuint32_t:5;\r
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */\r
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */\r
+ vuint32_t:2;\r
+ vuint32_t VIS:1; /* SCM Visability */\r
+ vuint32_t:5;\r
+ vuint32_t GTBE:1; /* Global Time Base Enable */\r
+ } B;\r
+ } MCR;\r
+\r
+ union { /* COHERENT DUAL-PARAMETER CONTROL */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t STS:1; /* Start Status bit */\r
+ vuint32_t CTBASE:5; /* Channel Transfer Base */\r
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */\r
+ vuint32_t PWIDTH:1; /* Parameter Width */\r
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */\r
+ vuint32_t WR:1;\r
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */\r
+ } B;\r
+ } CDCR;\r
+\r
+ uint32_t etpu_reserved1;\r
+\r
+ union { /* MISC Compare Register */\r
+ vuint32_t R;\r
+ } MISCCMPR;\r
+\r
+ union { /* SCM off-range Date Register */\r
+ vuint32_t R;\r
+ } SCMOFFDATAR;\r
+\r
+ union { /* ETPU_A Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEND:1; /* Force END */\r
+ vuint32_t MDIS:1; /* Low power Stop */\r
+ vuint32_t:1;\r
+ vuint32_t STF:1; /* Stop Flag */\r
+ vuint32_t:4;\r
+ vuint32_t HLTF:1; /* Halt Mode Flag */\r
+ vuint32_t:4;\r
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */\r
+ vuint32_t CDFC:2;\r
+ vuint32_t:9;\r
+ vuint32_t ETB:5; /* Entry Table Base */\r
+ } B;\r
+ } ECR_A;\r
+ uint32_t etpu_reserved3; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved4;\r
+\r
+ union { /* ETPU_A Timebase Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */\r
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */\r
+ vuint32_t:1;\r
+ vuint32_t AM:1; /* Angle Mode */\r
+ vuint32_t:3;\r
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */\r
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */\r
+ vuint32_t:6;\r
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */\r
+ } B;\r
+ } TBCR_A;\r
+\r
+ union { /* ETPU_A TCR1 Visibility Register */\r
+ vuint32_t R;\r
+ } TB1R_A;\r
+\r
+ union { /* ETPU_A TCR2 Visibility Register */\r
+ vuint32_t R;\r
+ } TB2R_A;\r
+\r
+ union { /* ETPU_A STAC Configuration Register */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REN1:1; /* Resource Enable TCR1 */\r
+ vuint32_t RSC1:1; /* Resource Control TCR1 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID1:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV1:4; /* Resource Server Slot */\r
+ vuint32_t REN2:1; /* Resource Enable TCR2 */\r
+ vuint32_t RSC2:1; /* Resource Control TCR2 */\r
+ vuint32_t:2;\r
+ vuint32_t SERVER_ID2:4;\r
+ vuint32_t:4;\r
+ vuint32_t SRV2:4; /* Resource Server Slot */\r
+ } B;\r
+ } REDCR_A;\r
+\r
+ uint32_t etpu_reserved5[4];\r
+ uint32_t etpu_reserved6[4]; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved7[108];\r
+\r
+/*****************************Status and Control Registers**************************/\r
+\r
+ union { /* ETPU_A Channel Interrut Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */\r
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */\r
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */\r
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */\r
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */\r
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */\r
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */\r
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */\r
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */\r
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */\r
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */\r
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */\r
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */\r
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */\r
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */\r
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */\r
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */\r
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */\r
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */\r
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */\r
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */\r
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */\r
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */\r
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */\r
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */\r
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */\r
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */\r
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */\r
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */\r
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */\r
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */\r
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */\r
+ } B;\r
+ } CISR_A;\r
+ uint32_t etpu_reserved8; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved9[2];\r
+\r
+ union { /* ETPU_A Data Transfer Request Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */\r
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */\r
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */\r
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */\r
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */\r
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */\r
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */\r
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */\r
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */\r
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */\r
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */\r
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */\r
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */\r
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */\r
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */\r
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */\r
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */\r
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */\r
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */\r
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */\r
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */\r
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */\r
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */\r
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */\r
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */\r
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */\r
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */\r
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */\r
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */\r
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */\r
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */\r
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */\r
+ } B;\r
+ } CDTRSR_A;\r
+ uint32_t etpu_reserved10; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved11[2];\r
+\r
+ union { /* ETPU_A Interruput Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */\r
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */\r
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */\r
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */\r
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */\r
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */\r
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */\r
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */\r
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */\r
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */\r
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */\r
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */\r
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */\r
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */\r
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */\r
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */\r
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */\r
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */\r
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */\r
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */\r
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */\r
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */\r
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */\r
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */\r
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */\r
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */\r
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */\r
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */\r
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */\r
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */\r
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */\r
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */\r
+ } B;\r
+ } CIOSR_A;\r
+ uint32_t etpu_reserved12; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved13[2];\r
+\r
+ union { /* ETPU_A Data Transfer Overflow Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */\r
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */\r
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */\r
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */\r
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */\r
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */\r
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */\r
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */\r
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */\r
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */\r
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */\r
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */\r
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */\r
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */\r
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */\r
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */\r
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */\r
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */\r
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */\r
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */\r
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */\r
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */\r
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */\r
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */\r
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */\r
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */\r
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */\r
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */\r
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */\r
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */\r
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */\r
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */\r
+ } B;\r
+ } CDTROSR_A;\r
+ uint32_t etpu_reserved14; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved15[2];\r
+\r
+ union { /* ETPU_A Channel Interruput Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */\r
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */\r
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */\r
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */\r
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */\r
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */\r
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */\r
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */\r
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */\r
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */\r
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */\r
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */\r
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */\r
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */\r
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */\r
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */\r
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */\r
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */\r
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */\r
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */\r
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */\r
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */\r
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */\r
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */\r
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */\r
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */\r
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */\r
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */\r
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */\r
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */\r
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */\r
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */\r
+ } B;\r
+ } CIER_A;\r
+ uint32_t etpu_reserved16; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved17[2];\r
+\r
+ union { /* ETPU_A Channel Data Transfer Request Enable */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */\r
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */\r
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */\r
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */\r
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */\r
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */\r
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */\r
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */\r
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */\r
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */\r
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */\r
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */\r
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */\r
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */\r
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */\r
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */\r
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */\r
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */\r
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */\r
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */\r
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */\r
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */\r
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */\r
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */\r
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */\r
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */\r
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */\r
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */\r
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */\r
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */\r
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */\r
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */\r
+ } B;\r
+ } CDTRER_A;\r
+ uint32_t etpu_reserved19; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20[10];\r
+ union { /* ETPU_A Channel Pending Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SR31:1; /* Channel 31 Pending Service Status */\r
+ vuint32_t SR30:1; /* Channel 30 Pending Service Status */\r
+ vuint32_t SR29:1; /* Channel 29 Pending Service Status */\r
+ vuint32_t SR28:1; /* Channel 28 Pending Service Status */\r
+ vuint32_t SR27:1; /* Channel 27 Pending Service Status */\r
+ vuint32_t SR26:1; /* Channel 26 Pending Service Status */\r
+ vuint32_t SR25:1; /* Channel 25 Pending Service Status */\r
+ vuint32_t SR24:1; /* Channel 24 Pending Service Status */\r
+ vuint32_t SR23:1; /* Channel 23 Pending Service Status */\r
+ vuint32_t SR22:1; /* Channel 22 Pending Service Status */\r
+ vuint32_t SR21:1; /* Channel 21 Pending Service Status */\r
+ vuint32_t SR20:1; /* Channel 20 Pending Service Status */\r
+ vuint32_t SR19:1; /* Channel 19 Pending Service Status */\r
+ vuint32_t SR18:1; /* Channel 18 Pending Service Status */\r
+ vuint32_t SR17:1; /* Channel 17 Pending Service Status */\r
+ vuint32_t SR16:1; /* Channel 16 Pending Service Status */\r
+ vuint32_t SR15:1; /* Channel 15 Pending Service Status */\r
+ vuint32_t SR14:1; /* Channel 14 Pending Service Status */\r
+ vuint32_t SR13:1; /* Channel 13 Pending Service Status */\r
+ vuint32_t SR12:1; /* Channel 12 Pending Service Status */\r
+ vuint32_t SR11:1; /* Channel 11 Pending Service Status */\r
+ vuint32_t SR10:1; /* Channel 10 Pending Service Status */\r
+ vuint32_t SR9:1; /* Channel 9 Pending Service Status */\r
+ vuint32_t SR8:1; /* Channel 8 Pending Service Status */\r
+ vuint32_t SR7:1; /* Channel 7 Pending Service Status */\r
+ vuint32_t SR6:1; /* Channel 6 Pending Service Status */\r
+ vuint32_t SR5:1; /* Channel 5 Pending Service Status */\r
+ vuint32_t SR4:1; /* Channel 4 Pending Service Status */\r
+ vuint32_t SR3:1; /* Channel 3 Pending Service Status */\r
+ vuint32_t SR2:1; /* Channel 2 Pending Service Status */\r
+ vuint32_t SR1:1; /* Channel 1 Pending Service Status */\r
+ vuint32_t SR0:1; /* Channel 0 Pending Service Status */\r
+ } B;\r
+ } CPSSR_A;\r
+ uint32_t etpu_reserved22; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved20a[2];\r
+\r
+ union { /* ETPU_A Channel Service Status */\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t SS31:1; /* Channel 31 Service Status */\r
+ vuint32_t SS30:1; /* Channel 30 Service Status */\r
+ vuint32_t SS29:1; /* Channel 29 Service Status */\r
+ vuint32_t SS28:1; /* Channel 28 Service Status */\r
+ vuint32_t SS27:1; /* Channel 27 Service Status */\r
+ vuint32_t SS26:1; /* Channel 26 Service Status */\r
+ vuint32_t SS25:1; /* Channel 25 Service Status */\r
+ vuint32_t SS24:1; /* Channel 24 Service Status */\r
+ vuint32_t SS23:1; /* Channel 23 Service Status */\r
+ vuint32_t SS22:1; /* Channel 22 Service Status */\r
+ vuint32_t SS21:1; /* Channel 21 Service Status */\r
+ vuint32_t SS20:1; /* Channel 20 Service Status */\r
+ vuint32_t SS19:1; /* Channel 19 Service Status */\r
+ vuint32_t SS18:1; /* Channel 18 Service Status */\r
+ vuint32_t SS17:1; /* Channel 17 Service Status */\r
+ vuint32_t SS16:1; /* Channel 16 Service Status */\r
+ vuint32_t SS15:1; /* Channel 15 Service Status */\r
+ vuint32_t SS14:1; /* Channel 14 Service Status */\r
+ vuint32_t SS13:1; /* Channel 13 Service Status */\r
+ vuint32_t SS12:1; /* Channel 12 Service Status */\r
+ vuint32_t SS11:1; /* Channel 11 Service Status */\r
+ vuint32_t SS10:1; /* Channel 10 Service Status */\r
+ vuint32_t SS9:1; /* Channel 9 Service Status */\r
+ vuint32_t SS8:1; /* Channel 8 Service Status */\r
+ vuint32_t SS7:1; /* Channel 7 Service Status */\r
+ vuint32_t SS6:1; /* Channel 6 Service Status */\r
+ vuint32_t SS5:1; /* Channel 5 Service Status */\r
+ vuint32_t SS4:1; /* Channel 4 Service Status */\r
+ vuint32_t SS3:1; /* Channel 3 Service Status */\r
+ vuint32_t SS2:1; /* Channel 2 Service Status */\r
+ vuint32_t SS1:1; /* Channel 1 Service Status */\r
+ vuint32_t SS0:1; /* Channel 0 Service Status */\r
+ } B;\r
+ } CSSR_A;\r
+ uint32_t etpu_reserved22a; /* For single ETPU implementations */\r
+\r
+ uint32_t etpu_reserved23[90];\r
+\r
+/*****************************Channels********************************/\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R; /* Channel Configuration Register */\r
+ struct {\r
+ vuint32_t CIE:1; /* Channel Interruput Enable */\r
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */\r
+ vuint32_t CPR:2; /* Channel Priority */\r
+ vuint32_t:3;\r
+ vuint32_t ETCS:1; /* Entry Table Condition Select */\r
+ vuint32_t:3;\r
+ vuint32_t CFS:5; /* Channel Function Select */\r
+ vuint32_t ODIS:1; /* Output disable */\r
+ vuint32_t OPOL:1; /* output polarity */\r
+ vuint32_t:3;\r
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */\r
+ } B;\r
+ } CR;\r
+ union {\r
+ vuint32_t R; /* Channel Status Control Register */\r
+ struct {\r
+ vuint32_t CIS:1; /* Channel Interruput Status */\r
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t DTRS:1; /* Data Transfer Status */\r
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */\r
+ vuint32_t:6;\r
+ vuint32_t IPS:1; /* Input Pin State */\r
+ vuint32_t OPS:1; /* Output Pin State */\r
+ vuint32_t OBE:1; /* Output Buffer Enable */\r
+ vuint32_t:11;\r
+ vuint32_t FM1:1; /* Function mode */\r
+ vuint32_t FM0:1; /* Function mode */\r
+ } B;\r
+ } SCR;\r
+ union {\r
+ vuint32_t R; /* Channel Host Service Request Register */\r
+ struct {\r
+ vuint32_t:29; /* Host Service Request */\r
+ vuint32_t HSR:3;\r
+ } B;\r
+ } HSRR;\r
+ uint32_t etpu_reserved23;\r
+ } CHAN[127];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : XBAR CrossBar */\r
+/****************************************************************************/\r
+ struct XBAR_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR0; /* Master Priority Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved1[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR0; /* General Purpose Control Register for Slave Port 0 */\r
+\r
+ uint32_t xbar_reserved2[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR1; /* Master Priority Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved3[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR1; /* General Purpose Control Register for Slave Port 1 */\r
+\r
+ uint32_t xbar_reserved4[123];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR3; /* Master Priority Register for Slave Port 3 */\r
+\r
+ uint32_t xbar_reserved5[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR3; /* General Purpose Control Register for Slave Port 3 */\r
+ uint32_t xbar_reserved6[187];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR6; /* Master Priority Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved7[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR6; /* General Purpose Control Register for Slave Port 6 */\r
+\r
+ uint32_t xbar_reserved8[59];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR4:3; /* Z3 core data and Nexus */\r
+\r
+ vuint32_t:4;\r
+\r
+ vuint32_t:1;\r
+ vuint32_t MSTR2:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR1:3;\r
+ vuint32_t:1;\r
+ vuint32_t MSTR0:3;\r
+ } B;\r
+ } MPR7; /* Master Priority Register for Slave Port 7 */\r
+\r
+ uint32_t xbar_reserved9[3];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RO:1;\r
+ vuint32_t:21;\r
+ vuint32_t ARB:2;\r
+ vuint32_t:2;\r
+ vuint32_t PCTL:2;\r
+ vuint32_t:1;\r
+ vuint32_t PARK:3;\r
+ } B;\r
+ } SGPCR7; /* General Purpose Control Register for Slave Port 7 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : ECSM */\r
+/****************************************************************************/\r
+ struct ECSM_tag {\r
+\r
+ uint32_t ecsm_reserved1[5];\r
+\r
+ uint16_t ecsm_reserved2;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ } SWTCR; //Software Watchdog Timer Control\r
+\r
+ uint8_t ecsm_reserved3[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTSR; //SWT Service Register\r
+\r
+ uint8_t ecsm_reserved4[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ } SWTIR; //SWT Interrupt Register\r
+\r
+ uint32_t ecsm_reserved5a[1];\r
+ uint32_t ecsm_reserved5b[1];\r
+\r
+ uint32_t ecsm_reserved5c[6];\r
+\r
+ uint8_t ecsm_reserved6[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t ERNCR:1;\r
+ vuint8_t EFNCR:1;\r
+ } B;\r
+ } ECR; //ECC Configuration Register\r
+\r
+ uint8_t mcm_reserved8[3];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t RNCE:1;\r
+ vuint8_t FNCE:1;\r
+ } B;\r
+ } ESR; //ECC Status Register\r
+\r
+ uint16_t ecsm_reserved9;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:6;\r
+ vuint16_t FRCNCI:1;\r
+ vuint16_t FR1NCI:1;\r
+ vuint16_t:1;\r
+ vuint16_t ERRBIT:7;\r
+ } B;\r
+ } EEGR; //ECC Error Generation Register\r
+\r
+ uint32_t ecsm_reserved10;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEAR:32;\r
+ } B;\r
+ } FEAR; //Flash ECC Address Register\r
+\r
+ uint16_t ecsm_reserved11;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t FEMR:4;\r
+ } B;\r
+ } FEMR; //Flash ECC Master Register\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } FEAT; //Flash ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDH:32;\r
+ } B;\r
+ } FEDRH; //Flash ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t FEDL:32;\r
+ } B;\r
+ } FEDRL; //Flash ECC Data Low Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REAR:32;\r
+ } B;\r
+ } REAR; //RAM ECC Address\r
+\r
+ uint8_t ecsm_reserved12[2];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t REMR:4;\r
+ } B;\r
+ } REMR; //RAM ECC Master\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t WRITE:1;\r
+ vuint8_t SIZE:3;\r
+ vuint8_t PROT0:1;\r
+ vuint8_t PROT1:1;\r
+ vuint8_t PROT2:1;\r
+ vuint8_t PROT3:1;\r
+ } B;\r
+ } REAT; // RAM ECC Attributes Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDH:32;\r
+ } B;\r
+ } REDRH; //RAM ECC Data High Register\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t REDL:32;\r
+ } B;\r
+ } REDRL; //RAMECC Data Low Register\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eDMA */\r
+/****************************************************************************/\r
+ struct EDMA_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t GRP3PRI:2;\r
+ vuint32_t GRP2PRI:2;\r
+ vuint32_t GRP1PRI:2;\r
+ vuint32_t GRP0PRI:2;\r
+ vuint32_t:4;\r
+ vuint32_t ERGA:1;\r
+ vuint32_t ERCA:1;\r
+ vuint32_t EDBG:1;\r
+ vuint32_t EBW:1;\r
+ } B;\r
+ } CR; /* Control Register */\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VLD:1;\r
+ vuint32_t:15;\r
+ vuint32_t GPE:1;\r
+ vuint32_t CPE:1;\r
+ vuint32_t ERRCHN:6;\r
+ vuint32_t SAE:1;\r
+ vuint32_t SOE:1;\r
+ vuint32_t DAE:1;\r
+ vuint32_t DOE:1;\r
+ vuint32_t NCE:1;\r
+ vuint32_t SGE:1;\r
+ vuint32_t SBE:1;\r
+ vuint32_t DBE:1;\r
+ } B;\r
+ } ESR; /* Error Status Register */\r
+ uint32_t edma_reserved_erqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERQ31:1;\r
+ vuint32_t ERQ30:1;\r
+ vuint32_t ERQ29:1;\r
+ vuint32_t ERQ28:1;\r
+ vuint32_t ERQ27:1;\r
+ vuint32_t ERQ26:1;\r
+ vuint32_t ERQ25:1;\r
+ vuint32_t ERQ24:1;\r
+ vuint32_t ERQ23:1;\r
+ vuint32_t ERQ22:1;\r
+ vuint32_t ERQ21:1;\r
+ vuint32_t ERQ20:1;\r
+ vuint32_t ERQ19:1;\r
+ vuint32_t ERQ18:1;\r
+ vuint32_t ERQ17:1;\r
+ vuint32_t ERQ16:1;\r
+ vuint32_t ERQ15:1;\r
+ vuint32_t ERQ14:1;\r
+ vuint32_t ERQ13:1;\r
+ vuint32_t ERQ12:1;\r
+ vuint32_t ERQ11:1;\r
+ vuint32_t ERQ10:1;\r
+ vuint32_t ERQ09:1;\r
+ vuint32_t ERQ08:1;\r
+ vuint32_t ERQ07:1;\r
+ vuint32_t ERQ06:1;\r
+ vuint32_t ERQ05:1;\r
+ vuint32_t ERQ04:1;\r
+ vuint32_t ERQ03:1;\r
+ vuint32_t ERQ02:1;\r
+ vuint32_t ERQ01:1;\r
+ vuint32_t ERQ00:1;\r
+ } B;\r
+ } ERQRL; /* DMA Enable Request Register Low */\r
+ uint32_t edma_reserved_eeirh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t EEI31:1;\r
+ vuint32_t EEI30:1;\r
+ vuint32_t EEI29:1;\r
+ vuint32_t EEI28:1;\r
+ vuint32_t EEI27:1;\r
+ vuint32_t EEI26:1;\r
+ vuint32_t EEI25:1;\r
+ vuint32_t EEI24:1;\r
+ vuint32_t EEI23:1;\r
+ vuint32_t EEI22:1;\r
+ vuint32_t EEI21:1;\r
+ vuint32_t EEI20:1;\r
+ vuint32_t EEI19:1;\r
+ vuint32_t EEI18:1;\r
+ vuint32_t EEI17:1;\r
+ vuint32_t EEI16:1;\r
+ vuint32_t EEI15:1;\r
+ vuint32_t EEI14:1;\r
+ vuint32_t EEI13:1;\r
+ vuint32_t EEI12:1;\r
+ vuint32_t EEI11:1;\r
+ vuint32_t EEI10:1;\r
+ vuint32_t EEI09:1;\r
+ vuint32_t EEI08:1;\r
+ vuint32_t EEI07:1;\r
+ vuint32_t EEI06:1;\r
+ vuint32_t EEI05:1;\r
+ vuint32_t EEI04:1;\r
+ vuint32_t EEI03:1;\r
+ vuint32_t EEI02:1;\r
+ vuint32_t EEI01:1;\r
+ vuint32_t EEI00:1;\r
+ } B;\r
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SERQR; /* DMA Set Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CERQR; /* DMA Clear Enable Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CIRQR; /* DMA Clear Interrupt Request Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CER; /* DMA Clear error Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } SSBR; /* Set Start Bit Register */\r
+ union {\r
+ vuint8_t R;\r
+ vuint8_t B;\r
+ } CDSBR; /* Clear Done Status Bit Register */\r
+ uint32_t edma_reserved_irqrh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t INT31:1;\r
+ vuint32_t INT30:1;\r
+ vuint32_t INT29:1;\r
+ vuint32_t INT28:1;\r
+ vuint32_t INT27:1;\r
+ vuint32_t INT26:1;\r
+ vuint32_t INT25:1;\r
+ vuint32_t INT24:1;\r
+ vuint32_t INT23:1;\r
+ vuint32_t INT22:1;\r
+ vuint32_t INT21:1;\r
+ vuint32_t INT20:1;\r
+ vuint32_t INT19:1;\r
+ vuint32_t INT18:1;\r
+ vuint32_t INT17:1;\r
+ vuint32_t INT16:1;\r
+ vuint32_t INT15:1;\r
+ vuint32_t INT14:1;\r
+ vuint32_t INT13:1;\r
+ vuint32_t INT12:1;\r
+ vuint32_t INT11:1;\r
+ vuint32_t INT10:1;\r
+ vuint32_t INT09:1;\r
+ vuint32_t INT08:1;\r
+ vuint32_t INT07:1;\r
+ vuint32_t INT06:1;\r
+ vuint32_t INT05:1;\r
+ vuint32_t INT04:1;\r
+ vuint32_t INT03:1;\r
+ vuint32_t INT02:1;\r
+ vuint32_t INT01:1;\r
+ vuint32_t INT00:1;\r
+ } B;\r
+ } IRQRL; /* DMA Interrupt Request Low */\r
+ uint32_t edma_reserved_erh;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t ERR31:1;\r
+ vuint32_t ERR30:1;\r
+ vuint32_t ERR29:1;\r
+ vuint32_t ERR28:1;\r
+ vuint32_t ERR27:1;\r
+ vuint32_t ERR26:1;\r
+ vuint32_t ERR25:1;\r
+ vuint32_t ERR24:1;\r
+ vuint32_t ERR23:1;\r
+ vuint32_t ERR22:1;\r
+ vuint32_t ERR21:1;\r
+ vuint32_t ERR20:1;\r
+ vuint32_t ERR19:1;\r
+ vuint32_t ERR18:1;\r
+ vuint32_t ERR17:1;\r
+ vuint32_t ERR16:1;\r
+ vuint32_t ERR15:1;\r
+ vuint32_t ERR14:1;\r
+ vuint32_t ERR13:1;\r
+ vuint32_t ERR12:1;\r
+ vuint32_t ERR11:1;\r
+ vuint32_t ERR10:1;\r
+ vuint32_t ERR09:1;\r
+ vuint32_t ERR08:1;\r
+ vuint32_t ERR07:1;\r
+ vuint32_t ERR06:1;\r
+ vuint32_t ERR05:1;\r
+ vuint32_t ERR04:1;\r
+ vuint32_t ERR03:1;\r
+ vuint32_t ERR02:1;\r
+ vuint32_t ERR01:1;\r
+ vuint32_t ERR00:1;\r
+ } B;\r
+ } ERL; /* DMA Error Low */\r
+ uint32_t edma_reserved1[52];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t ECP:1;\r
+\r
+ vuint8_t:1;\r
+ vuint8_t GRPPRI:2;\r
+ vuint8_t CHPRI:4;\r
+\r
+ } B;\r
+ } CPR[64]; /* Channel n Priority */\r
+\r
+ uint32_t edma_reserved2[944];\r
+\r
+/****************************************************************************/\r
+/* DMA2 Transfer Control Descriptor */\r
+/****************************************************************************/\r
+\r
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITER:15;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
+ vuint16_t BITER:15;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+\r
+ };\r
+\r
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+\r
+ struct tcd_alt1_t {\r
+ vuint32_t SADDR; /* source address */\r
+\r
+ vuint16_t SMOD:5; /* source address modulo */\r
+ vuint16_t SSIZE:3; /* source transfer size */\r
+ vuint16_t DMOD:5; /* destination address modulo */\r
+ vuint16_t DSIZE:3; /* destination transfer size */\r
+ vint16_t SOFF; /* signed source address offset */\r
+\r
+ vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
+\r
+ vint32_t SLAST; /* last destination address adjustment, or\r
+\r
+ scatter/gather address (if e_sg = 1) */\r
+ vuint32_t DADDR; /* destination address */\r
+\r
+ vuint16_t CITERE_LINK:1;\r
+ vuint16_t CITERLINKCH:6;\r
+ vuint16_t CITER:9;\r
+\r
+ vint16_t DOFF; /* signed destination address offset */\r
+\r
+ vint32_t DLAST_SGA;\r
+\r
+ vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
+ vuint16_t BITERLINKCH:6;\r
+ vuint16_t BITER:9;\r
+\r
+ vuint16_t BWC:2; /* bandwidth control */\r
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
+ vuint16_t DONE:1; /* channel done */\r
+ vuint16_t ACTIVE:1; /* channel active */\r
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
+ vuint16_t D_REQ:1; /* disable ipd_req when done */\r
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
+ vuint16_t START:1; /* explicit channel start */\r
+ } TCD[64]; /* transfer_control_descriptor */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : INTC */\r
+/****************************************************************************/\r
+ struct INTC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:26;\r
+ vuint32_t VTES:1;\r
+ vuint32_t:4;\r
+ vuint32_t HVEN:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t INTC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t PRI:4;\r
+ } B;\r
+ } CPR; /* Current Priority Register */\r
+\r
+ uint32_t intc_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t VTBA:21;\r
+ vuint32_t INTVEC:9;\r
+ vuint32_t:2;\r
+ } B;\r
+ } IACKR; /* Interrupt Acknowledge Register */\r
+\r
+ uint32_t intc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } EOIR; /* End of Interrupt Register */\r
+\r
+ uint32_t intc_reserved3;\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:6;\r
+ vuint8_t SET:1;\r
+ vuint8_t CLR:1;\r
+ } B;\r
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */\r
+\r
+ uint32_t intc_reserved4[6];\r
+\r
+ union {\r
+ vuint8_t R;\r
+ struct {\r
+ vuint8_t:4;\r
+ vuint8_t PRI:4;\r
+ } B;\r
+ } PSR[358]; /* Software Set/Clear Interrupt Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : EQADC */\r
+/****************************************************************************/\r
+ struct EQADC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:24;\r
+ vuint32_t ICEA0:1;\r
+ vuint32_t ICEA1:1;\r
+ vuint32_t:1;\r
+ vuint32_t ESSIE:2;\r
+ vuint32_t:1;\r
+ vuint32_t DBG:2;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ int32_t EQADC_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:6;\r
+ vuint32_t NMF:26;\r
+ } B;\r
+ } NMSFR; /* Null Message Send Format Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:28;\r
+ vuint32_t DFL:4;\r
+ } B;\r
+ } ETDFR; /* External Trigger Digital Filter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFPUSH:32;\r
+ } B;\r
+ } CFPR[6]; /* CFIFO Push Registers */\r
+\r
+ uint32_t eqadc_reserved1;\r
+\r
+ uint32_t eqadc_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RFPOP:16;\r
+ } B;\r
+ } RFPR[6]; /* Result FIFO Pop Registers */\r
+\r
+ uint32_t eqadc_reserved3;\r
+\r
+ uint32_t eqadc_reserved4;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t SSE:1;\r
+ vuint16_t CFINV:1;\r
+ vuint16_t:1;\r
+ vuint16_t MODE:4;\r
+ vuint16_t:4;\r
+ } B;\r
+ } CFCR[6]; /* CFIFO Control Registers */\r
+\r
+ uint32_t eqadc_reserved5;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t NCIE:1;\r
+ vuint16_t TORIE:1;\r
+ vuint16_t PIE:1;\r
+ vuint16_t EOQIE:1;\r
+ vuint16_t CFUIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t CFFE:1;\r
+ vuint16_t CFFS:1;\r
+ vuint16_t:4;\r
+ vuint16_t RFOIE:1;\r
+ vuint16_t:1;\r
+ vuint16_t RFDE:1;\r
+ vuint16_t RFDS:1;\r
+ } B;\r
+ } IDCR[6]; /* Interrupt and DMA Control Registers */\r
+\r
+ uint32_t eqadc_reserved6;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t NCF:1;\r
+ vuint32_t TORF:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t CFUF:1;\r
+ vuint32_t SSS:1;\r
+ vuint32_t CFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t CFCTR:4;\r
+ vuint32_t TNXTPTR:4;\r
+ vuint32_t RFCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } FISR[6]; /* FIFO and Interrupt Status Registers */\r
+\r
+ uint32_t eqadc_reserved7;\r
+\r
+ uint32_t eqadc_reserved8;\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t:5;\r
+ vuint16_t TCCF:11;\r
+ } B;\r
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */\r
+\r
+ uint32_t eqadc_reserved9;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB0:4;\r
+ vuint32_t TC_LCFTCB0:11;\r
+ } B;\r
+ } CFSSR0; /* CFIFO Status Register 0 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:5;\r
+ vuint32_t LCFTCB1:4;\r
+ vuint32_t TC_LCFTCB1:11;\r
+ } B;\r
+ } CFSSR1; /* CFIFO Status Register 1 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:4;\r
+ vuint32_t ECBNI:1;\r
+ vuint32_t LCFTSSI:4;\r
+ vuint32_t TC_LCFTSSI:11;\r
+ } B;\r
+ } CFSSR2; /* CFIFO Status Register 2 */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CFS0:2;\r
+ vuint32_t CFS1:2;\r
+ vuint32_t CFS2:2;\r
+ vuint32_t CFS3:2;\r
+ vuint32_t CFS4:2;\r
+ vuint32_t CFS5:2;\r
+ vuint32_t:20;\r
+ } B;\r
+ } CFSR;\r
+\r
+ uint32_t eqadc_reserved11;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:21;\r
+ vuint32_t MDT:3;\r
+ vuint32_t:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } SSICR; /* SSI Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t RDV:1;\r
+ vuint32_t:5;\r
+ vuint32_t RDATA:26;\r
+ } B;\r
+ } SSIRDR; /* SSI Recieve Data Register */\r
+\r
+ uint32_t eqadc_reserved12[17];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved13[12];\r
+\r
+ } CF[6];\r
+\r
+ uint32_t eqadc_reserved14[32];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:32;\r
+ } B;\r
+ } R[4];\r
+\r
+ uint32_t eqadc_reserved15[12];\r
+\r
+ } RF[6];\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : DSPI */\r
+/****************************************************************************/\r
+ struct DSPI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MSTR:1;\r
+ vuint32_t CONT_SCKE:1;\r
+ vuint32_t DCONF:2;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t MTFE:1;\r
+ vuint32_t PCSSE:1;\r
+ vuint32_t ROOE:1;\r
+ vuint32_t:2;\r
+ vuint32_t PCSIS5:1;\r
+ vuint32_t PCSIS4:1;\r
+ vuint32_t PCSIS3:1;\r
+ vuint32_t PCSIS2:1;\r
+ vuint32_t PCSIS1:1;\r
+ vuint32_t PCSIS0:1;\r
+ vuint32_t DOZE:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t DIS_TXF:1;\r
+ vuint32_t DIS_RXF:1;\r
+ vuint32_t CLR_TXF:1;\r
+ vuint32_t CLR_RXF:1;\r
+ vuint32_t SMPL_PT:2;\r
+ vuint32_t:7;\r
+ vuint32_t HALT:1;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ uint32_t dspi_reserved1;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCNT:16;\r
+ vuint32_t:16;\r
+ } B;\r
+ } TCR;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t DBR:1;\r
+ vuint32_t FMSZ:4;\r
+ vuint32_t CPOL:1;\r
+ vuint32_t CPHA:1;\r
+ vuint32_t LSBFE:1;\r
+ vuint32_t PCSSCK:2;\r
+ vuint32_t PASC:2;\r
+ vuint32_t PDT:2;\r
+ vuint32_t PBR:2;\r
+ vuint32_t CSSCK:4;\r
+ vuint32_t ASC:4;\r
+ vuint32_t DT:4;\r
+ vuint32_t BR:4;\r
+ } B;\r
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCF:1;\r
+ vuint32_t TXRXS:1;\r
+ vuint32_t:1;\r
+ vuint32_t EOQF:1;\r
+ vuint32_t TFUF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFF:1;\r
+ vuint32_t:5;\r
+ vuint32_t RFOF:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDF:1;\r
+ vuint32_t:1;\r
+ vuint32_t TXCTR:4;\r
+ vuint32_t TXNXTPTR:4;\r
+ vuint32_t RXCTR:4;\r
+ vuint32_t POPNXTPTR:4;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TCFRE:1;\r
+ vuint32_t:2;\r
+ vuint32_t EOQFRE:1;\r
+ vuint32_t TFUFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t TFFFRE:1;\r
+ vuint32_t TFFFDIRS:1;\r
+ vuint32_t:4;\r
+ vuint32_t RFOFRE:1;\r
+ vuint32_t:1;\r
+ vuint32_t RFDFRE:1;\r
+ vuint32_t RFDFDIRS:1;\r
+ vuint32_t:16;\r
+ } B;\r
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t CONT:1;\r
+ vuint32_t CTAS:3;\r
+ vuint32_t EOQ:1;\r
+ vuint32_t CTCNT:1;\r
+ vuint32_t:4;\r
+ vuint32_t PCS5:1;\r
+ vuint32_t PCS4:1;\r
+ vuint32_t PCS3:1;\r
+ vuint32_t PCS2:1;\r
+ vuint32_t PCS1:1;\r
+ vuint32_t PCS0:1;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } PUSHR; /* PUSH TX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } POPR; /* POP RX FIFO Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TXCMD:16;\r
+ vuint32_t TXDATA:16;\r
+ } B;\r
+ } TXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_txf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXDATA:16;\r
+ } B;\r
+ } RXFR[4]; /* Transmit FIFO Registers */\r
+\r
+ vuint32_t DSPI_reserved_rxf[12];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MTOE:1;\r
+ vuint32_t:1;\r
+ vuint32_t MTOCNT:6;\r
+ vuint32_t:3;\r
+ vuint32_t TSBC:1;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t TPOL:1;\r
+ vuint32_t TRRE:1;\r
+ vuint32_t CID:1;\r
+ vuint32_t DCONT:1;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:6;\r
+ vuint32_t DPCS5:1;\r
+ vuint32_t DPCS4:1;\r
+ vuint32_t DPCS3:1;\r
+ vuint32_t DPCS2:1;\r
+ vuint32_t DPCS1:1;\r
+ vuint32_t DPCS0:1;\r
+ } B;\r
+ } DSICR; /* DSI Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t SER_DATA:16;\r
+ } B;\r
+ } SDR; /* DSI Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t ASER_DATA:16;\r
+ } B;\r
+ } ASDR; /* DSI Alternate Serialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t COMP_DATA:16;\r
+ } B;\r
+ } COMPR; /* DSI Transmit Comparison Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t DESER_DATA:16;\r
+ } B;\r
+ } DDR; /* DSI deserialization Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:2;\r
+ vuint32_t TSBCNT:6;\r
+ vuint32_t:4;\r
+ vuint32_t TXSS:1;\r
+ vuint32_t:4;\r
+ vuint32_t DSICTAS:3;\r
+ vuint32_t:4;\r
+ vuint32_t DPCS1_7:1;\r
+ vuint32_t DPCS1_6:1;\r
+ vuint32_t DPCS1_5:1;\r
+ vuint32_t DPCS1_4:1;\r
+ vuint32_t DPCS1_3:1;\r
+ vuint32_t DPCS1_2:1;\r
+ vuint32_t DPCS1_1:1;\r
+ vuint32_t DPCS1_0:1;\r
+ } B;\r
+ } DSICR1; /* DSI Configuration Register 1 */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t SBR:13;\r
+ vuint32_t LOOPS:1;\r
+ vuint32_t SCISDOZ:1;\r
+ vuint32_t RSRC:1;\r
+ vuint32_t M:1;\r
+ vuint32_t WAKE:1;\r
+ vuint32_t ILT:1;\r
+ vuint32_t PE:1;\r
+ vuint32_t PT:1;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TCIE:1;\r
+ vuint32_t RIE:1;\r
+ vuint32_t ILIE:1;\r
+ vuint32_t TE:1;\r
+ vuint32_t RE:1;\r
+ vuint32_t RWU:1;\r
+ vuint32_t SBK:1;\r
+ } B;\r
+ } CR1; /* Control Register 1 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t MDIS:1;\r
+ vuint16_t FBR:1;\r
+ vuint16_t BSTP:1;\r
+ vuint16_t IEBERR:1;\r
+ vuint16_t RXDMA:1;\r
+ vuint16_t TXDMA:1;\r
+ vuint16_t BRK13:1;\r
+ vuint16_t:1;\r
+ vuint16_t BESM13:1;\r
+ vuint16_t SBSTP:1;\r
+ vuint16_t M2:1;\r
+ vuint16_t INPOL:1;\r
+ vuint16_t ORIE:1;\r
+ vuint16_t NFIE:1;\r
+ vuint16_t FEIE:1;\r
+ vuint16_t PFIE:1;\r
+ } B;\r
+ } CR2; /* Control Register 2 */\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R8:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t:6;\r
+ vuint8_t D;\r
+ } B;\r
+ } DR; /* Data Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t TDRE:1;\r
+ vuint32_t TC:1;\r
+ vuint32_t RDRF:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t OR:1;\r
+ vuint32_t NF:1;\r
+ vuint32_t FE:1;\r
+ vuint32_t PF:1;\r
+ vuint32_t:3;\r
+ vuint32_t BERR:1;\r
+ vuint32_t:3;\r
+ vuint32_t RAF:1;\r
+ vuint32_t RXRDY:1;\r
+ vuint32_t TXRDY:1;\r
+ vuint32_t LWAKE:1;\r
+ vuint32_t STO:1;\r
+ vuint32_t PBERR:1;\r
+ vuint32_t CERR:1;\r
+ vuint32_t CKERR:1;\r
+ vuint32_t FRC:1;\r
+ vuint32_t:7;\r
+ vuint32_t OVFL:1;\r
+ } B;\r
+ } SR; /* Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LRES:1;\r
+ vuint32_t WU:1;\r
+ vuint32_t WUD0:1;\r
+ vuint32_t WUD1:1;\r
+ vuint32_t LDBG:1;\r
+ vuint32_t DSF:1;\r
+ vuint32_t PRTY:1;\r
+ vuint32_t LIN:1;\r
+ vuint32_t RXIE:1;\r
+ vuint32_t TXIE:1;\r
+ vuint32_t WUIE:1;\r
+ vuint32_t STIE:1;\r
+ vuint32_t PBIE:1;\r
+ vuint32_t CIE:1;\r
+ vuint32_t CKIE:1;\r
+ vuint32_t FCIE:1;\r
+ vuint32_t:7;\r
+ vuint32_t OFIE:1;\r
+ vuint32_t:8;\r
+ } B;\r
+ } LCR; /* LIN Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LTR; /* LIN Transmit Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LRR; /* LIN Recieve Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } LPR; /* LIN CRC Polynom Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : eSCI */\r
+/****************************************************************************/\r
+ struct ESCI_12_13_bit_tag {\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint16_t R12:1;\r
+ vuint16_t T8:1;\r
+ vuint16_t ERR:1;\r
+ vuint16_t:1;\r
+ vuint16_t D:12;\r
+ } B;\r
+ } DR; /* Data Register */\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : FlexCAN */\r
+/****************************************************************************/\r
+ struct FLEXCAN2_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t:1;\r
+ vuint32_t HALT:1;\r
+ vuint32_t NOTRDY:1;\r
+ vuint32_t:1;\r
+ vuint32_t SOFTRST:1;\r
+ vuint32_t FRZACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t WRNEN:1;\r
+\r
+ vuint32_t MDISACK:1;\r
+ vuint32_t:1;\r
+ vuint32_t:1;\r
+\r
+ vuint32_t SRXDIS:1;\r
+ vuint32_t MBFEN:1;\r
+ vuint32_t:10;\r
+\r
+ vuint32_t MAXMB:6;\r
+ } B;\r
+ } MCR; /* Module Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t PRESDIV:8;\r
+ vuint32_t RJW:2;\r
+ vuint32_t PSEG1:3;\r
+ vuint32_t PSEG2:3;\r
+ vuint32_t BOFFMSK:1;\r
+ vuint32_t ERRMSK:1;\r
+ vuint32_t CLKSRC:1;\r
+ vuint32_t LPB:1;\r
+\r
+ vuint32_t TWRNMSK:1;\r
+ vuint32_t RWRNMSK:1;\r
+ vuint32_t:2;\r
+\r
+ vuint32_t SMP:1;\r
+ vuint32_t BOFFREC:1;\r
+ vuint32_t TSYN:1;\r
+ vuint32_t LBUF:1;\r
+ vuint32_t LOM:1;\r
+ vuint32_t PROPSEG:3;\r
+ } B;\r
+ } CR; /* Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TIMER; /* Free Running Timer */\r
+ int32_t FLEXCAN_reserved00;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RXGMASK; /* RX Global Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX14MASK; /* RX 14 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t MI:29;\r
+ } B;\r
+ } RX15MASK; /* RX 15 Mask */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t RXECNT:8;\r
+ vuint32_t TXECNT:8;\r
+ } B;\r
+ } ECR; /* Error Counter Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+\r
+ vuint32_t TWRNINT:1;\r
+ vuint32_t RWRNINT:1;\r
+\r
+ vuint32_t BIT1ERR:1;\r
+ vuint32_t BIT0ERR:1;\r
+ vuint32_t ACKERR:1;\r
+ vuint32_t CRCERR:1;\r
+ vuint32_t FRMERR:1;\r
+ vuint32_t STFERR:1;\r
+ vuint32_t TXWRN:1;\r
+ vuint32_t RXWRN:1;\r
+ vuint32_t IDLE:1;\r
+ vuint32_t TXRX:1;\r
+ vuint32_t FLTCONF:2;\r
+ vuint32_t:1;\r
+ vuint32_t BOFFINT:1;\r
+ vuint32_t ERRINT:1;\r
+ vuint32_t:1;\r
+ } B;\r
+ } ESR; /* Error and Status Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63M:1;\r
+ vuint32_t BUF62M:1;\r
+ vuint32_t BUF61M:1;\r
+ vuint32_t BUF60M:1;\r
+ vuint32_t BUF59M:1;\r
+ vuint32_t BUF58M:1;\r
+ vuint32_t BUF57M:1;\r
+ vuint32_t BUF56M:1;\r
+ vuint32_t BUF55M:1;\r
+ vuint32_t BUF54M:1;\r
+ vuint32_t BUF53M:1;\r
+ vuint32_t BUF52M:1;\r
+ vuint32_t BUF51M:1;\r
+ vuint32_t BUF50M:1;\r
+ vuint32_t BUF49M:1;\r
+ vuint32_t BUF48M:1;\r
+ vuint32_t BUF47M:1;\r
+ vuint32_t BUF46M:1;\r
+ vuint32_t BUF45M:1;\r
+ vuint32_t BUF44M:1;\r
+ vuint32_t BUF43M:1;\r
+ vuint32_t BUF42M:1;\r
+ vuint32_t BUF41M:1;\r
+ vuint32_t BUF40M:1;\r
+ vuint32_t BUF39M:1;\r
+ vuint32_t BUF38M:1;\r
+ vuint32_t BUF37M:1;\r
+ vuint32_t BUF36M:1;\r
+ vuint32_t BUF35M:1;\r
+ vuint32_t BUF34M:1;\r
+ vuint32_t BUF33M:1;\r
+ vuint32_t BUF32M:1;\r
+ } B;\r
+ } IMRH; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31M:1;\r
+ vuint32_t BUF30M:1;\r
+ vuint32_t BUF29M:1;\r
+ vuint32_t BUF28M:1;\r
+ vuint32_t BUF27M:1;\r
+ vuint32_t BUF26M:1;\r
+ vuint32_t BUF25M:1;\r
+ vuint32_t BUF24M:1;\r
+ vuint32_t BUF23M:1;\r
+ vuint32_t BUF22M:1;\r
+ vuint32_t BUF21M:1;\r
+ vuint32_t BUF20M:1;\r
+ vuint32_t BUF19M:1;\r
+ vuint32_t BUF18M:1;\r
+ vuint32_t BUF17M:1;\r
+ vuint32_t BUF16M:1;\r
+ vuint32_t BUF15M:1;\r
+ vuint32_t BUF14M:1;\r
+ vuint32_t BUF13M:1;\r
+ vuint32_t BUF12M:1;\r
+ vuint32_t BUF11M:1;\r
+ vuint32_t BUF10M:1;\r
+ vuint32_t BUF09M:1;\r
+ vuint32_t BUF08M:1;\r
+ vuint32_t BUF07M:1;\r
+ vuint32_t BUF06M:1;\r
+ vuint32_t BUF05M:1;\r
+ vuint32_t BUF04M:1;\r
+ vuint32_t BUF03M:1;\r
+ vuint32_t BUF02M:1;\r
+ vuint32_t BUF01M:1;\r
+ vuint32_t BUF00M:1;\r
+ } B;\r
+ } IMRL; /* Interruput Masks Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF63I:1;\r
+ vuint32_t BUF62I:1;\r
+ vuint32_t BUF61I:1;\r
+ vuint32_t BUF60I:1;\r
+ vuint32_t BUF59I:1;\r
+ vuint32_t BUF58I:1;\r
+ vuint32_t BUF57I:1;\r
+ vuint32_t BUF56I:1;\r
+ vuint32_t BUF55I:1;\r
+ vuint32_t BUF54I:1;\r
+ vuint32_t BUF53I:1;\r
+ vuint32_t BUF52I:1;\r
+ vuint32_t BUF51I:1;\r
+ vuint32_t BUF50I:1;\r
+ vuint32_t BUF49I:1;\r
+ vuint32_t BUF48I:1;\r
+ vuint32_t BUF47I:1;\r
+ vuint32_t BUF46I:1;\r
+ vuint32_t BUF45I:1;\r
+ vuint32_t BUF44I:1;\r
+ vuint32_t BUF43I:1;\r
+ vuint32_t BUF42I:1;\r
+ vuint32_t BUF41I:1;\r
+ vuint32_t BUF40I:1;\r
+ vuint32_t BUF39I:1;\r
+ vuint32_t BUF38I:1;\r
+ vuint32_t BUF37I:1;\r
+ vuint32_t BUF36I:1;\r
+ vuint32_t BUF35I:1;\r
+ vuint32_t BUF34I:1;\r
+ vuint32_t BUF33I:1;\r
+ vuint32_t BUF32I:1;\r
+ } B;\r
+ } IFRH; /* Interruput Flag Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BUF31I:1;\r
+ vuint32_t BUF30I:1;\r
+ vuint32_t BUF29I:1;\r
+ vuint32_t BUF28I:1;\r
+ vuint32_t BUF27I:1;\r
+ vuint32_t BUF26I:1;\r
+ vuint32_t BUF25I:1;\r
+ vuint32_t BUF24I:1;\r
+ vuint32_t BUF23I:1;\r
+ vuint32_t BUF22I:1;\r
+ vuint32_t BUF21I:1;\r
+ vuint32_t BUF20I:1;\r
+ vuint32_t BUF19I:1;\r
+ vuint32_t BUF18I:1;\r
+ vuint32_t BUF17I:1;\r
+ vuint32_t BUF16I:1;\r
+ vuint32_t BUF15I:1;\r
+ vuint32_t BUF14I:1;\r
+ vuint32_t BUF13I:1;\r
+ vuint32_t BUF12I:1;\r
+ vuint32_t BUF11I:1;\r
+ vuint32_t BUF10I:1;\r
+ vuint32_t BUF09I:1;\r
+ vuint32_t BUF08I:1;\r
+ vuint32_t BUF07I:1;\r
+ vuint32_t BUF06I:1;\r
+ vuint32_t BUF05I:1;\r
+ vuint32_t BUF04I:1;\r
+ vuint32_t BUF03I:1;\r
+ vuint32_t BUF02I:1;\r
+ vuint32_t BUF01I:1;\r
+ vuint32_t BUF00I:1;\r
+ } B;\r
+ } IFRL; /* Interruput Flag Register */\r
+\r
+ uint32_t flexcan2_reserved2[19];\r
+\r
+ struct canbuf_t {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:4;\r
+ vuint32_t CODE:4;\r
+ vuint32_t:1;\r
+ vuint32_t SRR:1;\r
+ vuint32_t IDE:1;\r
+ vuint32_t RTR:1;\r
+ vuint32_t LENGTH:4;\r
+ vuint32_t TIMESTAMP:16;\r
+ } B;\r
+ } CS;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:3;\r
+ vuint32_t STD_ID:11;\r
+ vuint32_t EXT_ID:18;\r
+ } B;\r
+ } ID;\r
+\r
+ union {\r
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
+ } DATA;\r
+\r
+ } BUF[32];\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Decimation Filter (DECFIL) */\r
+/****************************************************************************/\r
+ struct DECFIL_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t SRES:1;\r
+ vuint32_t:2;\r
+ vuint32_t IDEN:1;\r
+ vuint32_t ODEN:1;\r
+ vuint32_t ERREN:1;\r
+ vuint32_t:1;\r
+ vuint32_t FTYPE:2;\r
+ vuint32_t:1;\r
+ vuint32_t SCAL:2;\r
+ vuint32_t:1;\r
+ vuint32_t SAT:1;\r
+ vuint32_t ISEL:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_RATE:4;\r
+ vuint32_t:8;\r
+ } B;\r
+ } MCR; /* Configuration Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t BSY:1;\r
+ vuint32_t:1;\r
+ vuint32_t DEC_COUNTER:4;\r
+ vuint32_t IDFC:1;\r
+ vuint32_t ODFC:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVFC:1;\r
+ vuint32_t OVRC:1;\r
+ vuint32_t IVRC:1;\r
+ vuint32_t:6;\r
+ vuint32_t IDF:1;\r
+ vuint32_t ODF:1;\r
+ vuint32_t:5;\r
+ vuint32_t OVF:1;\r
+ vuint32_t OVR:1;\r
+ vuint32_t IVR:1;\r
+ } B;\r
+ } MSR; /* Status Register */\r
+\r
+ uint32_t decfil_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:14;\r
+ vuint32_t PREFILL:1;\r
+ vuint32_t FLUSH:1;\r
+ vuint32_t INPBUF:16;\r
+ } B;\r
+ } IB;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t OUTTEG:4;\r
+ vuint32_t OUTBUF:16;\r
+ } B;\r
+ } OB;\r
+\r
+ uint32_t decfil_reserved2[2];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } COEF[9]; /* Filter Coefficient Registers */\r
+\r
+ uint32_t decfil_reserved3[13];\r
+\r
+ union {\r
+ vuint16_t R;\r
+ struct {\r
+ vuint32_t:8;\r
+ vuint32_t COEF:24;\r
+ } B;\r
+ } TAP[8]; /* Filter TAP Registers */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Periodic Interval Timer (PIT) */\r
+/****************************************************************************/\r
+ struct PIT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:29;\r
+ vuint32_t MDIS_RTI:1;\r
+ vuint32_t MDIS:1;\r
+ vuint32_t FRZ:1;\r
+ } B;\r
+ } MCR; /* PIT Module Control Register */\r
+\r
+ uint32_t pit_reserved1[59];\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } RTI; /* RTI Channel */\r
+\r
+ struct {\r
+ union {\r
+ vuint32_t R;\r
+ } LDVAL; /* Timer Load Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CVAL; /* Current Timer Value Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:30;\r
+ vuint32_t TIE:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } TCTRL; /* Timer Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } TFLG; /* Timer Flag Register */\r
+ } TIMER[4]; /* Timer Channels */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : System Timer Module (STM) */\r
+/****************************************************************************/\r
+ struct STM_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t CPS:8;\r
+ vuint32_t:6;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t TEN:1;\r
+ } B;\r
+ } CR; /* STM Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CNT; /* STM Counter Value */\r
+\r
+ uint32_t stm_reserved1[2];\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR0; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR0; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP0; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved2;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR1; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR1; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP1; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved3;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR2; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR2; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP2; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved4;\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CEN:1;\r
+ } B;\r
+ } CCR3; /* STM Channel 0 Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t CIF:1;\r
+ } B;\r
+ } CIR3; /* STM Channel 0 Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CMP3; /* STM Channel 0 Compare Register */\r
+\r
+ uint32_t stm_reserved5;\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Software Watchdog Timer (SWT) */\r
+/****************************************************************************/\r
+ struct SWT_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t MAP0:1;\r
+ vuint32_t MAP1:1;\r
+ vuint32_t MAP2:1;\r
+ vuint32_t MAP3:1;\r
+ vuint32_t MAP4:1;\r
+ vuint32_t MAP5:1;\r
+ vuint32_t MAP6:1;\r
+ vuint32_t MAP7:1;\r
+ vuint32_t:15;\r
+ vuint32_t RIA:1;\r
+ vuint32_t WNO:1;\r
+ vuint32_t ITR:1;\r
+ vuint32_t HLK:1;\r
+ vuint32_t SLK:1;\r
+ vuint32_t CSL:1;\r
+ vuint32_t STP:1;\r
+ vuint32_t FRZ:1;\r
+ vuint32_t WEN:1;\r
+ } B;\r
+ } CR; /* SWT Control Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:31;\r
+ vuint32_t TIF:1;\r
+ } B;\r
+ } IR; /* SWT Interrupt Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } TO; /* SWT Time-out Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } WN; /* SWT Window Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:16;\r
+ vuint32_t WSC:16;\r
+ } B;\r
+ } SR; /* SWT Service Register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ } CO; /* Counter Output Register */\r
+\r
+ };\r
+/****************************************************************************/\r
+/* MODULE : Power Management Controller (PMC) */\r
+/****************************************************************************/\r
+ struct PMC_tag {\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t LVIRR:1;\r
+ vuint32_t LVIHR:1;\r
+ vuint32_t LVI5R:1;\r
+ vuint32_t LVI3R:1;\r
+ vuint32_t LVI1R:1;\r
+ vuint32_t BRW:1;\r
+ vuint32_t BGS1:1;\r
+ vuint32_t BGS2:1;\r
+ vuint32_t LVIRE:1;\r
+ vuint32_t LVIHE:1;\r
+ vuint32_t LVI5E:1;\r
+ vuint32_t LVI3E:1;\r
+ vuint32_t LVI1E:1;\r
+ vuint32_t:2;\r
+ vuint32_t TLK:1;\r
+ vuint32_t LVIRC:1;\r
+ vuint32_t LVIHC:1;\r
+ vuint32_t LVI5C:1;\r
+ vuint32_t LVI3C:1;\r
+ vuint32_t LVI1C:1;\r
+ vuint32_t:3;\r
+ vuint32_t LVIRF:1;\r
+ vuint32_t LVIHF:1;\r
+ vuint32_t LVI5F:1;\r
+ vuint32_t LVI3F:1;\r
+ vuint32_t LVI1F:1;\r
+ vuint32_t:3;\r
+ } B;\r
+ } CFGR; /* Configuration and status register */\r
+\r
+ union {\r
+ vuint32_t R;\r
+ struct {\r
+ vuint32_t:12;\r
+ vuint32_t LVI50TRIM:4;\r
+ vuint32_t V33TRIM:4;\r
+ vuint32_t LVI33TRIM:4;\r
+ vuint32_t V12TRIM:4;\r
+ vuint32_t LVI12TRIM:4;\r
+ } B;\r
+ } TRIMR; /* Trimming register */\r
+ };\r
+\r
+/* Define memories */\r
+\r
+#define SRAM_START 0x40000000\r
+#define SRAM_SIZE 0xC000\r
+#define SRAM_END 0x4000BFFF\r
+\r
+#define FLASH_START 0x0\r
+#define FLASH_SIZE 0x100000\r
+#define FLASH_END 0xFFFFF\r
+\r
+/* Define instances of modules */\r
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)\r
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)\r
+#define FLASH (*( volatile struct FLASH_tag *) 0xC3F88000)\r
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)\r
+\r
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)\r
+#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)\r
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)\r
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)\r
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)\r
+#define ETPU_DATA_RAM_END 0xC3FC89FC\r
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)\r
+#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)\r
+\r
+#define PBRIDGE (*( struct PBRIDGE_tag *) 0xFFF00000)\r
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)\r
+#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)\r
+#define STM (*( volatile struct STM_tag *) 0xFFF3C000)\r
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)\r
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)\r
+#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000)\r
+\r
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)\r
+\r
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006)\r
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)\r
+#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006)\r
+\r
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)\r
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)\r
+\r
+#ifdef __MWERKS__\r
+#pragma pop\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+#endif /* ifdef _MPC563M_H */\r
+/*********************************************************************\r
+ *\r
+ * Copyright:\r
+ * Freescale Semiconductor, INC. All Rights Reserved.\r
+ * You are hereby granted a copyright license to use, modify, and\r
+ * distribute the SOFTWARE so long as this entire notice is\r
+ * retained without alteration in any modified and/or redistributed\r
+ * versions, and that such modified versions are clearly identified\r
+ * as such. No licenses are granted by implication, estoppel or\r
+ * otherwise under any patents or trademarks of Freescale\r
+ * Semiconductor, Inc. This software is provided on an "AS IS"\r
+ * basis and without warranty.\r
+ *\r
+ * To the maximum extent permitted by applicable law, Freescale\r
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,\r
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A\r
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH\r
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)\r
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.\r
+ *\r
+ * To the maximum extent permitted by applicable law, IN NO EVENT\r
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER\r
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,\r
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER\r
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.\r
+ *\r
+ * Freescale Semiconductor assumes no responsibility for the\r
+ * maintenance and support of this software\r
+ *\r
+ ********************************************************************/\r
projects / arc.git / commitdiff