+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
-#include "typedefs.h"\r
-#include "asm_book_e.h"\r
-#include "mpc55xx.h"\r
-#if !defined(USE_KERNEL)\r
-#include "Mcu.h"\r
-#endif\r
-#include <assert.h>\r
-//#include <stdio.h>\r
-\r
-#if defined(USE_KERNEL)\r
-#include "pcb.h"\r
-#include "sys.h"\r
-#include "internal.h"\r
-#include "task_i.h"\r
-#include "hooks.h"\r
-#include "swap.h"\r
-\r
-#define INTC_SSCIR0_CLR7 7\r
-#define MLB_SERVICE_REQUEST 293\r
-#define CRITICAL_INPUT_EXCEPTION 320\r
-#define DEBUG_EXCEPTION 335\r
-#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 336\r
-\r
-#include "Trace.h"\r
-#endif\r
-\r
-static void dump_exception_regs( uint32_t *regs );\r
-\r
-typedef void (*f_t)( uint32_t *);\r
-typedef void (*func_t)();\r
-\r
-#if defined(USE_KERNEL)\r
-extern void * intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-extern uint8 intc_type_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-#else\r
-extern func_t intc_vector_tbl[];\r
-#endif\r
-\r
-/* Handle INTC\r
- *\r
- * When we get here we have saved\r
- * - exception frame\r
- * - VGPR\r
- * - ?\r
- *\r
- * */\r
-\r
-\r
-\r
-void IntCtrl_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector,uint8_t prio) {\r
-#if defined(CFG_MPC5516)\r
- uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */\r
-#endif\r
-\r
- intc_vector_tbl[vector] = (void *)entry;\r
- intc_type_tbl[vector] = PROC_ISR1;\r
-\r
- if (vector <= MLB_SERVICE_REQUEST) {\r
-#if defined(CFG_MPC5516)\r
- INTC.PSR[vector].B.PRC_SEL = cpu;\r
-#endif\r
- INTC.PSR[vector].B.PRI = prio;\r
-\r
- } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector\r
- <= DEBUG_EXCEPTION)) {\r
- } else {\r
- /* Invalid vector! */\r
- assert(0);\r
- }\r
-\r
-}\r
-\r
-void IntCtrl_AttachIsr2(TaskType tid,void *int_ctrl,uint32_t vector ) {\r
-#if defined(CFG_MPC5516)\r
- uint8_t cpu = 0; /* 0- cpu Z1, 1-CPU Z0(slave) */\r
-#endif\r
- pcb_t *pcb;\r
-\r
- pcb = os_find_task(tid);\r
- intc_vector_tbl[vector] = (void *)pcb;\r
- intc_type_tbl[vector] = PROC_ISR2;\r
-\r
- if (vector <= MLB_SERVICE_REQUEST) {\r
-#if defined(CFG_MPC5516)\r
- INTC.PSR[vector].B.PRC_SEL = cpu;\r
-#endif\r
- INTC.PSR[vector].B.PRI = pcb->prio;\r
-\r
- } else if ((vector >= CRITICAL_INPUT_EXCEPTION) && (vector\r
- <= DEBUG_EXCEPTION)) {\r
- } else {\r
- /* Invalid vector! */\r
- assert(0);\r
- }\r
-}\r
-\r
-\r
-/**\r
- *\r
- * USE_KERNEL\r
- * Following must be done before coming here:\r
- * - Swapped to interrupt stack, or???\r
- *\r
- * @param stack Ptr to current stack. The context just saved\r
- * can be access with positive offsets.\r
- */\r
-\r
-void *mcu_intc( uint32_t *stack ) {\r
- uint32_t vector;\r
-\r
-#if defined(CFG_MPC5516)\r
- struct INTC_tag *intc = &INTC;\r
-#else\r
- volatile struct INTC_tag *intc = &INTC;\r
-#endif\r
-\r
-#if defined(USE_KERNEL)\r
- struct pcb_s *pcb;\r
- struct pcb_s *preempted_pcb;\r
-#else\r
- func_t t;\r
-#endif\r
-\r
- // Check for exception\r
- if( stack[EXC_VECTOR_OFF/sizeof(uint32_t)]>=CRITICAL_INPUT_EXCEPTION )\r
- {\r
- vector = stack[EXC_VECTOR_OFF/sizeof(uint32_t)];\r
- }\r
- else\r
- {\r
-#if defined(CFG_MPC5516)\r
- vector = (intc->IACKR_PRC0.B.INTVEC_PRC0);\r
-#else\r
- vector = (intc->IACKR.B.INTVEC);\r
-#endif\r
- // save the vector for later\r
- stack[EXC_VECTOR_OFF/sizeof(uint32_t)] = vector;\r
-\r
- // Check for software interrupt\r
- if((uint32_t)vector<=INTC_SSCIR0_CLR7)\r
- {\r
- // Clear soft int\r
- intc->SSCIR[vector].B.CLR = 1;\r
- }\r
- }\r
-\r
-#if defined(USE_KERNEL)\r
-\r
- os_sys.int_nest_cnt++;\r
-\r
- if( intc_type_tbl[vector] == PROC_ISR1 ) {\r
- // It's a function, just call it.\r
- ((func_t)intc_vector_tbl[vector])();\r
- } else {\r
- // It's a PCB\r
-\r
- // Save info for preemted pcb\r
- preempted_pcb = get_curr_pcb();\r
- preempted_pcb->stack.curr = stack;\r
- preempted_pcb->state = ST_READY;\r
- os_isr_printf(D_TASK,"Preempted %s\n",preempted_pcb->name);\r
-\r
- POSTTASKHOOK();\r
-\r
- pcb = intc_vector_tbl[vector];\r
- pcb->state = ST_RUNNING;\r
- set_curr_pcb(pcb);\r
-\r
- PRETASKHOOK();\r
-\r
- // We should not get here if we're SCHEDULING_NONE\r
- if( pcb->scheduling == SCHEDULING_NONE) {\r
- // TODO:\r
- // assert(0);\r
- while(1);\r
- }\r
- //Irq_Enable(); // Added by Mattias\r
- //Irq_Enable();\r
- pcb->entry();\r
- Irq_Disable();\r
- }\r
-\r
- pcb->state = ST_SUSPENDED;\r
- POSTTASKHOOK();\r
-\r
- // write 0 to pop INTC stack\r
-\r
-#if defined(CFG_MPC5516)\r
- intc->EOIR_PRC0.R = 0;\r
-#else\r
- intc->EOIR.R = 0;\r
-#endif\r
- --os_sys.int_nest_cnt;\r
-\r
- // TODO: Check stack check marker....\r
- // We have preempted a task\r
- if( (os_sys.int_nest_cnt == 0) ) { //&& is_idle_task() ) {\r
- /* If we get here:\r
- * - the preempted task is saved with large context.\r
- * - We are on interrupt stack..( this function )\r
- *\r
- * if we find a new task:\r
- * - just switch in the new context( don't save the old because\r
- * its already saved )\r
- *\r
- */\r
- pcb_t *new_pcb;\r
- new_pcb = os_find_top_prio_proc();\r
- if( new_pcb != preempted_pcb ) {\r
- os_isr_printf(D_TASK,"Found candidate %s\n",new_pcb->name);\r
-//#warning os_swap_context_to should call the pretaskswaphook\r
- os_swap_context_to(NULL,new_pcb);\r
- } else {\r
- if( new_pcb == NULL ) {\r
- assert(0);\r
- }\r
- preempted_pcb->state = ST_RUNNING;\r
- set_curr_pcb(preempted_pcb);\r
- }\r
- }\r
-\r
- return stack;\r
-\r
-#else\r
- //read address\r
- t = (func_t)intc_vector_tbl[vector];\r
-\r
- if( t == ((void *)0) )\r
- {\r
- while(1);\r
- }\r
-\r
- // Enable nestling interrupts\r
- Irq_Enable();\r
- t();\r
- Irq_Disable();\r
-\r
- if( vector < INTC_NUMBER_OF_INTERRUPTS )\r
- {\r
- // write 0 to pop INTC stack\r
- intc->EOIR_PRC0.R = 0;\r
- }\r
- return NULL;\r
-#endif\r
-}\r
-\r
-void dummy (void);\r
-\r
-// Critical Input Interrupt\r
-void IVOR0Exception (uint32_t *regs)\r
-{\r
-// srr0 = get_spr(SPR_SRR0);\r
-// srr1 = get_spr(SPR_SRR0);\r
-// ExceptionSave(srr0,srr1,esr,mcsr,dear;)\r
- // CSRR0, CSSR1\r
- // Nothing more\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Machine check\r
-void IVOR1Exception (uint32_t *regs)\r
-{\r
- // CSRR0, CSSR1\r
- // MCSR - Source of machine check\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-// Data Storage Interrupt\r
-void IVOR2Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR - lots of stuff\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Instruction Storage Interrupt\r
-void IVOR3Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR - lots of stuff\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Alignment Interrupt\r
-void IVOR5Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR - lots of stuff\r
- // DEAR - Address of load store that caused the exception\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Program Interrupt\r
-void IVOR6Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR - lots of stuff\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Floating point unavailable\r
-void IVOR7Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// System call\r
-void IVOR8Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Aux processor Unavailable\r
-void IVOR9Exception (uint32_t *regs)\r
-{\r
- // Does not happen on e200\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-#if 0\r
-// Decrementer\r
-void IVOR10Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- while (1);\r
-}\r
-#endif\r
-\r
-// FIT\r
-void IVOR11Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Watchdog Timer\r
-void IVOR12Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-// Data TLB Error Interrupt\r
-void IVOR13Exception (uint32_t *regs)\r
-{\r
-#if 0\r
- uint32_t srr0,srr1,esr,dear;\r
-\r
- srr0 = regs[SC_GPRS_SIZE+(EXC_SRR0_OFF/4)];\r
- srr1 = regs[SC_GPRS_SIZE+(EXC_SRR1_OFF/4)];\r
- esr = regs[SC_GPRS_SIZE+(EXC_ESR_OFF/4)];\r
- dear = regs[SC_GPRS_SIZE+(EXC_DEAR_OFF/4)];\r
- dump_exception_regs(regs);\r
-#endif\r
-\r
- // SRR0, SRR1\r
- // ESR - lots\r
- // DEAR -\r
- while (1);\r
-}\r
-\r
-// Instruction TLB Error Interupt\r
-void IVOR14Exception (uint32_t *regs)\r
-{\r
- // SRR0, SRR1\r
- // ESR - MIF set, All others cleared\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-void IVOR15Exception (uint32_t *regs)\r
-{\r
- // Debug\r
- dump_exception_regs(regs);\r
- while (1);\r
-}\r
-\r
-#if defined(CFG_CONSOLE_T32) || defined(CFG_CONSOLE_WINIDEA)\r
-\r
-typedef struct {\r
- uint32_t sp;\r
- uint32_t bc; // backchain\r
- uint32_t pad;\r
- uint32_t srr0;\r
- uint32_t srr1;\r
- uint32_t lr;\r
- uint32_t ctr;\r
- uint32_t xer;\r
- uint32_t cr;\r
- uint32_t esr;\r
- uint32_t mcsr;\r
- uint32_t dear;\r
- uint32_t vector;\r
- uint32_t r3;\r
- uint32_t r4;\r
-} exc_stack_t;\r
-\r
-\r
-\r
-static void dump_exception_regs( uint32_t *regs ) {\r
- exc_stack_t *r = (exc_stack_t *)regs;\r
-\r
-dbg_printf("sp %08x srr0 %08x srr1 %08x\n",r->sp,r->srr0,r->srr1);\r
-dbg_printf("lr %08x ctr %08x xer %08x\n",r->lr,r->ctr,r->xer);\r
-dbg_printf("cr %08x esr %08x mcsr %08x\n",r->cr,r->esr,r->mcsr);\r
-dbg_printf("dear %08x vec %08x r3 %08x\n",r->dear,r->vector,r->r3);\r
-dbg_printf("r4 %08x\n",r->r4);\r
-}\r
-\r
-#else\r
-static void dump_exception_regs( uint32_t *regs ) {\r
-}\r
-#endif\r
-\r
-#if !defined(USE_KERNEL)\r
-func_t intc_vector_tbl[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS] __attribute__ ((aligned (0x800))) = {\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 00 - 04 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 05 - 09 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 10 - 14 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 15 - 19 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 20 - 24 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 25 - 29 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 30 - 34 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 35 - 39 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 40 - 44 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 45 - 49 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 50 - 54 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 59 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 60 - 64 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 55 - 69 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 70 - 74 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 75 - 79 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 80 - 84 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 85 - 89 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 90 - 94 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 95 - 99 */\r
-\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 100 - 104 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 105 - 109 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 110 - 114 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 115 - 119 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 120 - 124 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 125 - 129 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 130 - 134 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 135 - 139 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 140 - 144 */\r
- dummy, dummy, dummy, dummy, dummy /* PIT1 */, /* ISRs 145 - 149 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 150 - 154 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 159 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 160 - 164 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 155 - 169 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 170 - 174 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 175 - 179 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 180 - 184 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 185 - 189 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 190 - 194 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 195 - 199 */\r
-\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 200 - 204 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 205 - 209 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 210 - 214 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 215 - 219 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 220 - 224 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 225 - 229 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 230 - 234 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 235 - 239 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 240 - 244 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 245 - 249 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 250 - 254 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 259 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 260 - 264 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 255 - 269 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 270 - 274 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 275 - 279 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 280 - 284 */\r
- dummy, dummy, dummy, dummy, dummy, /* ISRs 285 - 289 */\r
- dummy, dummy, dummy, dummy, /* ISRs 290 - 293 */\r
-\r
- /* Some reserved vectors between INC interrupts and exceptions. */\r
- dummy, /* INTC_NUMBER_OF_INTERRUPTS */\r
-\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
- dummy, dummy, dummy, dummy, dummy,\r
-\r
- IVOR0Exception, /* CRITICAL_INPUT_EXCEPTION, */\r
- IVOR1Exception, /* MACHINE_CHECK_EXCEPTION */\r
- IVOR2Exception, /* DATA_STORAGE_EXCEPTION */\r
- IVOR3Exception, /* INSTRUCTION_STORAGE_EXCEPTION */\r
- dummy, /* EXTERNAL_INTERRUPT */\r
- /* This is the place where the "normal" interrupts will hit the CPU... */\r
- IVOR5Exception, /* ALIGNMENT_EXCEPTION */\r
- IVOR6Exception, /* PROGRAM_EXCEPTION */\r
- IVOR7Exception, /* FLOATING_POINT_EXCEPTION */\r
- IVOR8Exception, /* SYSTEM_CALL_EXCEPTION */\r
- dummy, /* AUX_EXCEPTION Not implemented in MPC5516. */\r
- dummy, /* DECREMENTER_EXCEPTION */\r
- IVOR11Exception, /* FIXED_INTERVAL_TIMER_EXCEPTION */\r
- IVOR12Exception, /* WATCHDOG_TIMER_EXCEPTION */\r
- IVOR13Exception, /* DATA_TLB_EXCEPTION */\r
- IVOR14Exception, /* INSTRUCTION_TLB_EXCEPTION */\r
- IVOR15Exception, /* DEBUG_EXCEPTION */\r
-};\r
-\r
-void dummy (void) {\r
- while (1){\r
- /* TODO: Rename and check for what spurious interrupt have happend */\r
- };\r
- }\r
-\r
-#endif\r